Image signal processor verification method, apparatus, device and readable storage medium

Abstract

A method, apparatus, device, and readable storage medium for verifying an image signal processor (ISP) are disclosed. In this method, random input image data and configuration files are generated based on random configuration, reducing the coupling between configuration and interface input in ISP verification. The random configuration is uniformly parsed and processed, ensuring consistency between the device under test (DUT) and the algorithm model configuration in the process, thus reducing the probability of errors in ISP verification. Through dynamic configuration of the ISP algorithm, algorithm parameter tuning can be achieved by combining simulation and randomization.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to an image signal processor verification method, apparatus, device, and computer-readable storage medium. Background Technology

[0002] In existing technical solutions, the verification of image signal processors (ISPs) mainly involves using a camera or directly generated inherent images as image data inputs for the verification of the ISP subsystem or system-on-a-chip (SoC). The image signal processor and its corresponding algorithm model are then configured according to the format of the original image, and finally, the image is displayed or the data is compared.

[0003] This verification method based on inherent image input is susceptible to errors. Changes in the input image parameters, such as image format and resolution, will alter the DUT configuration parameters and simulation model configuration parameters during ISP verification, making random verification impossible. Furthermore, after parameter changes, manual maintenance of the correspondence between the input image and configuration parameters is required, which is prone to errors. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides an image signal processor verification method, apparatus, device, and computer-readable storage medium.

[0005] In a first aspect, embodiments of this application provide an image signal processor verification method, the image signal processor verification method comprising:

[0006] Random images, the register configuration file of the design under test (DUT), the register configuration file of the algorithm model, and the storage configuration file are generated based on the random configuration in the image signal processor (ISP) verification. The random values ​​of the random configuration are generated based on random constraints.

[0007] Configure the DUT according to its register configuration file and storage configuration file;

[0008] Configure the algorithm model according to the register configuration file and storage configuration file of the algorithm model;

[0009] The random image is processed based on the configured DUT to obtain real data;

[0010] The random image is processed based on the configured algorithm model to obtain the desired data;

[0011] The image signal processor verification results are obtained based on the comparison between the actual data and the expected data.

[0012] In conjunction with the first aspect, in one implementation, generating the register profile of the design under test (DUT) based on a random configuration during image signal processor (ISP) verification includes:

[0013] The correspondence between random configurations and strings in the ISP image signal processor verification is determined. The strings are obtained by parsing the register model in the TB image processor verification platform. Each string includes the address, name, and domain name of a register.

[0014] Based on the aforementioned correspondence, the mapping relationship between random values, addresses, register names, and register fields is obtained;

[0015] Based on the mapping relationship, the register configuration statement of the DUT corresponding to each random value is generated, and all the register configuration statements of the DUT are filled into the initial register configuration file of the DUT to obtain the register configuration file of the DUT.

[0016] In conjunction with the first aspect, in one implementation, the register configuration file for generating the algorithm model based on the random configuration in the image signal processor ISP verification includes:

[0017] Based on the mapping relationship, the register configuration statement of the algorithm model corresponding to each random value is generated, and the register configuration statements of all algorithm models are filled into the initial register configuration file of the algorithm model to obtain the register configuration file of the algorithm model.

[0018] In conjunction with the first aspect, in one implementation, generating a stored configuration file based on a random configuration in the image signal processor (ISP) verification includes:

[0019] The transformation matrix or vector of the algorithm model is updated based on the random configuration in the image signal processor (ISP) verification.

[0020] The default storage configuration file is updated based on the new transformation matrix or vector to obtain the storage configuration file.

[0021] In conjunction with the first aspect, in one implementation, obtaining the image signal processor verification result based on the comparison between the actual data and the expected data includes:

[0022] If the actual data matches the expected data, the image signal processor verification result is "verification passed".

[0023] If the actual data does not match the expected data, the image signal processor verification result will be verification failure.

[0024] In conjunction with the first aspect, in one implementation, after obtaining the image signal processor verification result based on the comparison result between the actual data and the expected data, the method further includes:

[0025] If the image signal processor verification result is verification failure, the cause is determined based on the simulation log;

[0026] If the reason is that the random constraints do not meet the ISP design requirements, then modify the random constraints.

[0027] In conjunction with the first aspect, in one implementation, the random configuration includes one or more of image format, image resolution, and storage type.

[0028] Secondly, embodiments of this application provide an image signal processor verification device, the image signal processor verification device comprising:

[0029] The generation module is used to generate random images, register configuration files of the design under test (DUT), register configuration files of the algorithm model, and storage configuration files based on the random configuration in the image signal processor (ISP) verification. The random values ​​of the random configuration are generated based on random constraints.

[0030] The configuration model is used to configure the DUT according to its register configuration file and storage configuration file; and to configure the algorithm model according to its register configuration file and storage configuration file.

[0031] The first processing module is used to process random images based on the configured DUT to obtain real data;

[0032] The second processing module is used to process random images based on the configured algorithm model to obtain the desired data;

[0033] The verification module is used to obtain the verification results of the image signal processor based on the comparison between the real data and the expected data.

[0034] Thirdly, embodiments of this application provide an image signal processor verification device, which includes a processor, a memory, and an image signal processor verification program stored in the memory and executable by the processor. When the image signal processor verification program is executed by the processor, it implements the steps of the image signal processor verification method as described in the first aspect.

[0035] Fourthly, embodiments of this application provide a computer-readable storage medium storing an image signal processor verification program, wherein when the image signal processor verification program is executed by a processor, it implements the steps of the image signal processor verification method as described in the first aspect.

[0036] The beneficial effects of the technical solutions provided in this application include:

[0037] Random input image data and configuration files are generated based on random configuration, reducing the coupling between configuration and interface input in ISP verification; the random configuration is parsed and processed in a unified manner, ensuring the consistency of the DUT and algorithm model configuration in the process, reducing the probability of errors in ISP verification; through the dynamic configuration of the ISP algorithm, the algorithm parameters can be optimized by combining simulation and randomness. Attached Figure Description

[0038] Figure 1 This is a flowchart illustrating an embodiment of the image signal processor verification method of this application;

[0039] Figure 2 This is a schematic diagram of random image generation and transmission in one embodiment of the image signal processor verification method of this application;

[0040] Figure 3 This is a schematic diagram of the register configuration file generation process in one embodiment of the image signal processor verification method of this application;

[0041] Figure 4 This is a schematic diagram illustrating the generation and configuration process of a storage configuration file in one embodiment of the image signal processor verification method of this application;

[0042] Figure 5 This is a functional module diagram of an embodiment of the image signal processor verification device of this application;

[0043] Figure 6 This is a schematic diagram of the hardware structure of the image signal processor verification device involved in the embodiments of this application. Detailed Implementation

[0044] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0045] First, some of the technical terms used in this application will be explained to help those skilled in the art understand this application.

[0046] SoC: System on Chip;

[0047] ISP: Image Signal Processor;

[0048] Stream output: ISP outputs a serial data stream;

[0049] Slot: The transmission channel of an ISP;

[0050] TB: Image Processor Verification Platform;

[0051] Scoreboard: The scoreboard in TB, which includes the comparison and checking of the final data;

[0052] Raw: The raw image data format that stores the grayscale values ​​of the image;

[0053] Msb: most significant bit;

[0054] Lsb: least significant bit;

[0055] DUT: Design Under Test.

[0056] Simulation: Using computer-aided software to simulate hardware designs.

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0058] In a first aspect, embodiments of this application provide an image signal processor verification method.

[0059] In one embodiment, reference is made to Figure 1 , Figure 1 This is a schematic flowchart of an embodiment of the image signal processor verification method of this application. Figure 1 As shown, the image signal processor verification method includes:

[0060] Step S10: Generate a random image, a register configuration file of the design under test (DUT), a register configuration file of the algorithm model, and a storage configuration file based on the random configuration in the image signal processor (ISP) verification. The random values ​​of the random configuration are generated based on random constraints.

[0061] In this embodiment, for configuration parameters that can be randomly configured during ISP verification (i.e., random configuration), random values ​​for the random configuration are generated according to predefined random constraints. This is achieved by adding a random component, which is a component in the verification environment that contains random variables (i.e., random configuration) and random variable control statements. The random variable control statements in the random component are used to fix a range for each random variable, allowing the random variable to be randomized within that range. Randomization is achieved by using a pseudo-random number generator to generate a value within the random constraints.

[0062] Furthermore, in one embodiment, the random configuration includes one or more of image format, image resolution, and storage type.

[0063] Among them, the image format is Raw8 / 10 / 12 / 14 / 16 / 20 / 24, the storage type is msb / lsb, and the layout is tight / non-tight.

[0064] Furthermore, in one embodiment, the configuration of specific scenario parameters can be added, enabling direct verification of specific scenarios. This is because in some cases, the verification scenario needs to be fixed, and the variables cannot be randomized. Therefore, a random switch mechanism is added to allow for enabling or disabling parameter randomization based on the verification environment configuration. If randomization is required, step S10 is executed. It should be noted that in the verification environment, the random switch mechanism and the configuration of the DUT and algorithm model are independent of each other.

[0065] After generating random values ​​for the random configuration, the random image generation script `randimg_gen` can be called to generate a random image based on these values. This random image (`input_img`) is then sent to the Data Under Test (DUT) and the ISP algorithm model (`isp_cmodel`) as input to their respective components. Illustratively, the `randimg_gen` script performs the following functions: determining which image generation function to call based on the random values; randomly generating data according to the size of bytes or words and filling it into the corresponding positions; and calculating the total number of bytes or words based on the data type to determine the end position of the filling. (See reference...) Figure 2 , Figure 2 This is a schematic diagram of random image generation and transmission in one embodiment of the image signal processor verification method of this application.

[0066] The configuration of the ISP includes two aspects: 1. Register class configuration, and 2. Storage class configuration. Register class configuration involves a small amount of data and is mainly used for independent functional control; storage class configuration involves a large amount of data and is mainly used to store algorithm matrices and vectors. The configuration processes for register classes and storage classes are independent, and the corresponding file generation processes are also independent. However, both parts are essential in the ISP configuration (including DUT configuration and algorithm model configuration).

[0067] Furthermore, in one embodiment, generating the register configuration file of the design under test (DUT) based on the random configuration in the image signal processor (ISP) verification includes:

[0068] The correspondence between random configurations and strings in the ISP image signal processor verification is determined. The strings are obtained by parsing the register model in the TB image processor verification platform. Each string includes the address, name, and domain name of a register.

[0069] Based on the aforementioned correspondence, the mapping relationship between random values, addresses, register names, and register fields is obtained;

[0070] Based on the mapping relationship, the register configuration statement of the DUT corresponding to each random value is generated, and all the register configuration statements of the DUT are filled into the initial register configuration file of the DUT to obtain the register configuration file of the DUT.

[0071] Furthermore, in one embodiment, the register configuration file for generating the algorithm model based on the random configuration in the image signal processor (ISP) verification includes:

[0072] Based on the mapping relationship, the register configuration statement of the algorithm model corresponding to each random value is generated, and the register configuration statements of all algorithm models are filled into the initial register configuration file of the algorithm model to obtain the register configuration file of the algorithm model.

[0073] In this embodiment, refer to Figure 3 , Figure 3 This is a schematic diagram of the register configuration file generation process in one embodiment of the image signal processor verification method of this application. Figure 3 As shown, random configurations are generated through random variables and random constraints. Random variables include, but are not limited to, image format, resolution, and endianness. Random constraints include, but are not limited to, the number of columns in a resolution corresponding to a specific image format being a multiple of 2 or 4. During TB's operation, all random constraints are combined to calculate the random value of the current random configuration.

[0074] After the randomization of TB ends, the script extracts the names and random values ​​of all random configurations based on the random configuration and generates a configuration form (cfg.list). The configuration form records the random configuration name and configuration value (i.e., random value), for example, "random configuration name - configuration value".

[0075] The script parses the register model in TB (the register model is generated at the beginning of the simulation by calling a general script parsing file), obtains the address, register name and register domain name, and encodes them into strings, such as "address-register name-register domain name", and generates a register list (reg.list).

[0076] The script uses classification algorithms (including but not limited to tree-like classification after regular expression matching) to match and classify the strings of registers in the register form and the strings of random configuration names in the file configuration form, and constructs a mapping relationship between addresses, registers (including register names and register domain names) and random values.

[0077] Based on the mapping relationship, the script generates register configuration statements used in the TB (e.g., reg.register.register_field.write(configuration_value)). For all random configurations, the generated register configuration statements of all DUTs are uniformly filled into the initial register configuration file of the DUT, generating the final register configuration file of the DUT used in the simulation by the TB.

[0078] Based on the mapping relationship, the script generates configuration statements for the algorithm model (e.g., whm.address.configuration value). For all random configurations, it generates register configuration statements for all algorithm models, which are then uniformly filled into the initial register configuration file of the algorithm model, generating the register configuration file of the algorithm model used in the final simulation.

[0079] In this embodiment, configuration forms and register forms are constructed based on the randomized configuration parameter information. Correlation is established through a classification algorithm to build a unified mapping relationship. The register configuration file of the DUT and the register configuration file of the algorithm model are automatically generated through the unified mapping relationship, and the configuration information is automatically synchronized to ensure the accuracy of the configuration.

[0080] Furthermore, in one embodiment, generating the stored configuration file based on the random configuration in the image signal processor (ISP) verification includes:

[0081] The transformation matrix or vector of the algorithm model is updated based on the random configuration in the image signal processor (ISP) verification; the default storage configuration file is updated based on the new transformation matrix or vector to obtain the storage configuration file.

[0082] In this embodiment, refer to Figure 4 , Figure 4 This is a schematic diagram illustrating the generation and configuration process of a storage configuration file in one embodiment of the image signal processor verification method of this application.

[0083] The mem configuration file (i.e., the storage configuration file) mainly records the algorithm matrices or vectors of various ISP algorithms. When the ISP is working, it transforms the input image information according to the algorithm matrices or vectors (for example, transforming the image grayscale from 16-bit linear to 24-bit non-linear using inverse gamma transform (gamma_be)). Figure 4 In the process of generating the storage configuration file, the following steps are taken:

[0084] 1) The default storage configuration file is generated by the ISP based on the information stored in the storage space under the default configuration. The format of the default storage configuration file is: address-data. Each algorithm's transformation matrix will be assigned an address range, such as the range 32'h0 ~ 32'h1000, and the data stored within the corresponding range is the transformation matrix of the corresponding algorithm.

[0085] 2) In different scenarios, based on different random configurations, the script identifies the algorithm name (e.g., the string for inverse gamma transform) and the corresponding algorithm parameters (e.g., the power of the inverse gamma transform expansion), selects different transformation matrices, and transforms the algorithm matrices or vectors stored in the default storage configuration file. For example, in inverse gamma transform, when extending from 16-bit linear to 24-bit nonlinear, different power expansions can be selected to simulate the inverse gamma curve.

[0086] 3) Based on the transformed algorithm matrix or vector obtained in 2), update the default storage configuration file and generate a new storage configuration file.

[0087] 4) The backdoor in TB loads the new storage configuration file into the DUT and completes the configuration process.

[0088] 5) The algorithm model loads the new storage configuration file and completes the configuration of the algorithm model.

[0089] The configuration processes in 4) and 5) are performed automatically after the storage configuration file is loaded.

[0090] By automatically generating input image files and configuration files for the DUT and algorithm model, the configuration and interface input files in ISP verification are decoupled, reducing the complexity of ISP verification.

[0091] One advantage of this method is that random configuration automatically generates DUT configuration files, algorithm model configuration files, and storage configuration files through unified parsing and processing, ensuring consistency between DUT and algorithm model configurations in the process. Compared to generating DUT and algorithm model configurations separately, this method offers better consistency and reduces errors and wasted time due to file mismatches during verification.

[0092] The configuration files for automatically generated DUTs and algorithm models differ from those generated manually:

[0093] 1) In image processor simulation, there are many combinations of configuration parameters. The configuration files for the Device Under Test (DUT) and the algorithm model are separate input files in the simulation. Each configuration parameter requires an independent configuration file for the DUT and a configuration file for the algorithm model. Manual maintenance requires maintaining a large number of configuration files, which is prone to errors.

[0094] 2) In terms of process, for a new configuration, the configuration files of the DUT and algorithm model need to be manually modified first. For variables with dependencies (such as the image format and resolution column count mentioned above), they need to be checked in advance. However, during the automatic generation process, TB will check whether the variables meet the constraints. If they do not meet the constraints, it will report an error in time to reduce the probability of errors.

[0095] 3) In SoC simulation, when the image processor and other subsystems are being integrated, the upstream and downstream personnel only know the current configuration when manually maintaining the configuration files of the DUT and algorithm model, but do not understand the meaning of these configuration files, which increases the usage cost for upstream and downstream personnel when integrating with the image processor.

[0096] Through the embodiments of this application, the algorithm matrix of the algorithm model in ISP verification is dynamically configured. This allows for the generation of algorithm models with different distributions based on random configurations, enabling optimization of algorithm parameters to a certain extent and improving image quality in different scenarios. For example, in specific scenarios, such as low-light scenes, adjusting the dynamic range-related configuration parameters and algorithm matrix can improve image contrast. In this method, numerous randomizations can generate many configurations. For the same image, after simulation, the image quality is evaluated using the simulation output.

[0097] Step S20: Configure the DUT according to the DUT's register configuration file and storage configuration file;

[0098] In this embodiment, the registers in the DUT are configured according to the DUT's register configuration file; then, they are loaded into storage according to the storage configuration file.

[0099] Step S30: Configure the algorithm model according to the register configuration file and storage configuration file of the algorithm model;

[0100] In this embodiment, the registers in the algorithm model are configured according to the register configuration file of the algorithm model; then, according to the storage configuration file, the algorithm model automatically selects the corresponding parameters based on the address and data when it runs.

[0101] Step S40: Process the random image based on the configured DUT to obtain real data;

[0102] Step S50: Process the random image based on the configured algorithm model to obtain the desired data;

[0103] Step S60: Based on the comparison results between the actual data and the expected data, the image signal processor verification result is obtained.

[0104] In this embodiment, the configured DUT and the configured algorithm model process the input random image respectively to obtain real data and expected data. The real data and expected data are stored byte-by-byte in queues within the TB (Data Base), and then the two queues are compared byte-by-byte. If a byte comparison error occurs, the image signal processor verification is deemed to have failed; if all bytes pass the comparison, the image signal processor verification is deemed to have succeeded.

[0105] Furthermore, in one embodiment, obtaining the image signal processor verification result based on the comparison between the actual data and the expected data includes:

[0106] If the actual data matches the expected data, the image signal processor verification result is "verification passed".

[0107] If the actual data does not match the expected data, the image signal processor verification result will be verification failure.

[0108] In this embodiment, the actual data and the expected data can be compared byte by byte, or the hash values ​​of the actual data and the expected data can be calculated separately and compared. If the actual data and the expected data have the same bytes or the same hash value, then the actual data and the expected data are determined to be consistent, and the image signal processor verification result is determined to be verification passed; otherwise, the image signal processor verification result is verification failed.

[0109] Furthermore, in one embodiment, after obtaining the image signal processor verification result based on the comparison result between the real data and the expected data, the method further includes:

[0110] If the image signal processor verification result is a verification failure, the cause is determined based on the simulation log; if the cause is that the random constraints do not meet the ISP design requirements, the random constraints are modified.

[0111] In this embodiment, if the image signal processor verification result is a verification failure, a comparison is made between the relevant random results in the simulation log and the relevant descriptions in the design document. For example, if the current randomization is 28 bits, but the document describes a maximum support of only 24 bits, then the 28-bit random result generated by this constraint does not meet the ISP design requirements, leading to the final data comparison failure. This problem is caused by the random constraint. Therefore, the relevant random constraint statements in the randomization component are modified, such as changing the 28-bit constraint [0:28] to [0:24]. It is easy to understand that after modifying the random constraint, steps S10 to S60 are re-executed.

[0112] If the problem isn't a constraint error, you need to combine simulation logs and waveform analysis to pinpoint the issue and resimulate. For example, check the descriptions of the error statements in the log; use waveform tools to open the waveform and trace the erroneous signal.

[0113] In this embodiment, random input image data and configuration files are generated based on random configuration, which reduces the coupling between configuration and interface input in ISP verification; the random configuration is uniformly parsed and processed, ensuring the consistency of DUT and algorithm model configuration in the process, reducing the probability of errors in ISP verification; through dynamic configuration of the ISP algorithm, the algorithm parameters can be optimized by combining simulation and randomness.

[0114] Secondly, embodiments of this application also provide an image signal processor verification device.

[0115] In one embodiment, reference is made to Figure 5 , Figure 5 This is a functional module diagram of an embodiment of the image signal processor verification device of this application. Figure 5 As shown, the image signal processor verification device includes:

[0116] The generation module 10 is used to generate random images, register configuration files of the design under test (DUT), register configuration files of the algorithm model, and storage configuration files based on the random configuration in the image signal processor (ISP) verification. The random values ​​of the random configuration are generated based on random constraints.

[0117] Configuration model 20 is used to configure the DUT according to the DUT's register configuration file and storage configuration file; and to configure the algorithm model according to the algorithm model's register configuration file and storage configuration file.

[0118] The first processing module 30 is used to process random images based on the configured DUT to obtain real data;

[0119] The second processing module 40 is used to process the random image based on the configured algorithm model to obtain the desired data;

[0120] The verification module 50 is used to obtain the verification result of the image signal processor based on the comparison result between the real data and the expected data.

[0121] Furthermore, in one embodiment, the generation module 10 is used for:

[0122] The correspondence between random configurations and strings in the ISP image signal processor verification is determined. The strings are obtained by parsing the register model in the TB image processor verification platform. Each string includes the address, name, and domain name of a register.

[0123] Based on the aforementioned correspondence, the mapping relationship between random values, addresses, register names, and register fields is obtained;

[0124] Based on the mapping relationship, the register configuration statement of the DUT corresponding to each random value is generated, and all the register configuration statements of the DUT are filled into the initial register configuration file of the DUT to obtain the register configuration file of the DUT.

[0125] Furthermore, in one embodiment, the generation module 10 is used for:

[0126] Based on the mapping relationship, the register configuration statement of the algorithm model corresponding to each random value is generated, and the register configuration statements of all algorithm models are filled into the initial register configuration file of the algorithm model to obtain the register configuration file of the algorithm model.

[0127] Furthermore, in one embodiment, the generation module 10 is used for:

[0128] The transformation matrix or vector of the algorithm model is updated based on the random configuration in the image signal processor (ISP) verification.

[0129] The default storage configuration file is updated based on the new transformation matrix or vector to obtain the storage configuration file.

[0130] Furthermore, in one embodiment, the verification module 50 is used for:

[0131] If the actual data matches the expected data, the image signal processor verification result is "verification passed".

[0132] If the actual data does not match the expected data, the image signal processor verification result will be verification failure.

[0133] Furthermore, in one embodiment, the image signal processor verification device further includes a correction module, used for:

[0134] If the image signal processor verification result is verification failure, the cause is determined based on the simulation log;

[0135] If the reason is that the random constraints do not meet the ISP design requirements, then modify the random constraints.

[0136] Furthermore, in one embodiment, the random configuration includes one or more of image format, image resolution, and storage type.

[0137] The functions of each module in the above-mentioned image signal processor verification device correspond to the steps in the above-mentioned image signal processor verification method embodiment, and their functions and implementation processes will not be described in detail here.

[0138] Thirdly, embodiments of this application provide an image signal processor verification device, which can be a personal computer (PC), laptop computer, server, or other device with data processing capabilities.

[0139] Reference Figure 6 , Figure 6 This is a schematic diagram of the hardware structure of the image signal processor verification device involved in the embodiments of this application. In the embodiments of this application, the image signal processor verification device may include a processor, a memory, a communication interface, and a communication bus.

[0140] The communication bus can be of any type and is used to interconnect the processor, memory, and communication interface.

[0141] The communication interface includes input / output (I / O) interfaces, physical interfaces, and logical interfaces used for interconnecting devices within the image signal processor verification device, as well as interfaces used for interconnecting the image signal processor verification device with other devices (such as other computing devices or user equipment). Physical interfaces can be Ethernet interfaces, fiber optic interfaces, ATM interfaces, etc.; user equipment can be displays, keyboards, etc.

[0142] Memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0143] The processor can be a general-purpose processor, which can call the image signal processor verification program stored in the memory and execute the image signal processor verification method provided in the embodiments of this application. For example, the general-purpose processor can be a central processing unit (CPU). The method executed when the image signal processor verification program is called can be referred to in the various embodiments of the image signal processor verification method of this application, and will not be repeated here.

[0144] Those skilled in the art will understand that Figure 6 The hardware structure shown does not constitute a limitation of this application and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0145] Fourthly, embodiments of this application also provide a computer-readable storage medium.

[0146] The present application provides a computer-readable storage medium storing an image signal processor verification program, wherein when the image signal processor verification program is executed by a processor, it implements the steps of the image signal processor verification method described above.

[0147] The method implemented when the image signal processor verification program is executed can be referred to in various embodiments of the image signal processor verification method of this application, and will not be repeated here.

[0148] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0149] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0150] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0151] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0152] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0153] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0154] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An image signal processor verification method, characterized by, The image signal processor verification method comprises: random images, a register configuration file of a design under test (DUT), a register configuration file of an algorithm model, and a storage configuration file are generated according to random configurations in image signal processor (ISP) verification, wherein random values of the random configurations are generated based on random constraints; the DUT is configured according to the register configuration file and the storage configuration file of the DUT; the algorithm model is configured according to the register configuration file and the storage configuration file of the algorithm model; real data is obtained by processing the random images based on the configured DUT; expected data is obtained by processing the random images based on the configured algorithm model; an ISP verification result is obtained according to a comparison result of the real data and the expected data; the register configuration file of the DUT is generated according to the random configurations in the ISP verification, which comprises: a correspondence between random configurations in ISP verification and strings is determined, the strings are obtained by analyzing a register model in a TB image processor verification platform, wherein one string comprises an address of a register, a register name, and a register domain name; a mapping relationship between random values, addresses, register names, and register domains is obtained according to the correspondence; register configuration statements of the DUT corresponding to each random value are generated according to the mapping relationship; all register configuration statements of the DUT are filled into an initial register configuration file of the DUT to obtain the register configuration file of the DUT; the register configuration file of the algorithm model is generated according to the random configurations in the ISP verification, which comprises: register configuration statements of the algorithm model corresponding to each random value are generated according to the mapping relationship; all register configuration statements of the algorithm model are filled into an initial register configuration file of the algorithm model to obtain the register configuration file of the algorithm model; the storage configuration file is generated according to the random configurations in the ISP verification, which comprises: a transformation matrix or a vector of the algorithm model is updated according to the random configurations in the ISP verification; a default storage configuration file is updated based on the new transformation matrix or the vector to obtain the storage configuration file.

2. The image signal processor verification method of claim 1, wherein, the ISP verification result is obtained according to the comparison result of the real data and the expected data, which comprises: if the real data is consistent with the expected data, the ISP verification result is passed; if the real data is inconsistent with the expected data, the ISP verification result fails.

3. The image signal processor verification method of claim 2, wherein, after the ISP verification result is obtained according to the comparison result of the real data and the expected data, the method further comprises: if the ISP verification result fails, a reason is determined based on a simulation log; if the reason is that the random constraints do not meet the ISP design requirements, the random constraints are modified.

4. The image signal processor verification method of any one of claims 1 to 3, wherein, The random configurations comprise one or more of an image format, an image resolution, and a storage type.

5. An image signal processor verification apparatus characterized by comprising: The image signal processor verification device comprises: The generating module is configured to generate a random image, a register configuration file of a design under test (DUT), a register configuration file of an algorithm model, and a storage configuration file according to random configurations in image signal processor (ISP) verification, wherein random values of the random configurations are generated based on random constraints; The configuration model is configured to configure the DUT according to the register configuration file and the storage configuration file of the DUT, and configure the algorithm model according to the register configuration file and the storage configuration file of the algorithm model; The first processing module is configured to process the random image based on the configured DUT to obtain real data; The second processing module is configured to process the random image based on the configured algorithm model to obtain expected data; The verification module is configured to obtain an image signal processor verification result according to a comparison result of the real data and the expected data. The generating module is configured to: determine a correspondence between random configurations in ISP image signal processor verification and strings, the strings being obtained by analyzing a register model in a TB image processor verification platform, wherein one string includes an address of a register, a register name, and a register domain name; obtain a mapping relationship among random values, addresses, register names, and register domains according to the correspondence; and generate register configuration statements of the DUT corresponding to each random value, fill the register configuration statements of all the DUTs into an initial register configuration file of the DUT, and obtain the register configuration file of the DUT; generate register configuration statements of the algorithm model corresponding to each random value according to the mapping relationship, fill the register configuration statements of all the algorithm models into an initial register configuration file of the algorithm model, and obtain the register configuration file of the algorithm model; update a transformation matrix or a vector of the algorithm model according to the random configurations in the ISP verification, and update a default storage configuration file based on the new transformation matrix or the vector to obtain the storage configuration file.

6. An image signal processor verification apparatus, characterized by, The image signal processor verification device includes a processor, a memory, and an image signal processor verification program stored on the memory and executable by the processor, wherein the image signal processor verification program, when executed by the processor, implements the steps of the image signal processor verification method according to any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores an image signal processor verification program, wherein the image signal processor verification program, when executed by a processor, implements the steps of the image signal processor verification method according to any one of claims 1 to 4.

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