Bottom-up clock tree synthesis method and system

Abstract

The application discloses a bottom-up clock tree synthesis method and system, which comprises inserting a logic unit to be inserted between a driver and a load connected to the driver; judging whether a clock tree with the inserted logic unit meets a design rule constraint, if yes, the insertion of the logic unit between the driver and the load connected to the driver is completed, if not, taking the inserted logic unit as a new load and starting from the insertion of the logic unit to be inserted between the driver and the load connected to the driver. When the logic unit is inserted, the logic unit is inserted layer by layer from bottom to top, and leaf nodes which need to share clock paths as much as possible due to clock skew, common control critical path and other reasons can be divided under the same sub-tree as early as possible in the bottom layer, so that the power consumption and the chip area occupied are reduced, the problem that the common path of the leaf nodes of the critical path is too short is avoided, and the clock tree synthesis situation of a buffer, an inverter or a mixture of both can be applied.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuit design technology, specifically to a bottom-up clock tree synthesis method and system. Background Technology

[0002] Clock tree synthesis is a key step in the physical design of digital integrated circuits. Its core lies in building a clock tree with low clock skew, clock path latency, and small power consumption area, so that the clock signal can reach timing components such as registers as synchronously as possible, thereby meeting the timing requirements of digital integrated circuits.

[0003] In related technologies, traditional clock tree synthesis uses a top-down approach, adding logic units to determine the basic structure of the clock tree, and then implementing or finely adjusting it based on factors such as Design Rule Constraints (DRC), clock path delay, or clock skew. The advantage of this approach is that it quickly breaks down large, complex circuits into smaller, simpler circuits for parallel processing, thereby reducing runtime and facilitating the selection of strategies for adding logic units. This logic is used in both the construction of classic H-trees and the more flexible skew groups. However, building a clock tree by adding logic units sequentially from top to bottom incurs significant area and power consumption costs, and can easily lead to excessively short common paths for leaf nodes on critical paths. Summary of the Invention

[0004] The main technical problem solved by this invention is that when constructing a clock tree sequentially from top to bottom, the area and power consumption required are too large, and the common path of the leaf nodes of the critical path is too short.

[0005] According to a first aspect, one embodiment of this application provides a bottom-up clock tree synthesis method applied to a clock tree, the clock tree including multiple drivers, each driver having a corresponding load connected to it. When the logic unit type inserted during clock tree synthesis is a buffer, for each driver, the bottom-up clock tree synthesis method includes:

[0006] A first utility layer buffer is inserted between the driver and the load connected thereto.

[0007] Determine whether the clock tree after adding the first utility layer buffer satisfies the design rule constraints;

[0008] If yes, then the insertion of a logic unit between the driver and its connected load is completed; if no, then the buffer in the currently added first utility layer buffer is taken as the new load, and execution begins from the step of inserting the first utility layer buffer between the driver and its connected load.

[0009] When the plurality of drivers form an upper driver level and a lower driver level, the upper driver level is used to drive the lower driver level. When inserting the logic unit into the plurality of drivers, the logic unit is inserted layer by layer along a first direction between each driver and its connected load. The first direction is opposite to the direction in which the clock signal of the clock tree propagates from the root node to the leaf node.

[0010] In some embodiments, inserting a first utility layer buffer between the driver and its connected load includes:

[0011] Based on the design rule constraints, a first number of buffers to be inserted between the driver and its connected load is determined;

[0012] Based on the first quantity, a first clustering algorithm is used to group the load connected to the driver to generate a first grouping family corresponding to the first quantity;

[0013] One buffer is inserted for each of the first group families to form a first auxiliary layer buffer, wherein the load in each of the first group families is connected to a buffer in the same first group family;

[0014] For each first group, a second number of buffers to be inserted between the load in each first group and the buffer connected to the load in the first group is determined based on the design rule constraints.

[0015] Based on the second quantity, a second clustering algorithm is used to group the load in each of the first grouping families to generate a second grouping family corresponding to the second quantity;

[0016] One of the buffers is inserted in each of the second groupings to form the first utility layer buffer, wherein the load in each of the second groupings is connected to the corresponding buffer in the first utility layer buffer;

[0017] Timing calculations are performed based on the first auxiliary layer buffer to adjust the specific insertion position of the inverter in the first practical layer inverter and the selected standard component library type;

[0018] Delete the first auxiliary layer buffer, and connect the buffer in the first utility layer buffer to which the deleted buffer in the first auxiliary layer buffer was connected to the driver.

[0019] According to the second aspect, one embodiment of this application provides a bottom-up clock tree synthesis method applied to a clock tree, the clock tree including multiple drivers, each driver having a corresponding load connected to it. When the logic unit type inserted during clock tree synthesis is an inverter, for each driver, the bottom-up clock tree synthesis method includes:

[0020] A first utility layer inverter and a second utility layer inverter are inserted between the driver and the load connected thereto, wherein the first utility layer inverter is close to the load connected to the driver.

[0021] Determine whether the clock tree after adding the first utility layer inverter and the second utility layer inverter meets the design rule constraints;

[0022] If yes, then the insertion of a logic unit between the driver and its connected load is completed; if no, then the inverter in the currently added second utility layer inverter is taken as the new load, and execution begins from the step of inserting the first utility layer inverter and the second utility layer inverter between the driver and its connected load.

[0023] When the plurality of drivers form an upper driver level and a lower driver level, the upper driver level is used to drive the lower driver level. When inserting the logic unit into the plurality of drivers, the logic unit is inserted layer by layer along a first direction between each driver and its connected load. The upper driver level is used to drive the lower driver level. The first direction is opposite to the direction in which the clock signal of the clock tree propagates from the root node to the leaf node.

[0024] In some embodiments, inserting a first utility layer inverter and a second utility layer inverter between the driver and the load connected thereto includes:

[0025] Based on the design rule constraints, a third number of inverters to be inserted between the driver and its connected load is determined;

[0026] Based on the third quantity, the first clustering algorithm is used to group the load connected to the driver to generate a third grouping family corresponding to the third quantity;

[0027] For each of the third group of cells, one inverter is inserted to form a first auxiliary layer inverter, wherein the load in each of the third group of cells is connected to the corresponding inverter in the first auxiliary layer inverter;

[0028] Insert one inverter into the output of each inverter in the first auxiliary layer inverter to form a second auxiliary layer inverter, and perform a timing calculation.

[0029] Delete the inverters in the second auxiliary layer inverter one by one, and insert the first practical layer inverter between the first auxiliary layer inverter and the load;

[0030] Timing calculations are performed based on the first auxiliary layer inverter to adjust the specific insertion position of the inverter in the first practical layer inverter and the selected standard component library type;

[0031] Remove the first auxiliary layer inverter and connect the inverter in the first utility layer inverter to the driver;

[0032] Using the inverters in the first practical layer inverter as new loads, a fourth number of inverters to be inserted between the driver and the new loads connected thereto is determined based on the design rule constraints.

[0033] Based on the fourth quantity, the first clustering algorithm is used to group all inverters of the first practical layer inverter to generate a fourth grouping family corresponding to the fourth quantity;

[0034] For each of the fourth group of inverters, one inverter is inserted to form a third auxiliary layer inverter, wherein a new load connected to the driver in each of the fourth group of inverters is connected to the corresponding inverter in the third auxiliary layer inverter;

[0035] An inverter is inserted into the output of each inverter in the third auxiliary layer inverter to form a fourth auxiliary layer inverter;

[0036] Timing calculations are performed based on the third auxiliary layer inverter and the fourth auxiliary layer inverter to determine the insertion position and driving capability of the second inverter to be inserted when the inverter is inserted between the load in each of the fourth group and the inverter connected to the load.

[0037] Based on the insertion position and driving capability of the second inverter to be inserted, the inverter is inserted between the inverter of the fourth auxiliary layer inverter and its connected load to form the second practical layer inverter;

[0038] Remove the third auxiliary layer inverter and the fourth auxiliary layer inverter, and connect the inverter in the second utility layer inverter to the driver.

[0039] According to a third aspect, one embodiment of this application provides a bottom-up clock tree synthesis method applied to a clock tree, the clock tree including multiple drivers, each driver having a corresponding load connected to it. When the logic unit type inserted during clock tree synthesis is a buffer and an inverter, for each driver, the bottom-up clock tree synthesis method includes:

[0040] An auxiliary layer buffer is inserted between the driver and the load connected thereto, and a second utility layer buffer is inserted between the driver and the auxiliary layer buffer based on the auxiliary layer buffer;

[0041] Acquire and record the maximum first delay value and the first identification parameter among the first delay values ​​of the signal output from each buffer in the auxiliary layer buffer to the corresponding load, the first identification parameter being used to restore the second practical layer buffer;

[0042] Delete the auxiliary layer buffer and the second utility layer buffer;

[0043] An auxiliary layer inverter is inserted between the driver and the load connected thereto, and a third practical layer inverter and a fourth practical layer inverter are inserted between the driver and the auxiliary layer inverter based on the auxiliary layer inverter, wherein the auxiliary layer inverter includes a plurality of auxiliary layer inverters;

[0044] Acquire and record the maximum second delay value among the second delay values ​​of the signal output from each of the auxiliary layer inverters closest to the driver to the corresponding load;

[0045] When the maximum second delay value is less than the maximum first delay value, the auxiliary layer inverter is deleted, and it is determined whether the clock tree after adding the third and fourth utility layer inverters meets the design rule constraints. If yes, the third and fourth utility layer inverters are retained, and the insertion of a logic unit between the driver and its connected load is completed. If no, the utility layer inverters are retained, and the currently added utility layer inverters are used as new loads. The process begins from the step of inserting a utility layer logic unit between the driver and its connected load.

[0046] When the maximum second delay value is greater than or equal to the maximum first delay value, delete the auxiliary layer inverter, the third practical layer inverter, and the fourth practical layer inverter;

[0047] Based on the first identification parameter, the second utility layer buffer is restored between the driver and its connected load, and it is determined whether the clock tree to which the second utility layer buffer is currently added meets the design rule constraints. If yes, the utility layer buffer is retained, and the insertion of logic units between the driver and its connected load is completed. If no, the second utility layer buffer is retained, and the currently added second utility layer buffer is used as a new load, and the process starts from the step of inserting the auxiliary layer buffer between the driver and its connected load.

[0048] When the plurality of drivers form an upper driver level and a lower driver level, the upper driver level is used to drive the lower driver level. When inserting the logic unit into the plurality of drivers, the logic unit is inserted layer by layer along a first direction between each driver and its connected load. The upper driver level is used to drive the lower driver level. The first direction is opposite to the direction in which the clock signal of the clock tree propagates from the root node to the leaf node.

[0049] In some embodiments, inserting an auxiliary layer buffer between the driver and the load connected thereto, and inserting a second utility layer buffer between the driver and the auxiliary layer buffer based on the auxiliary layer buffer, includes:

[0050] Based on the design rule constraints, a fifth number of buffers to be inserted between the driver and its connected load is determined;

[0051] Based on the fifth quantity, the first clustering algorithm is used to group the load connected to the driver to generate a fifth grouping family corresponding to the fifth quantity;

[0052] For each of the fifth group families, one of the buffers is inserted to form a second auxiliary layer buffer, wherein the load in each of the fifth group families is connected to the buffer in the same fifth group family;

[0053] The second utility layer buffer is inserted between the second auxiliary layer buffer and the load. After the second utility layer buffer is inserted, timing calculations are performed based on the second auxiliary layer buffer to adjust the specific insertion position of the buffer in the second utility layer buffer and the selected standard component library type.

[0054] In some embodiments, the plurality of auxiliary layer inverters includes a fifth auxiliary layer inverter, a sixth auxiliary layer inverter, a seventh auxiliary layer inverter, and an eighth auxiliary layer inverter. The step of inserting auxiliary layer inverters between the driver and the load connected thereto, and inserting a third utility layer inverter and a fourth utility layer inverter between the driver and the auxiliary layer inverters based on the auxiliary layer inverters, includes:

[0055] Based on the design rule constraints, a seventh number of inverters to be inserted between the driver and its connected load is determined;

[0056] Based on the seventh quantity, the first clustering algorithm is used to group the load connected to the driver to generate a seventh grouping family corresponding to the seventh quantity;

[0057] For each of the seventh group, one inverter is inserted to form the fifth auxiliary layer inverter, wherein in each of the seventh group, the load in each of the seventh group is connected to the corresponding inverter in the fifth auxiliary layer inverter;

[0058] An inverter is inserted into the output of each inverter in the fifth auxiliary layer inverter to form the sixth auxiliary layer inverter;

[0059] The sixth auxiliary layer inverters are deleted one by one. A third practical layer inverter is inserted between the fifth auxiliary layer inverter and the load. After inserting the third practical layer inverter, timing calculations are performed based on the fifth auxiliary layer inverter to adjust the specific insertion position of the inverter in the third practical layer inverter and the selected standard component library type.

[0060] Remove each inverter in the fifth auxiliary layer inverter and connect the inverters in the third utility layer inverter to the driver;

[0061] Using the inverters in the third practical layer inverter as new loads, determine the eighth number of inverters to be inserted between the driver and the new load connected thereto, based on the design rule constraints.

[0062] Based on the eighth number, the first clustering algorithm is used to group all inverters of the third practical layer inverter to generate an eighth grouping family corresponding to the eighth number;

[0063] For each of the eighth group, one inverter is inserted to form the seventh auxiliary layer inverter, wherein a new load connected to the driver in each of the eighth group is connected to the corresponding inverter in the seventh auxiliary layer inverter;

[0064] An inverter is inserted into the output of each inverter in the seventh auxiliary layer inverter to form the eighth auxiliary layer inverter;

[0065] Timing calculations are performed based on the seventh auxiliary layer inverter and the eighth auxiliary layer inverter to determine the insertion position and driving capability of the second inverter to be inserted when the inverter is inserted between the load in each of the eighth group and the inverter connected to the load.

[0066] Based on the insertion position and driving capability of the second inverter to be inserted, the inverter is inserted between the eighth auxiliary layer inverter and its connected load to form the fourth practical layer inverter;

[0067] Remove the seventh auxiliary layer inverter and the eighth auxiliary layer inverter, and connect the inverter in the fourth utility layer inverter to the driver.

[0068] In some embodiments, the first identification parameter includes at least the standard component library type, insertion position, insertion direction, and connected load of each buffer in the second utility layer buffer, wherein the standard component library type includes buffer driving capability.

[0069] In some embodiments, the design rule constraints include that the output signal transition time of each driver's input pin is less than or equal to the maximum signal transition time defined in the timing design rules of the clock tree, the total load capacitance driven by each driver's output pin is less than or equal to the maximum load capacitance value defined in the timing design rules of the clock tree, and the number of loads connected to each driver's output pin is less than or equal to the maximum fan-out number defined in the timing design rules of the clock tree. If the driver is a non-port driver, at least one timing estimation is performed. The result of the timing estimation is used to efficiently determine the identifier parameter with the smallest delay value in the logic unit, so that the specific insertion position of the logic unit and the selected standard component library type are adjusted according to the identifier parameter with the smallest delay value, and timing calculations are performed.

[0070] According to a fourth aspect, one embodiment of this application provides a bottom-up clock tree synthesis system, comprising: a memory and a processor, wherein the memory is used to store a computer program, and the computer program, when executed by the processor, implements the bottom-up clock tree synthesis method as described above.

[0071] According to the bottom-up clock tree synthesis method and system of the above embodiments, when inserting logic units between the driver and its connected load during clock tree synthesis, the logic units are inserted layer by layer from bottom to top. When there are upper-level driver stages and lower-level driver stages, the logic units are also inserted layer by layer from bottom to top. This allows leaf nodes that need to share clock paths as much as possible due to clock skew, common control critical paths, etc., to be divided into the same subtree at the bottom layer as early as possible. This reduces power consumption and chip area, avoids the problem of the common path of leaf nodes of the critical path being too short, and is applicable to clock tree synthesis using buffers, inverters, or a combination of both. Attached Figure Description

[0072] Figure 1 A logic block diagram of the bottom-up clock tree synthesis method;

[0073] Figure 2 A flowchart illustrating the insertion of a logic unit when the logic unit is a buffer, according to one embodiment;

[0074] Figure 3A clock tree without a buffer in one embodiment;

[0075] Figure 4 A clock tree that completes the first iteration when adding a buffer in one embodiment;

[0076] Figure 5 A clock tree that completes the second iteration when adding a buffer in one embodiment;

[0077] Figure 6 A clock tree that completes its third iteration when adding a buffer in one embodiment;

[0078] Figure 7 A flowchart of one iteration when adding a buffer in one embodiment;

[0079] Figure 8 A clock tree without a buffer, as in another embodiment;

[0080] Figure 9 A clock tree with a first auxiliary layer buffer added as one embodiment;

[0081] Figure 10 For one embodiment, a clock tree is used to add a first auxiliary layer buffer and begin adding a first utility layer buffer;

[0082] Figure 11 Adding a first auxiliary layer buffer and completing the clock tree for adding a first utility layer buffer in one embodiment;

[0083] Figure 12 One embodiment of deleting the clock tree of the first auxiliary layer buffer;

[0084] Figure 13 A flowchart illustrating the insertion of a logic unit when the logic unit is an inverter, as described in one embodiment.

[0085] Figure 14 A flowchart of one iteration of adding a first utility layer inverter and a second utility layer inverter in one embodiment;

[0086] Figure 15 This is a clock tree in one embodiment without the addition of a first utility layer inverter and a second utility layer inverter;

[0087] Figure 16 A clock tree with a first auxiliary layer inverter added in one embodiment;

[0088] Figure 17 A clock tree with a first auxiliary layer inverter and a second auxiliary layer inverter in one embodiment;

[0089] Figure 18One embodiment involves deleting the clock tree of one inverter in the second auxiliary layer inverter;

[0090] Figure 19 A clock tree with a first utility layer inverter is added at the beginning of one embodiment;

[0091] Figure 20 Add a complete clock tree to the first utility layer inverter of one embodiment;

[0092] Figure 21 A clock tree for deleting the first auxiliary layer inverter in one embodiment;

[0093] Figure 22 A clock tree with a third auxiliary layer inverter in one embodiment;

[0094] Figure 23 A clock tree with a fourth auxiliary layer inverter added at the beginning of one embodiment;

[0095] Figure 24 A clock tree with a second utility layer inverter added at the beginning of one embodiment;

[0096] Figure 25 Add a complete clock tree to the fourth auxiliary layer inverter and the second utility layer inverter in one embodiment;

[0097] Figure 26 A clock tree for deleting the third auxiliary layer inverter and the fourth auxiliary layer inverter in one embodiment;

[0098] Figure 27 A flowchart illustrating the insertion of logic units when the logic units are buffers and inverters, as one embodiment;

[0099] Figure 28 This is a block diagram of a clock tree structure according to one embodiment. Detailed Implementation

[0100] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0101] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0102] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0103] like Figure 1 The diagram shown is a flowchart of the bottom-up clock tree synthesis method. Figure 1 As can be seen, during clock tree iteration, the logic unit can be a buffer, an inverter, or both. When the logic unit is a buffer, a buffer is added according to the buffer addition logic during each iteration. When the logic unit is an inverter, an inverter is added according to the inverter addition logic during each iteration. When the logic unit is both a buffer and an inverter, a buffer is added according to the buffer addition logic during each iteration. Then, the maximum first delay value and the first identifier parameter are recorded, and the added buffer is deleted. After deletion, an inverter is added according to the inverter addition logic, and the maximum second delay value is recorded. The comparison between the maximum first delay value and the maximum second delay value determines whether to retain the newly added inverter or delete the newly added inverter and restore the previously added buffer. The maximum first delay value, the maximum second delay value, and the first identifier parameter are described in detail in the following embodiments.

[0104] During clock tree synthesis, the type of logic unit inserted can be pre-written into the standard cell library configuration information. This configuration information can have three scenarios: First, the standard cell library configuration specifies that the inserted logic unit is a buffer, meaning only buffers can be inserted during clock tree synthesis. Second, the standard cell library configuration specifies that the inserted logic unit is an inverter, meaning only inverters can be inserted during clock tree synthesis. Third, the standard cell library configuration specifies that the inserted logic unit is both an inverter and a buffer, meaning both inverters and buffers can be inserted during clock tree synthesis. Different clock tree synthesis methods are required for different standard cell library configurations.

[0105] In some embodiments, this application provides a bottom-up clock tree synthesis method applied to a clock tree, which includes multiple drivers, each driver having a corresponding load connected to it. When the logic unit type inserted during clock tree synthesis is a buffer, for each driver and its connected load, such as... Figure 2 As shown, the bottom-up clock tree synthesis method may include the following steps:

[0106] S11. Insert a first utility layer buffer between the driver and the load connected thereto;

[0107] S12. Determine whether the clock tree after adding the first utility layer buffer meets the design rule constraints.

[0108] In some embodiments, after inserting a first utility layer buffer between the driver and its connected load, it is necessary to determine whether the clock tree after adding the first utility layer buffer meets the design rule constraints. If yes (i.e., the clock tree after adding the first utility layer buffer meets the design rule constraints), then the insertion of logic units between the driver and its connected load is completed; in other words, it is sufficient to insert one first utility layer buffer between the driver and its connected load. If no (i.e., the clock tree after adding the first utility layer buffer does not meet the design rule constraints), then the buffer in the currently added first utility layer buffer is used as a new load, and execution starts from step S11; in other words, after inserting one first utility layer buffer between the driver and its connected load, it is necessary to continue adding first utility layer buffers as new loads until the clock tree after adding the first utility layer buffer meets the design rule constraints.

[0109] It should be noted that the driver can also be called a circuit driver, and the load can also be called a circuit load.

[0110] In some embodiments, step S11 includes the following steps:

[0111] S111. Determine the first number of buffers to be inserted between the driver and its connected load based on design rule constraints;

[0112] S112. Based on the first quantity, the load connected to the driver is grouped using a first clustering algorithm to generate a first grouping family corresponding to the first quantity;

[0113] S113. Insert a buffer for each first group to form a first auxiliary layer buffer, wherein the load in each first group is connected to the buffer in the same first group.

[0114] S114. For each first group, determine the second number of buffers to be inserted between the load in each first group and the buffer connected to the load in the first group based on the design rule constraints.

[0115] S115. Based on the second quantity, a second clustering algorithm is used to group the load in each first grouping group to generate a second grouping group corresponding to the second quantity;

[0116] S116. Insert a buffer in each second group to form a first utility layer buffer, wherein the load in each second group is connected to the corresponding buffer in the first utility layer buffer.

[0117] S117. Perform timing calculations based on the first auxiliary layer buffer to adjust the specific insertion position of the inverter in the first practical layer inverter and the selected standard component library type.

[0118] S118. Delete each buffer in the first auxiliary layer buffer and connect the buffers in the first utility layer buffer to which the deleted buffers in the first auxiliary layer buffer are connected to the driver.

[0119] like Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown, when inserting a buffer between a driver and its connected load, the buffer is added layer by layer, with the direction of adding the buffer starting from the load connected to the driver and gradually moving closer to the driver. Figure 4 In the first iteration, a, b, c, and d represent the buffers added. Figure 5 In the first iteration, a, b, c, and d represent buffers added in the first iteration; e, f, g, and h represent buffers added in the second iteration. Figure 6 In the first iteration, a, b, c, and d represent buffers added in the first iteration; e, f, g, and h represent buffers added in the second iteration; and l and m represent buffers added in the third iteration.

[0120] In some embodiments, such as Figure 7 , Figure 8 , Figure 9As shown, when adding the first practical layer buffer, the number of buffers to be inserted between the driver and its connected load is estimated according to design rule constraints, i.e., a first number. After the first number is determined, a first clustering algorithm is used to cluster the loads connected to the driver into first group clusters, where the number of first group clusters corresponds to the first number, meaning the number of first group clusters is equal to the first number. After grouping, one buffer is inserted into each first group cluster, and the loads in each first group cluster are connected to the buffers in the same first group cluster. The buffers inserted in each first group cluster are connected to the driver, and the first number of buffers inserted in the first instance form the first auxiliary layer buffer.

[0121] like Figure 10 , Figure 11 As shown, after the first auxiliary layer buffer is formed, a first practical layer buffer is inserted between the first auxiliary layer buffer and the load. After inserting the first practical layer buffer, timing calculations can be performed based on the first auxiliary layer buffer to obtain timing calculation results. Further, the specific insertion position of the buffers in the first practical layer buffer and the selected standard component library type are adjusted according to the timing calculation results. The selected standard component library type includes the buffer driving capability. In other words, after inserting the first practical layer buffer, the specific insertion position and buffer driving capability of the buffers in the first practical layer buffer need to be adjusted through timing calculations.

[0122] like Figure 12 As shown, after the first practical layer buffer is formed and the specific insertion position and driving capability of the buffers in the first practical layer buffer are adjusted, the buffers in the first auxiliary layer buffer are deleted. After the buffers in the first auxiliary layer buffer are deleted, the buffers in the first practical layer buffer are connected to the driver. At this point, a buffer layer is inserted between the driver and its connected load. When the clock tree meets the design rule constraints, the insertion of the buffer between the driver and its connected load is completed. Afterwards, the same process can be used to insert the first practical layer buffer between another driver that needs a buffer and its connected load. If the clock tree does not meet the design rule constraints, the buffer in the currently added first practical layer buffer is used as a new load, and the same process of inserting the first practical layer buffer between the driver and its connected load (the new load) is used again to insert the first practical layer buffer between the driver and its connected load (the new load) until the clock tree meets the design rule constraints. Afterwards, the same process can be used to insert the first practical layer buffer between another driver that needs a buffer and its connected load.

[0123] In some embodiments, when inserting the first utility layer buffer, for each first group, the number of buffers to be inserted in each first group is estimated by design rule constraints, i.e., the second number. When forming the first utility layer buffer, the number of buffers inserted is the sum of all the second numbers. After the second number corresponding to each first group is determined, a second clustering algorithm is used to group the loads in each first group to form second groups. In each first group, the number of second groups formed corresponds to the second number, where corresponding means that the second number corresponding to each first group and the number of second groups in each first group are equal. After the second number and the second groups are determined, a buffer is inserted in each second group to form the first utility layer buffer. Each load in the second group is connected to a buffer in the corresponding first utility layer buffer; that is, each buffer in the first utility layer buffer acts as a driver for the load in its respective second group.

[0124] It should be noted that when adjusting the specific insertion position and driving capability of the buffer in the first practical layer buffer, only the specific insertion position and driving capability of the buffer in the currently added first practical layer buffer are adjusted.

[0125] In some embodiments, this application provides a bottom-up clock tree synthesis method applied to a clock tree, which includes multiple drivers, each driver being connected to a load. For each driver and its connected load, logic units can be inserted between the driver and its connected load using the bottom-up clock tree synthesis method. For each driver and its connected load, such as... Figure 13 As shown, the bottom-up clock tree synthesis method may include the following steps:

[0126] S21. Insert a first utility layer inverter and a second utility layer inverter between the driver and the load connected thereto, wherein the first utility layer inverter is close to the load connected to the driver.

[0127] S22. Determine whether the clock tree after adding the first and second utility layer inverters meets the design rule constraints.

[0128] In some embodiments, when the type of logic unit is an inverter, after inserting two utility layer inverters (the first utility layer inverter and the second utility layer inverter) between the driver and its connected load, it is determined whether the clock tree meets the design rule constraints. If so (i.e., the clock tree after adding the first utility layer inverter and the second utility layer inverter meets the design rule constraints), the insertion of logic units between the driver and its connected load is completed; in other words, after inserting the currently added first utility layer inverter and the second utility layer inverter between the driver and its connected load, the addition of logic units between the driver and its connected load can be stopped. If not (i.e., the clock tree after adding the first and second utility layer inverters does not meet the design rule constraints), then the inverter in the currently added second utility layer inverter is treated as a new load, and execution restarts from step S20; in other words, after inserting the current first and second utility layer inverters between the driver and its connected load, it is necessary to continue adding the first and second utility layer inverters as new loads until the clock tree after adding the first and second utility layer inverters meets the design rule constraints.

[0129] In some embodiments, such as Figure 14 As shown, step S21 includes the following steps:

[0130] S210. Determine the third number of inverters to be inserted between the driver and its connected load based on design rule constraints;

[0131] S211. Based on the third quantity, the first clustering algorithm is used to group the load connected to the driver to generate a third grouping family corresponding to the third quantity;

[0132] S212. Insert an inverter for each third group to form a first auxiliary layer inverter, wherein the load in each third group is connected to the corresponding inverter in the first auxiliary layer inverter.

[0133] S213. Insert an inverter into the output terminal of each inverter in the first auxiliary layer inverter to form the second auxiliary layer inverter, and perform a timing calculation.

[0134] S214. Delete the inverters in the second auxiliary layer inverter one by one, and insert the first practical layer inverter between the first auxiliary layer inverter and the load.

[0135] S215. Perform timing calculations based on the inverter in the first auxiliary layer to adjust the specific insertion position of the inverter in the first practical layer and the type of the selected standard component library.

[0136] S216. Remove each inverter in the first auxiliary layer inverter and connect the inverters in the first utility layer inverter to the driver.

[0137] S217. Using the inverters in the first practical layer inverter as new loads, determine the fourth number of inverters to be inserted between the driver and the new loads connected to it based on design rule constraints.

[0138] S218. Based on the fourth quantity, the first clustering algorithm is used to group all inverters of the first practical layer inverter to generate a fourth grouping family corresponding to the fourth quantity.

[0139] S219. Insert an inverter for each fourth group to form a third auxiliary layer inverter, wherein a new load connected to the driver in each fourth group is connected to the corresponding inverter in the third auxiliary layer inverter.

[0140] S220. Insert an inverter into the output terminal of each inverter in the third auxiliary layer inverter to form a fourth auxiliary layer inverter.

[0141] S221. Based on the third auxiliary layer inverter and the fourth auxiliary layer inverter, perform timing calculations to determine the insertion position and driving capability of the second inverter to be inserted when an inverter is inserted between the load in each fourth group and the inverter connected to that load.

[0142] S222. Based on the insertion position and driving capability of the second inverter to be inserted, an inverter is inserted between the inverter of the fourth auxiliary layer inverter and its connected load to form a second practical layer inverter.

[0143] S223. Remove each inverter in the third auxiliary layer inverter and the fourth auxiliary layer inverter, and connect the inverter in the second utility layer inverter to the driver.

[0144] In some embodiments, such as Figure 15 , Figure 16 As shown, the number of inverters initially inserted between the driver and its connected loads is estimated based on design rule constraints; this is the third number. Once the third number is determined, the first clustering algorithm is used to group the loads connected to the driver, forming third group families, where the number of third group families equals the third number. One inverter is inserted into each third group family to form a first auxiliary layer inverter, and the loads in the third group family are connected to the inverters in their respective groups. Figure 17 As shown, to ensure correct circuit phase and calculate timing, an inverter is added to the output of each inverter in the first auxiliary layer inverter. After the second auxiliary layer inverter is formed, a timing calculation can be performed. Then, as... Figure 19 , Figure 20 As shown, one inverter in the second auxiliary layer inverter can be deleted, and the load connected to the deleted inverter can be connected to the inverter in the first auxiliary layer inverter that the deleted inverter was connected to. Then, a first utility layer inverter is inserted between the first auxiliary layer inverter and the connected load. Adding the first utility layer inverter can be understood as a replacement process, that is, each inverter in the second auxiliary layer inverter is replaced one by one to form the first utility layer inverter. When replacing the second auxiliary layer inverters one by one with the first utility layer inverters, the existence of the unreplaced second auxiliary layer inverters allows timing calculations to be performed based on the first auxiliary layer inverters.

[0145] When inserting the first practical layer inverters, the number of inverters to be inserted in each third group (referred to as the ninth number) is estimated using design rule constraints. The total number of inverters inserted when forming the first practical layer inverters is the sum of all ninth numbers. After determining the ninth number corresponding to each third group, a second clustering algorithm is used to group the loads in each third group to form ninth groups. The number of ninth groups formed within each third group corresponds to the ninth number; this correspondence means that when inserting the first practical layer inverters, the ninth number corresponding to each third group and the number of ninth groups are equal. Figure 20 As shown, after the ninth group and the ninth quantity are determined, an inverter is inserted in each ninth group to form a first practical layer inverter, wherein each load in the ninth group is connected to the inverter in the corresponding first practical layer inverter, that is, each inverter in the first practical layer inverter is used as a driver for the load in the ninth group.

[0146] After the first practical layer inverter is formed, timing calculations are performed based on the first auxiliary layer inverter to obtain timing calculation results. Based on the timing calculation results, the specific insertion position and inverter driving capability of each inverter in the first practical layer inverter are adjusted. The specific adjustment process will not be elaborated here.

[0147] Furthermore, such as Figure 21 As shown, after inserting the first practical layer inverter, each inverter in the first auxiliary layer inverter is deleted, and each inverter in the first practical layer inverter is connected to the load connected to the deleted inverter in the first auxiliary layer inverter. Then, the inverters in the first practical layer inverter are treated as new loads. Based on design rule constraints, a fourth number of inverters to be inserted between the driver and its connected load (the new load) is determined. After the fourth number is determined, a first clustering algorithm is used to group the inverters in the first practical layer inverter, forming a fourth group family, where the number of the fourth group families is equal to the fourth number.

[0148] Furthermore, such as Figure 22 As shown, an inverter is inserted in each fourth group, and the inverter in the first practical layer inverter in each fourth group is connected to the inverter inserted in its group. The inverters inserted in each fourth group form a third auxiliary layer inverter. Similarly, an inverter is inserted at the output of each inverter in the third auxiliary layer inverter to form a fourth auxiliary layer inverter.

[0149] like Figure 23 , Figure 24 and Figure 25 As shown, when inserting the second practical layer inverter, after inserting an inverter (one of the inverters in the fourth auxiliary layer) at the output of one of the inverters in the third auxiliary layer inverter, a timing calculation can be performed. This timing calculation determines the insertion position and drive capability between the inverter inserted at the output of that first inverter and the new load. The second clustering algorithm then determines the number of inverters inserted between the output of that first inverter and the new load. The specific process for determining the number of inverters can be referenced from the process described above for determining the number of inverters inserted when forming the first practical layer inverter. Further, based on the insertion position and drive capability, and the number of inverters inserted, an inverter is inserted between the inverter inserted at the output of that first inverter and the new load.

[0150] like Figure 23 , Figure 24 , Figure 25 and Figure 26 As shown, when inserting the second practical layer inverter, the number of inverters to be inserted in each fourth group (called the tenth number) is estimated using design rule constraints. The number of inverters inserted when forming the second practical layer inverter is the sum of all tenth numbers. After determining the tenth number corresponding to each fourth group, the load in each fourth group is grouped using a second clustering algorithm to form tenth groups. The number of tenth groups formed in each fourth group corresponds to the tenth number; this correspondence means that the tenth number and the number of tenth groups are equal when inserting the second practical layer inverter. After determining the tenth groups and the tenth number, one inverter is inserted in each tenth group to form the second practical layer inverter. In the tenth group, the inverter in the first practical layer inverter is connected to the inverter in the corresponding second practical layer inverter. That is, each inverter in the second practical layer inverter serves as the driver for the inverter in the first practical layer inverter in its respective tenth group. At this point, the first and second utility layer inverters are inserted between the driver and its connected load, and then each of the third and fourth auxiliary layer inverters is removed.

[0151] Further determine whether the clock tree meets the design rule constraints. If the clock tree meets the design rule constraints, an inverter is inserted between the driver and its connected load. If the clock tree does not meet the design rule constraints, the inverter in the currently added second utility layer inverter is used as the new load. The above process is used to insert the first utility layer inverter and the second utility layer inverter again between the driver and the new load (the inverter in the second utility layer inverter) until the clock tree meets the design rule constraints.

[0152] In some embodiments, this application provides a bottom-up clock tree synthesis method applied to a clock tree, which includes multiple drivers, each driver being connected to a load. When the logic unit type inserted during clock tree synthesis is a buffer and an inverter, for each driver and its connected load, such as... Figure 27 As shown, the bottom-up clock synthesis method includes the following steps:

[0153] S31. Insert an auxiliary layer buffer between the driver and the load connected thereto, and insert a second utility layer buffer between the driver and the auxiliary layer buffer based on the auxiliary layer buffer;

[0154] S32. Obtain and record the maximum first delay value and the first identification parameter among the first delay values ​​of the signal output from each buffer to the corresponding load in the auxiliary layer buffer. The first identification parameter is used to restore the second practical layer buffer.

[0155] S33, Delete the auxiliary layer buffer and the second utility layer buffer;

[0156] S34. An auxiliary layer inverter is inserted between the driver and the load connected thereto, and a third practical layer inverter and a fourth practical layer inverter are inserted between the driver and the auxiliary layer inverter based on the auxiliary layer inverter. The auxiliary layer inverter includes multiple auxiliary layer inverters.

[0157] S35. Acquire and record the maximum second delay value of the second delay value of the signal output from each inverter to the corresponding load in the auxiliary layer inverter closest to the driver among the multiple auxiliary layer inverters in the auxiliary layer;

[0158] S36. When the maximum second delay value is less than the maximum first delay value, delete multiple auxiliary layer inverters and determine whether the clock tree after adding the third and fourth practical layer inverters meets the design rule constraints. If yes, retain the third and fourth practical layer inverters and insert logic units between the driver and its connected load. If no, retain the practical layer inverters and treat the currently added practical layer inverters as new loads, and start executing from step S31.

[0159] S37. When the maximum second delay value is greater than or equal to the maximum first delay value, delete multiple auxiliary layer inverters, the third utility layer inverter and the fourth utility layer inverter, and restore the second utility layer buffer between the driver and its connected load based on the first identification parameter.

[0160] S38. Determine whether the clock tree after restoring the second utility layer buffer meets the design rule constraints. If yes, retain the second utility layer buffer and insert a logic unit between the driver and its connected load. If no, retain the second utility layer buffer and use the currently restored second utility layer buffer as the new load, and start executing from step S31.

[0161] In some embodiments, step S31 includes the following steps:

[0162] S311. Determine the fifth number of buffers to be inserted between the driver and its connected load based on design rule constraints;

[0163] S312. Based on the fifth quantity, the first clustering algorithm is used to group the load connected to the driver to generate a fifth grouping family corresponding to the fifth quantity;

[0164] S313. Insert a buffer for each fifth group to form a second auxiliary layer buffer, wherein the load in each fifth group is connected to the buffer in the same fifth group.

[0165] S314. Insert a second practical layer buffer between the second auxiliary layer buffer and the load. After inserting the second practical layer buffer, perform timing calculations based on the second auxiliary layer buffer to adjust the specific insertion position of the buffer in the second practical layer buffer and the selected standard component library type.

[0166] In some embodiments, the process of inserting the second utility layer buffer is the same as the process of inserting the first utility layer buffer described above, and will not be repeated here. When inserting the second utility layer buffer, after inserting the second utility layer buffer, the maximum first delay value and the first identification parameter are obtained and recorded among the first delay values ​​of the signal from each buffer in the second auxiliary layer buffer to the corresponding load output signal; the first identification parameter is used to restore the second utility layer buffer, that is, when the second utility layer buffer is deleted, the second utility layer buffer can be restored through the first identification parameter.

[0167] In some embodiments, after the second practical layer buffer is formed, timing calculations can be performed based on the second auxiliary layer buffer, and the specific insertion position of the buffer in the second practical layer buffer and the selected standard component library type can be adjusted according to the timing calculation results.

[0168] Furthermore, after recording the maximum first delay value and the first identification parameter, the second auxiliary layer buffer and the second utility layer buffer are removed, and an inverter is further inserted between the driver and the load connected thereto.

[0169] In some embodiments, the plurality of auxiliary layer inverters include a fifth auxiliary layer inverter, a sixth auxiliary layer inverter, a seventh auxiliary layer inverter, and an eighth auxiliary layer inverter, and step S34 includes the following steps:

[0170] S340. Determine the seventh number of inverters to be inserted between the driver and its connected load based on design rule constraints;

[0171] S341. Based on the seventh quantity, the first clustering algorithm is used to group the load connected to the driver to generate a seventh group family corresponding to the seventh quantity;

[0172] S342. Insert an inverter for each seventh group to form a fifth auxiliary layer inverter, wherein in each seventh group, the load in each seventh group is connected to the corresponding inverter in the fifth auxiliary layer inverter.

[0173] S343. Insert an inverter into the output terminal of each inverter in the fifth auxiliary layer inverter to form the sixth auxiliary layer inverter;

[0174] S344. Delete the sixth auxiliary layer inverters one by one, insert the third practical layer inverter between the fifth auxiliary layer inverter and the load, and perform timing calculations based on the fifth auxiliary layer inverter after inserting the third practical layer inverter to adjust the specific insertion position of the inverter in the third practical layer inverter and the selected standard component library type.

[0175] S345. Remove each inverter in the fifth auxiliary layer inverter and connect the inverters in the third utility layer inverter to the driver.

[0176] S346. Using the inverters in the third practical layer inverter as new loads, determine the eighth number of inverters to be inserted between the driver and the new loads connected to it based on design rule constraints.

[0177] S347. Based on the eighth quantity, the first clustering algorithm is used to group all inverters of the third practical layer inverter to generate an eighth grouping family corresponding to the eighth quantity;

[0178] S348. Insert an inverter for each eighth group to form a seventh auxiliary layer inverter, wherein a new load connected to the driver in each eighth group is connected to the corresponding inverter in the seventh auxiliary layer inverter.

[0179] S349. Insert an inverter into the output terminal of each inverter in the seventh auxiliary layer inverter to form the eighth auxiliary layer inverter;

[0180] S350. Based on the seventh auxiliary layer inverter and the eighth auxiliary layer inverter, perform timing calculations to determine the insertion position and driving capability of the second inverter to be inserted when an inverter is inserted between the load in each eighth group and the inverter connected to that load.

[0181] S351. Based on the insertion position and driving capability of the second inverter to be inserted, an inverter is inserted between the eighth auxiliary layer inverter and its connected load to form a fourth practical layer inverter.

[0182] S352, Remove the seventh auxiliary layer inverter and the eighth auxiliary layer inverter, and connect the inverter in the fourth utility layer inverter to the driver.

[0183] In some embodiments, when inserting the inverter, a third and fourth practical layer inverter need to be inserted based on the auxiliary layer inverter. The auxiliary layer inverter includes multiple auxiliary layer inverters, including a fifth, sixth, seventh, and eighth auxiliary layer inverter. When inserting the third practical layer inverter, the fifth and sixth auxiliary layer inverters also need to be inserted. The formation process of the third practical layer inverter can refer to the formation process of the first practical layer inverter described above. Here, the third practical layer inverter is considered as the first practical layer inverter, the fifth auxiliary layer inverter is considered as the first auxiliary layer inverter, and the sixth auxiliary layer inverter is considered as the second auxiliary layer inverter. The specific process will not be elaborated further here.

[0184] When inserting the fourth practical layer inverter, the seventh and eighth auxiliary layer inverters also need to be inserted. The formation process of the fourth practical layer inverter can be referred to the formation process of the second practical layer inverter described above. Here, the fourth practical layer inverter can be regarded as the second practical layer inverter, the seventh auxiliary layer inverter as the third auxiliary layer inverter, and the eighth auxiliary layer inverter as the fourth auxiliary layer inverter. The specific process will not be elaborated further here. After inserting the fourth practical layer inverter, the seventh auxiliary layer inverter, and the eighth auxiliary layer inverter, obtain the maximum second delay value among the second delay values ​​of the signal output from each inverter in the seventh auxiliary layer inverter to the corresponding load. Then, delete the seventh and eighth auxiliary layer inverters.

[0185] In some embodiments, the first identification parameter includes at least the insertion position, insertion direction, and initial leaf node to which each buffer in the second utility layer buffer is connected. Provided the insertion position of each buffer in the second utility layer buffer can be determined, the first identification parameter may also include other parameters, which can be determined by those skilled in the art according to the actual situation, and are not limited in detail here.

[0186] In some embodiments, design rule constraints may include: the output signal transition time of each driver's output pin being less than or equal to the maximum signal transition time defined in the timing design rules of the clock tree; the total load capacitance driven by each driver's output pin being less than or equal to the maximum load capacitance value defined in the timing design rules of the clock tree; and the number of loads connected to each driver's output pin being less than or equal to the maximum fan-out number defined in the timing design rules of the clock tree. If the driver is a non-port driver, at least one timing estimation is performed. The result of the timing estimation is used to efficiently determine the identifier parameter with the smallest delay value in the logic unit, so that the specific insertion position of the logic unit and the selected standard component library type are adjusted according to the identifier parameter with the smallest delay value, and timing calculations are performed. The maximum signal transition time, the maximum load capacitance value defined in the timing design rules of the clock tree, and the maximum fan-out number defined in the timing design rules of the clock tree are determined according to the specific chip design process and will not be elaborated on here. The output signal transition time refers to the time required for the output signal of the output pin to change from a first logic level to a second logic level. For example, the time required for the output signal of the output pin to change from a high-level signal to a low-level signal. The maximum load capacitance value refers to the upper limit set on the maximum total downstream capacitive load that any driver on the clock tree is allowed to drive. The maximum fan-out refers to the maximum number of inputs of subsequent logic units that the driver's output is allowed to directly connect to.

[0187] When the logic unit is a buffer, if the driver is a non-port driver, after inserting the first practical layer buffer and before deleting the first auxiliary layer buffer, at least one timing estimation is performed from the output pin of the first auxiliary layer buffer to the load (the load connected to the buffer in the first auxiliary layer buffer). The timing estimation result is used to efficiently determine the identifier parameter with the smallest delay value in the first practical layer buffer. The specific insertion position of the buffer in the first practical layer buffer and the selected standard component library type are further adjusted according to the identifier parameter with the smallest delay value. Then, timing calculation is performed between the non-port driver and its connected load to obtain the timing calculation result, so as to ensure accurate timing after the clock tree synthesis is completed.

[0188] When the logic unit is an inverter, if the driver is a non-port driver, after deleting the second auxiliary layer inverter and inserting the first practical layer inverter, and before deleting the first auxiliary layer inverter, at least one timing estimation is performed from the output pin of the first auxiliary layer inverter to the load (the load connected to the inverter in the first auxiliary layer inverter). The timing estimation result is used to efficiently determine the identifier parameter with the minimum delay value in the first practical layer inverter. Further, based on the identifier parameter with the minimum delay value, the specific insertion position of the inverter in the first practical layer inverter and the selected standard component library type are adjusted. Then, timing calculations are performed between the non-port driver and its connected load to obtain the timing calculation result, ensuring... To ensure accurate timing after clock tree synthesis, after inserting the second practical layer inverter and before deleting the third and fourth auxiliary layer inverters, at least one timing estimation is performed from the output pin of the third auxiliary layer inverter to the load (the load connected to the inverter in the third auxiliary layer inverter). The timing estimation result is used to efficiently determine the identifier parameter with the smallest delay value in the second practical layer inverter. Further, the specific insertion position of the inverter in the second practical layer inverter and the selected standard component library type are adjusted according to the identifier parameter with the smallest delay value. Then, timing calculations are performed between the non-port driver and its connected load to obtain the timing calculation result, so as to ensure accurate timing after clock tree synthesis.

[0189] When the logic unit is a buffer and an inverter, if the driver is a non-port driver, after inserting the second practical layer buffer and before deleting the second auxiliary layer buffer, at least one timing estimation is performed from the output pin of the second auxiliary layer buffer to the load (the load connected to the buffer in the second auxiliary layer buffer). The timing estimation result is used to efficiently determine the identifier parameter with the smallest delay value in the second practical layer buffer. Further, the specific insertion position of the buffer in the second practical layer buffer and the selected standard component library type are adjusted according to the identifier parameter with the smallest delay value. Then, timing calculation is performed between the non-port driver and its connected load to obtain the timing calculation result, so as to ensure accurate timing after the clock tree synthesis is completed.

[0190] After deleting the sixth auxiliary layer inverter and inserting the third practical layer inverter, but before deleting the fifth auxiliary layer inverter, at least one timing estimate is performed from the output pin of the fifth auxiliary layer inverter to the load (the load connected to the inverter in the fifth auxiliary layer inverter). The timing estimate result is used to efficiently determine the identifier parameter with the minimum delay value in the third practical layer inverter. Further, based on the identifier parameter with the minimum delay value, the specific insertion position of the inverter in the third practical layer inverter and the selected standard component library type are adjusted. Then, timing calculations are performed between the non-port driver and its connected load to obtain the timing calculation result, ensuring timing accuracy after clock tree synthesis. Indeed; after inserting the fourth practical layer inverter and before deleting the seventh and eighth auxiliary layer inverters, at least one timing estimation is performed from the output pin of the seventh auxiliary layer inverter to the load (the load connected to the inverter in the seventh auxiliary layer inverter). The timing estimation result is used to efficiently determine the identifier parameter with the smallest delay value in the fourth practical layer inverter. Further, the specific insertion position of the inverter in the fourth practical layer inverter and the selected standard component library type are adjusted according to the identifier parameter with the smallest delay value. Then, timing calculations are performed between the non-port driver and its connected load to obtain the timing calculation result, so as to ensure the timing accuracy after the clock tree synthesis is completed.

[0191] In some embodiments, each driver can be connected to multiple loads. For example, three, five, seven, ten, etc., without further limitation.

[0192] In some embodiments, when multiple drivers form an upper driver level and a lower driver level, the upper driver level is used to drive the lower driver level. When multiple drivers are inserted into logic units, along the first direction ( Figure 28 The first direction is the opposite of the direction in which the clock signal of the clock tree propagates from the root node to the leaf node. Logic units are inserted layer by layer between each driver and its connected load; the upper driver level is used to drive the lower driver level; the first direction is the opposite of the direction in which the clock signal of the clock tree propagates from the root node to the leaf node.

[0193] like Figure 28 As shown, the clock tree has an upper-level driver stage and a lower-level driver stage, wherein the lower-level driver stage is... Figure 28The system consists of multiplexers (MUX) and integrated clock gates (ICGs). The upper-level driver stage is the clock tree root node, which drives the multiplexers, clock gates, and loads connected to the clock tree root node. Multiplexers drive their connected loads, and ICGs drive their connected loads. When inserting logic units, processing begins at the lower-level driver stage, followed by the upper-level driver stage. At the lower-level driver stage, logic units are inserted starting from the circuit connection between the multiplexer and its connected load, then from the circuit connection between the timing gate and its connected load. At the upper-level driver stage, logic units are inserted starting from the circuit connection between the clock tree root node and the multiplexer, then from the circuit connection between the clock tree root node and the clock gate, and finally from the circuit connection between the clock tree and the clock leaf nodes. Therefore, when inserting a logic unit, processing can start from the circuit connection (net) where the leaf node is located. After processing all the circuit connections of the subtree where each element is located, the circuit connection where the input terminal of the element is located is processed, until the circuit connection connected to the root node is processed.

[0194] In some embodiments, there may be multiple upper-level driver stages. One scenario is that the lowest-level driver stage is connected to a driver stage that forms an upper-level driver stage (the second-level driver stage), and the upper-level driver stage of the second-level driver stage is connected to another driver stage (the third-level driver stage), and so on. In this case, when inserting a logic unit, the process begins with the driver in the lower-level driver stage and its connected load. After each driver in the lower-level driver stage is processed, the process starts again with inserting a logic unit between each driver in the second-level driver stage and its corresponding connected load, and so on, until the clock tree root node is reached. Another scenario involves two levels of driver stages, such as... Figure 28 As shown, in this case, you can refer to the following: Figure 28 The process of inserting logic units into the clock tree shown will not be described in detail here.

[0195] When the inserted logic unit is a buffer, the above process is used to insert buffers into multiple drivers; when the inserted logic unit is an inverter, the above process is used to insert inverters into multiple drivers; when the inserted logic unit is both an inverter and a buffer, the above process is used to insert inverters into multiple drivers.

[0196] In some embodiments, if the driver is a non-port driver, timing estimation is performed at least once. The result of the timing estimation is used to efficiently determine the identifier parameter with the smallest delay value in the logic unit, so that the specific insertion position of the logic unit and the selected standard component library type are adjusted according to the identifier parameter with the smallest delay value, and timing calculation is performed.

[0197] In summary, when inserting logic units, the type of the logic unit can be either a buffer or an inverter. When inserting logic units between a driver and its connected load, the insertion proceeds from bottom to top, layer by layer. Similarly, when there are upper and lower driver levels in the clock tree, the insertion also proceeds from bottom to top. Therefore, leaf nodes that need to share clock paths as much as possible due to clock skew, shared critical paths, etc., can be grouped into the same subtree at the bottom layer as early as possible. This reduces power consumption and chip area, avoids the problem of excessively short common paths for leaf nodes in critical paths, and makes clustering less susceptible to slight movement of leaf nodes. Furthermore, it is applicable to three cases: inserted logic units are buffers, inserted logic units are inverters, and inserted logic units are both buffers and inverters.

[0198] In some embodiments, this application also provides a bottom-up clock tree synthesis system, including a memory and a processor. The memory stores a computer program, which, when executed by the processor, implements the bottom-up clock tree synthesis method as described above. Specific details are provided in the embodiment of the bottom-up clock tree synthesis method, and will not be elaborated further here.

[0199] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A bottom-up clock tree synthesis method, applied to clock trees, characterized in that, The clock tree includes multiple drivers, each connected to a corresponding load. When the logic unit inserted during clock tree synthesis is a buffer, the bottom-up clock tree synthesis method for each driver includes: A first utility layer buffer is inserted between the driver and the load connected thereto. Determine whether the clock tree after adding the first utility layer buffer satisfies the design rule constraints; If yes, then the insertion of a logic unit between the driver and its connected load is completed; if no, then the buffer in the currently added first utility layer buffer is taken as the new load, and execution begins from the step of inserting the first utility layer buffer between the driver and its connected load. When the plurality of drivers form an upper driver level and a lower driver level, the upper driver level is used to drive the lower driver level. When inserting the logic unit into the plurality of drivers, the logic unit is inserted layer by layer along a first direction between each driver and its connected load. The first direction is opposite to the direction in which the clock signal of the clock tree propagates from the root node to the leaf node. The design rule constraints include: the output signal transition time of each driver's output pin is less than or equal to the maximum signal transition time defined in the timing design rules of the clock tree; the total load capacitance driven by each driver's output pin is less than or equal to the maximum load capacitance value defined in the timing design rules of the clock tree; and the number of loads connected to each driver's output pin is less than or equal to the maximum fan-out number defined in the timing design rules of the clock tree. If the driver is a non-port driver, at least one timing estimation is performed. The result of the timing estimation is used to efficiently determine the identifier parameter with the smallest delay value in the logic unit, so that the specific insertion position of the logic unit and the selected standard component library type are adjusted according to the identifier parameter with the smallest delay value, and timing calculations are performed.

2. The bottom-up clock tree synthesis method as described in claim 1, characterized in that, The insertion of a first utility layer buffer between the driver and its connected load includes: Based on the design rule constraints, a first number of buffers to be inserted between the driver and its connected load is determined; Based on the first quantity, a first clustering algorithm is used to group the load connected to the driver to generate a first grouping family corresponding to the first quantity; One buffer is inserted for each of the first group families to form a first auxiliary layer buffer, wherein the load in each of the first group families is connected to a buffer in the same first group family; For each first group, a second number of buffers to be inserted between the load in each first group and the buffer connected to the load in the first group is determined based on the design rule constraints. Based on the second quantity, a second clustering algorithm is used to group the load in each of the first grouping families to generate a second grouping family corresponding to the second quantity; One of the buffers is inserted in each of the second groupings to form the first utility layer buffer, wherein the load in each of the second groupings is connected to the corresponding buffer in the first utility layer buffer; Timing calculations are performed based on the first auxiliary layer buffer to adjust the specific insertion position of the buffer in the first practical layer buffer and the selected standard component library type; Delete the first auxiliary layer buffer, and connect the buffer in the first utility layer buffer to which the deleted buffer in the first auxiliary layer buffer was connected to the driver.

3. A bottom-up clock tree synthesis method, applied to clock trees, characterized in that, The clock tree includes multiple drivers, each connected to a corresponding load. When the logic unit inserted during clock tree synthesis is an inverter, the bottom-up clock tree synthesis method for each driver includes: A first utility layer inverter and a second utility layer inverter are inserted between the driver and the load connected thereto, wherein the first utility layer inverter is close to the load connected to the driver. Determine whether the clock tree after adding the first utility layer inverter and the second utility layer inverter meets the design rule constraints; If yes, then the insertion of a logic unit between the driver and its connected load is completed; if no, then the inverter in the currently added second utility layer inverter is taken as the new load, and execution begins from the step of inserting the first utility layer inverter and the second utility layer inverter between the driver and its connected load. When the plurality of drivers form an upper driver level and a lower driver level, the upper driver level is used to drive the lower driver level. When inserting the logic unit into the plurality of drivers, the logic unit is inserted layer by layer along a first direction between each driver and its connected load. The upper driver level is used to drive the lower driver level. The first direction is opposite to the direction in which the clock signal of the clock tree propagates from the root node to the leaf node. The design rule constraints include: the output signal transition time of each driver's output pin is less than or equal to the maximum signal transition time defined in the timing design rules of the clock tree; the total load capacitance driven by each driver's output pin is less than or equal to the maximum load capacitance value defined in the timing design rules of the clock tree; and the number of loads connected to each driver's output pin is less than or equal to the maximum fan-out number defined in the timing design rules of the clock tree. If the driver is a non-port driver, at least one timing estimation is performed. The result of the timing estimation is used to efficiently determine the identifier parameter with the smallest delay value in the logic unit, so that the specific insertion position of the logic unit and the selected standard component library type are adjusted according to the identifier parameter with the smallest delay value, and timing calculations are performed.

4. The bottom-up clock tree synthesis method as described in claim 3, characterized in that, The insertion of a first utility layer inverter and a second utility layer inverter between the driver and the load connected thereto includes: Based on the design rule constraints, a third number of inverters to be inserted between the driver and its connected load is determined; Based on the third quantity, the first clustering algorithm is used to group the load connected to the driver to generate a third grouping family corresponding to the third quantity; For each of the third group of cells, one inverter is inserted to form a first auxiliary layer inverter, wherein the load in each of the third group of cells is connected to the corresponding inverter in the first auxiliary layer inverter; Insert one inverter into the output of each inverter in the first auxiliary layer inverter to form a second auxiliary layer inverter, and perform a timing calculation. Delete the inverters in the second auxiliary layer inverter one by one, and insert the first practical layer inverter between the first auxiliary layer inverter and the load; Timing calculations are performed based on the first auxiliary layer inverter to adjust the specific insertion position of the inverter in the first practical layer inverter and the selected standard component library type; Remove the first auxiliary layer inverter and connect the inverter in the first utility layer inverter to the driver; Using the inverters in the first practical layer inverter as new loads, a fourth number of inverters to be inserted between the driver and the new loads connected thereto is determined based on the design rule constraints. Based on the fourth quantity, the first clustering algorithm is used to group all inverters of the first practical layer inverter to generate a fourth grouping family corresponding to the fourth quantity; For each of the fourth group of inverters, one inverter is inserted to form a third auxiliary layer inverter, wherein a new load connected to the driver in each of the fourth group of inverters is connected to the corresponding inverter in the third auxiliary layer inverter; One inverter is inserted into the output terminal of each inverter in the third auxiliary layer inverter to form a fourth auxiliary layer inverter; Timing calculations are performed based on the third auxiliary layer inverter and the fourth auxiliary layer inverter to determine the insertion position and driving capability of the second inverter to be inserted when the inverter is inserted between the load in each of the fourth group and the inverter connected to the load. Based on the insertion position and driving capability of the second inverter to be inserted, the inverter is inserted between the inverter of the fourth auxiliary layer inverter and its connected load to form the second practical layer inverter; Remove the third auxiliary layer inverter and the fourth auxiliary layer inverter, and connect the inverter in the second utility layer inverter to the driver.

5. A bottom-up clock tree synthesis method, applied to clock trees, characterized in that, The clock tree includes multiple drivers, each connected to a corresponding load. When the logic unit type inserted during clock tree synthesis is a buffer and an inverter, the bottom-up clock tree synthesis method for each driver includes: An auxiliary layer buffer is inserted between the driver and the load connected thereto, and a second utility layer buffer is inserted between the driver and the auxiliary layer buffer based on the auxiliary layer buffer; Acquire and record the maximum first delay value and the first identification parameter among the first delay values ​​of the signal output from each buffer in the auxiliary layer buffer to the corresponding load, the first identification parameter being used to restore the second practical layer buffer; Delete the auxiliary layer buffer and the second utility layer buffer; An auxiliary layer inverter is inserted between the driver and the load connected thereto, and a third practical layer inverter and a fourth practical layer inverter are inserted between the driver and the auxiliary layer inverter based on the auxiliary layer inverter, wherein the auxiliary layer inverter includes a plurality of auxiliary layer inverters; Acquire and record the maximum second delay value among the second delay values ​​of the signal output from each of the auxiliary layer inverters closest to the driver to the corresponding load; When the maximum second delay value is less than the maximum first delay value, the auxiliary layer inverter is deleted, and it is determined whether the clock tree after adding the third and fourth utility layer inverters meets the design rule constraints. If yes, the third and fourth utility layer inverters are retained, and a logic unit is inserted between the driver and its connected load. If no, the utility layer inverter is retained, and the currently added utility layer inverter is used as a new load, and execution begins from the step of inserting the auxiliary layer buffer between the driver and its connected load. When the maximum second delay value is greater than or equal to the maximum first delay value, delete the auxiliary layer inverter, the third practical layer inverter, and the fourth practical layer inverter; Based on the first identification parameter, the second utility layer buffer is restored between the driver and its connected load, and it is determined whether the clock tree to which the second utility layer buffer is currently added meets the design rule constraints. If yes, the utility layer buffer is retained, and the insertion of logic units between the driver and its connected load is completed. If no, the second utility layer buffer is retained, and the currently added second utility layer buffer is used as a new load, and the process starts from the step of inserting the auxiliary layer buffer between the driver and its connected load. When the plurality of drivers form an upper driver level and a lower driver level, the upper driver level is used to drive the lower driver level. When inserting the logic unit into the plurality of drivers, the logic unit is inserted layer by layer along a first direction between each driver and its connected load. The upper driver level is used to drive the lower driver level. The first direction is opposite to the direction in which the clock signal of the clock tree propagates from the root node to the leaf node. The design rule constraints include: the output signal transition time of each driver's output pin is less than or equal to the maximum signal transition time defined in the timing design rules of the clock tree; the total load capacitance driven by each driver's output pin is less than or equal to the maximum load capacitance value defined in the timing design rules of the clock tree; and the number of loads connected to each driver's output pin is less than or equal to the maximum fan-out number defined in the timing design rules of the clock tree. If the driver is a non-port driver, at least one timing estimation is performed. The result of the timing estimation is used to efficiently determine the identifier parameter with the smallest delay value in the logic unit, so that the specific insertion position of the logic unit and the selected standard component library type are adjusted according to the identifier parameter with the smallest delay value, and timing calculations are performed.

6. The bottom-up clock tree synthesis method as described in claim 5, characterized in that, The step of inserting an auxiliary layer buffer between the driver and the load connected thereto, and inserting a second utility layer buffer between the driver and the auxiliary layer buffer based on the auxiliary layer buffer, includes: Based on the design rule constraints, a fifth number of buffers to be inserted between the driver and its connected load is determined; Based on the fifth quantity, the first clustering algorithm is used to group the load connected to the driver to generate a fifth grouping family corresponding to the fifth quantity; For each of the fifth group families, one of the buffers is inserted to form a second auxiliary layer buffer, wherein the load in each of the fifth group families is connected to the buffer in the same fifth group family; The second utility layer buffer is inserted between the second auxiliary layer buffer and the load. After the second utility layer buffer is inserted, timing calculations are performed based on the second auxiliary layer buffer to adjust the specific insertion position of the buffer in the second utility layer buffer and the selected standard component library type.

7. The bottom-up clock tree synthesis method as described in claim 6, characterized in that, The plurality of auxiliary layer inverters includes a fifth auxiliary layer inverter, a sixth auxiliary layer inverter, a seventh auxiliary layer inverter, and an eighth auxiliary layer inverter. The step of inserting auxiliary layer inverters between the driver and its connected load, and inserting a third practical layer inverter and a fourth practical layer inverter between the driver and the auxiliary layer inverters based on the auxiliary layer inverters, includes: Based on the design rule constraints, a seventh number of inverters to be inserted between the driver and its connected load is determined; Based on the seventh quantity, the first clustering algorithm is used to group the load connected to the driver to generate a seventh grouping family corresponding to the seventh quantity; For each of the seventh group, one inverter is inserted to form the fifth auxiliary layer inverter, wherein the load in each of the seventh group is connected to the corresponding inverter in the fifth auxiliary layer inverter; An inverter is inserted into the output of each inverter in the fifth auxiliary layer inverter to form the sixth auxiliary layer inverter; The sixth auxiliary layer inverters are deleted one by one. A third practical layer inverter is inserted between the fifth auxiliary layer inverter and the load. After inserting the third practical layer inverter, timing calculations are performed based on the fifth auxiliary layer inverter to adjust the specific insertion position of the inverter in the third practical layer inverter and the selected standard component library type. Remove each inverter in the fifth auxiliary layer inverter and connect the inverters in the third utility layer inverter to the driver; Using the inverters in the third practical layer inverter as new loads, determine the eighth number of inverters to be inserted between the driver and the new load connected thereto, based on the design rule constraints. Based on the eighth number, the first clustering algorithm is used to group all inverters of the third practical layer inverter to generate an eighth grouping family corresponding to the eighth number; For each of the eighth group, one inverter is inserted to form the seventh auxiliary layer inverter, wherein a new load connected to the driver in each of the eighth group is connected to the corresponding inverter in the seventh auxiliary layer inverter; An inverter is inserted into the output of each inverter in the seventh auxiliary layer inverter to form the eighth auxiliary layer inverter; Timing calculations are performed based on the seventh auxiliary layer inverter and the eighth auxiliary layer inverter to determine the insertion position and driving capability of the second inverter to be inserted when the inverter is inserted between the load in each of the eighth group and the inverter connected to the load. Based on the insertion position and driving capability of the second inverter to be inserted, the inverter is inserted between the eighth auxiliary layer inverter and its connected load to form the fourth practical layer inverter; Remove the seventh auxiliary layer inverter and the eighth auxiliary layer inverter, and connect the inverter in the fourth utility layer inverter to the driver.

8. The bottom-up clock tree synthesis method as described in claim 5, characterized in that, The first identification parameter includes at least the standard component library type, insertion position, insertion direction, and connected load of each buffer in the second utility layer buffer, wherein the standard component library type includes buffer driving capability.

9. A bottom-up clock tree synthesis system, characterized in that, include: A memory and a processor, the memory being used to store a computer program that, when executed by the processor, implements the bottom-up clock tree synthesis method as described in any one of claims 1-8.

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