Prediction method and device of voltage frequency curve, equipment and storage medium

Abstract

The invention discloses a voltage frequency curve prediction method and device, equipment and a storage medium, and relates to the technical field of chips. The method comprises the steps of obtaining design information of a chip design file; obtaining process information of different process corners; and predicting a voltage frequency curve of the chip design file according to the design information and the process information. Optionally, the design information is a design matrix, the process information is a process matrix, and the product result of the design matrix and the process matrix is directly used for modeling the voltage frequency curve so as to predict the voltage frequency curve. According to the invention, the prediction efficiency of the voltage frequency curve is improved, complex circuit simulation is not needed, and the prediction cost is also reduced. Furthermore, according to the invention, the pre-silicon calibration after the silicon and the pre-silicon prediction after the silicon are adopted, so that the pre-silicon and post-silicon consistency is embodied.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method, apparatus, device and storage medium for predicting voltage-frequency curves. Background Technology

[0002] In chip design, it is usually necessary to obtain the frequency corresponding to each voltage point within the chip's operating voltage range, so as to achieve adaptive adjustment of the chip's voltage or frequency and reduce the chip's power consumption.

[0003] In related technologies, the frequencies corresponding to various voltage points within the operating voltage range of a chip, i.e., the voltage-frequency curve, are typically determined using circuit simulation. Specifically, circuit simulation is performed based on the circuit model designed in the chip design documents. By setting different power supply voltages, the operating frequencies of the chip under various voltages are simulated, thereby obtaining the voltage-frequency curve.

[0004] However, the circuit simulation method in related technologies is relatively inefficient in determining the voltage-frequency curve because the simulation process is complex and time-consuming. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for predicting voltage-frequency curves. The technical solution provided by this application is as follows.

[0006] According to one aspect of the embodiments of this application, a method for predicting a voltage frequency curve is provided, the method comprising: Obtain design information, which includes path feature information of N critical paths in the chip design file under different process angles, where N is an integer greater than 1; Obtain process information, which includes process feature information for K process angles, and the process feature information includes the relationship between voltage and delay of at least one standard cell of threshold type, where K is an integer greater than 1; Based on the design information and the process information, the voltage-frequency curve of the chip design file is predicted. The voltage-frequency curve is used to indicate the correspondence between the voltage and frequency of the chip corresponding to the chip design file.

[0007] In some embodiments, predicting the voltage-frequency curve of the chip design document based on the design information and the process information includes: Based on the design information and the process information, the correspondence between voltage and delay in the chip design file under the K process angles is obtained; Based on the correspondence between voltage and delay in the chip design document at the K process angles, predict the voltage-frequency curve of the chip design document at the K process angles.

[0008] In some embodiments, the design information is a design matrix, the process information is a process matrix, and obtaining the correspondence between voltage and delay in the chip design file under the K process angles based on the design information and the process information includes: Based on the product of the design matrix and the process matrix, the correspondence between voltage and delay in the chip design file under the K process angles is obtained.

[0009] In some embodiments, for the i-th process angle among the K process angles, where i is a positive integer, predicting the voltage-frequency curve of the chip design document under the K process angles based on the delay information of the chip design document under the K process angles includes: Based on the delay information in the chip design document at the i-th process angle, determine the correspondence between the voltage and the reciprocal of the delay in the chip design document at the i-th process angle; The correspondence between the voltage and the reciprocal of the delay in the chip design file at the i-th process angle is modeled to obtain the voltage-frequency curve of the chip design file at the i-th process angle.

[0010] In some embodiments, the method further includes: For the chip design document, for each of the K process corners, the path feature information of the N critical paths is extracted to obtain the design information.

[0011] In some embodiments, the design information is a design matrix, which includes K path feature elements. The i-th path feature element among the K path feature elements is used to indicate the path feature information of the N critical paths in the chip design file under the i-th process angle out of K process angles. K is a positive integer, and i is a positive integer less than or equal to K. The path feature information includes at least one of the following: The actual logic level, equivalent logic level, pure logic gate level after excluding buffers, delay ratio of standard cells with different threshold types on the data path, line delay ratio, delay of clock transmission path, delay of capture clock path, clock offset, and clock uncertainty factors.

[0012] In some embodiments, the method further includes: The relationship between voltage and delay of standard cells with different threshold types at different process angles and temperature points is extracted to obtain the process information.

[0013] In some embodiments, the process information is a process matrix, which includes S*K process feature elements. The p*q-th process feature element among the S*K process feature elements is used to indicate the correspondence between the voltage and delay of at least one standard cell of a threshold type under the conditions of the p-th temperature point among S temperature points and the q-th process angle among K process angles. S and K are positive integers, p is a positive integer less than or equal to S, and q is a positive integer less than or equal to K.

[0014] In some embodiments, the correspondence between voltage and delay is obtained by simulating the FO4 delay of inverters or buffers of different threshold types as a function of voltage at a specific temperature point under the process angle.

[0015] In some embodiments, the method further includes: Obtain the post-silicon testing results of the chip, the post-silicon testing results including the correspondence between the voltage and frequency actually measured by the chip; Based on the difference between the post-silicon testing results and the voltage-frequency curve, at least one of the design information and the process information is adjusted, and the adjusted design information or the adjusted process information is used to re-predict the voltage-frequency curve of the chip design document.

[0016] In some embodiments, the method further includes: Based on the post-silicon testing results, the yield prediction model corresponding to the chip design file is adjusted to obtain the adjusted yield prediction model, which is used to predict the yield of the chip.

[0017] In some embodiments, the method further includes: Based on the voltage-frequency curve in the chip design document, determine the voltage-frequency change under at least one voltage drop, and the voltage-frequency change under at least one voltage drop is used to guide the design of the chip.

[0018] According to one aspect of the embodiments of this application, a voltage frequency curve prediction device is provided, the device comprising: The design information acquisition module is used to acquire design information, which includes path feature information of N critical paths in the chip design file under different process angles, where N is an integer greater than 1; A process information acquisition module is used to acquire process information, which includes process feature information of K process corners. The process feature information includes the relationship between voltage and delay of at least one standard cell of threshold type, where K is an integer greater than 1. The curve determination module is used to predict the voltage-frequency curve of the chip design file based on the design information and the process information. The voltage-frequency curve is used to indicate the correspondence between the voltage and frequency of the chip corresponding to the chip design file.

[0019] In some embodiments, the curve determination module is configured to: Based on the design information and the process information, the correspondence between voltage and delay in the chip design file under the K process angles is obtained; Based on the correspondence between voltage and delay in the chip design document at the K process angles, predict the voltage-frequency curve of the chip design document at the K process angles.

[0020] In some embodiments, the design information is a design matrix, the process information is a process matrix, and the curve determination module is used for: Based on the product of the design matrix and the process matrix, the correspondence between voltage and delay in the chip design file under the K process angles is obtained.

[0021] In some embodiments, the apparatus further includes: The result acquisition module is used to acquire the post-silicon testing results of the chip, the post-silicon testing results including the correspondence between the voltage and frequency actually measured by the chip; An information adjustment module is used to adjust at least one of the design information and the process information based on the difference between the post-silicon testing results and the voltage-frequency curve. The adjusted design information or the adjusted process information is used to re-predict the voltage-frequency curve of the chip design document.

[0022] In some embodiments, the information adjustment module is further configured to: Based on the post-silicon testing results, the yield prediction model corresponding to the chip design file is adjusted to obtain the adjusted yield prediction model, which is used to predict the yield of the chip.

[0023] In some embodiments, the apparatus further includes: The change determination module is used to determine the voltage frequency change under at least one voltage drop based on the voltage frequency curve in the chip design document, and the voltage frequency change under at least one voltage drop is used to guide the design of the chip.

[0024] According to one aspect of the present application, a computer device is provided, the computer device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the above-described method for predicting voltage frequency curves.

[0025] According to one aspect of the present application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer program, which is loaded and executed by a processor to implement the above-described method for predicting voltage frequency curves.

[0026] According to one aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program, the computer program being loaded and executed by a processor to implement the above-described method for predicting voltage frequency curves.

[0027] The beneficial effects of the technical solutions provided in this application include at least the following: This application eliminates the need for complex circuit simulations; it can quickly determine the voltage-frequency curve, i.e., the correspondence between voltage and frequency, using design and process information. Therefore, this application improves the prediction efficiency of the voltage-frequency curve.

[0028] Specifically, the design information includes path characteristic information of N critical paths in the chip design file under different process corners, and the process information includes process characteristic information of K process corners, including the relationship between voltage and delay of standard cells. Therefore, based on the design information and process information, the delay corresponding to the chip under different voltages and different process corners can be quickly determined, that is, the correspondence between voltage and frequency (i.e., the reciprocal of delay) can be quickly determined. In addition, since complex circuit simulation is not required, the prediction cost of voltage-frequency curves can be reduced. Attached Figure Description

[0029] Figure 1 This is a structural block diagram of a computer system provided in one embodiment of this application; Figure 2 This is a block diagram of a voltage frequency curve prediction method provided in one embodiment of this application; Figure 3 This is a flowchart of a voltage frequency curve prediction method provided in one embodiment of this application; Figure 4 This is a flowchart of a voltage frequency curve prediction method provided in another embodiment of this application; Figure 5 This is a schematic diagram of the product of a design matrix and a process matrix provided in one embodiment of this application; Figure 6 This is a flowchart of a voltage frequency curve prediction method provided in another embodiment of this application; Figure 7 This is a schematic diagram of a voltage frequency curve provided in one embodiment of this application; Figure 8 This is a block diagram of a voltage frequency curve prediction method provided in another embodiment of this application; Figure 9 This is a structural block diagram of a voltage frequency curve prediction device provided in one embodiment of this application; Figure 10 This is a structural block diagram of a computer device provided in one embodiment of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0031] refer to Figure 1 The diagram illustrates a structural block diagram of a computer system provided in one embodiment of this application. This computer system can be implemented as a voltage frequency curve prediction system. Optionally, the computer system may include a terminal device 10 and a server 20.

[0032] Terminal device 10 includes, but is not limited to, mobile phones, tablets, smart voice interaction devices, game consoles, wearable devices, multimedia playback devices, PCs (Personal Computers), in-vehicle terminals, smart home appliances, and other electronic devices. A client application for the target application can be installed on terminal device 10. Optionally, the target application can be an application that requires downloading and installation, or it can be an application that can be used instantly; this embodiment of the application does not limit this.

[0033] In this embodiment, the target application described above is an application used to determine the correspondence between voltage and frequency. Exemplarily, the target application acquires design information, including path feature information of N critical paths in a chip design document under different process corners, where N is an integer greater than 1; acquires process information, including process feature information for K process corners, where the process feature information includes the relationship between voltage and delay of at least one threshold-type standard cell, where K is an integer greater than 1; and predicts the voltage-frequency curve of the chip design document based on the design information and process information, where the voltage-frequency curve indicates the correspondence between voltage and frequency of the chip corresponding to the chip design document.

[0034] Of course, the specific type of the target application is not limited. The target application can be a chip design application, a simulation application, etc. This application embodiment does not limit the specific category of the target application. In other embodiments, the target application can be considered a separate functional module, such as being implemented as one of the functional modules in a simulation application for determining the correspondence between voltage and frequency. For example, a client of the aforementioned target application runs in the terminal device 10.

[0035] Server 20 is used to provide backend services for the client of the target application in terminal device 10. For example, server 20 can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms, but it is not limited to these.

[0036] Terminal device 10 and server 20 can communicate with each other via a network. This network can be a wired network or a wireless network.

[0037] In other embodiments of this application, the explanation is only based on the computer device as the entity performing each step. For example, the computer device may be the terminal device 10 described above, or the server 20.

[0038] The following is a brief explanation of the methods for determining voltage-frequency curves in related technologies.

[0039] In related technologies, voltage-frequency curves (also known as VF curves) are typically obtained in various ways, including circuit simulation, STA (Static Timing Analysis), and post-silicon testing.

[0040] The first method is circuit simulation.

[0041] Using professional circuit simulation tools, simulations are performed based on the chip's circuit model. By setting different power supply voltages, the operating frequency of the chip under various voltages is simulated, thus obtaining the voltage-frequency curve.

[0042] The advantage of this method is that it can perform accurate simulations based on the specific circuit structure and parameters of the chip, taking into account various factors such as process variations and temperature effects. However, the disadvantages are that the simulation process is complex, time-consuming, and requires accurate circuit models and parameters. It also requires extensive simulations to comprehensively reflect all aspects and cannot provide rapid results during process and design migration.

[0043] The second type is STA.

[0044] Through design implementation, synthesis and placement and routing are used to realize the physical design of the chip. The chip operating frequency of multiple process corners is obtained through STAR method to obtain the voltage-frequency curve.

[0045] The advantage of this method is that STA can serve as a signoff for the corresponding process corner. The disadvantages are that STA results are typically obtained in the later stages of chip design, the resulting curves are discontinuous, and for process corners, the limited number of process corners in the database usually prevents the acquisition of sufficient information on continuous PVT (Process-Voltage-Temperature) variations.

[0046] The third type is post-silicon testing (i.e., actual measurement).

[0047] A test platform was set up, and the chip was placed in a real working environment. A high-precision power supply was used to provide different voltages, and a frequency measuring instrument was used to measure the chip's operating frequency at the corresponding voltage to obtain a voltage-frequency curve.

[0048] The advantage of this method is that it can obtain the most realistic and accurate voltage-frequency curve, reflecting the characteristics of the chip in practical applications. The disadvantages are that it requires specialized testing equipment, the testing process may be affected by environmental factors, and it is quite difficult to test some complex chips.

[0049] Considering the advantages and disadvantages of the three methods mentioned above, the voltage frequency curve prediction method proposed in this application, that is, the voltage frequency curve determination method, balances efficiency, cost, and ease of determination. It not only has high determination efficiency but also relatively low determination cost and difficulty. See the following explanation of the embodiments for details.

[0050] The following is combined Figure 2 The following is a brief description of the technical solutions involved in this application.

[0051] refer to Figure 2 The diagram illustrates a method for predicting voltage-frequency curves according to an embodiment of this application.

[0052] According to the embodiments of this application, the voltage frequency curve (i.e., VF curve) can be determined based on the design matrix 210 and the process matrix 220.

[0053] Specifically, the design matrix 210 includes path feature information of N critical paths in the chip design document under different process angles.

[0054] Specifically, the process matrix 220 includes process feature information for K types of process angles.

[0055] In one possible implementation, the voltage frequency matrix, or competition matrix, can be obtained by directly multiplying the design matrix 210 and the process matrix 220.

[0056] In another possible implementation, the VF curve can be modeled based on the voltage-frequency matrix to obtain the predicted voltage-frequency curve.

[0057] In another possible implementation, at least one of the design matrix 210 and the process matrix 220 is calibrated based on the difference between the post-silicon test results 230 and the voltage-frequency curve.

[0058] For specific implementation details, please refer to the explanation of the following embodiments, which will not be repeated here.

[0059] The following is combined Figure 3 The following explanation is provided regarding the voltage frequency curve prediction method proposed in this application.

[0060] refer to Figure 3 The diagram illustrates a flowchart of a voltage frequency curve prediction method provided in one embodiment of this application. The execution entity for each step of this method can be the computer device described above. The method may include at least one of the following steps (310-330).

[0061] Step 310: Obtain design information, which includes path feature information of N critical paths in the chip design file under different process angles, where N is an integer greater than 1.

[0062] A chip design file is used to indicate at least two standard cells and the connection relationships between them. The chip design file includes at least two paths, each indicating a connection path from one standard cell to another. The chip design file in this application is a design diagram describing how the components (or standard cells) in the chip are laid out, arranged, and connected; it is a planar geometric description of the physical circuitry in the actual chip. The chip design file can be a chip layout for a memory chip, a chip layout for a digital multimedia chip, etc. This application does not limit the type of chip the chip design file corresponds to. The chip design file contains information such as the shape, area, and position of each hardware unit on the circuit. Through automatic routing, routing information connecting various points can be added to the chip design file, ultimately generating a chip design file with routing and layout information.

[0063] It should be noted that the standard units or components in the chip design files mentioned in the embodiments of this application do not refer to actual physical devices, but rather to analog devices corresponding to actual physical devices, or what may be called device patterns. For example, each actual device corresponds to a device pattern (or graphic) on the chip design file, which is used to simulate the actual device.

[0064] In this application, each path indicates a connection path from one standard unit to another. The first mentioned standard unit is considered the starting point of the path, and the second mentioned standard unit is considered the ending point. Optionally, for a path, in addition to the starting and ending points, the path may also pass through other standard units; that is, between the starting and ending points, the path passes through other standard units. This application does not limit the type of standard units passed through by the path; the standard units passed through by the path can be of any type, including register units. Of course, the path may also not pass through any standard units; that is, between the starting and ending points, the path does not pass through other standard units.

[0065] The design information in this application includes path feature information of N critical paths in the chip design document under different process corners. The path feature information here is used to indicate at least one attribute of the path. This application does not limit the type of path feature information; all information used to indicate the attributes of a path can be considered as the path feature information described here.

[0066] For example, the attributes of a path include at least one of the following: the type of standard cell traversed, the level of the standard cell, the location of the standard cell, path delay, etc.

[0067] Optionally, the paths in the chip design file may differ at different process corners and voltage points. These paths can be arbitrary, or they can be critical paths, which are the paths with the longest signal propagation time. That is, all paths in this application are considered critical paths.

[0068] The process corner in this application is used to simulate the impact of manufacturing process variations on transistor performance (speed, power consumption, etc.). Different process corner combinations cover various scenarios for NMOS (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor) and PMOS (P-channel Metal-Oxide-Semiconductor Field-Effect Transistor) in terms of speed (Fast, Slow, Typical) and variations (Global, Narrow, Peripheral). Optionally, the process parameters differ under different process corners.

[0069] Optionally, the process corner includes at least one of the following: SS (Slow-Slow), SSG (Slow-Slow Global), SSGNP (Slow-Slow Global With NMOS / PMOS cancellation), FSG (Fast-Slow Global), TT (Typical-Typical), SFG (Slow-Fast Global), FFGNP (Fast-Fast Global With NMOS / PMOS cancellation), FFG (Fast-Fast Global), and FF (Fast-Fast). This application does not limit the type of process corner.

[0070] Optionally, the critical path in the chip design document will also change when the process corner changes. Optionally, this application obtains at least one critical path under different process corners. Specifically, it obtains the path feature information of at least one critical path.

[0071] This application does not limit the form in which the design information is represented. Optionally, the design information may be represented in at least one of the following forms: vector, array, matrix, table, or database.

[0072] Step 320: Obtain process information, which includes process feature information for K process angles. The process feature information includes the relationship between voltage and delay of at least one standard cell of threshold type, where K is an integer greater than 1.

[0073] Optionally, the process feature information for each process angle is different. Optionally, obtain the process feature information corresponding to K process angles respectively. K is a positive integer.

[0074] The process information in this application includes process feature information for K types of process corners. This process feature information is used to indicate at least one attribute of the process corner. This application does not limit the types of process feature information; all information used to indicate the attributes of a process corner can be considered as the process feature information described here. For example, the attributes of a process corner include at least one of the following: process parameters, the type of process corner, and the impact of the process corner on standard cells.

[0075] This application does not limit the format in which the process information is represented. Optionally, the process information may be represented in at least one of the following formats: vector, array, matrix, table, or database.

[0076] Optionally, process information can be obtained from a server or a pre-set database. Optionally, this process information is not generated in real time, but is pre-set and can be obtained directly.

[0077] Step 330: Based on the design information and process information, predict the voltage-frequency curve of the chip design file. The voltage-frequency curve is used to indicate the correspondence between the voltage and frequency of the chip corresponding to the chip design file.

[0078] Optionally, the voltage-frequency curve includes at least one pair of arrays, each pair including a voltage point value and a frequency value with a corresponding relationship. This application does not limit the representation of the voltage-frequency curve. Optionally, the voltage-frequency curve can be represented in at least one of the following forms: vector, array, matrix, table, or database. Optionally, the voltage-frequency curve is used to indicate the correspondence between the voltage and frequency of the chip. Optionally, the voltage-frequency curve is obtained by modeling a voltage-frequency matrix. That is, based on the voltage-frequency matrix, the functional relationship between the chip's voltage and frequency can be simulated, i.e., the VF curve can be simulated.

[0079] For example, the voltage-frequency matrix of the chip design file is obtained based on the design information and process information. Optionally, a voltage-frequency curve is modeled based on the voltage-frequency matrix. See the explanation of the following embodiments for details, which will not be repeated here.

[0080] For example, design information and process information are input into a data prediction model, which then predicts the voltage-frequency curve. The data prediction model is a pre-defined neural network model that uses design information and process information to predict either the voltage-frequency matrix or the voltage-frequency curve.

[0081] For example, design information and process information are input into a first calculation formula, and the voltage-frequency curve is obtained by the first calculation formula. The first calculation formula is a preset formula for calculating the correspondence between voltage and frequency based on the design information and process information.

[0082] In one possible implementation, for each voltage point of the chip, the corresponding delay value is found by combining design and process information. Optionally, the corresponding frequency value is determined based on the delay value. Optionally, the frequency value is the reciprocal of the delay value. For each voltage point, the corresponding delay value is found, and then the corresponding frequency value is calculated. After obtaining the voltage-frequency matrix, a voltage-frequency curve is modeled.

[0083] In another possible implementation, for each voltage point of the chip, the corresponding frequency value is found by combining design and process information, resulting in a voltage-frequency matrix. After obtaining the voltage-frequency matrix, a voltage-frequency curve is modeled.

[0084] It should also be noted that the voltage-frequency curves here correspond to at least one process corner. That is, the voltage-frequency curves are used to indicate the voltage-frequency relationship of the chip at at least one process corner. Optionally, if the number of process corners is K, then the voltage-frequency curves are used to indicate the voltage-frequency relationship of the chip at K different process corners.

[0085] The specific determination method involved here is explained in the following embodiments and will not be repeated here.

[0086] This application eliminates the need for complex circuit simulations; it can quickly determine the voltage-frequency curve, i.e., the correspondence between voltage and frequency, using design and process information. Therefore, this application improves the prediction efficiency of the voltage-frequency curve.

[0087] Specifically, the design information includes path characteristic information of N critical paths in the chip design file under different process corners, and the process information includes process characteristic information of K process corners, including the relationship between voltage and delay of standard cells. Therefore, based on the design information and process information, the delay corresponding to the chip under different voltages and different process corners can be quickly determined, that is, the correspondence between voltage and frequency (i.e., the reciprocal of delay) can be quickly determined. In addition, since complex circuit simulation is not required, the prediction cost of voltage-frequency curves can be reduced.

[0088] The following is combined Figure 4 The following explanation details the specific method for predicting the voltage-frequency curve in this application.

[0089] refer to Figure 4 The diagram illustrates a flowchart of a voltage frequency curve prediction method according to another embodiment of this application. The execution entity for each step of this method can be the computer device described above. The method may include at least one of the following steps (410-440).

[0090] Step 410: Obtain design information. The design information includes path feature information of N critical paths in the chip design file under different process angles, where N is an integer greater than 1.

[0091] Step 420: Obtain process information, which includes process feature information for K process angles. The process feature information includes the relationship between voltage and delay of at least one standard cell of threshold type, where K is an integer greater than 1.

[0092] Before introducing steps 430 and 440 below, we will further explain the design information, process information, and voltage-frequency curve.

[0093] Firstly, the design information is explained as follows.

[0094] In some embodiments, the design information is a design matrix.

[0095] Optionally, the design matrix includes: K path feature elements, where the i-th path feature element is used to indicate the path feature information of the N critical paths in the chip design file under the i-th process angle among the K process angles, where K is a positive integer and i is a positive integer less than or equal to K.

[0096] For example, the i-th path feature element is used to indicate the path feature information of the N critical paths in the chip design document under the case of the i-th process angle.

[0097] For example, if the chip design file has N critical paths in the case of the i-th process angle, then the i-th path feature element includes the path feature information corresponding to each of the N critical paths. For example, the i-th path feature element can also be represented as a matrix. Optionally, if the dimension of the path feature information corresponding to each critical path is R, then the dimension of the i-th path feature element is N*R, where N and R are positive integers.

[0098] Optionally, the path characteristic information includes at least one of the following: the actual number of logic levels, the equivalent number of logic levels, the number of pure logic gate levels after excluding buffers, the delay ratio of standard cells with multiple threshold types, the line delay ratio, the delay of the clock transmission path, the delay of the capture clock path, clock offset, clock uncertainty, and other factors.

[0099] The equivalent logic level is equivalent to the delay level of a pure inverter or buffer with a fanout of 4 (FO4) at a specific process corner.

[0100] In some embodiments, the relationship between voltage and delay of standard cells with different threshold types at different process angles and different temperature points is extracted to obtain process information.

[0101] In this application, the standard cell of threshold type refers to a standard cell classified according to the high or low threshold voltage of the transistor. Optionally, the standard cell of threshold type includes at least one of the following: RVT (Regular Voltage Threshold) cell, LVT (Low Voltage Threshold) cell, and SLVT (Super Low Voltage Threshold) cell.

[0102] Optionally, as shown in Table 1 below, a path feature element is illustrated.

[0103] Table 1. Path Feature Elements

[0104] As shown in Table 1, the first column represents the number of paths available in process corner 1. Table 1 shows 5 paths, but there may actually be more than 5. Table 1 also represents the path characteristic elements under process corner 1. All instances of "xx" in Table 1 are merely references (or examples) and do not represent actual numerical values.

[0105] As shown in Table 1, the first row of Table 1 indicates the types (or attributes) of path feature information. As shown in Table 1, path feature information includes: path_delay (path delay), RVT_delay (RVT cell delay), RVT_level (RVT cell level), LVT_delay (LVT cell delay), and LVT_level (LVT cell level). Of course, path feature information may also include other information, which is not shown in Table 1.

[0106] Optionally, the path feature information may also include at least one of the following: SLVT_delay (SLVT cell delay), SLVT_level (SLVT cell level), net_delay_percent (net delay percentage, i.e., the above-mentioned line delay ratio), equ_logic_level (equivalent logic level), logic_level (actual logic level), logic_level_no_buf (unbuffered logic level, i.e., the above-mentioned pure logic gate level excluding buffers), launch_lat (delay of clock transmit path), capture_lat (capture clock delay, i.e., the above-mentioned capture clock path delay), crpr (clock reconvergence compensation), skew (clock skew), RVT derate (RVT cell derating factor), LVT derate (LVT cell derating factor), and ULVTderate (ULVT cell derating factor).

[0107] For example, such as Figure 5 As shown, the design matrix 510 includes path feature information for at least one path under K process angles.

[0108] Optionally, extract the design matrix (which reflects the influence of different logic levels, different cell delays, net delays, different threshold types, clock skew, uncertainty, etc.), extract n critical paths from each corner of the low-voltage to high-voltage signoff corner, and extract design feature information.

[0109] Optionally, feature information of the current design is extracted from the low-voltage to high-voltage corners of the STA signoff. Optionally, the critical path may differ for each corner from low-voltage to high-voltage. In the low-voltage region, the path is mainly cell delay dominant, and the proportion of path RVT and VT (threshold type) is relatively high. Gradually moving towards high voltage, the proportion of net delay gradually increases, and the VT type of the path gradually changes to LVT or ULVT dominated by the path. Therefore, n or n sets of critical paths are extracted from the low-voltage and high-voltage corners respectively to construct the design feature matrix.

[0110] The technical solution provided in this application adopts a design matrix approach to carry the path feature information of at least one critical path under different process corners, which reflects the flexibility of information presentation, and the rectangular form is beneficial for subsequent voltage frequency curve calculation.

[0111] Secondly, the process information is explained as follows.

[0112] In some embodiments, the process information is a process matrix.

[0113] Optionally, the process matrix includes: S*K process feature elements, wherein the p*q-th process feature element among the S*K process feature elements is used to indicate the correspondence between the voltage and delay of at least one standard cell of threshold type under the conditions of the p-th temperature point among S temperature points and the q-th process angle among K process angles, where S and K are positive integers, p is a positive integer less than or equal to S, and q is a positive integer less than or equal to K.

[0114] For example, the p*q-th process feature element is used to indicate the correspondence between the voltage and delay of a standard cell of at least one threshold type at the p-th temperature point and the q-th process angle.

[0115] For example, if simulations are performed on standard cells of M threshold types at the p-th temperature point and the q-th process angle, the correspondence between the voltage and delay of the standard cells of the M threshold types can be obtained. Optionally, the p*q-th process feature element is used to indicate the correspondence between the voltage and delay of the standard cells of the M threshold types, where M is a positive integer. Optionally, the p*q-th process feature element includes M sets of correspondences, each set indicating the correspondence between the voltage and delay of a standard cell of one threshold type. Optionally, the p*q-th process feature element can also be represented as a matrix.

[0116] Optionally, as shown in Table 2 below, a process feature element is illustrated.

[0117] Table 2. A process characteristic element

[0118] Table 2 shows the voltage and delay relationships of the SLVT, LVT, and RVT units when the process angle is TT and the temperature is 0 or 25°C. Table 1 only shows partial data. All "xx" in Table 2 are for reference only (or examples) and do not represent actual values.

[0119] As shown in Table 2, Table 2 shows the delays corresponding to standard cells of different threshold types at multiple voltage points (0.5, 0.525, 0.55...) for the process angle TT.

[0120] For example, the relationship between voltage and delay of standard cells with different threshold types at different process angles and temperature points is extracted to obtain process information.

[0121] For example, such as Figure 5 As shown, the process matrix 520 includes the correspondence between the voltage and delay of a standard cell of at least one threshold type at at least one temperature point and at least one process angle. TT in the process matrix 520 is used to indicate process characteristic information at process angle TT, that is, the correspondence between the voltage and delay of a standard cell of at least one threshold type when the process angle is TT.

[0122] Optionally, obtain the Tech matrix (which reflects process characteristics, V&delay of voltage, temperature, and transition time at different process angles SS, SSG, SSGNP, FSG, TT, SFG, FFGNP, ​​FFG, FF, obtained through simulation), and the delay-voltage relationship matrix of standard cells of different threshold types at different process angles and temperatures.

[0123] For example, the correspondence between voltage and delay is obtained by simulating the FO4 delay of different threshold types of inverters or buffers as a function of voltage at a specific temperature point under this process angle. Optionally, this simulation is a SPICE simulation. Optionally, FO4 can be determined based on the transition time and load statistically derived from the actual design matrix.

[0124] Optionally, the process-related feature matrix (i.e., the process matrix) is the spice simulation matrix of the FO4 (Fanout-of-4) single-stage delay as a function of voltage under this process, which includes the process feature matrix (i.e., the process feature information mentioned above) of different corners (process corners, such as SS / SSG / SSGNP / FSGNP / TT / SFGNP / FFGNP / FFG / FF) at different temperatures.

[0125] The technical solution provided in this application uses a process matrix to carry process feature information of at least one process corner, which reflects the flexibility of information presentation and the rectangular form is beneficial for subsequent voltage frequency curve calculation.

[0126] Thirdly, the voltage-frequency curve is explained as follows.

[0127] In some embodiments, the voltage-frequency curve is obtained by modeling the voltage-frequency matrix. Here, the voltage-frequency matrix is ​​also considered to be the voltage delay matrix.

[0128] Optionally, the voltage-frequency matrix includes: an X*Y group correspondence, where the x*y group correspondence is used to indicate the correspondence between the chip's voltage and frequency at the xth temperature point among X temperature points and the yth process angle among Y process angles, where X and Y are positive integers, x is a positive integer less than or equal to X, and y is a positive integer less than or equal to Y.

[0129] For example, the x*y group of correspondences is used to indicate the correspondence between the voltage and frequency of the chip at the x-th temperature point and the y-th process angle.

[0130] Optionally, Table 3 below shows a set of correspondences.

[0131] Table 3 A set of correspondences

[0132] Table 3 shows the relationship between voltage and delay (total delay) at process angle TT and temperature points of 0 or 25°C. Only partial data is shown in Table 3. Optionally, the relationship between voltage and frequency can be deduced based on the voltage-delay relationship shown in Table 3. That is, the x*y-th group of relationships indicates the relationship between chip voltage and frequency at the x-th temperature point and the y-th process angle.

[0133] The voltage-frequency matrix described above yields the X*Y correspondence, which represents the relationship between the chip's voltage and frequency at X temperature points and Y process angles. Optionally, after obtaining this correspondence, a simulation tool can be used to model the curve and obtain the VF curve.

[0134] In one possible implementation, such as Figure 5 As shown, the voltage-frequency matrix 530 includes the correspondence between the voltage and frequency of the chip at at least one temperature point and at least one process angle. TT in the voltage-frequency matrix 530 is used to indicate the correspondence between voltage and frequency when the process angle is TT.

[0135] The technical solution provided in this application uses a voltage-frequency matrix to represent the correspondence between voltage and frequency, thereby improving the speed of subsequent modeling of voltage-frequency curves.

[0136] Step 430: Based on the design information and process information, obtain the correspondence between voltage and delay in the chip design file under K process angles.

[0137] Optionally, since the process information includes the relationship between voltage and delay of at least one standard cell of threshold type, the correspondence between voltage and delay in the chip design file at K process angles can be determined using the design information and process information.

[0138] In some embodiments, the correspondence between voltage and delay in the chip design file at K process angles is determined based on the product of design information and process information.

[0139] Optionally, the correspondence between voltage and delay in the chip design file at K process angles can be determined based on the product of design information and process information.

[0140] Optionally, if the design information is a design matrix and the process information is a process matrix, then the product of the design information and the process information is also the product of the design matrix and the process matrix. Optionally, the product of the design matrix and the process matrix can be used as the correspondence between voltage and delay in the chip design file under K process angles.

[0141] In one possible implementation, the correspondence between voltage and delay in the chip design file at K process angles is also called the voltage-frequency matrix, or the competition matrix.

[0142] Step 440: Based on the correspondence between voltage and delay in the chip design file at K process angles, predict the voltage-frequency curves of the chip design file at K process angles.

[0143] Optionally, since there is a correlation between delay and frequency, the voltage-frequency curve can be derived after obtaining the correspondence between voltage and delay. That is, after obtaining the voltage-frequency matrix, the voltage-frequency curve can be modeled.

[0144] Optionally, the conversion from voltage frequency matrix to voltage frequency curve is achieved through a preset formula or model.

[0145] In some embodiments, for the i-th process angle among K process angles, where i is a positive integer, the voltage-frequency curve under the i-th process angle is determined by the following steps. Optionally, for each process angle, the voltage-frequency curve is calculated separately.

[0146] For example, based on the delay information in the chip design document at the i-th process angle, the correspondence between the voltage and the reciprocal of the delay in the chip design document at the i-th process angle is determined.

[0147] Since frequency is equal to the reciprocal of delay, after determining the correspondence between voltage and delay, we take the reciprocal of delay to obtain the correspondence between voltage and the reciprocal of delay.

[0148] For example, the correspondence between the voltage and the reciprocal of the delay in the chip design file at the i-th process angle is modeled to obtain the voltage-frequency curve of the chip design file at the i-th process angle.

[0149] Specifically, the correspondence between the voltage and the reciprocal of the delay in the chip design file at the i-th process angle is modeled to obtain the voltage-frequency curve of the chip design file at the i-th process angle.

[0150] Optionally, the product of the design matrix and the process matrix can be used as the voltage delay matrix. Taking the reciprocal of the delay in the voltage delay matrix yields the voltage delay matrix from the chip design file. This voltage-frequency matrix is ​​then modeled to obtain the voltage-frequency curve. In other words, the correspondence between voltage and frequency is obtained.

[0151] Optionally, the VF curve is modeled using a design matrix multiplied by a process matrix, while simultaneously employing post-silicon calibration for pre-silicon and pre-silicon prediction for post-silicon. See the explanation of the embodiments below for details.

[0152] The technical solution provided in this application does not require a complex simulation process. It obtains the correspondence between voltage and frequency through simple matrix operations, demonstrating the predictive efficiency of the voltage-frequency curve. Furthermore, converting frequencies that are difficult to calculate into delays for calculation also helps reduce computational costs and improve computational speed.

[0153] The following is combined Figure 6The following explanation details the specific method for predicting the voltage-frequency curve in this application.

[0154] refer to Figure 6 The diagram illustrates a flowchart of a voltage frequency curve prediction method according to another embodiment of this application. The execution entity for each step of this method can be the computer device described above. The method may include at least one of the following steps (610-650).

[0155] Step 610: Obtain design information, which includes path feature information of N critical paths in the chip design file under different process angles, where N is an integer greater than 1.

[0156] Step 620: Obtain process information, which includes process feature information for K process angles. The process feature information includes the relationship between voltage and delay of at least one standard cell of threshold type, where K is an integer greater than 1.

[0157] Step 630: Based on the design information and process information, predict the voltage-frequency curve of the chip design file. The voltage-frequency curve is used to indicate the correspondence between the voltage and frequency of the chip corresponding to the chip design file.

[0158] Step 640: Obtain the post-silicon testing results of the chip. The post-silicon testing results include the correspondence between the voltage and frequency actually measured by the chip.

[0159] Optionally, post-silicon testing results can be obtained. Post-silicon testing results refer to the statistical results obtained from actual post-silicon testing of the chip. Optionally, information such as process OCV (On-Chip Variation), voltage OCV, temperature OCV, system-level VF curve, and guardband information for standard cells of different threshold types can be extracted. Optionally, post-silicon testing results include at least one of the following: process variation, voltage variation, temperature variation, post-silicon yield, and binning Sigma.

[0160] Optionally, the post-silicon data predicted using the aforementioned voltage-frequency curve is referred to as the post-silicon prediction result. For example, the measured OCV margin after silicon is back-calibrated using the aforementioned voltage-frequency curve, including process deviation, voltage deviation, temperature deviation, post-silicon yield, and binning Sigma (the chip is graded (Bin) based on performance (e.g., frequency) / power consumption, and the Sigma value of each grade reflects the process control level of that Bin). Optionally, the post-silicon prediction result includes at least one of the following: process deviation, voltage deviation, temperature deviation, post-silicon yield, and binning Sigma.

[0161] Step 650: Based on the difference between the post-silicon testing results and the voltage-frequency curve, adjust at least one of the design information and process information. The adjusted design information or the adjusted process information is used to re-predict the voltage-frequency curve of the chip design file.

[0162] Optionally, the design information can be adjusted based on the difference between post-silicon testing results and the voltage-frequency profile. Optionally, the process information can be adjusted based on the difference between post-silicon testing results and the voltage-frequency profile. Optionally, the design information and process information can be adjusted based on the difference between post-silicon testing results and the voltage-frequency profile.

[0163] For example, based on the difference between post-silicon testing results and post-silicon prediction results, at least one of the design information and process information is adjusted, and the adjusted design information or adjusted process information is used to redetermine the voltage-frequency curve of the chip design file.

[0164] For example, design information is adjusted based on the difference between post-silicon testing results and post-silicon prediction results. For example, process information is adjusted based on the difference between post-silicon testing results and post-silicon prediction results. Optionally, design information and process information are adjusted based on the difference between post-silicon testing results and post-silicon prediction results.

[0165] The technical solution provided in this application provides a method to predict post-silicon development before silicon development, and then adjust at least one of the design information and process information based on the difference between the prediction results and the test results after silicon development. This helps to improve the accuracy of the design information and process information, thereby improving the accuracy of subsequent VF curve prediction.

[0166] In some embodiments, based on the post-silicon testing results, the yield prediction model corresponding to the chip design file is adjusted to obtain an adjusted yield prediction model, which is used to predict the yield of the chip.

[0167] For example, based on the post-silicon yield in the post-silicon testing results, the yield prediction model corresponding to the chip design file is adjusted to obtain the adjusted yield prediction model.

[0168] For example, the yield of the chip is predicted using a yield prediction model corresponding to the chip design document, resulting in a pre-silicon yield prediction result. Optionally, the yield prediction model is adjusted based on the difference between the pre-silicon yield prediction result and the post-silicon yield, resulting in an adjusted yield prediction model. Optionally, the yield prediction model is adjusted with the objective of minimizing the difference between the pre-silicon yield prediction result and the post-silicon yield, resulting in an adjusted yield prediction model.

[0169] The technical solution provided in this application introduces a yield prediction model to predict the yield rate, and adjusts the yield prediction model based on the post-silicon testing results, which helps to improve the prediction accuracy of the yield rate.

[0170] In some embodiments, based on the voltage-frequency curve of the chip design document, the voltage-frequency change under at least one voltage drop is determined, and the voltage-frequency change under at least one voltage drop is used to guide the chip design.

[0171] Optionally, by analyzing the package voltage drop and IR drop (voltage drop) of the above voltage-frequency curves, the voltage-frequency change under at least one voltage drop can be obtained.

[0172] Optionally, such as Figure 7 Subplot (a) shows the VF curves under different process angles. These VF curves comprehensively consider the effects of OCV and actual margins, analyzing the derating factors for RVT, LVT, and ULVT derate cells, and simulating clock skew, toggle time, and uncertainties. Furthermore, these VF curves under different process angles can be used to predict VF curves for other process angles, such as those for FFG and SSG.

[0173] Optionally, such as Figure 7 Subplot (b) shows the VF change (i.e., voltage frequency change) obtained with 5% or 10% IR drop.

[0174] Optionally, such as Figure 8 As shown, inputting design information yields design matrix 810. Optionally, inputting process information yields process matrix 820. Optionally, multiplying design matrix 810 and process matrix 820 yields product result 830. Optionally, this product result 830 can be considered as the voltage-frequency curve or voltage-frequency matrix mentioned in the above embodiments, or it can also be considered as a voltage delay matrix.

[0175] Optionally, such as Figure 8 As shown, post-silicon testing yields a post-silicon testing result 850. Optionally, a post-silicon prediction result is obtained using the product result 830. Optionally, the design matrix 810 and process matrix 820 are calibrated based on the difference between the post-silicon prediction result and the post-silicon testing result 850.

[0176] Optionally, such as Figure 8 As shown, the VF curve 840 can be obtained by modeling the product result 830.

[0177] The technical solution provided in this application can quickly obtain VF curves related to chip design, and can accurately predict process and design changes by combining pre-silicon and post-silicon methods. This can assist product managers and approvers in quickly determining the performance benefits of process corner changes. Furthermore, by combining power consumption models, it can help chip designers quickly find the balance between performance and power consumption, thereby improving chip performance.

[0178] Specifically, it offers the following advantages: it eliminates the need for extensive simulations, does not rely on numerous Liberty (.lib) libraries, and requires no STA (Standard Instrumentation) process; it can quickly and accurately reflect the true relationship between the VF curve and the design reality; it can quickly predict the changes in VF curves of the same design under different processes when switching between different processes; it can obtain relatively complete multi-process corner information early in the design process; it can quickly reflect design changes through equivalent logic levels; it can reflect the impact of OCV (Optical Characteristic Value) on the VF curve; it can reflect the impact of different process corners on the chip; it can reflect post-silicon measurements (including process deviations (Performance-Relevant-Offset, PerfRO)), and the PVT OCV impact can be back-annotated to pre-silicon chip yield prediction.

[0179] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0180] refer to Figure 9 This diagram illustrates a block diagram of a voltage frequency curve prediction apparatus according to an embodiment of this application. The apparatus has the function of implementing the aforementioned voltage frequency curve prediction method; this function can be implemented in hardware or by hardware executing corresponding software. The apparatus can be the computer device described above, or it can be installed within a computer device. For example... Figure 9 As shown, the device 900 may include: a design information acquisition module 910, a process information acquisition module 920, and a curve determination module 930.

[0181] The design information acquisition module 910 is used to acquire design information, which includes path feature information of N critical paths in the chip design file under different process angles, where N is an integer greater than 1.

[0182] The process information acquisition module 920 is used to acquire process information, which includes process feature information of K process corners. The process feature information includes the relationship between voltage and delay of at least one standard cell of threshold type, where K is an integer greater than 1.

[0183] The curve determination module 930 is used to predict the voltage-frequency curve of the chip design file based on the design information and the process information. The voltage-frequency curve is used to indicate the correspondence between the voltage and frequency of the chip corresponding to the chip design file.

[0184] In some embodiments, the curve determination module 930 is configured to: obtain the correspondence between voltage and delay of the chip design file under the K process angles based on the design information and the process information; and predict the voltage frequency curve of the chip design file under the K process angles based on the correspondence between voltage and delay of the chip design file under the K process angles.

[0185] In some embodiments, the design information is a design matrix, the process information is a process matrix, and the curve determination module 930 is used to: obtain the correspondence between voltage and delay of the chip design file under the K process angles based on the product of the design matrix and the process matrix.

[0186] In some embodiments, for the i-th process angle among the K process angles, where i is a positive integer, the curve determination module 930 is configured to: determine the correspondence between the voltage and the reciprocal of the delay in the chip design file at the i-th process angle based on the delay information in the chip design file at the i-th process angle; and model the correspondence between the voltage and the reciprocal of the delay in the chip design file at the i-th process angle to obtain the voltage-frequency curve of the chip design file at the i-th process angle.

[0187] In some embodiments, the design information acquisition module 910 is used to extract the path feature information of the N critical paths for each of the K process angles in the chip design file, and obtain the design information.

[0188] In some embodiments, the design information is a design matrix, which includes K path feature elements. The i-th path feature element among the K path feature elements is used to indicate the path feature information of the N critical paths in the chip design file under the i-th process angle among K process angles. K is a positive integer, and i is a positive integer less than or equal to K. The path feature information includes at least one of the following: the actual logic level of standard cells of different threshold types on the data path, the equivalent logic level, the pure logic gate level after excluding buffers, the delay ratio of standard cells of multiple threshold types, the line delay ratio, the delay of the clock transmit path, the delay of the capture clock path, the clock offset, and the clock uncertainty factor.

[0189] In some embodiments, the process information acquisition module 920 is used to extract the relationship between voltage and delay of standard cells of different threshold types at different process angles and different temperature points to obtain the process information.

[0190] In some embodiments, the process information is a process matrix, which includes S*K process feature elements. The p*q-th process feature element among the S*K process feature elements is used to indicate the correspondence between the voltage and delay of at least one standard cell of a threshold type under the conditions of the p-th temperature point among S temperature points and the q-th process angle among K process angles. S and K are positive integers, p is a positive integer less than or equal to S, and q is a positive integer less than or equal to K.

[0191] In some embodiments, the correspondence between voltage and delay is obtained by simulating the FO4 delay of inverters or buffers of different threshold types as a function of voltage at a specific temperature point under the process angle.

[0192] In some embodiments, the device 900 further includes a result acquisition module and an information adjustment module (not shown in the figure).

[0193] The result acquisition module is used to acquire the post-silicon testing results of the chip, which include the correspondence between the voltage and frequency actually measured by the chip.

[0194] An information adjustment module is used to adjust at least one of the design information and the process information based on the difference between the post-silicon testing results and the voltage-frequency curve. The adjusted design information or the adjusted process information is used to re-predict the voltage-frequency curve of the chip design document.

[0195] In some embodiments, the information adjustment module is further configured to: adjust the yield prediction model corresponding to the chip design file according to the post-silicon testing results, to obtain an adjusted yield prediction model, wherein the adjusted yield prediction model is used to predict the yield of the chip.

[0196] In some embodiments, the device 900 further includes a change determination module (not shown in the figure).

[0197] The change determination module is used to determine the voltage frequency change under at least one voltage drop based on the voltage frequency curve in the chip design document, and the voltage frequency change under at least one voltage drop is used to guide the design of the chip.

[0198] The technical solution provided in this application does not require complex circuit simulation; the voltage-frequency curve can be quickly determined using design and process information. Therefore, this application improves the prediction efficiency of the voltage-frequency curve.

[0199] Specifically, since the design information includes path feature information of at least one path in the chip design file under different process corners, and the process information includes process feature information of at least one process corner, including the relationship between the voltage and delay of standard cells, the delay corresponding to the chip under different voltages and different process corners can be quickly determined based on the design information and process information. In other words, the correspondence between voltage and frequency (i.e., the reciprocal of the delay) can be quickly determined. Furthermore, since complex circuit simulation is not required, the cost of predicting voltage-frequency curves can be reduced.

[0200] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the content structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0201] refer to Figure 10 This diagram illustrates a structural block diagram of a computer device 1000 provided in one embodiment of this application. The computer device 1000 can be any electronic device capable of data calculation, processing, and storage. The computer device 1000 can be used to implement the voltage frequency curve prediction method provided in the above embodiments. This includes the computer device mentioned in the above embodiments.

[0202] Typically, computer device 1000 includes a processor 1001 and a memory 1002.

[0203] Processor 1001 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1001 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1001 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1001 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 1001 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0204] The memory 1002 may include one or more computer-readable storage media, which may be non-transitory. The memory 1002 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1002 is used to store a computer program configured to be executed by one or more processors to implement the voltage frequency curve prediction method described above.

[0205] Those skilled in the art will understand that Figure 10 The structure shown does not constitute a limitation on the computer device 1000, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0206] In an exemplary embodiment, a computer-readable storage medium is also provided, wherein a computer program is stored in the storage medium, and the computer program, when executed by a processor, implements the above-described method for predicting the voltage frequency curve. Optionally, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random Access Memory), SSD (Solid State Drives), or optical disk, etc. The random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0207] In an exemplary embodiment, a computer program product is also provided, the computer program product including a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, causing the computer device to perform the above-described voltage frequency curve prediction method.

[0208] It should be understood that "multiple" as mentioned herein refers to two or more. Furthermore, the step numbers described herein are merely illustrative of one possible order of execution. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this practice.

[0209] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for predicting voltage-frequency curves, characterized in that, The method includes: Obtain design information, which includes path feature information of N critical paths in the chip design file under different process angles, where N is an integer greater than 1; Obtain process information, which includes process feature information for K process angles, and the process feature information includes the relationship between voltage and delay of at least one standard cell of threshold type, where K is an integer greater than 1; Based on the design information and the process information, the voltage-frequency curve of the chip design file is predicted. The voltage-frequency curve is used to indicate the correspondence between the voltage and frequency of the chip corresponding to the chip design file.

2. The method according to claim 1, characterized in that, The step of predicting the voltage-frequency curve of the chip design file based on the design information and the process information includes: Based on the design information and the process information, the correspondence between voltage and delay in the chip design file under the K process angles is obtained; Based on the correspondence between voltage and delay in the chip design document at the K process angles, predict the voltage-frequency curve of the chip design document at the K process angles.

3. The method according to claim 2, characterized in that, The design information is a design matrix, and the process information is a process matrix. The step of obtaining the correspondence between voltage and delay in the chip design file under the K process angles based on the design information and the process information includes: Based on the product of the design matrix and the process matrix, the correspondence between voltage and delay in the chip design file under the K process angles is obtained.

4. The method according to claim 2 or 3, characterized in that, For the i-th process angle among the K process angles, where i is a positive integer, the step of predicting the voltage-frequency curve of the chip design document under the K process angles based on the delay information of the chip design document under the K process angles includes: Based on the delay information in the chip design document at the i-th process angle, determine the correspondence between the voltage and the reciprocal of the delay in the chip design document at the i-th process angle; The correspondence between the voltage and the reciprocal of the delay in the chip design file at the i-th process angle is modeled to obtain the voltage-frequency curve of the chip design file at the i-th process angle.

5. The method according to any one of claims 1 to 4, characterized in that, The method further includes: For the chip design document, for each of the K process corners, the path feature information of the N critical paths is extracted to obtain the design information.

6. The method according to claim 5, characterized in that, The design information is a design matrix, which includes K path feature elements. The i-th path feature element in the K path feature elements indicates the path feature information of the N critical paths in the chip design file under the i-th process angle out of K process angles. K is a positive integer, and i is a positive integer less than or equal to K. The path feature information includes at least one of the following: The actual logic level, equivalent logic level, pure logic gate level after excluding buffers, delay ratio of standard cells with different threshold types on the data path, line delay ratio, delay of clock transmission path, delay of capture clock path, clock offset, and clock uncertainty factors.

7. The method according to any one of claims 1 to 6, characterized in that, The relationship between voltage and delay of standard cells with different threshold types at different process angles and temperatures is extracted to obtain the process information.

8. The method according to claim 7, characterized in that, The process information is a process matrix, which includes S*K process feature elements. The p*q-th process feature element among the S*K process feature elements is used to indicate the correspondence between the voltage and delay of at least one standard cell of threshold type under the conditions of the p-th temperature point among S temperature points and the q-th process angle among K process angles. S and K are positive integers, p is a positive integer less than or equal to S, and q is a positive integer less than or equal to K.

9. The method according to claim 8, characterized in that, The correspondence between voltage and delay is obtained by simulating the FO4 delay of inverters or buffers of different threshold types with voltage changes at a specific temperature point under the process angle.

10. The method according to any one of claims 1 to 9, characterized in that, The method further includes: Obtain the post-silicon testing results of the chip, the post-silicon testing results including the correspondence between the voltage and frequency actually measured by the chip; Based on the difference between the post-silicon testing results and the voltage-frequency curve, at least one of the design information and the process information is adjusted, and the adjusted design information or the adjusted process information is used to re-predict the voltage-frequency curve of the chip design document.

11. The method according to claim 10, characterized in that, The method further includes: Based on the post-silicon testing results, the yield prediction model corresponding to the chip design file is adjusted to obtain the adjusted yield prediction model, which is used to predict the yield of the chip.

12. The method according to any one of claims 1 to 11, characterized in that, The method further includes: Based on the voltage-frequency curve in the chip design document, determine the voltage-frequency change under at least one voltage drop, and the voltage-frequency change under at least one voltage drop is used to guide the design of the chip.

13. A device for predicting voltage-frequency curves, characterized in that, The device includes: The design information acquisition module is used to acquire design information, which includes path feature information of N critical paths in the chip design file under different process angles, where N is an integer greater than 1; A process information acquisition module is used to acquire process information, which includes process feature information of K process corners. The process feature information includes the relationship between voltage and delay of at least one standard cell of threshold type, where K is an integer greater than 1. The curve determination module is used to predict the voltage-frequency curve of the chip design file based on the design information and the process information. The voltage-frequency curve is used to indicate the correspondence between the voltage and frequency of the chip corresponding to the chip design file.

14. The apparatus according to claim 13, characterized in that, The curve determination module is used for: Based on the design information and the process information, the correspondence between voltage and delay in the chip design file under the K process angles is obtained; Based on the correspondence between voltage and delay in the chip design document at the K process angles, predict the voltage-frequency curve of the chip design document at the K process angles.

15. The apparatus according to claim 14, characterized in that, The design information is a design matrix, the process information is a process matrix, and the curve determination module is used for: Based on the product of the design matrix and the process matrix, the correspondence between voltage and delay in the chip design file under the K process angles is obtained.

16. The apparatus according to any one of claims 13 to 15, characterized in that, The device further includes: The result acquisition module is used to acquire the post-silicon testing results of the chip, the post-silicon testing results including the correspondence between the voltage and frequency actually measured by the chip; An information adjustment module is used to adjust at least one of the design information and the process information based on the difference between the post-silicon testing results and the voltage-frequency curve. The adjusted design information or the adjusted process information is used to re-predict the voltage-frequency curve of the chip design document.

17. The apparatus according to claim 16, characterized in that, The information adjustment module is also used for: Based on the post-silicon testing results, the yield prediction model corresponding to the chip design file is adjusted to obtain the adjusted yield prediction model, which is used to predict the yield of the chip.

18. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that is loaded and executed by the processor to implement the voltage frequency curve prediction method as described in any one of claims 1 to 12.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the voltage frequency curve prediction method as described in any one of claims 1 to 12.

20. A computer program product, characterized in that, The computer program product includes a computer program that is loaded and executed by a processor to implement the voltage frequency curve prediction method as described in any one of claims 1 to 12.

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