An addition tree architecture supporting DNN sparse perception and an implementation method thereof

Abstract

The application relates to the technical field of artificial intelligence chips, and particularly discloses an addition tree architecture supporting DNN sparse sensing and an implementation method thereof. The architecture comprises an index and data reordering module, a reconfigurable sparse addition array, an address mapping module, a partial sum storage area and an interface control unit thereof. The dynamic accumulation of random sparse data is realized by indexing and reordering the sparse multiplication results and adopting an adder array activated only when the indexes are consistent. The architecture removes the local accumulators in the traditional processing units, supports the parallel operation of calculation and accumulation decoupling, effectively improves the hardware utilization and accumulation efficiency, is suitable for the efficient addition accumulation of various neural network layers such as convolution, full connection and normalization, and has the advantages of strong structure universality, high energy efficiency ratio and low area overhead.

Description

Technical Field

[0001] This invention belongs to the field of on-chip self-learning accelerated computing for artificial intelligence chips, specifically involving an addition tree architecture that supports DNN sparse perception and its implementation method. Background Technology

[0002] With the widespread application of DNN (Deep Neural Network) in fields such as image recognition, natural language processing, and autonomous driving, the demand for hardware acceleration of DNN computation is increasing. To improve processing efficiency and reduce energy consumption, various DNN accelerators are constantly being developed, becoming one of the core directions in current artificial intelligence chip design.

[0003] In typical DNN computations, numerous convolutional and fully connected operations are primarily comprised of MAC (Multiply-Accumulate) operations. While many accelerator designs have optimized the MAC structure, these designs generally assume dense input data and fail to adequately consider the data sparsity prevalent in DNN models. In recent years, with the development of techniques such as model pruning and quantization, the weight matrices and feature maps in DNNs often exhibit high sparsity. For example, the sparsity of pruned weights can reach 90%, and the activation sparsity under the ReLU function can exceed 50%. How to effectively utilize this sparsity has become a key technical challenge for improving accelerator performance and energy efficiency.

[0004] Several sparse-aware accelerator designs have been proposed, mainly focusing on: sparse scheduling based on non-zero data; skipping zero-value computation to reduce multiplier resources; and using sparse indexes to compress storage. However, most designs still focus on optimizing the front-end multiplication stage, with less optimization for the post-multiplication accumulation operation and the inter-channel accumulation stage. Although these back-end operations have a small computational load each time, they occur frequently and usually consume a large amount of local cache or shared addition tree resources. Without optimization, this will lead to the following problems: 1. Large local buffer usage: Traditional designs set up a storage area within each PE (Processing Element) to temporarily store computation results, resulting in a significant increase in chip area; 2. PE and addition tree modules cannot be parallelized: The accumulation operation usually can only start after the PE calculation is completed. The addition tree and PE cannot be piped in parallel, which seriously affects the throughput. 3. High index dynamism and difficulty in accumulation: Due to the variable position and quantity of sparse input data, traditional fixed-structure addition trees are difficult to adapt to different indexing scenarios and lack versatility.

[0005] Existing designs attempt to alleviate the aforementioned problems using pipelined addition trees, but these typically require a fixed input format (e.g., dense, ordered), making it difficult to handle out-of-order sparse input data and exhibiting poor adaptability. Therefore, there is an urgent need for an addition tree structure capable of dynamically handling random sparse indices, which can achieve efficient data accumulation while reducing storage overhead and improving overall operational efficiency. Summary of the Invention

[0006] To address the series of cross-channel accumulation problems introduced by sparsity in current DNN accelerators and overcome the performance bottleneck of existing DNN accelerators in the accumulation stage, this invention proposes an addition tree architecture and its implementation method that supports DNN sparsity awareness. This addition tree architecture optimizes the accumulation operation of the result after multiplication in DNN, supports dynamic accumulation of sparse indexes, and coordinated optimization of computing and storage resources. It has the characteristics of high parallelism and high adaptability, which can significantly improve computing efficiency and reduce chip resources.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: An addition tree architecture supporting DNN sparsity awareness includes: The index reordering module is used to sort the input sparse multiplication results by index in real time. The data reordering module is used to reorder the data calculated by the PE array based on the results of the index reordering module. A reconfigurable sparse adder array is used to process out-of-order sparse input data. It includes multiple pipelined adder units and registers. Each pipelined adder unit is configured with an index comparator and an interconnect selector. When the input indices match, the addition operation is performed. Otherwise, the input data is bypassed or buffered through registers to the next layer for processing. The address mapping module is used to map the indices of each input channel output by the addition tree to the addresses of the partial and memory areas; The partial sum storage module is used to store the intermediate results of the reconstructable sparse addition array output in the addressing mode of index and output channel. When a duplicate index appears, the data in the partial sum storage area that is the same as the output index of the addition tree is retrieved for the addition tree to accumulate, perform incremental addition and write back to the original address.

[0008] A further improvement of the present invention is that the index reordering module is a Bitonic sorting network, used to sort the index data of multiple input channels in ascending order.

[0009] A further improvement of the present invention is that the reconfigurable sparse adder array supports 2... n The exponentially expanded number of inputs is used, employing an n-layer pipeline structure, with each layer consisting of 2... n-1 An index-driven pipelined adder unit and registers.

[0010] A further improvement of the present invention is that the output path of the pipeline adder unit is controlled by the index comparison result, and the addition, forwarding or buffering is determined by the interconnection logic.

[0011] A further improvement of the present invention is that the pipeline adder unit of the reconfigurable sparse adder array supports path gating control, which automatically shuts down the corresponding path to reduce power consumption when the input data is invalid or the index does not match.

[0012] A further improvement of the present invention is that the address mapping module uses a two-dimensional row and column index table to manage the mapping relationship between the index and the storage area, and the output address is a one-hot code.

[0013] A further improvement of the present invention is that the address mapping module is set between the adder tree array and the partial sum storage area. It is responsible for mapping the accumulation result output by the adder tree of the reconfigurable sparse adder array to the corresponding partial sum storage area according to its output channel and index, and for retrieving the data in the partial sum storage area that has the same index as the adder tree output and sending it to the adder tree for accumulation operation.

[0014] A further improvement of the present invention is that the storage area is organized in a two-dimensional structure, with the vertical grouping based on the number of output channels T and the horizontal grouping based on the depth of the storage cells F.

[0015] A further improvement of this invention is that the addition tree architecture is applicable to computational scenarios involving the efficient accumulation of sparse computation results in deep neural network structures such as convolutional layers, fully connected layers, and batch normalization layers.

[0016] An implementation method for an addition tree architecture supporting DNN sparsity awareness includes: The index reordering module sorts the input sparse multiplication results by index in real time; The data reordering module reorders the data calculated by the PE array based on the results of the index reordering module. The reconfigurable sparse adder array processes out-of-order sparse input data. Each pipeline adder unit is equipped with an index comparator and an interconnect selector. When the input indices match, the addition operation is performed. Otherwise, the input data is bypassed or buffered to the next layer for processing via registers. The address mapping module maps the indices of each input channel output by the adder tree to the addresses of the partial and memory areas; The partial sum storage module stores the intermediate results of the reconstructable sparse addition array output using index and output channel addressing. When a duplicate index appears, it retrieves the data in the partial sum storage area that is the same as the output index of the addition tree for the addition tree to accumulate, performs incremental addition, and writes it back to the original address.

[0017] The present invention has at least the following beneficial technical effects: This invention designs an index reordering and data reordering module for real-time reordering of sparse multiplication results output by a PE array based on their index values, ensuring that results at the same position can be effectively merged. This invention also designs a reconfigurable sparse adder array capable of dynamically identifying and accumulating data with the same index; it introduces a partial storage area and removes the local accumulator within the PE array, moving the accumulation function to the adder tree for unified completion; this invention achieves parallel operation of the PE array and the adder tree through a pipelined control mechanism, reducing waiting time; the inter-adder connections of the reconfigurable sparse adder array are controlled by an index comparator, effectively realizing dynamic accumulation.

[0018] This invention addresses key issues in existing DNN accelerators when processing highly sparse models, such as large local cache resource consumption, inability to parallelize computational units, rigid accumulation module structure, and difficulty in adapting sparse indexes. It proposes a sparse-aware addition tree architecture and its implementation method for deep neural network accelerators, achieving the following technical effects: Significantly reduces accelerator chip area resource consumption. In traditional DNN accelerators, in order to handle the accumulation of intermediate values ​​of multiplication results, a local buffer is often set in each PE to store part of the sum, resulting in redundancy of local storage resources and a large proportion of the total area.

[0019] This invention centralizes all accumulation operations into a reconfigurable sparse adder array, eliminating the internal accumulator of the PE (Programmable Entity). The reconfigurable sparse adder array handles all sparse data accumulation across channels, significantly reducing the amount of local storage resources and area occupied. Because the accumulation is performed uniformly within the reconfigurable sparse adder array, it simplifies the structure and control logic of the PE, reduces logic area and power consumption, and allows accumulation calculations to be performed across PEs, supporting cross-channel collaborative accumulation, enabling resource sharing and reuse, and improving resource utilization. This structure effectively alleviates the area bottleneck caused by the increase in the number of on-chip registers, and also lays the foundation for subsequent modular design and chip scalability. Experimental results show that, using TSMC's 65nm process, the area efficiency is improved by approximately 1.71 times compared to the reference design.

[0020] This invention significantly improves the matching rate of adders in each stage of the pipeline structure through indexing and data reordering. This ensures that data with the same index can meet and be added in the correct adder, reducing path bypassing and latency buildup caused by mismatches. This design improves adder efficiency, especially in network models with high index sparsity.

[0021] This invention decouples the PE computation and accumulation process by employing a reconfigurable adder array and a dynamic index scheduling mechanism, enabling parallel computation of the PE array and the adder tree, thus significantly improving overall throughput. In traditional structures, the PE array and the adder tree are sequentially dependent; the former must wait for the latter to complete its accumulation before it can continue, creating a pipeline bottleneck. When processing pruned ResNet18 networks (90% weight sparsity), the computational speedup is improved by approximately 1.39 times.

[0022] This invention avoids redundant storage and effectively reduces hardware size by centralizing local buffers into a portion of the shared addition tree module and storage area, and by combining a pipeline mechanism with unified management. Attached Figure Description

[0023] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is the overall architecture of the sparse-aware addition tree based on random index proposed in this invention.

[0025] Figure 2 This is a schematic diagram of an index reordering module based on the bitone sorting algorithm.

[0026] Figure 3 This is a diagram of the reconfigurable sparse additive array architecture proposed in this invention.

[0027] Figure 4 This is a schematic diagram of the reconfigurable sparse adder array circuit proposed in this invention.

[0028] Figure 5 This is a schematic diagram of the mapping logic of the address mapping module proposed in this invention.

[0029] Figure 6 This is a schematic diagram of the partial and storage area read / write process proposed in this invention. Detailed Implementation

[0030] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0031] In the description of this invention, it should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0032] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0033] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0034] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0035] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0036] Example 1: An addition tree architecture supporting DNN sparse awareness, comprising: The index reordering module is used to sort the input sparse multiplication results by index in real time. The data reordering module is used to reorder the data calculated by the PE array based on the results of the index reordering module. A reconfigurable sparse adder array is used to process out-of-order sparse input data. It includes multiple pipelined adder units and registers. Each pipelined adder unit is configured with an index comparator and an interconnect selector. When the input indices match, the addition operation is performed. Otherwise, the input data is bypassed or buffered through registers to the next layer for processing. The address mapping module is used to map the indices of each input channel output by the addition tree to the addresses of the partial and memory areas; The partial sum storage module is used to store the intermediate results of the reconstructable sparse addition array output in the addressing mode of index and output channel. When a duplicate index appears, the data in the partial sum storage area that is the same as the output index of the addition tree is retrieved for the addition tree to accumulate, perform incremental addition and write back to the original address.

[0037] In this embodiment, the index reordering module is a Bitonic sorting network, used to sort the index data of multiple input channels in ascending order.

[0038] In this embodiment, the reconfigurable sparse adder array supports 2... n The exponentially expanded number of inputs is used, employing an n-layer pipeline structure, with each layer consisting of 2... n-1 An index-driven pipelined adder unit and registers.

[0039] In this embodiment, the output path of the pipeline adder unit is controlled by the index comparison result, and the addition, forwarding or caching is determined by the interconnection logic.

[0040] In this embodiment, the pipeline adder unit of the reconfigurable sparse adder array supports path gating control, which automatically shuts down the corresponding path to reduce power consumption when the input data is invalid or the index does not match.

[0041] In this embodiment, the address mapping module uses a two-dimensional row and column index table to manage the mapping relationship between the index and the storage area, and the output address is a one-hot code.

[0042] In this embodiment, the address mapping module is located between the adder tree array and the partial sum storage area. It is responsible for mapping the accumulated result output by the reconfigurable sparse adder array adder tree to the corresponding partial sum storage area according to its output channel and index, and for retrieving data in the partial sum storage area that has the same index as the adder tree output and sending it to the adder tree for accumulation operation.

[0043] In this embodiment, the storage area is organized in a two-dimensional structure, with the vertical grouping based on the number of output channels T and the horizontal grouping based on the depth of the storage unit F.

[0044] In this embodiment, the addition tree architecture is suitable for computational scenarios involving the efficient accumulation of sparse computation results in deep neural network structures such as convolutional layers, fully connected layers, and batch normalization layers.

[0045] Example 2: Overall Architecture and Module Connection Method of Sparse-Aware Addition Tree Based on Random Index This invention discloses a sparsity-aware addition tree architecture supporting DNNs and its implementation method. It proposes a sparsity-aware addition tree architecture based on random indexing. This technical solution is applicable to all DNN layers involving sparse data summation and channel accumulation, including convolutional layers, fully connected layers, and normalization layers. The invention adopts the following technical solution: Figure 1 The overall architecture of the sparse-aware addition tree proposed in this invention is shown. Its core structure includes: PE array, index reordering module and data reordering module, reconfigurable sparse addition array, address mapping module and partial storage area.

[0046] In this architecture, the input is divided into feature map data and its indices. The PE array performs multiplication operations on the input sparse feature map data and weights, where parameter M is the convolution kernel dimension and parameter N is the number of input channels that the accelerator can compute in a single pass. The index reordering module sorts the input indices in ascending order, and the data reordering module rearranges the data according to the index reordering result. Simultaneously, to ensure that the data output by the PE array is time-synchronized with the index reordering result, a buffer circuit is added before the data input to the PE array to stifle the data.

[0047] The rearranged data is fed into an adder tree array, which contains N adder trees (AT1~ATN). Each adder tree contains a reconfigurable sparse adder array that dynamically adds and accumulates data pairs with the same index. The output of the reconfigurable sparse adder array is input to an address mapping module. The address mapping module maps the data to registers in the partial and memory areas according to the index. If the corresponding index already has a value, the addition and accumulation are performed; otherwise, the initial value is written directly. This design eliminates the local accumulator and buffer in the PE (Programmer), enabling parallel operation of the computation unit and the adder tree.

[0048] Example 3: Index Reordering Module Structure The index data reordering module is a crucial pre-construction component of the sparse-aware addition tree structure. Its function is to dynamically and in real-time sort the sparse multiplication results from the PE array according to their index values, providing an ordered input data stream for subsequent accumulation operations in the addition tree. The module's input is a set of output data from the PE array, in the format Index[i]. The index represents the position of the data in the feature map. To sort the input data in ascending order according to the index, this invention uses a Bitonic sorting network for data processing. This network supports fully parallel sorting, has high throughput and pipelining capabilities, and is suitable for small-scale static input scenarios in chip design.

[0049] The principle of the Bitonic sorting module is as follows: Figure 2As shown, the sorting network consists of several levels of comparators, each level performing pairwise comparisons and swaps of data pairs. For a fully sorted network with n=8 inputs, a total of log2(n)×(log2(n)+1) / 2 levels of comparator structure are required. Each comparator unit contains: two input ports (Index[i], Index[i+1]), one index comparator (used to compare the two input indices), and two output ports (if Index[i]≤ Index[i+1], output in the original order; otherwise, swap the outputs). Each level of the sorting network is connected to a register to achieve high-frequency operation; all data is output after a fixed delay of log2(n) cycles.

[0050] Example 4: Design of a reconfigurable sparse additive array To address the inefficiency and resource waste inherent in traditional addition trees when processing sparse input data, and to improve the efficiency of sparse data summation operations in deep neural network accelerators, this invention proposes a reconfigurable sparse addition array to replace conventional fixed-connection adder networks, enabling dynamic accumulation of random sparse index data.

[0051] Figure 3 This demonstrates the architecture of a reconfigurable sparse adder array, which is the core construction of the entire adder tree. The reconfigurable sparse adder array is organized in a pipeline structure, receiving multiple sets of information streams with sparse indices as input. If the number of inputs is 2... n Then the number of rows and columns of the array are n and 2 respectively. n The number of pipeline adder units and registers required for each row is 2. n-1 Each register and adder's input and output contain an index and data, and the input indices of the left and right operands of each adder must be equal. In each cycle, each adder adds the input data of its left and right operands, and then uses the input index and the result of the adder's operation as the output index and output data, respectively. Each register only needs to delay its input by one cycle to obtain its output.

[0052] Specifically, for the first row, the left operand of the adder in column 2i is the 2i-th input data, and the right operand of the adder in column 2i is determined by comparing the indices of the 2i and 2i+1 inputs. If these two indices are equal, the 2i+1-th input data will be assigned to the right operand of the adder in column 2i. If they are not equal, the 2i+1-th input data will be assigned to the register in column 2i+1, and the right operand of the adder in column 2i will be set to 0, where i = 0, 1, ..., 7.

[0053] Furthermore, if the output of an adder or register in the reconfigurable sparse adder array is assigned as the right operand of an adder in the next row, then the corresponding register and adder in the column containing that output and the next column will be marked as invalid and turned off. Otherwise, the output will be sent to the input of a register or adder in the current position or adjacent column of the next row. For the second row, the left operand of each adder comes from the output of the corresponding column in the first row; simultaneously, the output of the i-th column in the first row can be sent to the right operand of the adder in the (i-2)-th or (i-1)-th column in the second row, depending on the index comparison result. The output index of the i-th column will be compared sequentially with the indices of the (i-2)-th and (i-1)-th columns: if the indices are equal, the output will be sent to the right operand of the corresponding adder; if they are not equal, the output will be temporarily stored in the register in the i-th column of the second row, where i = 2, 6, 10, 14. Furthermore, the interconnection method between subsequent adjacent rows is similar to the connection method between the first and second rows.

[0054] To more clearly describe the proposed reconfigurable sparse adder array, a typical case with 8 inputs is selected as a reference, and its specific circuit is shown in Figure 4. It is assumed that the inputs to the reconfigurable sparse adder array have been sorted by the aforementioned data reordering module. The reconfigurable sparse adder array can dynamically accumulate input data based on index values. The input data stream is passed from top to bottom, and the accumulation condition is determined layer by layer through multiple pipeline stages. Finally, combined with the data reordering module, the reconfigurable sparse adder array proposed in this invention can efficiently perform cross-channel accumulation operations in sparse neural networks.

[0055] The entire reconfigurable sparse adder array, through its dynamic index-driven mechanism, enables dynamic accumulation of any number of non-zero values ​​in the input data, regardless of their distribution or location, without requiring prior dense alignment or forced encoding of the input. This structure is particularly suitable for accumulating multiplication results in high-sparse-rate deep neural network models. Finally, each accumulated result is output to the next layer buffer structure or partial sum storage area, written to the corresponding location according to its index. The reconfigurable sparse adder array not only improves the utilization of accumulation resources but also reduces power consumption and processing latency. This structure employs a dynamic interconnection mechanism controlled by index values ​​between data paths, allowing for flexible adjustment of computation paths and enabling step-by-step accumulation of sparse data in different pipeline layers. The reconfigurable sparse adder array supports input data with arbitrary sparsity and random distribution. By enabling signals to gate adder paths not involved in computation, dynamic power consumption is significantly reduced. Furthermore, this structure eliminates the need for local accumulators or buffers in processing units; all accumulation operations are performed within the adder tree, thereby reducing chip area and improving the versatility and resource utilization efficiency of addition operations. The reconfigurable sparse adder array can run in parallel with the upstream multiplier array, supporting high-throughput pipeline processing, and is especially suitable for neural network models with sparse weights and sparse activations.

[0056] Example 5: Address Mapping Module and Partial Storage Area Design To support efficient indexing, accumulation, and storage of sparse multiplication results, this embodiment provides a configurable mapping mechanism jointly controlled by the output channel and the index, as well as a corresponding part and storage area for storing intermediate accumulation results and supporting subsequent accumulation and reading operations.

[0057] In this embodiment, the address mapping module is located between the adder tree array and the partial sum memory area. It is responsible for mapping the accumulated result output from the reconfigurable sparse adder array (adder tree) to the corresponding register group according to its output channel and index, and for retrieving data from the partial sum memory area that has the same index as the adder tree output and sending it to the adder tree for accumulation. Its mapping logic is as follows: Figure 5 As shown, assuming there are M input channels of data, they need to be mapped to F registers in the partial and memory areas, where F is the feature map size. The mapping module uses a two-dimensional row and column index table to manage the mapping relationship between the output channels and the register group, outputting M one-hot code addresses, each with a bit width of F.

[0058] like Figure 6As shown, the partial sum and storage areas are organized in a two-dimensional structure, grouped vertically by the number of output channels T, and horizontally by the storage cell depth F. Each group of buffer registers is used to store the accumulation results at a specific output channel and feature map location. Whenever the adder tree outputs a set of accumulation results, its index is compared with the current partial sum and storage area content: if the target index has not yet been written to the partial sum and storage area, the result is directly written to the corresponding address; if the address already contains partial sum data, the internal adder is started to complete further accumulation operations. The column index for writing or reading data is determined according to the output channel number (1~T) corresponding to the current write cycle. This design allows multiple adder tree units to poll and write to different output channels in different time slices, avoiding write conflicts. This module adopts a fully pipelining data interaction protocol with the reconfigurable sparse adder array, which supports decoupling of data writing and reading, ensuring that the adder tree runs continuously without blocking, and is one of the key components for realizing efficient sparse accumulation.

[0059] Example 6: An implementation method for an addition tree architecture supporting DNN sparse awareness, comprising: The index reordering module sorts the input sparse multiplication results by index in real time; The data reordering module reorders the data calculated by the PE array based on the results of the index reordering module. The reconfigurable sparse adder array processes out-of-order sparse input data. Each pipeline adder unit is equipped with an index comparator and an interconnect selector. When the input indices match, the addition operation is performed. Otherwise, the input data is bypassed or buffered to the next layer for processing via registers. The address mapping module maps the indices of each input channel output by the adder tree to the addresses of the partial and memory areas; The partial sum storage module stores the intermediate results of the reconstructable sparse addition array output using index and output channel addressing. When a duplicate index appears, it retrieves the data in the partial sum storage area that is the same as the output index of the addition tree for the addition tree to accumulate, performs incremental addition, and writes it back to the original address.

[0060] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the scope of the invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0061] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be appropriately combined to form other embodiments that can be understood by those skilled in the art. The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. An addition tree architecture supporting DNN sparse awareness, characterized in that, include: The index reordering module is used to sort the input sparse multiplication results by index in real time. The data reordering module is used to reorder the data calculated by the PE array based on the results of the index reordering module. A reconfigurable sparse adder array is used to process out-of-order sparse input data. It includes multiple pipelined adder units and registers. Each pipelined adder unit is configured with an index comparator and an interconnect selector. When the input indices match, the addition operation is performed. Otherwise, the input data is bypassed or buffered through registers to the next layer for processing. The address mapping module is used to map the indices of each input channel output by the addition tree to the addresses of the partial and memory areas; The partial sum storage module is used to store the intermediate results of the reconstructable sparse addition array output in the addressing mode of index and output channel. When a duplicate index appears, the data in the partial sum storage area that is the same as the output index of the addition tree is retrieved for the addition tree to accumulate, perform incremental addition and write back to the original address.

2. The addition tree architecture supporting DNN sparse awareness according to claim 1, characterized in that, The index reordering module is a Bitonic sorting network used to sort the index data of multiple input channels in ascending order.

3. The addition tree architecture supporting DNN sparse awareness according to claim 1, characterized in that, The reconfigurable sparse adder array supports 2... n The exponentially expanded number of inputs is used, employing an n-layer pipeline structure, with each layer consisting of 2... n-1 An index-driven pipelined adder unit and registers.

4. An addition tree architecture supporting DNN sparse awareness according to claim 3, characterized in that, The output path of the pipeline adder unit is controlled by the index comparison result, and the interconnection logic determines whether to perform addition, forwarding, or caching.

5. An addition tree architecture supporting DNN sparse awareness according to claim 3, characterized in that, The pipelined adder unit of the reconfigurable sparse adder array supports path gating control, which automatically shuts down the corresponding path to reduce power consumption when the input data is invalid or the index does not match.

6. An addition tree architecture supporting DNN sparse awareness according to claim 1, characterized in that, The address mapping module uses a two-dimensional row and column index table to manage the mapping relationship between the index and the storage area, and the output address is a one-hot code.

7. An addition tree architecture supporting DNN sparse awareness according to claim 1, characterized in that, The address mapping module is located between the adder tree array and the partial sum storage area. It is responsible for mapping the accumulated result output by the reconfigurable sparse adder array adder tree to the corresponding partial sum storage area according to its output channel and index, and for retrieving data in the partial sum storage area that has the same index as the adder tree output and sending it to the adder tree for accumulation operation.

8. An addition tree architecture supporting DNN sparse awareness according to claim 1, characterized in that, The storage area is organized in a two-dimensional structure, with vertical groups based on the number of output channels (T) and horizontal groups based on the depth of the storage cells (F).

9. An addition tree architecture supporting DNN sparse awareness according to claim 1, characterized in that, The additive tree architecture is suitable for computational scenarios involving the efficient accumulation of sparse computation results in deep neural network structures such as convolutional layers, fully connected layers, and batch normalization layers.

10. A method for implementing an addition tree architecture supporting DNN sparse awareness, as described in any one of claims 1 to 9, characterized in that, include; The index reordering module sorts the input sparse multiplication results by index in real time; The data reordering module reorders the data calculated by the PE array based on the results of the index reordering module. The reconfigurable sparse adder array processes out-of-order sparse input data. Each pipeline adder unit is equipped with an index comparator and an interconnect selector. When the input indices match, the addition operation is performed. Otherwise, the input data is bypassed or buffered to the next layer for processing via registers. The address mapping module maps the indices of each input channel output by the adder tree to the addresses of the partial and memory areas; The partial sum storage module stores the intermediate results of the reconstructable sparse addition array output using index and output channel addressing. When a duplicate index appears, it retrieves the data in the partial sum storage area that is the same as the output index of the addition tree for the addition tree to accumulate, performs incremental addition, and writes it back to the original address.

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