A decoding method

Abstract

A decoding method, the decoding method is on: acquire X bit binary number, map the binary number directly as line state block representing line state;The binary number and the line state block correspond one by one;The line state block contains 1 or N line state values;According to the line state value of the line state block, the A line, B line and C line of C-PHY are driven to be in the line state corresponding to the line state value, wherein the line state is the voltage combination of A line, B line and C line.Further, a flag bit is set to reduce the number of binary encoding bits and improve the encoding efficiency.The present application reduces the complexity of the encoding and decoding circuit, maintains the integrity of the information transmitted in the encoding and decoding process, and improves the encoding efficiency and transmission real-time through a series of methods such as flag bit, line state sub-block and the like.

Description

Technical Field

[0001] This invention relates to the field of C-PHY signal transmission, specifically to a method for demapping binary codes to line states in C-PHY, thereby reducing the overhead and latency caused by line state decoding and encoding. Furthermore, the aforementioned binary codes are transmitted as serial signals and converted into parallel data. This invention can reduce the number and diameter of transmission media, such as copper cables or optical cables. Background Technology

[0002] The MIPI Alliance defines a set of interface standards that standardize internal interfaces of mobile devices, such as cameras, displays, baseband, and RF interfaces. This increases design flexibility while reducing cost, design complexity, power consumption, and EMI (Electromagnetic Interference). C-PHYs achieve high throughput performance through bandwidth-limited channels, such as connecting displays and cameras to application processors. It provides PHYs for the MIPI Camera Serial Interface (MIPI CSI-2) and MIPI Display Interface (MIPI CSI-2) ecosystems, helping designers extend their implementations to support a variety of higher-resolution image sensors and displays.

[0003] The MIPI Alliance's publicly released C-PHY protocol (Specification for C-PHY Version 2.1) uses a channel configuration called "Trio." Each Trio consists of three wires used for data transmission, representing a data channel. C-PHY transmission channels have three modes: HS (high speed) Mode, LP (Low-Power) Mode, and ALP (Alternate Low-Power) Mode. HS Mode transmission lines have six states: +x, -x, +y, -y, +z, and –z. LP Mode transmission lines have four states: LP-000, LP-001, LP-100, and LP-111. In addition to the six states of HS Mode, ALP Mode defines two more states: ALP-Pause state (VOD = 0) and ALP-Pause Wake state (VOD = |VOD|Strong). Except for the two states related to ALP Pause, the other states in ALP Mode are the same as those in HS wire State. These states are also called wire states.

[0004] C-PHY is based on 3-Phase symbol encoding technology, using three wires (A / B / C) to transmit signals instead of the differential pairs used previously. It transmits 2.28 bits / symbol via three-wire trios, with a target rate of 8 Gsymbols / s. C-PHY uses 5-ary transmission, which is 2.28 times more efficient than the binary transmission of D-PHY.

[0005] In traditional C-PHY transmission schemes, one C-PHY signal requires three copper wires for transmission. The cables are relatively thick and are quite sensitive to electromagnetic interference. The higher the speed, the shorter the transmission distance, which limits the application scenarios.

[0006] With the rapid development of intelligent driving, in-vehicle systems now involve multiple displays and multiple video captures, making them increasingly sensitive to transmission latency and placing high demands on the number of cables and the distance between them. How to reduce cable diameter, increase transmission distance, and simultaneously reduce transmission latency to improve system compatibility is a pressing issue that needs to be addressed when C-PHY is applied to complex, multi-channel, long-distance systems.

[0007] Therefore, simplifying the complexity of encoding and decoding, reducing data transmission volume, improving the real-time performance of signal transmission, and making it applicable to existing C-PHY transmission devices, improving the transmission medium, and enhancing system compatibility have become urgent technical problems to be solved in order to further expand the application of C-PHY. Summary of the Invention

[0008] The purpose of this invention is to propose an encoding and decoding method and circuit for transmitting C-PHY signals, which directly maps the received C-PHY line status values ​​into binary coded numbers and transmits them on the data link through a single optical fiber or a set of differential copper wires. The encoding circuit has low complexity, good integrity of encoded information, and low transmission delay.

[0009] To achieve this objective, the present invention adopts the following technical solution:

[0010] In a first aspect, the present invention discloses an encoding method for transmitting C-PHY signals. According to the mode of the C-PHY transmission channel, the line status of the A line, B line and C line of the C-PHY transmission channel is obtained and a line status block is generated, wherein the line status is the voltage combination of the A line, B line and C line; and the line status block is mapped to a binary number that can uniquely identify the line status block.

[0011] Optionally, the line status block is directly mapped to an X-bit binary number, so that the X-bit binary number uniquely represents the different values ​​of the line status block.

[0012] Optionally, in the process of directly mapping the line state block to an X-bit binary number, the symbols represented by adjacent line states are not recognized.

[0013] Optionally, the line state block includes at least one real wire state value; and the line state block includes zero, one, or more dummy wire state values.

[0014] Optionally, the real wire state value is a voltage combination (wire state) value obtained by sampling the real voltages of the A, B, and C lines respectively.

[0015] Optionally, the mode in which the transmission channel of C-PHY is located includes the HS (high speed) mode and the non-HS mode, and the non-HS mode includes the LP (low speed) mode and the ALP (Alternate Low-Power) mode.

[0016] Optionally, if the mode in which the transmission channel of C-PHY is located is the LP mode, the generated line state block is the second line state block, and the second state block only includes one line state value; the X-bit binary number directly mapped from the second line state block only represents one line state value of the LP mode; if the mode in which the transmission channel of C-PHY is located is the ALP mode, the generated line state block is the third line state block, and the third state block only includes one line state value; wherein, the X-bit binary number directly mapped from the third line state block only represents one line state value of the ALP mode.

[0017] Optionally, if the mode in which the transmission channel of C-PHY is located is the HS mode, the generated line state block is the first line state block, and the first line state block includes N line state values; where the N line state values include at least one real wire state value of the HS mode.

[0018] Optionally, if the mode in which the transmission channel of C-PHY is located is the HS mode, in response to obtaining N consecutive line states, a complete line state block including N real wire state values corresponding to the N line states is generated, and the complete line state block belongs to the first line state block.

[0019] Optionally, in response to the transmission channel of C-PHY switching from the HS mode to the non-HS mode, if M line states for generating the first line state block have been obtained and M < N, an incomplete line state block is generated, where the incomplete line state block includes M real wire state values corresponding to the M line states and N - M dummy wire state values; the incomplete line state block belongs to the first line state block.

[0020] Optionally, when the first line status block is directly mapped to an X-bit binary number that uniquely identifies the first line status block, the X-bit binary number represents the N line status values ​​when the C-PHY's transmission channel is in HS mode.

[0021] Optionally, when an incomplete line state block is directly mapped to an X-bit binary number that uniquely identifies the first line state block, the X-bit binary number represents the M real line state values ​​and NM virtual line state values ​​of the HS mode.

[0022] Optionally, X is satisfied Integers.

[0023] Optionally, X is satisfied The smallest integer.

[0024] Optionally, X = 1 + L, where 1 bit of the X-bit binary number represents whether the line state block is the first, second, or third line state block; for the first line state block, it is encoded as L bits of the X-bit binary number, where L satisfies An integer; for the second or third line status block, it is encoded as an L-bit binary number in an X-bit binary number.

[0025] Optionally, X = 1 + L, where 1 bit of the X-bit binary number represents whether the line state block is a complete line state block of the first line state block, an incomplete line state block of the first line state block, a second line state block, or a third line state block; for a complete line state block of the first line state block, it is encoded as an L-bit binary number in the X-bit binary number, where L is the number of bits that satisfy the condition... An integer; for an incomplete line state block of the first line state block, the second line state block, or the third line state block, it is encoded as an L-bit binary number in an X-bit binary number.

[0026] Optionally, the first line state block contains k line state sub-blocks, each containing m line state values, where N = k × m, and both k and m are integers.

[0027] Optionally, k line state sub-blocks are generated from the first line state block; or, in response to obtaining m consecutive line states of lines A, B, and C, a line state sub-block including m line state values ​​corresponding to the m line states is generated, and the first line state block is obtained by combining the k consecutive line state sub-blocks.

[0028] Optionally, directly mapping the first line status block to an X-bit binary number includes encoding each line status sub-block of the first line status block into a p-bit binary number that can uniquely represent all the values of the line status sub-block, and combining the p-bit binary numbers corresponding to k line status sub-blocks of the first line status block to obtain an X-bit binary number.

[0029] Optionally, the line status sub-block is a complete line status sub-block or an incomplete line status sub-block; the complete line status sub-block is generated from m true line status values; the incomplete line status sub-block includes j HS-mode true line status values and m - j virtual line status values, and j < m.

[0030] Optionally, in response to obtaining m consecutive line statuses, a complete line status sub-block including m true line status values corresponding to the m line statuses is generated; in response to the transmission channel of C-PHY switching from the HS mode to a non-HS mode, if j line statuses for generating the first line status block have been obtained and j < m, an incomplete line status sub-block is generated, where the incomplete line status sub-block contains j true line status values corresponding to the j line statuses and m - j virtual line status values.

[0031] Optionally, p is an integer satisfying 2 p >6×5 （m-1） + (m - 1)×6.

[0032] Optionally, p is the smallest integer satisfying 2 p >6×5 （m-1） + (m - 1)×6.

[0033] Optionally, X = L, or X = 1 + L, where L = k×p.

[0034] Optionally, X = L, where when directly mapping the first line status block to an X-bit binary number, each line status sub-block is directly mapped to a p-bit binary number that can uniquely represent all the values of the line status sub-block, and the p-bit binary numbers corresponding to k line status sub-blocks are combined to obtain an X-bit binary number; when directly mapping the second line status block or the third line status block to an X-bit binary number, the second line status block or the third line status block is encoded using the codewords in the X-bit binary number codeword space that are excluded for encoding the first line status block.

[0035] Optionally, X = 1 + L, where 1 bit of the X-bit binary number is used to indicate whether the line state block is the first line state block, the second line state block, or the third line state block; for the first line state block, it is encoded as an L-bit binary number in the X-bit binary number, where L = k × p, and where each line state sub-block is encoded as a p-bit binary number that can uniquely represent all the values ​​of the line state sub-block, and the p-bit binary numbers corresponding to each of the k line state sub-blocks are combined to obtain an L-bit binary number; for the second or third line state block, it is encoded as an L-bit binary number in the X-bit binary number.

[0036] Optionally, the X-bit binary number also includes a flag bit. The first value of the flag bit indicates that the X-bit binary number is encoded by the first line status block; the second value of the flag bit indicates that the X-bit binary number is encoded by the second line status block or the third line status block.

[0037] Optionally, L is the condition that satisfies 2. L >k×6×5 (m-1) An integer consisting of + (m-1)×6.

[0038] Optionally, L is the condition that satisfies 2. L >k×6×5 (m-1) The smallest integer of + (m-1)×6.

[0039] Optionally, L is the condition that satisfies 2. L >k×6×5 (m-1) Integers.

[0040] Optionally, L is the condition that satisfies 2. L >k×6×5 (m-1) The smallest integer.

[0041] Optionally, when the transmission channel is in HS mode, the line status of HS mode is sampled using a first clock, and a first line status block is generated based on the sampled line status.

[0042] Optionally, the first clock is obtained from the line state changes in HS mode.

[0043] Optionally, the first clock is divided by N to obtain the second clock; based on the second clock, the first line status block is mapped to a binary number that can uniquely identify the line status block.

[0044] Optionally, when the transmission channel is in a non-HS mode, the line status of the non-HS mode is sampled, and a second line status block or a third line status block is generated based on each sampling result; according to the second clock, the first line status block, the second line status block or the third line status block is mapped to a binary number that can uniquely identify the line status block.

[0045] Optionally, the binary number is converted from parallel to serial to generate serial data; the serial data is then transmitted through a transmission medium.

[0046] Optionally, converting binary numbers from parallel to serial data to generate serial data further includes inserting a synchronization code and converting the synchronization code from parallel to serial data.

[0047] Optionally, the synchronization code insertion includes periodically inserting the synchronization code before the first binary number is transmitted, when switching between HS line state and non-HS line state, or when the non-HS line state lasts too long.

[0048] Optionally, the process of inserting a synchronization code to generate a binary number also includes using a second clock to DC balance the data.

[0049] Optionally, using a second clock to DC balance the data also includes scrambling the data.

[0050] Secondly, the present invention discloses a method for storing a bit stream, comprising storing the bit stream in a storage medium, wherein the bit stream is generated by the above-described encoding method.

[0051] Thirdly, the present invention discloses a method for transmitting a bit stream, comprising transmitting a bit stream, wherein the bit stream is generated by the above-described encoding method.

[0052] Fourthly, this invention discloses a decoding method to obtain an X-bit binary number, which is then directly mapped to a line status block representing the line status. The binary number and the line status block are in one-to-one correspondence. The line status block contains one or N line status values. Based on the line status values ​​of the line status block, the A, B, and C lines of the C-PHY are driven to be in the line status corresponding to the line status values, wherein the line status is a voltage combination of the A, B, and C lines.

[0053] Optionally, the line state block contains at least one real wire state value; and the line state block contains zero, one, or more dummy wire state values.

[0054] Optionally, the actual wire state value is a voltage combination (wirestate) value representing the actual voltage of each of the A, B, and C lines.

[0055] Optionally, the transmission channel of the C-PHY corresponding to the line status block is in the mode of HS (high speed) mode and non-HS mode. The non-HS mode includes LP (low speed) mode and ALP (Alternate Low-Power) mode.

[0056] Optionally, in response to the transmission channel of the C-PHY corresponding to the line status block being in HS mode, the binary number is mapped to the line status block representing the line status as the first line status block, and the X-bit binary number represents at least one real line status value in HS mode.

[0057] Optionally, in response to the mode of the transmission channel of the C-PHY corresponding to the line status block being in LP mode, the line status block representing the line status mapped by the binary number is the second line status block, and the X-bit binary number represents only one line status value in LP mode; in response to the mode of the line status block being in ALP mode, the line status block representing the line status mapped by the binary number is the third line status block, and the X-bit binary number represents only one line status value in ALP mode.

[0058] Optionally, the first line status block contains N line status values; wherein, the first line status block containing N real line status values ​​is a complete line status block.

[0059] Optionally, the first line state block contains N line state values; wherein, the first line state block, which includes M real line state values ​​in HS mode and NM virtual line state values, is an incomplete line state block, and M... <N。

[0060] Optionally, based on the actual line state values ​​of the M HS modes of the incomplete line state block, the A, B, and C lines of the C-PHY are driven to be in the line states corresponding to the line state values.

[0061] Optionally, X = 1 + L, where 1 bit in the X binary number represents whether the line status block is a first line status block mode, a second line status block, or a third line status block; directly mapping the binary number to a line status block representing the line status includes: in response to the line status block being a first line status block, removing the flag bit in the X binary number and mapping the remaining L binary number to the first line status block; in response to the line status block being a second or third line status block, removing the flag bit in the X binary number and mapping the remaining L binary number to a line status value.

[0062] Optionally, X=L, where the binary number is directly mapped to a line status block representing the line status, comprising: dividing the X-bit binary number into k parts, each part containing p-bit binary numbers, where L=k×p.

[0063] Optionally, the p-bit binary number is mapped to a first line state sub-block representing the line state; the first line state sub-block contains m line state values, where N=m×k; the first line state block is obtained by combining k consecutive line state sub-blocks, or the A, B and C lines of the C-PHY are driven to be in the line state corresponding to the line state value according to the line state value of the line state sub-block.

[0064] Optionally, mapping the L-bit binary number to the first line state block also includes dividing the L-bit binary number into k parts, each part containing p-bit binary numbers, where L = k × p.

[0065] Optionally, the p-bit binary number is mapped to a first line state sub-block representing the line state; the first line state sub-block contains m line state values, where N=m×k; the first line state block is obtained by combining k consecutive line state sub-blocks, or the A, B and C lines of the C-PHY are driven to be in the line state corresponding to the line state value according to the line state value of the line state sub-block.

[0066] Fifthly, the present invention discloses a decoding method, which obtains an X-bit binary number and directly maps the binary number to a line status block representing the line status; the binary number and the line status block correspond one-to-one; the line status block contains 1 or N line status values.

[0067] Optionally, the line state block contains at least one real wire state value; and the line state block contains zero, one, or more dummy wire state values.

[0068] Optionally, the actual wire state value is a voltage combination (wirestate) value representing the actual voltage of each of the A, B, and C lines.

[0069] Optionally, the transmission channel of the C-PHY corresponding to the line status block is in the mode of HS (high speed) mode and non-HS mode. The non-HS mode includes LP (low speed) mode and ALP (Alternate Low-Power) mode.

[0070] Optionally, in response to the transmission channel of the C-PHY corresponding to the line status block being in HS mode, the binary number is mapped to the line status block representing the line status as the first line status block, and the X-bit binary number represents at least one real line status value in HS mode.

[0071] Optionally, in response to the C-PHY transmission channel being in LP mode corresponding to the line status block, the line status block representing the line status mapped by the binary number is the second line status block, and the X-bit binary number represents only one line status value in LP mode; in response to the line status block being in ALP mode, the line status block representing the line status mapped by the binary number is the third line status block, and the X-bit binary number represents only one line status value in ALP mode; according to a line status value in LP mode or a line status value in ALP mode, the A, B, and C lines of the C-PHY are driven to be in the line status corresponding to the line status value, wherein the line status is the voltage combination of the A, B, and C lines.

[0072] Optionally, the first line status block contains N line status values; wherein, the first line status block containing N real line status values ​​is a complete line status block.

[0073] Optionally, the first line state block contains N line state values; wherein, the first line state block, which includes M real line state values ​​in HS mode and NM virtual line state values, is an incomplete line state block, and M... <N。

[0074] Optionally, X = 1 + L, where 1 bit in the X binary number represents whether the line status block is a first line status block mode, a second line status block, or a third line status block; directly mapping the binary number to a line status block representing the line status includes: in response to the line status block being a first line status block, removing the flag bit in the X binary number and mapping the remaining L binary number to the first line status block; in response to the line status block being a second or third line status block, removing the flag bit in the X binary number and mapping the remaining L binary number to a line status value.

[0075] Optionally, X=L, where the binary number is directly mapped to a line status block representing the line status, comprising: dividing the X-bit binary number into k parts, each part containing p-bit binary numbers, where L=k×p.

[0076] Optionally, the p-bit binary number is mapped to a first line state sub-block representing the line state; the first line state sub-block contains m line state values, where N = m × k; according to the line state values ​​of the line state sub-block, the A, B and C lines driving the C-PHY are respectively in the line state corresponding to the line state values.

[0077] Optionally, mapping the L-bit binary number to the first line state block also includes dividing the L-bit binary number into k parts, each part containing p-bit binary numbers, where L = k × p.

[0078] Optionally, the p-bit binary number is mapped to a first line state sub-block representing the line state; the first line state sub-block contains m line state values, where N = m × k; according to the line state values ​​of the line state sub-block, the A, B and C lines driving the C-PHY are respectively in the line state corresponding to the line state values.

[0079] Optionally, the X-bit binary number is directly mapped to a line status block representing the line status; when the mode corresponding to the line status block is HS (high speed) mode, according to the first clock, the line status value of the line status block is used to drive the A, B and C lines of the C-PHY to be in the line status corresponding to the line status value.

[0080] Optionally, the timing of the first clock is the same as that of the HS mode voltage state.

[0081] Optionally, the first clock is divided by N to obtain the second clock; based on the second clock, the X-bit binary number is mapped to the first line status block, the second line status block, or the third line status block.

[0082] Optionally, when the mode corresponding to the line status block is non-HS (non-high speed) mode, the second clock and X-bit binary number are mapped to a line status value containing one line status value, and the A, B and C lines of the C-PHY are respectively in the line status corresponding to the line status value.

[0083] Optionally, the first clock can be extracted or recovered from the serial signal obtained from the transmission medium.

[0084] Optionally, the serial signal obtained from the transmission medium is converted from serial to parallel to generate parallel data containing X bits of binary data.

[0085] Optionally, a synchronization code is detected on the serial signal obtained from the transmission medium, and the Y bits of parallel data after the synchronization code are decoded by Xb / Yb to obtain an X-bit binary number.

[0086] Optionally, the serial signal obtained from the transmission medium is subjected to DC-balanced decoding.

[0087] Optionally, DC-balanced decoding is performed on the parallel data obtained from the transmission medium and after serial-to-parallel conversion.

[0088] Optionally, the parallel data after DC balanced decoding is descrambled to obtain X bits of binary data.

[0089] Optionally, the descrambled X-bit binary number can be mapped to a line status block representing the line status.

[0090] Optionally, the mode of the transmission channel of the C-PHY corresponding to the line status block can be identified based on the physical layer signal characteristics of the serial signal obtained from the transmission medium.

[0091] Optionally, the mode of the transmission channel of the C-PHY corresponding to the line status block can be identified based on the synchronization code.

[0092] Optionally, the mode of the transmission channel of the C-PHY corresponding to the line status block is identified based on the flag bits in the X-bit binary number.

[0093] Optionally, the mode of the transmission channel of the C-PHY corresponding to the line status block is identified based on the X-bit binary number.

[0094] In a sixth aspect, the present invention discloses a circuit for encoding C-PHY signals, wherein the C-PHY transmission channel includes A line, B line and C line, and the circuit includes: a preprocessing circuit for receiving the line status of A line, B line and C line, identifying the mode of the C-PHY transmission channel according to the line status, and generating a line status block according to the mode of the C-PHY transmission channel; and a mapping circuit for mapping the line status block to a binary number that can uniquely identify the line status block.

[0095] Optionally, the mapping circuit directly maps the line state block to an X-bit binary number, so that the X-bit binary number uniquely represents the different values ​​of the line state block.

[0096] Optionally, the preprocessing state block generates a line state block based on the line states of lines A, B, and C, without recognizing the symbols represented by adjacent line states.

[0097] Optionally, the line state block generated by the preprocessing circuit contains at least one real wire state value; and the line state block generated by the preprocessing circuit contains zero, one, or more dummy wire state values; wherein the real wire state value is generated by the preprocessing circuit using the voltage combination (wire state) value obtained by the preprocessing circuit using the real voltages of wires A, B, and C respectively.

[0098] Optionally, the preprocessing circuit identifies the mode in which the transmission channel of C-PHY is located. The mode in which the transmission channel of C-PHY is located includes the HS (high speed) mode and the non-HS mode. The non-HS mode includes the LP (low speed) mode and the ALP (Alternate Low-Power) mode; and outputs information representing the HS mode, the LP mode or the ALP mode.

[0099] Optionally, in response to the mode in which the transmission channel of C-PHY is located being the LP mode, the preprocessing circuit generates a second line status block for each real line status value in the LP mode, and the mapping circuit maps the second line status block to an X-bit binary number; in response to the mode in which the transmission channel of C-PHY is located being the ALP mode, the preprocessing circuit generates a third line status block for each real line status value in the ALP mode, and the mapping circuit maps the third line status block to an X-bit binary number.

[0100] Optionally, in response to the mode in which the transmission channel of C-PHY is located being the HS mode, the preprocessing circuit generates a first line status block from the real line status values in the HS mode. The first line status block contains N line status values; the N line status values include at least one real line status value in the HS mode.

[0101] Optionally, in response to the mode in which the transmission channel of C-PHY is located being the HS mode, the first line status block generated by the preprocessing circuit from every N real line status values in the HS mode is a complete line status.

[0102] Optionally, in response to the transmission channel of C-PHY switching from the HS mode to the non-HS mode, if the preprocessing circuit receives the line statuses of M A-lines, B-lines and C-lines, and M < N, the preprocessing circuit generates N - M virtual line status values, and the first line status block generated by the M real line status values in the HS mode and the N - M virtual line status values is an incomplete line status block.

[0103] Optionally, the mapping circuit maps the first line status block to an X-bit binary number that uniquely identifies the first line status block, where the X-bit binary number represents the N line status values when the transmission channel of C-PHY is in the HS mode.

[0104] Optionally, when the mapping circuit maps the incomplete line status block to an X-bit binary number that uniquely identifies the first line status block, the X-bit binary number represents the M real line status values in the HS mode and the N - M virtual line status values.

[0105] Optionally, X is an integer that satisfies

[0106] ​Optionally, X is satisfied The smallest integer.

[0107] Optionally, X = 1 + L, where the mapping circuit uses 1 bit of the X-bit binary number as a flag to indicate whether the line state block is the first line state block, the second line state block, or the third line state block; the mapping circuit encodes the first line state block into L bits of the X-bit binary number, where L is a binary number that satisfies... The integer; the mapping circuit encodes the second line state block or the third line state block into an L-bit binary number in an X-bit binary number.

[0108] Optionally, in response to the transmission channel of the C-PHY being in HS mode, the preprocessing circuit generates a line state sub-block for every m line state values, and combines k line state sub-blocks to generate the first line state block, where N = k × m.

[0109] Optionally, in response to the C-PHY transmission channel being in HS mode, the preprocessing circuit generates a first line state block for every N line state values, and generates k line state sub-blocks containing m line state values ​​from the first line state block.

[0110] Optionally, the mapping circuit encodes each line state sub-block into a p-bit binary number that can uniquely represent all the values ​​of the line state sub-block, and combines the p-bit binary numbers corresponding to each of the k line state sub-blocks to obtain an X-bit binary number that uniquely identifies the first line state block.

[0111] Optionally, the line state sub-block generated by the preprocessing circuit contains m real line state values ​​of HS mode, forming a complete line state sub-block; the line state sub-block generated by the preprocessing circuit contains j real line state values ​​of HS mode and mj virtual line state values, forming an incomplete line state sub-block, where j <m。

[0112] Optionally, p is a condition that satisfies 2 p >6×5 （m-1） An integer consisting of + (m-1)×6.

[0113] Optionally, p is a condition that satisfies 2 p >6×5 （m-1） The smallest integer of + (m-1)×6.

[0114] Optionally, the mapping circuit maps the first line state block to an X-bit binary number that uniquely identifies the first line state block, where X = L, or X = 1 + L, and L = k × p.

[0115] Optionally, the mapping circuit encodes each line state sub-block into a p-bit binary number that can uniquely represent all the values ​​of the line state sub-block, and combines the p-bit binary numbers corresponding to each of the k line state sub-blocks to obtain an X-bit binary number that uniquely identifies the first line state block; when the mapping circuit encodes the second or third line state block into an X-bit binary number, it uses the codewords in the codeword space of the X-bit binary number, excluding the codewords used to encode the first line state block, to encode the second or third line state block.

[0116] Optionally, when X=1+L, the mapping circuit uses 1 bit of the X-bit binary number as a flag to indicate whether the line state block is the first line state block, the second line state block, or the third line state block; the mapping circuit encodes the first line state block as an L-bit binary number in the X-bit binary number, where L=k×p, encodes each line state sub-block as a p-bit binary number that can uniquely represent all the values ​​of the line state sub-block, and combines the p-bit binary numbers corresponding to each of the k line state sub-blocks to obtain an L-bit binary number; the mapping circuit encodes the second or third line state block as an L-bit binary number in the X-bit binary number.

[0117] Optionally, the mapping circuit directly maps the line status block to an X-bit binary number. The X-bit binary number also includes a flag bit. The first value of the flag bit indicates that the X-bit binary number is encoded by the first line status block; the second value of the flag bit indicates that the X-bit binary number is encoded by the second or third line status block.

[0118] Optionally, L is the condition that satisfies 2. L >k×6×5 (m-1) An integer consisting of + (m-1)×6.

[0119] Optionally, L is the condition that satisfies 2. L >k×6×5 (m-1) The smallest integer of + (m-1)×6.

[0120] Optionally, L is the condition that satisfies 2. L >k×6×5 (m-1) Integers.

[0121] Optionally, L is the condition that satisfies 2. L >k×6×5 (m-1) The smallest integer.

[0122] Optionally, the preprocessing circuit uses a first clock to sample the line state of the HS mode and generates a first line state block from the sampling results.

[0123] Optionally, the preprocessing circuit further includes a clock unit and a frequency divider unit; the clock unit is used to obtain a first clock; the frequency divider unit divides the first clock by N to generate a second clock; and the mapping circuit maps the first line state block to an X-bit binary number that can uniquely identify the line state block according to the second clock.

[0124] Optionally, the timing of the first clock is the same as that of the HS mode voltage state.

[0125] Optionally, the clock unit generates a first clock locally, or recovers the timing of the HS mode based on the voltage states of lines A, B, and C.

[0126] Optionally, the preprocessing circuit samples the line state in non-HS mode and generates a second line state block or a third line state block for each sampling result; the mapping circuit maps the first line state block, the second line state block or the third line state block to a binary number that can uniquely identify the line state block according to the second clock.

[0127] Optionally, it also includes a parallel-to-serial conversion circuit, the input of which is connected to the mapping circuit, for converting the received binary number into serial data; the serial data is transmitted through a transmission medium.

[0128] Optionally, it also includes a frame synchronization (Sync TX) circuit, whose input is connected to the frequency divider unit and the mapping circuit respectively, for periodically inserting synchronization codes before the first valid binary number is transmitted using the second clock, when the binary number switches between the line state of HS mode and the line state of other modes, or when the line state of other modes lasts for too long; the input of the parallel-to-serial conversion circuit is connected to the frame synchronization (Sync TX) circuit, and performs parallel-to-serial conversion on the received synchronization code to generate serial data.

[0129] Optionally, it also includes a DC balance encoding circuit, whose input is connected to the frequency divider unit and the mapping circuit respectively, and whose output is connected to the frame synchronization circuit. It is used to perform DC balance on the data sent to the frame synchronization circuit using a second clock, so that the number of "0" and "1" codewords in the data stream is equal.

[0130] Optionally, it also includes a scrambler circuit, whose input is connected to the frequency division unit and the mapping circuit respectively, and whose output is connected to the DC balanced encoding circuit, for scrambling the received data.

[0131] Optionally, the number N of line state values ​​contained in the line state block is selected according to the complexity and efficiency of the mapping in the mapping circuit. The larger N is, the greater the complexity of binary encoding / decoding, scrambling / descrambling, and DC balanced encoding / decoding.

[0132] Optionally, the binary code obtained by the mapping circuit is a binary code of at least X bits, where X represents the codeword length of the line status signal grouped in HS mode and represented by binary code. The length of X is determined according to the number N of line status values ​​contained in the line status block.

[0133] Optionally, the preprocessing circuit identifies the mode of the C-PHY's transmission channel and assigns a signal type flag and a signal enable (EN) flag. The signal type flag is used to assist the mapping circuit in performing binary number mapping, and the signal enable flag is used to pass the signal to subsequent circuits step by step so that the subsequent circuits can start working.

[0134] In a seventh aspect, the present invention discloses a circuit for decoding C-PHY signals, wherein the transmission channel (Lane) of the C-PHY includes A line, B line and C line, and the circuit includes: a receiving circuit for receiving an X-bit binary number; a demapping circuit for directly mapping the X-bit binary number into a line state block representing the line state; the binary number and the line state block correspond one-to-one; the line state block contains one or N line state values; and a post-processing circuit for driving the A line, B line and C line of the C-PHY to be in the line state corresponding to the line state value of the line state block, wherein the line state is a voltage combination of the A line, B line and C line.

[0135] Optionally, the line state block contains at least one real wire state value; and the line state block contains zero, one, or more dummy wire state values; the real wire state value is a voltage combination (wire state) value used to represent the real voltages of the A, B, and C lines of the C-PHY.

[0136] Optionally, the mode corresponding to the line status block includes HS (high speed) mode and non-HS mode. The non-HS mode includes LP (low speed) mode and ALP (Alternate Low-Power) mode.

[0137] Optionally, in response to the mode corresponding to the line state block being LP mode, the demapping circuit maps the binary number to a second line state block, the second line state block containing one actual line state value of LP mode; in response to the mode corresponding to the line state block being ALP mode, the demapping circuit maps the binary number to a third line state block, the third line state block containing one actual line state value of ALP mode.

[0138] Optionally, in response to the mode corresponding to the line state block being the HS mode, the demapping circuit maps the X-bit binary number to a first line state block, and the first line state block includes at least one true line state value in the HS mode; the post-processing circuit drives the A line, B line, and C line of the C-PHY to be in line states corresponding to the true line state values in the HS mode, respectively.

[0139] In response to the mode corresponding to the line state block being the HS mode, the demapping circuit maps the X-bit binary number to a first line state block including N true line state values in the HS mode as a complete line state block; the post-processing circuit drives the A line, B line, and C line of the C-PHY to be in line states corresponding to the N true line state values in the HS mode, respectively.

[0140] Optionally, in response to the mode corresponding to the line state block being the HS mode, the demapping circuit maps the X-bit binary number to a first line state block including M true line state values in the HS mode and M < N as an incomplete line state block; the incomplete line state block includes M true line state values and N - M virtual line state values; the post-processing circuit drives the A line, B line, and C line of the C-PHY to be in line states corresponding to the M true line state values in the HS mode, respectively.

[0141] Optionally, X = 1 + L, where 1 bit in the X-bit binary number represents whether the line state block is in the first line state block mode, the second line state block, or the third line state block; in response to the line state block being the first line state block, the demapping circuit removes the flag bit in the X-bit binary number and maps the L-bit binary number to a first line state block with at least one true line state value in the HS mode; in response to the line state block being the second line state block or the third line state block, the demapping circuit removes the flag bit in the X-bit binary number and maps the L-bit binary number to a line state value.

[0142] Optionally, X = L, and the binary number is mapped to a line state block representing the line state as the first line state block, including that the demapping circuit samples the X-bit binary number into k parts, each part including p-bit binary numbers, where L = k × p; and maps the p-bit binary number to a first line state sub-block including m line state values, and combines k consecutive line state sub-blocks to obtain the first line state block; the post-processing circuit drives the A line, B line, and C line of the C-PHY to be in line states corresponding to the line state values of the first line state block, respectively.

[0143] Optionally, X=L, the binary number is mapped to a line state block representing the line state as the first line state block, which includes: a demapping circuit sampling an X-bit binary number to obtain k parts, each part containing a p-bit binary number, where L=k×p; and mapping the p-bit binary number to a first line state sub-block containing m line state values. The post-processing circuit drives the A, B, and C lines of the C-PHY to be in the line state corresponding to the line state value according to the line state value of the first line state sub-block.

[0144] Optionally, it also includes a clock circuit for obtaining a first clock; when the mode corresponding to the line state block is HS (high speed) mode, the post-processing circuit drives the A, B and C lines of the C-PHY to be in the line states corresponding to the line state values ​​according to the first clock rate and the line state value of the line state block.

[0145] Optionally, the timing of the first clock is the same as that of the HS mode voltage state.

[0146] Optionally, the clock circuit is also used to divide the first clock by N to obtain the second clock, where N is the line state value contained in the line state block; the input of the demapping circuit is connected to the output of the clock circuit, and the X-bit binary number is mapped to one of the first line state block, the second line state block, or the third line state block according to the received second clock.

[0147] Optionally, when the mode corresponding to the line status block is non-HS (non-high speed) mode, the post-processing circuit maps the second clock signal and the X-bit binary number to a line status value containing one line status value, and drives the A, B and C lines of the C-PHY to be in the line status corresponding to the line status value.

[0148] Optionally, it also includes a serial-to-parallel conversion circuit, whose input terminals are respectively connected to the receiving circuit, for converting the received X-bit serial binary number into a serial-to-parallel binary number; the binary number is a parallel X-bit binary number.

[0149] Optionally, it also includes a synchronization code detection circuit, whose input is connected to the clock circuit and whose output is connected to the serial-to-parallel conversion circuit and the demapping circuit, respectively, for receiving serial high-speed binary data, performing synchronization code detection, and assigning a synchronization code signal flag when a synchronization code is detected.

[0150] Optionally, the serial-to-parallel conversion of the serial-to-parallel conversion circuit specifically involves using the synchronization code signal flag received from the synchronization code detection circuit to perform the serial-to-parallel conversion.

[0151] Optionally, it also includes a DC Balance decoding circuit, whose input is connected to a synchronization code detection circuit, a clock circuit, and a serial-to-parallel conversion circuit, and whose output is connected to a demapping circuit. It is used to obtain the synchronization code signal flag and parallel binary data, perform DC Balance decoding, and obtain binary data in units of X-bits.

[0152] Optionally, the receiving circuit also includes a descrambling circuit, whose input is connected to the clock circuit and the DC balanced decoding circuit respectively, and whose output is connected to the DC balanced circuit, for descrambling the binary data entering the demapping circuit.

[0153] The eighth aspect of the present invention discloses a high-speed active transmission device, comprising a circuit for encoding C-PHY signals as described above, a circuit for decoding C-PHY signals as described above, and a high-speed signal transmission medium located between the two. The circuit for encoding is used to connect to a primary device to receive the line status of lines A, B and C, and the circuit for decoding signals is used to connect to a secondary device.

[0154] Optionally, the high-speed signal transmission medium includes at least a single optical fiber or two differential copper wires.

[0155] Optionally, it also includes at least two photoelectric conversion modules. The photoelectric conversion modules are connected to the transmitting circuit to convert the received binary number into an optical signal, or connected to the receiving circuit to convert the received optical signal into an electrical signal. The photoelectric conversion modules transmit the optical signal through optical fiber.

[0156] Optionally, it also includes a signal conditioner for enabling long-distance transmission of electrical signals via copper wires.

[0157] In summary, the present invention has the following advantages:

[0158] 1. Obtain the C-PHY line status, generate line status blocks, and map the line status blocks to binary numbers that can uniquely identify the line status blocks. Directly use the line status for a binary encoding mapping, realize the conversion of line status to binary numbers, greatly reduce the complexity of encoding circuits and encoding methods, reduce encoding overhead, and increase speed.

[0159] 2. By using the line status mapping to a binary number that includes all symbols in the C-PHY protocol, the integrity of the transmitted information is ensured;

[0160] 2. Since only X bits of binary encoding are needed to achieve the encoding mapping of line status, the amount of data transmission is reduced and the encoding efficiency is improved.

[0161] 3. Set flags to distinguish between HS mode, LP mode and ALP mode, further reducing the number of bits in binary encoding and improving encoding efficiency.

[0162] 4. Line status sub-blocks can be set in the HS mode line status block. Encoding and decoding can be performed on each line status sub-block without waiting for all line status sub-blocks to be sent and received. This reduces the complexity of encoding and decoding and improves the efficiency and real-time performance of encoding and decoding.

[0163] 5. Convert the data transmitted on the three lines (A, B, and C) of a C-PHY channel into serial binary numbers for transmission, reducing the number of transmission media.

[0164] 6. During the decoding process, binary numbers are directly used to decode into line status blocks representing the line status. Only one decoding conversion process is required, which reduces the complexity of the decoding circuit and decoding method, with less overhead, faster speed, and complete information. Attached Figure Description

[0165] Figure 1 This is a schematic diagram of C-PHY signal transmission using copper wires in existing technology;

[0166] Figure 2(a) and Figure 2(b) are diagrams of the line state encoding and decoding process in the prior art. Figure 2(a) is a diagram of the process by which the master device maps the data to be transmitted to the line state, and Figure 2(b) is a diagram of the process by which the slave device maps the received line state back to the transmitted data.

[0167] Figure 3 This is a schematic diagram of an application scenario according to a specific embodiment of the present invention;

[0168] Figure 4 This is a schematic diagram of a C-PHY encoding method according to a specific embodiment of the present invention;

[0169] Figure 5 This is a schematic diagram of a C-PHY decoding method according to a specific embodiment of the present invention;

[0170] Figures 6(a) and 6(b) are schematic diagrams of line state mapping according to a specific embodiment of the present invention, wherein Figure 6(a) is a schematic diagram of line state block mapping according to a specific embodiment of the present invention, and Figure 6(b) is a schematic diagram of line state sub-block mapping according to a specific embodiment of the present invention.

[0171] Figures 7(a) and 7(b) are schematic diagrams of incomplete line state blocks according to specific embodiments of the present invention, wherein Figure 7(a) shows the case where the first line state is +x and Figure 7(b) shows the case where the first line state is -x.

[0172] Figure 8This is a classification diagram of flag-less bit encoding according to a specific embodiment of the present invention;

[0173] Figure 9 This is a schematic diagram of the encoding with flag bits according to a specific embodiment of the present invention;

[0174] Figure 10 This is a classification diagram with flag bits encoded according to a specific embodiment of the present invention;

[0175] Figure 11 This is a flag-coded classification diagram according to another specific embodiment of the present invention;

[0176] Figure 12 This is a schematic diagram of C-PHY signal transmission according to a specific embodiment of the present invention;

[0177] Figure 13 This is a decoding schematic diagram containing flag bits but without line status sub-blocks according to a specific embodiment of the present invention;

[0178] Figure 14 This is a decoding schematic diagram containing flag bits and line status sub-blocks according to a specific embodiment of the present invention;

[0179] Figure 15 This is a decoding schematic diagram without flag bits and without line status sub-blocks according to a specific embodiment of the present invention;

[0180] Figure 16 This is a decoding schematic diagram of a specific embodiment of the present invention, which does not include flag bits but includes line status sub-blocks;

[0181] Figure 17 This is a schematic diagram of C-PHY signal decoding according to a specific embodiment of the present invention;

[0182] Figure 18 This is a schematic diagram of a circuit for encoding C-PHY signals according to a specific embodiment of the present invention;

[0183] Figure 19 This is a schematic diagram of a decoding circuit for generating C-PHY signals according to a specific embodiment of the present invention;

[0184] Figure 20 This is a schematic diagram of an active transmission device according to a specific embodiment of the present invention;

[0185] Figure 21 This is a schematic diagram of an active transmission device according to a specific embodiment of the present invention.

[0186] The technical features referred to by the reference numerals in the figure are as follows:

[0187] 10. Circuit for encoding C-PHY signal; 11. Preprocessing circuit; 12. Mapping circuit; 13. Scrambling circuit; 14. DC balanced encoding circuit; 15. Frame synchronization circuit; 16. Parallel-to-serial conversion circuit; 17. Transmitting circuit; 20. Decoding circuit for generating C-PHY signal; 21. Post-processing circuit; 22. Demapping circuit; 23. Descrambling circuit; 24. DC balanced decoding circuit; 25. Synchronization code detection circuit; 26. Serial-to-parallel conversion circuit; 27. Clock circuit; 28. Receiving circuit. Detailed Implementation

[0188] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0189] In this invention, the terminology used is defined as follows:

[0190] Wire State: The wire state of the C-PHY protocol is the combination of analog signal levels driven on the three lines (A line / B line / C line) of a lane in C-PHY.

[0191] According to the C-PHY protocol, when the C-PHY transmission channel is in HS mode, there are six possible line statuses:

[0192] If the line level of line A is high, the line level of line B is low, and the line level of line C is medium, then the line status is +x, and the line status value at this time is recorded as (b'100).

[0193] If the line level of line A is low, the line level of line B is high, and the line level of line C is medium, then the line status is -x, and the line status value at this time is recorded as (b'011).

[0194] If the line level of line A is medium, the line level of line B is high, and the line level of line C is low, then the line status is +y, and the line status value at this time is recorded as (b'010).

[0195] If the line level of line A is medium, the line level of line B is low, and the line level of line C is high, then the line status is -y, and the line status value at this time is recorded as (b'101).

[0196] If the line level of line A is low, the line level of line B is medium, and the line level of line C is high, then the line status is +z, and the line status value at this time is recorded as (b'001).

[0197] If the line level of line A is high, the line level of line B is medium, and the line level of line C is low, then the line status is -z, and the line status value at this time is recorded as (b'100).

[0198] When the C-PHY transmission channel is in LP mode, there are four possible line states: LP-000, LP-001, LP-100, and LP-111.

[0199] If the C-PHY transmission channel is in ALP mode, there are two possible line states: ALP-Pausestate (VOD = 0) and ALP-Pause Wake state (VOD = |VOD| Strong).

[0200] Symbol: The symbol value is defined by the change in wire state values ​​from one unit interval to the next.

[0201] For ease of description, the Wire State Value is introduced, which refers to the digital signal converted from the wire state driven on the three lines (A / B / C) of a channel in a C-PHY through sampling.

[0202] See Figure 1 This diagram illustrates the transmission of C-PHY copper cables in the prior art. The C-PHY Primary (DataSource, also known as the master device) encodes the received data into line status values ​​and drives the A, B, and C lines to the corresponding line statuses via drivers.

[0203] The master device encodes binary data into line status values. Specifically, in HS mode, each 16-bit binary number is mapped to a 21-bit number representing 7 symbols using a mapping table defined by the C-PHY protocol. These 21-bit numbers are then converted from parallel to serial to obtain the 7 symbols to be transmitted sequentially. Each symbol is represented by a 3-bit number, and this 3-bit symbol is encoded into the line status according to the C-PHY protocol (see also Figure 2(a)). In HS mode, symbols transmitted at specific times for control, synchronization, training, etc., are called special symbols, and these special symbols are transmitted in 21-bit increments. These 21 bits are divided into 7 3-bit symbols, and each symbol is encoded into the line status according to the C-PHY protocol. Signals in ALP mode are transmitted in the same way as special symbols. Low-speed signals are transmitted in LP mode.

[0204] High-speed and low-speed signals share a physical transmission channel between the C-PHY Primary and C-PHY Secondary (Data Sink, also known as the slave device). On the Secondary side, the received line status is restored to a binary number and output. Specifically, for HS mode, the C-PHY Secondary detects the line status, decodes each line status into a 3-bit Symbol, and then serializes and parallelizes the 7 Symbols to convert them into 21-bit data. This 21-bit data is then mapped to a 16-bit binary number through a mapping table defined by the C-PHY protocol (see also Figure 2(b)). For special symbols in HS mode or signals in ALP mode, special symbols are directly generated from the 21-bit data. If it is an LP mode signal, an LP mode detection circuit is used to detect the signal and obtain the LP mode data.

[0205] exist Figure 1 In this system, a three-phase cable is used to transmit line status between the Primary and Secondary levels. The three-phase cable consists of three copper wires that directly connect the Primary and Secondary levels. The cable is relatively thick and sensitive to electromagnetic interference; higher speeds result in shorter transmission distances, limiting its application scenarios.

[0206] Figure 3A communication system applying embodiments of this application is illustrated. It includes a C-PHY Primary and a C-PHY Secondary that communicate with each other. The C-PHY Primary and C-PHY Secondary are connected via an active transmission device according to embodiments of this application. The active transmission device of this application is, for example, an active optical cable or an active copper cable. The active transmission device includes a transmitter and a receiver, and a high-speed signal transmission medium located between them. The transmitter is used to connect to the master device (C-PHY Primary) to receive the C-PHY line status, encode it, output a binary number, and transmit it to the receiver via the transmission medium. This replaces the prior art three-phase cable for transmitting line status between the Primary and Secondary.

[0207] The transmitting end includes circuitry 10 for encoding C-PHY signals, and the receiving end includes decoding circuitry 20 for generating C-PHY signals (see also...). Figure 12 , 18 19).

[0208] The main features of this invention are: obtaining C-PHY line status values, generating line status blocks, mapping the line status blocks to binary numbers that can uniquely identify the line status blocks, thereby transmitting the complete line status blocks with only one encoding, improving transmission efficiency and reducing transmission loss.

[0209] See Figure 4 The diagram illustrates a C-PHY encoding method according to a specific embodiment of the present invention.

[0210] Figure 4 The encoding method is used in the circuit 10 for encoding C-PHY signals in this embodiment of the application. The circuit 10 for encoding C-PHY signals receives the line status from the Primary, converts it into a binary number, and outputs it through the transmission medium of optical fiber or copper cable.

[0211] The encoding method of this application embodiment obtains the line status of the A, B, and C lines of the C-PHY transmission channel according to the mode of the C-PHY transmission channel and generates line status blocks. The line status blocks are then mapped to binary numbers that can uniquely identify the line status blocks.

[0212] The mapped binary number includes, for example, X bits, such that the X bits uniquely represent the different values ​​of the line status block. The symbols representing adjacent line states are not recognized during the direct mapping of line status blocks to X bits. This "X" represents the X bits of binary data, not the line status value "x".

[0213] In order to obtain binary numbers from the line status of the C-PHY, the encoding method of this application embodiment is not used in the prior art C-PHY Secondary process of identifying the transmitted data from the line status.

[0214] Referring to Figure 2(b), the process by which Secondary maps the received line status to binary numbers in HS mode includes the following steps: continuously receiving line status, obtaining the specific voltage levels (high, medium, low) of lines A, B, and C at each moment through sampling, and obtaining the line status value. Decoding a 3-bit Symbol based on the changes in line status values ​​between adjacent unit intervals (UI), i.e., line status decoding. For a continuously received 3-bit Symbol symbol stream, every 7 Symbols are accumulated and converted from serial to parallel to obtain 21 bits of data. Finally, using the reverse lookup table defined in the C-PHY protocol specification, this 7-symbol combination is mapped back to the original 16-bit binary number. It should be noted that this explanation only focuses on the HS mode data (excluding special symbols in HS mode). It is evident that the existing technology involves multiple encoding conversions in the process of converting line status to binary numbers, which is complex, slow, time-consuming, and requires complex encoding circuits, resulting in high costs. See [link to relevant documentation] Figure 4 The encoding method in this application embodiment directly uses the line state to perform a one-time mapping to obtain binary code, realizing the conversion of line state to binary number, greatly reducing the complexity of encoding circuit and encoding method, with less encoding overhead and faster speed.

[0215] In this embodiment, the line status is directly mapped to binary numbers. The directly mapped line status includes all possible symbol combinations in the 16-bit mapping code table of the HS mode signal 7 Symbol in the C-PHY protocol, special symbols of the HS mode defined by the C-PHY protocol, signals of the ALP mode, and signals of the LP mode. This ensures that the line status information is complete during the mapping process to binary numbers, and avoids data transmission errors caused by incomplete three-phase encoding and de-mapping of C-PHY Symbols, thus improving system compatibility. Optionally, in addition to the symbols defined by the C-PHY protocol, custom information codes added to facilitate the encoding and decoding of C-PHY signals are also directly mapped.

[0216] A line status block consists of N line status values. When generating binary numbers, each line status block is directly mapped to an X-bit binary number, which facilitates the hardware implementation of the mapping circuit.

[0217] Furthermore, on the decoding side, the demapping circuit directly restores the X-bit binary number into N line states of a line state block, greatly reducing the complexity of the encoding circuit and achieving fast encoding. This eliminates the need for multiple conversions as in existing technologies, preserving the integrity of the encoded information. During decoding, it also eliminates the need for existing technologies to first identify the line state value, then identify the symbol represented by adjacent line state values, then convert multiple 3-bit symbols serially and in parallel into 7 21-bit symbols, and finally map the 21-bit symbols to 16-bit binary numbers. This significantly improves the encoding / decoding efficiency and data transmission efficiency of cables transmitting C-PHY signals.

[0218] A wire state block must include at least one real wire state value. It may also include zero, one, or more dummy wire state values.

[0219] The actual line state value is the voltage combination value obtained by sampling the actual voltages of lines A, B and C in the C-PHY.

[0220] Virtual line status values ​​are line status values ​​corresponding to voltage combinations that will not appear on lines A, B, and C according to the C-PHY protocol. They are used to fill in other positions besides the real line status values ​​when generating line status blocks to form line status blocks of the target length (N).

[0221] Optionally, the multiple real line status values ​​in the line status block have a temporal order in which each line status value is sampled from the C-PHY channel, so that the order in which each line status value is sent can be known after decoding the line status block.

[0222] See Figure 6(a), which shows a schematic diagram of a line status block, using HS mode as an example.

[0223] A line state block contains N line states. In line state block 0, the first line state value "100" is obtained by sampling line state W0 at time T0, the second line state value "011" is obtained by sampling line state W1 at time T1, the third line state value "010" is obtained by sampling line state W2 at time T2, and so on. The Nth line state value W... N-1 The sampling time in the figure is marked as T. N-1 In this application, each line state block used in HS mode has the same structure as line state block 0.

[0224] In this embodiment, the line state block obtained in HS mode is referred to as the first line state block. All possible different values ​​of the first line state block are uniquely represented by an X-bit binary number.

[0225] The C-PHY protocol stipulates that adjacent line state values ​​cannot be the same; therefore, the maximum number of possible combinations of actual line state values ​​in the first line state block is 6. The above 6 types are represented using X-bit binary encoding. For each combination of cases, it is only necessary to satisfy... That's it. Therefore, the value of X can be greater than Log2( The smallest integer of ) is X. It can be understood that taking a smaller value for X helps shorten the length of the binary number after encoding the line status block, thus shortening the transmission time; while increasing the value of X is beneficial for transmitting more information, such as accommodating the line status of LP mode and ALP mode, as well as custom information codes. However, LP mode only needs to accommodate 4 line statuses, and ALP mode only needs 2 line statuses, so to accommodate these statuses, there is no need to significantly increase the value of X. For example, it can be calculated using Log2( Add 1 bit to the smallest integer of ).

[0226] For example, if the C-PHY transmission channel is in HS mode, in response to acquiring N consecutive line states, a complete line state block is generated, containing N actual line state values ​​corresponding to the N line states. This complete line state block belongs to the first line state block. In this case, the possible permutations of line state values ​​in the complete line block have 6... kind.

[0227] In another embodiment, when the C-PHY's transmission channel switches from HS mode to non-HS mode, it may be unable to obtain N consecutive line states, thus generating an incomplete line state block. The incomplete line state block contains M real line state values ​​and NM virtual line state values. The incomplete line state block also belongs to the first line state block, where M... <N。

[0228] Specifically, before the C-PHY transmission channel switches from HS mode to non-HS mode, the line status of the A line, B line and C line in the C-PHY is sampled to obtain M real line status values. NM virtual line status values ​​are generated to fill other positions outside the real line status values ​​to form a line status block containing N line status values.

[0229] According to the C-PHY protocol definition, the last transmitted symbol in HS mode always ends with Z C-PHY Symbols "4", and Z is an integer multiple of 7. That is, the last transmitted Symbol in HS mode can be 7 consecutive "4"s or 14 consecutive "4"s, and so on. Z is also called TGR_Post_Length in the protocol, which is the length of the Symbol "4", and its value ranges from 7 to 1792 according to the protocol. It should be noted that in this invention, "Z" represents the number of Symbols with the value "4", not the line status value "z".

[0230] According to the protocol, the symbol "4" represents alternating x, -x, y, -y, or z, -z. This means that there are six possible line states in the final transmission of HS mode. Taking a value of Z equal to 7 as an example, the specific details are shown in the table below:

[0231]

[0232] Referring to Figures 7(a) and 7(b), schematic diagrams illustrating possible scenarios for incomplete line state blocks according to specific embodiments of the present invention are shown. Since the length of the received HS mode line state is uncertain and the value of Z fluctuates, there are multiple possibilities for incomplete line state blocks, as shown in Figures 7(a) and 7(b). Figure 7(a) shows the case where the first line state is +x, including N-1 cases. The first case (case 1) is that the incomplete line state block contains only one real line state value; the second case (case 2) is that the incomplete line state block contains two real line state values, and so on, until the incomplete line state block contains N-1 real line state values. Figure 7(b) shows the case where the first line state is -x, including N-1 cases. The first case (case 1) is that the incomplete line state block contains only one real line state value; the second case (case 2) is that the incomplete line state block contains two real line state values, and so on, until the incomplete line state block contains N-1 real line state values.

[0233] For each case of the first line state of an incomplete line state block, there are N-1 possible cases for the incomplete line state block. Understandably, when forming the line state block, virtual line state values ​​are filled in to form a line state block containing N line state values. In the diagram, NULL represents a virtual line state value filled in the line state block. Referring to Figures 7(a) and 7(b), the +x / -x state at the end indicates that its value is related to the parity of N; if N is odd, the value before the " / " is taken; otherwise, the value after the " / " is taken.

[0234] Figures 7(a) and 7(b) take the first line state in the incomplete line state block as +x or -x as an example. For the cases where the first line state in the incomplete line state block is +y, -y, +z, or -z, the situation is similar to the above and will not be elaborated here.

[0235] Therefore, for N < Z, there are a total of (N - 1) × 6 combinations of line states in the incomplete line state block at most. Therefore, to cover all cases, these cases need to be further accommodated in the X-bit binary number of the encoded line state block. Thus, by increasing X, it is ensured that the encoding space is sufficient.

[0236] In a possible embodiment, when N ≥ Z, that is, there may be other line state values in the incomplete line state block. Taking the first case above as an example, that is, the line states corresponding to the line state values may include y, -y, z, or -z. At this time, the possible permutations and combinations of the line state values are species, less than 6 .

[0237] When the incomplete line state block only contains one virtual line state value, at this time, there are 6 possible line state values for the first bit of the line state block, 5 possible line state values for the second bit, and so on. For the Zth bit, since it needs to be different from the Z - 1th bit, there is only one possible value at this time, and there is also only one possible value for the subsequent line state values. At this time, the possible permutations and combinations of the line state values are 6 .

[0238] When the incomplete line state block only contains two virtual line state values, at this time, there are 6 possible line state values for the first bit of the line state block, 5 possible line state values for the second bit, and so on. For the Z - 1th bit, since it needs to be different from the Z - 2th bit, there is only one possible value at this time, and there is also only one possible value for the subsequent line state values. At this time, the possible permutations and combinations of the line state values are 6 .

[0239] When the incomplete line state block contains three virtual line state values, at this time, the possible permutations and combinations of the line state values are 6 .

[0240] And so on, until the incomplete line state only contains Z real line state values. At this time, the possible permutations and combinations of the line state values are 6. It can be understood that when the number of real line state values contained in the line state block is less than Z, the possible line state combinations are the same as the case of N < Z, which will not be elaborated here, and there are 6 × (Z - 1) combinations.

[0241] That is, the possible combinations at this time are

[0242] After summing up the formula, we get

[0243] To verify the above reasoning process, take N = 10 and Z = 7 as an example below. Here, the numbers in each cell represent the possible true line state values, and -- represents the current virtual line state value.

[0244]

[0245] That is, there are 6×5×5 + 6×5 + 6×7 = 222 permutations and combinations.

[0246] Substitute the values into the formula, 3 / 2(5 3 -1) + 6×6 = 222 permutations and combinations.

[0247] When the mode of the transmission channel of C-PHY is the LP mode, the generated line state block is the second line state block, and the second state block only includes one line state. There are 4 possible line state values in the LP mode. Therefore, there are 4 possible values for the line state values included in the corresponding second line state block.

[0248] If the mode of the transmission channel of C-PHY is the ALP mode, the generated line state block is the third line state block, and the third state block only includes one line state value. There are two possible line states in the ALP mode. Therefore, there are 2 line state values included in the third line state block.

[0249] In the prior art, for the line states in the HS mode, ALP mode or LP mode in C-PHY, the line state values are sampled respectively. After obtaining the line state values, different binary coding methods are adopted according to different modes. In the embodiments of the present application, for the sampling results of the line state values in the three modes, a line state block with a unified structure is generated. Thus, a unified mapping circuit can be used to map the line state block into a binary number. The binary number coding space includes all possible symbol combination cases in the C-PHY protocol, ensuring the integrity of the transmitted information.

[0250] See Figure 8 shows a coding classification diagram. To accommodate the above various possibilities, for the case of N < Z, the number of bits X of the binary number is an integer that satisfies

[0251] To reduce the number of bits of the binary number and improve the coding efficiency, the number of bits X of the binary number is the smallest integer that satisfies At this time, all cases of the first line state block, the second line state block and the third line state block can be accommodated.

[0252] In one example, if Z=14, and N is set to be less than Z, then N can be set to 10. The complete line state block of the first line state block contains 6×5... 9 =11,718,750 possibilities. The first, second, and third line state blocks have 11,718,750 + 6 × (10⁻¹) + 2 + 4 = 11,718,810 possible combinations. To map all possible line states to a unique X-bit binary number, X must be at least 24. Understandably, X of 25, 26, or even larger values ​​is also feasible.

[0253] For the case where N>Z, the number of bits X in the binary number satisfies... Integers.

[0254] To reduce the number of bits in a binary number and improve encoding efficiency, the number of bits X in the binary number must satisfy... The smallest integer.

[0255] In another embodiment, if Z=14, and N is set to be greater than Z, then N=20 can be used. In this case, the complete line state block of the first line state block includes 6×5 19 The incomplete line status block includes (5) possible combinations. 6 -1) × 3 / 2 + 78 combinations, the first line state block, the second line state block, and the third line state block have 6 × 5 combinations. 19 +(5) 6 -1)×3 / 2+78+2+4 possible combinations. At this time, the minimum value of X is 47.

[0256] This invention further proposes an encoding method with flag bits to distinguish different encoding methods, which can further compress the number of bits of the binary number representing the line status block, improve encoding efficiency, and facilitate decoding.

[0257] For details, see Figure 9 The diagram illustrates the encoding with flag bits. The encoding result of the line status block is represented by an X-bit binary number, where 1 flag bit from the X-bit binary number indicates the corresponding encoding situation, and L bits represent the binary mapping result of the line status block, where X = 1 + L.

[0258] See Figure 10 The X-bit binary number uses a 1-bit flag to indicate whether the line status block belongs to case A or case B. Case A indicates that the first line status block is encoded, including complete and incomplete line status blocks, while case B indicates that the second or third line status block is encoded.

[0259] It can be understood that for the first line status block, it is encoded as an L-bit binary number among the X-bit binary numbers. At this time, the L-bit binary number needs to cover all possible values of the first line status block.

[0260] When N < Z, L is an integer that satisfies Furthermore, L is the smallest integer that satisfies

[0261] Among them, as described above, the permutations and combinations of the possible line status values in the complete line block have 6 kinds, and the maximum number of possibilities for the incomplete line status block is (N - 1) × 6.

[0262] When N > Z, L is an integer that satisfies Furthermore, L is the smallest integer that satisfies

[0263] For the second line status block or the third line status block, it is encoded as an L-bit binary number among the X-bit binary numbers.

[0264] Since a 1-bit flag is used to distinguish the HS mode (the first line status block) and the non-HS mode (the second line status block or the third line status block), the value space of the encoding result is expanded. For the non-HS mode, the required number of codewords is much smaller than that of the first line status. At this time, the redundant codewords in the state space can also be used to represent other custom information codes to provide more functions.

[0265] In another embodiment, refer to Figure 11 , use a 1-bit flag in the X-bit binary number to indicate whether the line status block belongs to case A or case B, where case A represents the complete line status block of the first line status block, and case B represents the incomplete line status block of the first line status block, the second line status block, or the third line status block.

[0266] For the complete line status block of the first line status block, it is encoded as an L-bit binary number among the X-bit binary numbers, and L is an integer that satisfies Furthermore, L is the smallest integer that satisfies

[0267] For the incomplete line status block of the first line status block, the second line status block, or the third line status block, it is encoded as an L-bit binary number among the X-bit binary numbers.

[0268] ​​​As described above, for the incomplete line status block in the HS mode and the second and third line status blocks in the non-HS mode, the possible values they have are still much smaller than the number of possible values of the complete line status block. Therefore, the L-bit binary numbers that meet the encoding requirements of the complete status block are sufficient to encode the incomplete line status block in the HS mode and the second and third line status blocks in the non-HS mode. At this time, the extra codewords in the state space can also be used to express other custom information codes to provide more functions.

[0269] In one embodiment, if Z = 14, for the case of the incomplete line status block when N > Z, assuming N > Z, N can take the value N = 20, and substituting N into , the calculated result is L = 47 bits. At this time, for the incomplete line status block, the second line status block, and the third line status block, there are (5 6 - 1) × 3 / 2 + 78 + 2 + 4 = 23,520 possible combination cases, which can be expressed using 15-bit encoding, much less than the number of bits required for encoding the complete line status block. It can be understood that for the case of N < Z, the possible combination cases of the incomplete line status block, the second line status block, and the third line status block are much less than those of the complete line status block. Therefore, L only needs to satisfy 即可。

[0270] According to a further embodiment of the present application, to simplify the size of the encoding code table, reduce the complexity of encoding, and improve the real-time performance and efficiency of encoding, for the first line status block in the HS mode, the line status block is divided into multiple line status sub-blocks. Each line status sub-block is mapped to a binary code, thus avoiding the problem of complex encoding caused when the N value is too large. By dividing it into multiple line status sub-blocks, encoding is performed separately or individually for each line status sub-block, thereby reducing the complexity of encoding. [[ID=!4]]

[0271] Specifically, referring to FIG. 6(b), an example of a line status sub-block according to the present invention is shown. A line status block includes k line status sub-blocks (sub-blocks), and each line status sub-block includes m line statuses, where both k and m are integers. It can be understood that the second and third line status blocks only contain one real line status value and do not need to be divided into multiple line status sub-blocks for encoding.

[0272] For example, after obtaining the first line status block containing N line status values, m line status values among the N line status values are used to generate a line status sub-block, and finally k line status sub-blocks are generated.

[0273] Alternatively, in response to obtaining m consecutive line states of lines A, B, and C, a line state sub-block including m line state values ​​is generated, and k consecutive line state sub-blocks are combined to obtain a first line state block.

[0274] Therefore, the mapping circuit only needs to receive a line state sub-block containing m line states and output a p-bit binary number that uniquely represents all possible values ​​of the line state sub-block after mapping. It also combines the p-bit binary numbers corresponding to the k line state sub-blocks of the first line state block to obtain an X-bit binary number.

[0275] Optionally, k mapping circuits are provided to encode the k line state sub-blocks of the first line state block in parallel, resulting in k p-bit binary numbers.

[0276] Alternatively, a single mapping circuit can be used to encode one of the line state sub-blocks at a time, resulting in a p-bit binary number. The k line state sub-blocks of the first line state block are encoded sequentially to obtain k p-bit binary numbers.

[0277] Therefore, in the above implementation, the encoder that performs binary encoding of the line state sub-blocks has a width of m line states instead of N line states. This simplifies the encoding size, reduces the encoding complexity, and improves the encoding / decoding and line state transmission rates.

[0278] Similar to the first line state block, which includes complete line state sub-blocks or incomplete line state sub-blocks, a line state sub-block can also be a complete line state sub-block or an incomplete line state sub-block.

[0279] The complete line state subblock includes m actual line state values. Because the C-PHY protocol stipulates that adjacent line states cannot be the same, the possible permutations and combinations of line state values ​​in the complete line state subblock have 6... Q combinations can be represented using p-bit binary encoding, requiring only 2... p >Q is sufficient. Therefore, p can be the smallest integer greater than Log2(Q). Then, the k line state sub-blocks are combined into a line state block, and each line state block has N=m×k line states, where k and m are both integers.

[0280] In one embodiment, if Z=14 and N=20, the line state block is divided into two line state sub-blocks with 10 line state values ​​each, i.e., k=2 and m=10. For a complete line state sub-block, substitute 2... p >6 The minimum value of p is obtained as 24 bits, which is much smaller than the 47 bits required for a complete line state block encoding with 20 line state values, thus reducing the hardware complexity of implementing the mapping circuit and helping to shorten the time required for mapping.

[0281] The incomplete line state sub-block includes j HS-mode real line state values and m - j virtual line state values, where j < m and j is a positive integer.

[0282] Similar to the above analysis of the line state combination for the line state block, referring to the analysis in conjunction with FIGS. 7(a) and 7(b), for m < Z, there are a total of (m - 1)×6 line state combination cases for the incomplete line state sub-block. Therefore, to cover all cases, take the value according to the maximum possible number (m - 1)×6 to ensure that the coding space is sufficient to accommodate all these possible values.

[0283] Therefore, in order to be compatible with the various possibilities of the complete line state sub-block and the incomplete line state sub-block, the codeword length p of the line state sub-block satisfies 2 p >6×5 （m-1） + (m - 1)×6 is an integer.

[0284] To further reduce the codeword length, p is the smallest integer that satisfies 2 p >6×5 （m-1） + (m - 1)×6.

[0285] For m > Z, the possible line state combination cases of the incomplete line state sub-block are the same as those for N > Z and will not be elaborated here. It should be noted that in the actual coding process, when using the line state sub-block for coding, the value of m is generally selected to be less than Z. The following analysis of the line state sub-block only considers the case of m < Z. It can be understood that if the value of m is too large, it will increase the difficulty of coding. The line state sub-block can be further split into line state sub-sub-blocks with fewer line state values, and the way of encoding by the line state sub-sub-blocks and combining them into the line state sub-block is the same as the way of encoding the line state sub-block and combining it into the line state block, which will not be elaborated here.

[0286] For the first line state block containing the line state sub-block, as described above, it represents the X-bit binary number of the first line state block. The codeword X may not include a flag bit, that is, X = L; or it may include a flag bit, that is, X = 1 + L, where L = k×p.

[0287] When the codeword X does not contain a flag bit, X=L. When the first line state block is directly mapped to an X-bit binary number, each line state sub-block is directly mapped to a p-bit binary number that can uniquely represent all the values ​​of the line state sub-block, and the p-bit binary numbers corresponding to each of the k line state sub-blocks are combined to obtain an X-bit binary number, where X=k×p.

[0288] When the codeword contains a flag bit, X = 1 + L. The 1-bit flag bit in the X-bit binary number indicates whether the line status block is the first line status block, the second line status block, or the third line status block.

[0289] For the first line state block, it is encoded as an L-bit binary number in an X-bit binary number, where L = k × p, and each line state sub-block is encoded as a p-bit binary number that can uniquely represent all the values ​​of the line state sub-block, and the p-bit binary numbers corresponding to each of the k line state sub-blocks are combined to obtain an L-bit binary number.

[0290] For the second or third line status block, which requires fewer binary bits, it can be encoded as an L-bit binary number within an X-bit binary number.

[0291] At this point, L satisfies 2. L >k×6×5 (m-1) An integer consisting of + (m-1)×6.

[0292] Furthermore, to reduce the size of the binary codeword, L satisfies 2 L >k×6×5 (m-1) The smallest integer of + (m-1)×6.

[0293] In another embodiment, a 1-bit flag in the X-bit binary number is used to indicate whether the line state block is a complete line state sub-block of the first line state block, or an incomplete line state sub-block of the first line state block, the second line state block, or the third line state block.

[0294] For the first line state block, it is encoded as an L-bit binary number within an X-bit binary number, where L = k × p. Each line state sub-block is encoded as a p-bit binary number that uniquely represents all values ​​of the sub-block. Combining the p-bit binary numbers corresponding to the k sub-blocks yields an L-bit binary number. L satisfies 2... L >k×6×5 (m-1) An integer to correspond to a complete line state sub-block.

[0295] The number of codewords required for incomplete line state sub-blocks and non-HS mode second and third line state blocks is much smaller than that for complete line state sub-blocks. In this case, the extra codewords can be used for other encodings after encoding the incomplete line state sub-block, second line state block or third line state block, so as to improve efficiency.

[0296] To reduce the size of binary codewords, L satisfies 2 L >k×6×5 (m-1) The smallest integer.

[0297] Furthermore, the flag bit of the present invention is not limited to a flag bit of size 1 bit. Any flag bit is sufficient. That is, different values ​​of the flag bit indicate which type of line state block the subsequent binary code corresponds to. In one embodiment, the first value of the flag bit represents the first case (case A) of the X-bit binary number encoding, such as the encoding of the complete line state sub-block of the first line state block; the second value of the flag bit represents the second case (case B) of the X-bit binary number encoding, such as the encoding of the incomplete line state sub-block of the first line state block, the second line state block, or the third line state block.

[0298] See Figure 12 A block diagram of a C-PHY signal transmission system according to a specific embodiment of the present invention is shown.

[0299] The C-PHY signal transmission system includes a C-PHY Primary and a C-PHY Secondary, and a cable connecting them. The cable includes a transmitting end and a receiving end, and a transmission medium connecting them. The transmitting end includes circuitry 10 for encoding C-PHY signals, and the receiving end includes decoding circuitry 20 for generating C-PHY signals. The transmission medium is, for example, a single optical fiber or a pair of copper wires for transmitting differential signals. Optionally, the transmission medium may be multiple optical fibers or a single copper wire. Still optionally, the transmission medium may also include a transmission medium for transmitting power and / or low-speed signals. The circuitry 10 for encoding the C-PHY signals is used to implement the encoding method for transmitting C-PHY signals disclosed above in this invention.

[0300] The circuit 10 for encoding C-PHY signals includes: a preprocessing circuit 11 for receiving the line states of lines A, B, and C, identifying the mode of the C-PHY transmission channel based on the line states, and generating line state blocks based on the mode of the C-PHY transmission channel; a mapping circuit 12 for mapping the line state blocks to binary numbers that can uniquely identify the line state blocks; and a transmitting circuit 17 for transmitting the binary numbers through a transmission medium.

[0301] In a C-PHY signal, the line state refers to the combination of analog signal levels driven on the three lines (A / B / C). This voltage combination can be sampled to obtain a digital signal, that is, the line state value. For example, sampling at the Symbol clock frequency and passing through a high-speed differential comparator can obtain a line state.

[0302] The preprocessing circuit 11 samples and combines the analog signal levels of the three lines (A / B / C) to obtain the line state value, and combines N line state values into a line state block. The preprocessing circuit 11 also identifies the mode in which the C-PHY transmission channel is located and outputs information indicating the HS mode, LP mode, or ALP mode. For example, it can be identified by characteristics of the physical layer such as amplitude and period.

[0303] In response to the mode of the C-PHY transmission channel being the LP mode, the preprocessing circuit 11 generates a second line state block for each real line state value in the LP mode. The second state block includes only one real line state value.

[0304] In response to the mode of the C-PHY transmission channel being the ALP mode, the generated line state block is the third line state block. The third state block includes only one real line state value.

[0305] If the mode of the C-PHY transmission channel is the HS mode, the preprocessing circuit 11 generates a first line state block from the received real line state values in the HS mode. The first line state block contains N line state values.

[0306] As an example, the preprocessing circuit 11 identifies the mode of the C-PHY channel based on the line state received on the C-PHY channel and the physical characteristics of the signal. For example, the preprocessing circuit 11 generates a first line state block (complete line state block) for each N real line state values in the HS mode.

[0307] For another example, when the C-PHY transmission channel switches from the HS mode to a non-HS mode, the preprocessing circuit 11 has received M line states of lines A, B, and C, and M < N. The preprocessing circuit 11 generates N - M virtual line state values, and combines the M real line state values in the HS mode and the N - M virtual line state values to generate a first line state block (incomplete line state block).

[0308] Optionally, the preprocessing circuit 11 further includes a clock unit and a frequency division unit. The clock unit is used to obtain a first clock; the frequency division unit is used to divide the first clock by N to generate a second clock.

[0309] When the transmission channel is in the HS mode, the clock unit extracts the first clock from the signals received from line A, line B, and line C. For example, the first clock is obtained according to the change of the line state. The preprocessing circuit 11 samples the line state in the HS mode using the first signal clock, and generates the first line state block according to the line state value obtained by sampling.

[0310] The frequency division unit also performs N-frequency division on the first clock to obtain the second clock, where N represents the number of line state values included in the line state block.

[0311] Optionally, the preprocessing circuit 11 also outputs an enable signal (EN), which represents, for example, that the line state block has been generated.

[0312] The preprocessing circuit 11 generates the line state block without recognizing the symbols represented by adjacent line states. The mapping circuit 12 directly generates an X-bit binary number according to the mapping of the line state block. Compared with the prior art in which the data transmitted by C-PHY is extracted by recognizing the symbols represented by adjacent line states and different coding processes are adopted according to different modes and symbols, the coding circuit of the present invention has fewer components, less coding overhead, high speed, complete coding information, and improves the encoding and decoding efficiency of the C-PHY line and the data transmission efficiency.

[0313] The mapping circuit 12 maps the first line state block into a binary number that can uniquely identify the line state block according to the second clock.

[0314] When the mode of the transmission channel is a non-HS mode, the preprocessing circuit 11 generates a second line state block or a third line state block.

[0315] The mapping circuit 12 maps the first line state block, the second line state block, or the third line state block into a binary number that can uniquely identify the line state block according to the second clock.

[0316] The mapping circuit 12 maps the first line state block into an X-bit binary number that uniquely identifies the first line state block, where the X-bit binary number represents N line state values in the HS mode. For the first line state block, when N < Z, the number of bits X of the binary number is an integer that satisfies For the case of N > Z, the number of bits X of the binary number is an integer that satisfies of the integer.

[0317] The X-bit binary number directly mapped by the mapping circuit 12 from the second line state block only represents one true line state value in the LP mode.

[0318] The X-bit binary number directly mapped by the mapping circuit 12 from the third line state block only represents one true line state value in the ALP mode.

[0319] Optionally, the mapping circuit 12 also sets a flag bit in the mapped X-bit binary number to distinguish the encoding methods for different cases.

[0320] For example, see also Figure 9 X = 1 + L. Mapping circuit 12 uses a 1-bit flag bit from the X-bit binary number to represent the corresponding encoding, and uses L bits to represent the corresponding line status block. See also... Figure 10 In the X-bit binary number, the 1-bit flag indicates whether the line status block belongs to condition A or condition B. See also another embodiment. Figure 11 The mapping circuit 12 uses a 1-bit flag bit in the X-bit binary number to indicate whether the line state block belongs to condition A or condition B.

[0321] In an optional implementation, to reduce the complexity of the mapping circuit 12 and improve the real-time performance and efficiency of the encoding, multiple line state sub-blocks are set within the line state block for the HS mode. Each line state sub-block is encoded separately or individually, thereby reducing the encoding difficulty and latency. The preprocessing circuit 11 generates k line state sub-blocks, each containing m line state values, where N = k × m. Optionally, the second and third line state blocks contain only one real line state value, eliminating the need to divide them into multiple line state sub-blocks for encoding.

[0322] Accordingly, the mapping circuit 12 encodes each line state sub-block of the first line state block into a p-bit binary number that can uniquely represent all the values ​​of the line state sub-block, and combines the p-bit binary numbers corresponding to the k line state sub-blocks of the first line state block to obtain an X-bit binary number.

[0323] Optionally, the mapping circuit 12 simultaneously encodes k line state sub-blocks and combines the codes of the k line state sub-blocks to obtain an X-bit binary output.

[0324] Optionally, the preprocessing circuit 11 sequentially obtains the line states. After obtaining m line states, the preprocessing circuit 11 generates a line state sub-block. Once a line state sub-block is obtained, the mapping circuit 12 performs encoding. After encoding k line state sub-blocks, the mapping circuit 12 combines the k codes to obtain an X-bit binary number for output.

[0325] Corresponding to complete line state blocks and incomplete line state blocks, line state sub-blocks are either complete line state sub-blocks or incomplete line state sub-blocks.

[0326] For the complete line status block, the line status sub-block generated by the preprocessing circuit 11 contains m true line status values in the HS mode, which is called the complete line status sub-block.

[0327] For the incomplete line status block, the line status sub-block generated by the preprocessing circuit 11 contains j true line status values in the HS mode and m - j virtual line status values, which is called the incomplete line status sub-block, where j < m and j is a positive integer.

[0328] The mapping circuit 12 encodes each complete line status sub-block or incomplete line status sub-block to obtain a p-bit binary number, and combines the p-bit binary numbers corresponding to each complete line status sub-block or incomplete line status sub-block to obtain an X-bit binary number.

[0329] For the embodiments including line status sub-blocks, as above, there are also cases with flag bits.

[0330] When the codeword X does not contain a flag bit, X = L. The mapping circuit 12 encodes each line status sub-block into a p-bit binary number that can uniquely represent all the values of the line status sub-block, and combines the p-bit binary numbers corresponding to k line status sub-blocks to obtain an X-bit binary number that uniquely identifies the first line status block, where X = k×p. When the mapping circuit 12 encodes the second line status block or the third line status block into an X-bit binary number, it can also use the codewords in the codeword space of the X-bit binary number except for the codewords used to encode the first line status block to encode the second line status block or the third line status block.

[0331] When the codeword contains a flag bit, X = 1 + L. The mapping circuit 12 uses a flag bit with a size of 1 bit in the X-bit binary number to represent two different combination cases of the line status block. For example, case A is the first line status block, and case B is the second line status block or the third line status block.

[0332] For the first line status block, the mapping circuit 12 encodes it into an L-bit binary number in the X-bit binary number, where L = k×p, and each line status sub-block is encoded into a p-bit binary number that can uniquely represent all the values of the line status sub-block, and combines the p-bit binary numbers corresponding to k line status sub-blocks to obtain an L-bit binary number.

[0333] For the second line status block or the third line status block, the mapping circuit 12 encodes it into an L-bit binary number in the X-bit binary number.

[0334] In another embodiment, a 1-bit flag in an X-bit binary number indicates whether the line state block is in case A or case B, where case A is a complete line state sub-block of the first line state block, and case B is an incomplete line state sub-block of the first line state block, a second line state block, or a third line state block.

[0335] In an optional embodiment, the preprocessing circuit 11 uses a second clock to sample the line state in non-HS mode, and generates a second line state block or a third line state block based on each sampling result. In this invention, a second clock (instead of a first clock) is used to sample the line state in non-HS mode because the signal rate of LP mode or ALP mode is lower than that of HS mode. If the high-speed clock of HS mode is directly used to sample the low-speed signals of LP mode or ALP mode, a large number of redundant sampling points will be generated, wasting power and increasing the complexity of subsequent processing.

[0336] The mapping circuit 12 uses a second clock to map the incomplete line state sub-blocks of the first line state block, as well as the second and third line state blocks. This ensures consistent circuit processing timing across the three modes. Subsequent circuits (such as the transmitting circuit 17) do not need to perceive the differences in the mapping results of the three line state blocks, and can therefore process the output of the mapping circuit 12 in the same way and transmit it to the receiving end. This enables fast and seamless switching between different modes: HS, LP, and ALP. The use of a unified second clock also allows the second and third line state blocks to carry a line state.

[0337] The transmitting circuit 17 is used to transmit the binary number output by the mapping circuit 12 through the transmission medium. The transmitting circuit 17 is, for example, a SerDes, which transmits, for example, an X-bit binary number output by the mapping circuit 12 serially over the transmission medium.

[0338] Optionally, the transmitter also includes an electro-optical conversion circuit to convert the serial signal output by the transmitter circuit 17 into an optical signal and send it to the receiver via an optical fiber.

[0339] Figure 18 A circuit 10 for encoding C-PHY signals according to yet another embodiment of this application is shown.

[0340] The circuit 10 used to encode C-PHY signals includes a preprocessing circuit 10, a mapping circuit 12, and a parallel-to-serial conversion circuit 16.

[0341] The input terminal of the parallel-to-serial conversion circuit 16 is connected to the mapping circuit 12. This connection can be direct or indirect, and it is used to convert the received binary number from parallel to serial to generate serial data.

[0342] The serial data generated by the parallel-to-serial conversion circuit 16 is suitable for serial transmission via a transmission medium. The serial data generated by this invention requires only one transmission medium for transmission, thereby reducing the number of transmission media. For example, the transmission medium of this invention can be a single optical fiber or a differential copper wire.

[0343] Optionally or further, the circuit 10 for encoding the C-PHY signal also includes a frame synchronization (Sync TX) circuit 15, whose inputs are connected to the frequency divider unit and the mapping circuit 12, respectively, for inserting a synchronization code into the data to be converted from parallel to serial. The output of the frame synchronization (Sync TX) circuit 15 is provided to the parallel-to-serial conversion circuit 16. The parallel-to-serial conversion circuit 16 also performs parallel-to-serial conversion on the synchronization code to generate serial data. For example, the synchronization code is not a symbol defined by the C-PHY protocol, but is used to transmit synchronization information between the circuit 10 for encoding the C-PHY signal and the decoding circuit 20 for generating the C-PHY signal, so that the circuit 10 for encoding the C-PHY signal informs the decoding circuit 20 for generating the C-PHY signal, for example, that the first X-bit binary number has started transmission, that a conversion from HS mode to non-HS mode has occurred, or that the operating status is indicated when there is no signal transmission from the Primary.

[0344] The frame synchronization (Sync TX) circuit 15 inserts a synchronization code before the transmission of the first binary number begins, during the switch between HS mode and non-HS mode, or when the non-HS mode lasts for an extended period. Optionally, the synchronization code inserted when the non-HS mode lasts for an extended period can be multiple synchronization codes inserted periodically.

[0345] In one embodiment, the frame synchronization (Sync TX) circuit 15 can insert a synchronization code by recognizing the different electrical characteristics of various line states.

[0346] The purpose of the synchronization code is to enable the receiver to perform frame synchronization. It can select special Y bit data that is not included in the DC balanced Xb / Yb encoding table. For example, it has a long pattern of consecutive "0" or "1" to make the receiver easily recognize the synchronization code.

[0347] Optionally or further, the circuit 10 for encoding the C-PHY signal also includes a DC balance encoding circuit 14, whose input is connected to the frequency division unit and the mapping circuit 12 respectively, and whose output is connected to the frame synchronization circuit 15, for DC balancing of the data using a second clock.

[0348] Before inserting the synchronization code, the DC balance encoding circuit 14 performs DC balance encoding on the data. The DC balance can be achieved using an Xb / Yb encoder.

[0349] When the number of bits X in a binary number is large, the Xb / Yb encoder can be divided into multiple smaller encoders to reduce encoder complexity. For example, multiple combinations of 3b / 4b encoders, 5b / 6b encoders, 7b / 8b encoders, 9b / 10b encoders, etc. are used. The final output Y bit data is composed of the outputs of multiple smaller encoders.

[0350] Optionally or further, the circuit 10 for encoding the C-PHY signal also includes a scrambler circuit 13, whose inputs are connected to the frequency divider unit and the mapping circuit 12, respectively, and whose output is connected to the DC-balanced encoding circuit 14, for scrambling the received data. Before DC balancing the data, the scrambler circuit 13 also scrambles the X-bit binary number. The scrambler circuit 13 is, for example, a non-self-synchronizing scrambler. Optionally, a synchronization code is also used to seed the scrambler circuit 13 / descrambler circuit 23 at the transmitting and receiving ends. When the transmitting end sends the synchronization code, it resets the seed of the scrambler circuit 13; and when the receiving end receives the synchronization code, it also uses the synchronization code to seed the descrambler circuit 23 at the receiving end. That is, by using the synchronization code, the scrambling circuit 13 / descrambling circuit 23 of both the transmitting and receiving parties reset their seeds to the same preset initial value at the same known time point, thereby ensuring that the pseudo-random sequences generated by both parties are completely consistent, laying the foundation for subsequent correct scrambling / descrambling.

[0351] The number N of line state values ​​contained in the line state block is optional. It is selected based on the complexity and efficiency of the mapping in the mapping circuit. The larger N is, the greater the complexity of binary encoding / decoding, scrambling / descrambling, and DC-balanced encoding / decoding.

[0352] See Figure 5 This invention discloses a decoding method for transmitting C-PHY signals, which is used to decode the binary number obtained by the encoding method of C-PHY signals disclosed in this invention.

[0353] Figure 5 The decoding method is used in the decoding circuit 20 for generating C-PHY signals in the embodiments of this application. The decoding circuit 20 for generating C-PHY signals receives the binary number output by the circuit 10 for encoding C-PHY signals, converts the binary number into line status and outputs it to the Secondary (slave device).

[0354] In this invention, the decoding method corresponds to the encoding method, and the decoding method is the inverse transformation of the encoding method. The same terms have the same definition and interpretation.

[0355] The decoding method of the decoding circuit 20 used in this application to generate C-PHY signals is not the same as the process in the prior art where the C-PHY Primary (master device) outputs the line status from binary numbers using three-phase encoding technology. See Figure 2(a) for a diagram illustrating the process of mapping binary numbers to line status at the master device end in the prior art. In HS mode, each 16-bit binary number is mapped into 7 Symbols through a specific mapping table defined by the C-PHY protocol, with each Symbol represented by a 3-bit binary number. The 7 Symbols are then converted from parallel to serial and output sequentially. This mapping process involves multiple encoding conversions, is complex, time-consuming, and prone to errors. See Figure 2(a) for more details. Figure 5 The decoding method of the present invention directly decodes the received X-bit binary number into a line status block representing the line status. It only requires one decoding conversion process, which reduces the complexity of the decoding circuit and decoding method, with low overhead, high speed, and complete information.

[0356] according to Figure 5 The method of the embodiment includes the following steps:

[0357] Obtain an X-bit binary number from the transmission medium connected to the transmitting end, and directly map the binary number to a line status block representing the line status; the binary number and the line status block correspond one-to-one; the line status block contains 1 or N line status values; and according to the line status values ​​of the line status block, drive the A line, B line and C line of the C-PHY to be in the line status corresponding to the line status values.

[0358] When the C-PHY transmission channel is in HS mode, the line status block obtained by mapping binary numbers is called the first line status block. The first line status block includes at least one real line status value in HS mode.

[0359] When the C-PHY transmission channel is in LP mode, the line status block obtained by mapping binary numbers is called the second line status block. The second line status block only represents one line status value in LP mode.

[0360] When the C-PHY transmission channel is in ALP mode, the line status block obtained by mapping binary numbers is called the third line status block. The third line status block only represents one line status value in ALP mode.

[0361] For ALP and LP modes, based on a line state value in LP mode or ALP mode, the A, B, and C lines of the C-PHY are driven to be in the line state corresponding to the line state value.

[0362] Corresponding to the encoding method in the embodiments of this application, the first line state block may include a complete line state block and an incomplete line state block.

[0363] Specifically, based on the N real line state values ​​of the complete line state block, the A, B, and C lines of the C-PHY are driven to be in the line states corresponding to the real line state values, respectively; based on the M real line state values ​​of the HS mode of the incomplete line state block, the A, B, and C lines of the C-PHY are driven to be in the line states corresponding to the real line state values, without needing to drive the C-PHY lines to be in the line states corresponding to the virtual line state values.

[0364] Corresponding to the encoding method in the embodiments of this application, the X-bit binary number received by the receiving end may not include the flag bit, i.e., X=L, or it may include the flag bit, i.e., X=1+L.

[0365] See Figure 13 This illustrates a decoding method for an X-bit binary number including a flag bit, where the 1-bit flag bit in the X-bit binary number indicates whether the line status block is the first line status block, the second line status block, or the third line status block.

[0366] To perform decoding, obtain an X-bit binary number. Remove the flag bits from the X-bit binary number to obtain an L-bit binary number. Map the L-bit binary number to a line status block.

[0367] Based on the flag values, the line status block is identified as either the first line status block, the second line status block, or the third line status block. For the first line status block, at least one line status value is used to sequentially drive the C-PHY channel. For the second or third line status block, one of the line status values ​​is used to drive the C-PHY channel.

[0368] See Figure 14 This illustrates a decoding method for an X-bit binary number that includes flag bits and has line status subblocks. In this case, the first line status block includes multiple line status subblocks.

[0369] To perform decoding, an X-bit binary number is obtained. The flag bits are removed from the X-bit binary number, resulting in an L-bit binary number. Based on the flag bits, if the line status block carried by the X-bit binary number is determined to be the first line status block, the L-bit binary number is divided into k parts, each containing p-bit binary numbers, where L = k × p. These k p-bit binary numbers are mapped to first line status sub-blocks; each first line status sub-block contains m line status values, N = m × k. For each first line status sub-block mapped from the p-bit binary number, the m line status values ​​are used to drive the C-PHY channel sequentially. Optionally, only the actual line status values ​​from the m line status values ​​are used to drive the C-PHY channel.

[0370] The process of mapping k p-bit binary numbers to first line state sub-blocks can be performed simultaneously or sequentially. If performed simultaneously, k mapping circuits are required; if performed sequentially, a single mapping circuit can be used in a time-sharing manner, thus reducing the required size of the mapping circuitry. Once a first line state sub-block is obtained, the C-PHY channel can be driven for output. Alternatively, the C-PHY channel can be driven for output after obtaining k first line state sub-blocks.

[0371] When determining whether the line status block carried by the X-bit binary number is the second or third line status block based on the flag bit, the C-PHY channel is driven by one of the line status values ​​of the second or third line status block mapped by the L-bit binary number.

[0372] See Figure 15 This illustrates a decoding method for an X-bit binary number excluding flag bits and without line status subblocks. For decoding, the X-bit binary number is directly mapped to line status blocks representing line states, such as first, second, or third line status blocks. The C-PHY channel is then driven based on the line status values ​​within each line status block.

[0373] See Figure 16 This paper illustrates a decoding method for an X-bit binary number without flag bits and containing line status sub-blocks. To perform decoding, an X-bit binary number is obtained; the X-bit binary number is then divided into k parts, each containing p bits, where X = k × p.

[0374] The p-bit binary number is mapped to a first line state sub-block representing the line state; the first line state sub-block contains m line state values, where N=m×k; each line state value is used to drive the A, B and C lines of the C-PHY to the line state corresponding to the line state value.

[0375] Optionally, when mapping the p-bit binary number, the line status block to which it belongs is also identified as either the second or third line status block. For example, the line status block to which it belongs is represented by a specified code of the p-bit binary number. Accordingly, the C-PHY channel is driven by a single line status value carried by the second or third line status block.

[0376] See Figure 17 This illustrates the decoding process for an X-bit binary number in one embodiment of the invention. This decoding process is applicable, for example, to... Figure 18 The binary data sent by the transmitter in the embodiment.

[0377] The receiving end obtains the serially transmitted binary data from the transmission medium and uses techniques such as CDR (Clock and Data Recovery) to obtain a clock synchronized with the data. The recovered clock is then used to generate a clock (also called the second clock) that operates at the same frequency as the second clock used by the transmitting end. By multiplying the second clock by N, a clock (also called the first clock) that operates at the same frequency as the first clock used by the transmitting end is also obtained.

[0378] Synchronization codes are extracted from binary data. Based on these synchronization codes, serial-to-parallel conversion is performed on the binary data between adjacent synchronization codes to obtain a Y-bit data block. DC-balanced decoding is performed on the Y-bit data block to obtain X-bit binary data. Descrambling is applied to the X-bit data to obtain descrambled X-bit data. Binary demapping is then performed on this X-bit data to obtain the line state block according to an embodiment of this application.

[0379] According to Figure 17 In the embodiments, DC balanced decoding, descrambling, and demapping are the inverse processes of DC balanced encoding, scrambling, and binary mapping performed by the transmitting end, respectively.

[0380] According to Figure 17 In the embodiments, the process of binary demapping of X-bit data is related to... Figures 13-16 The illustrated embodiments are similar. For example, if X bits of data do not include flag bits, when performing binary demapping on the X bits of data, it becomes clear whether the demapping result is a first line state block, a second line state block, or a third line state block. For the first line state block, the C-PHY channel is driven sequentially using a first clock and N line state values ​​from the first line state block to provide the line state values ​​to the C-PHY Secondary. If the first line state block is an incomplete line state block, only the actual line state values ​​within it are used to drive the C-PHY channel. For the second or third line state block, a single line state value from it is used to drive the C-PHY channel.

[0381] Return to view Figure 12 The receiving end of the cable connecting the C-PHY Primary and Secondary includes a decoding circuit 20 for generating C-PHY signals.

[0382] The decoding circuit 20 for generating C-PHY signals decodes signals received from the transmission medium of the cable, generates C-PHY line status, and provides it to the Secondary. The decoding circuit 20 for generating C-PHY signals also implements the decoding method for transmitting C-PHY signals according to embodiments of the present invention.

[0383] The decoding circuit 20 used to generate C-PHY signals includes a receiving circuit 28, a demapping circuit 22, and a post-processing circuit 21.

[0384] The receiving circuit 28 is used to receive binary numbers. The demapping circuit 22 is used to directly map the received X-bit binary number into a line status block representing the line status; the binary number and the line status block correspond one-to-one; the line status block contains at least one line status value. The post-processing circuit 21 is used to drive the A, B, and C lines of the C-PHY to the line status corresponding to the line status value.

[0385] For ALP and LP modes, the demapping circuit 22 maps the X-bit binary number into a second or third line state block containing only one real line state value. The post-processing circuit 21 drives the A, B and C lines of the C-PHY to be in the line states corresponding to the line state values.

[0386] For HS mode, the demapping circuit 22 maps the X-bit binary number to a first line state block, which contains at least one real line state value of HS mode; the post-processing circuit 21 drives the A line, B line and C line of C-PHY to be in the line state corresponding to the real line state value of HS mode.

[0387] In one embodiment, the X-bit binary number includes a flag bit. The demapping circuit 22 obtains the X-bit binary number. Based on the flag bit, the demapping circuit 22 determines whether the demapped line state block is a first line state block. If the line state block is the first line state block, the L-bit binary number (after removing the flag bit) is mapped to at least one true HS mode line state value for the first line state block. If the demapping circuit 22 determines based on the flag bit that the demapped line state block is a second or third line state block, the L-bit binary number is mapped to either a second or third line state block with one line state value.

[0388] In yet another embodiment, the flag bit is used to indicate whether the demapping obtained line state block is a complete line state block in the first line state block, or an incomplete line state block in the first line state block, a second line state block, or a third line state block (see also...). Figure 11 For an incomplete line state block in the first line state block, the demapping circuit 22 removes the flag bits from the X-bit binary number and maps the remaining L-bit binary number to an incomplete line state block containing M real line state values.

[0389] In another embodiment, the first line state block obtained by demapping the X-bit binary number includes multiple line state sub-blocks. Accordingly, the demapping circuit 22 determines that the demapping obtained line state block is the first line state block based on the flag bit, then removes the flag bit from the X-bit binary number to obtain an L-bit binary number; divides the L-bit binary number into k parts, each part containing a p-bit binary number, where L = k × p, to obtain k p-bit binary numbers; and maps each p-bit binary number to a first line state sub-block containing m line state values, where N = m × k.

[0390] The post-processing circuit 21 drives the A, B and C lines of the C-PHY according to the line status values ​​in each line status sub-block.

[0391] Optionally, the demapping circuit 22 performs time-division multiplexing on each p-bit binary number. Thus, the input bit width of the demapping circuit 22 is p, instead of N. The post-processing circuit 21 responds to the line state sub-block containing m line state values ​​output each time, i.e., it drives the C-PHY channel. This reduces the complexity of the demapping circuit 22.

[0392] Optionally, the demapping circuit 22 may include multiple (e.g., k) sub-mapping circuits, each mapping a p-bit binary number to a line state sub-block. Multiple sub-mapping circuits can operate in parallel / simultaneously, thereby reducing the delay of the decoding circuit 20 used to generate the C-PHY signal.

[0393] Optionally, since the second and third line state blocks do not contain line state sub-blocks, the decoding method for the second and third line state blocks is the same as the decoding method for the case where flag bits are included but no line state sub-blocks are included.

[0394] In one embodiment, the X-bit binary number does not include the flag bit, and the first line state block obtained by demapping the X-bit binary number includes multiple line state sub-blocks. The demapping circuit 22 obtains the X-bit binary number and divides it into k parts, each part containing a p-bit binary number, where L = k × p; the demapping circuit 22 maps the k p-bit binary numbers to a first line state sub-block containing m line state values, where N = m × k.

[0395] The post-processing circuit 21 drives the A, B and C lines of the C-PHY to be in the line states corresponding to the actual line state values, based on the line state values ​​of each first line state sub-block.

[0396] Optionally, the receiver also includes a photoelectric conversion circuit to convert the optical signal from the optical fiber into an electrical signal and provide it to the receiving circuit 28.

[0397] Optionally, when the C-PHY channel is in HS mode, the post-processing circuit 21 drives the C-PHY to output the line status to the Secondary channel using a clock with the same frequency as the first clock that outputs the line status to the Primary channel. The receiving circuit 28 extracts clock information from the received data to obtain a clock with the same frequency as the first clock. Optionally, the post-processing circuit 21 may use a clock with a frequency higher than the first clock to drive the C-PHY to output the line status to the Secondary channel. The receiving circuit 28 may also use a clock signal generated by a local clock with a frequency greater than or equal to the first clock frequency.

[0398] Figure 19 A decoding circuit 20 for generating C-PHY signals according to yet another embodiment of this application is shown.

[0399] The decoding circuit 20 used to generate C-PHY signals includes a clock circuit 27, a demapping circuit 22, and a post-processing circuit 21.

[0400] Clock circuit 27 is, for example, a CDR (Clock and Data Recovery) circuit, used to recover the clock from the received serial signal. The first clock in the HS mode Primary output line state has a specified relationship with the clock of the serial signal transmitted on the transmission medium. Therefore, clock circuit 27 generates a clock (also referred to as the first clock) with the same frequency as the first clock based on the clock recovered from the received serial signal.

[0401] Optionally, the circuit 10 for encoding the C-PHY signal sends the frequency of the first clock to the decoding circuit 20 for generating the C-PHY signal via a custom information code. Thus, the decoding circuit 20 for generating the C-PHY signal extracts the frequency of the first clock from the received serial signal.

[0402] Clock circuit 27 generates a second clock using the clock recovered from the received serial signal. The second clock is an N-division of the first clock. The second clock serves as the operating clock for demapping circuit 22.

[0403] Optionally, clock circuit 27 utilizes a clock recovered from the received serial signal (denoted as Clock_s), dividing Clock_s by N to serve as a second clock used in decoding circuit 20 for generating C-PHY signals. This clock may be slightly larger than the symbol rate at which the Primary transmits data in HS mode.

[0404] The demapping circuit 22 maps the X-bit binary number to one of the first line state block, the second line state block, or the third line state block according to the second clock.

[0405] When the demapping circuit 22 outputs the first line status block, the post-processing circuit 21 drives the C-PHY channel according to the line status values ​​of the first line status block based on the first clock. When the demapping circuit 22 outputs the second line status block or the third status block, the post-processing circuit 21 drives the C-PHY channel according to one line status value contained in the second line status block or the third status block.

[0406] Optionally, the decoding circuit 20 for generating the C-PHY signal further includes a serial-to-parallel conversion circuit 26, whose input terminals are respectively connected to the receiving circuit 28, for converting the serial binary number obtained from the transmission medium into a serial-to-parallel conversion.

[0407] The synchronization code detection circuit 25, with its input connected to the clock circuit 27 and its output connected to the serial-to-parallel conversion circuit 26 and the demapping circuit 22 respectively, is used to detect the synchronization code in the received serial data. When the synchronization code is detected, a synchronization flag is generated. The synchronization flag indicates the start position of the valid data block. Then, the serial-to-parallel conversion circuit 26 extracts the valid data and outputs each Y bit of data in parallel.

[0408] Optionally, the decoding circuit 20 for generating the C-PHY signal further includes a DC balance decoding circuit 24, whose inputs are connected to the synchronization code detection circuit 25, the clock circuit 27, and the serial-to-parallel conversion circuit 26, respectively, and whose output is connected to the demapping circuit 22. This circuit performs DC balance decoding on the Y-bit binary data output by the serial-to-parallel conversion circuit 26 according to the synchronization flag, obtaining X-bit binary data. The process of the DC balance decoding circuit 24 mapping Y-bit data to X-bit data is the reverse process of the operation performed by the DC balance encoding circuit 14.

[0409] Optionally, the decoding circuit 20 for generating the C-PHY signal further includes a descrambler circuit 23, whose inputs are connected to the clock circuit 27 and the DC balanced decoding circuit 24, respectively, and whose output is connected to the demapping circuit 22. This circuit descrambles the X-bit binary data output by the DC balanced decoding circuit 24 and provides the descrambled X-bit data to the demapping circuit 22. The demapping circuit 22 maps the descrambled X-bit data to obtain a line status block representing the line status. The operation performed by the descrambling circuit 23 is the reverse process of the operation performed by the scrambling circuit 13. The operation performed by the demapping circuit 22 is the reverse process of the operation performed by the mapping circuit 12.

[0410] Optionally, a synchronization code is also used to seed the descrambling circuit 23. When the receiver receives the synchronization code, it resets its seed to a preset initial value, thereby ensuring that it generates the specified pseudo-random sequence.

[0411] The second clock serves as the operating clock for the DC balanced decoding circuit 24, the descrambling circuit 23, and the demapping circuit 22.

[0412] The post-processing circuit 21 transmits the line status to the Secondary based on the mode of the C-PHY channel. The present invention has already listed methods for identifying the mode of the C-PHY channel using flag bits. However, the present invention is not limited to this and also discloses various other methods for identifying the mode of the C-PHY channel.

[0413] In one embodiment, even if the X-bit binary number does not include the flag bit, the mode of the C-PHY transmission channel corresponding to the line status block is identified based on the X-bit binary number. Since the binary number corresponding to the line status block for different modes is different when generating the X-bit binary number, the mode of the C-PHY transmission channel can be identified when the demapping circuit 22 demaps the X-bit binary number.

[0414] In another embodiment, a synchronization code is used to identify the mode of the C-PHY transmission channel corresponding to the line status block. The transmitter inserts a synchronization code when switching between HS and LP modes or between HS and ALP modes. Since the rates of LP and ALP modes are much lower than HS mode, the synchronization code can occupy the time the transmitter spends transmitting the LP / ALP mode line status block, and the resulting delay will not affect the transmission of the LP / ALP mode line status block. The synchronization code detection circuit 25 detects the synchronization code and identifies that a mode switch has occurred. The serial-to-parallel conversion circuit 26 discards the synchronization code and uses the data after the synchronization code as valid data to generate Y bits of parallel data. This data is then DC balanced decoded and descrambled to obtain X bits of data, which are then demapped to obtain one line status value for the LP / ALP mode. The post-processing circuit then drives the C-PHY channel according to the line status.

[0415] Optionally or further, when the demapping circuit 22 generates an incomplete line state block, the post-processing circuit 21 drives the C-PHY channel based on the actual line state values ​​in the incomplete line state block. However, for virtual line state values, the post-processing circuit 21 does not use them to drive the C-PHY channel; instead, it drives the C-PHY channel based on the mode of the C-PHY transmission channel identified next. For example, if the next mode is LP, LP-111 is sent to the C-PHY channel; if it is ALP mode, ALP-Pause line state is sent.

[0416] according to Figure 18 and Figure 19In the illustrated embodiment of this application, if the Symbol rate for high-speed data transmission by the C-PHY Primary is St Gsps, and the period of each Symbol is Tt, then after signal grouping, the signal rate of each line state block is Sb = St / N, and the period is Tb = Tt × N. In the mapping circuit 12 / demapping circuit 22, scrambling circuit 13 / descrambling circuit 23, and DC balanced encoding circuit 14 / DC balanced decoding circuit 24, the X-bit or Y-bit data representing the line state block are processed in parallel, and the processing clock is the second clock. For example, the mapping circuit 12 / demapping circuit 22 requires 2 second clock cycles, the scrambling circuit 13 / descrambling circuit 23 requires 1 second clock cycle, the DC balanced encoding circuit 14 / DC balanced decoding circuit 24 requires 2 second clock cycles, and the parallel-to-serial conversion circuit 16 / serial-to-parallel conversion circuit 26 requires 1 second clock cycle. Therefore, the total delay between the transmitting and receiving ends of the cable is approximately 2 × (2 + 1 + 2 + 1) = 12 second clock cycles = 12 × Tt × N. Thus, the transmission delay of this embodiment is much smaller than that of other transmission schemes that require C PHY Symbol decoding, encoding, synchronization, and other processing.

[0417] See Figure 20 This invention discloses an active transmission device comprising a circuit 10 for encoding C-PHY signals, a decoding circuit 20 for generating C-PHY signals, and a high-speed signal transmission medium located between the two. The circuit 10 for encoding C-PHY signals is connected to a primary device (C-PHY Primary) to receive the line status of lines A, B, and C. The decoding circuit 20 for generating C-PHY signals is connected to a secondary device (C-PHY Secondary).

[0418] The high-speed signal transmission medium includes at least a single optical fiber or two differential copper wires.

[0419] In one embodiment, the high-speed signal transmission medium is optical fiber, and the active transmission device further includes at least two photoelectric conversion modules. One of the photoelectric conversion modules is connected to a transmitting circuit and is used to convert the received binary number into an optical signal. The other photoelectric conversion module is connected to a receiving circuit and is used to convert the received optical signal into an electrical signal. The photoelectric conversion module transmits the optical signal through the optical fiber. The photoelectric conversion module includes, for example, a photoelectric conversion driver, a photoelectric converter, and an optical component. The photoelectric converter is connected to the photoelectric conversion driver and the transmitting or receiving circuit. Based on the drive signal of the photoelectric conversion driver, the binary number output by the transmitting circuit is converted into an optical signal, or based on the drive signal of the photoelectric converter driver, the received optical signal is converted into a binary number for output. The optical component is used to couple the photoelectric converter to the optical fiber, coupling the received optical signal to the optical fiber or outputting it through the optical fiber.

[0420] In one embodiment, the high-speed signal transmission medium is copper wire, and the active transmission device further includes a signal conditioner. The signal conditioner is used to achieve long-distance transmission of electrical signals via the copper wire. The signal conditioner includes a signal repeater and a signal regenerator. The signal repeater is used to restore the original waveform characteristics of the high-speed digital signal through signal regeneration technology. The signal regenerator is used to compensate for signal loss through equalization and pre-emphasis. It is understood that there can be one or more signal conditioners. When there are multiple signal conditioners, they can be connected to the transmitting circuit and the receiving circuit respectively. When there is only one signal conditioner, it is connected to the transmitting circuit.

[0421] It should be noted that the above description pertains to the encoding and decoding of data from one channel (Lane) of a C-PHY. Those skilled in the art should understand that when a C-PHY uses multiple channels for transmission, it encodes and decodes the data from each channel (Lane), and the corresponding circuits for encoding the C-PHY signal and generating the C-PHY signal will also change accordingly. Optionally, two photoelectric conversion modules can be provided for one channel (Lane) of the C-PHY; if the C-PHY uses multiple channels (Lanes) for transmission, multiple sets of photoelectric conversion modules can be used.

[0422] In one embodiment, the active transmission device is a cable. Circuit 10 for encoding C-PHY signals is located inside a first plug, which is used to connect to a primary device. Decoding circuit 20 for generating C-PHY signals is located inside a second plug, which is used to connect to a secondary device. A transmission medium, which can be optical fiber or differential copper wire, is located between the first and second plugs.

[0423] In another embodiment, circuit 10 for encoding C-PHY signals is located within a first adapter for connection to a primary device, and decoding circuit 20 for generating C-PHY signals is located within a second adapter for connection to a secondary device. The first and second adapters are independent of each other. The first adapter has an output interface, and the second adapter has a receiving interface. A transmission cable connects the output and receiving interfaces, with the transmitting end (TX) and receiving end (RX) of the cable having photoelectric conversion modules or signal conditioners. The interface can be any of the following: Type-C, Type-A, HDMI, SFP / SFP optical module, QSFP, QSFP-DD, etc.

[0424] In another embodiment, see Figure 21 The circuit 10 for encoding C-PHY signals and the Primary (master device) are located within the host device, while the decoding circuit 20 for generating C-PHY signals and the Secondary (slave device) are located within the destination device. The host device provides one output interface, and the destination device has one receive interface; a cable connects the output interface and the receive interface.

[0425] Furthermore, the present invention can also be a combination of the above three solutions. For example, the circuit 10 for encoding the C-PHY signal is located inside the host, the host provides an output interface, and the decoding circuit 20 for generating the C-PHY signal is located inside the plug, which is used to connect to the destination device, and the output interface and the plug are connected by a cable; or the circuit 10 for encoding the C-PHY signal is located inside the host, the decoding circuit 20 for generating the C-PHY signal is located inside the destination device, and photoelectric conversion modules are provided inside both the host and the destination device, with fiber optic patch cords connecting the output interface and the receiving interface. The circuit 10 for encoding the C-PHY signal, the decoding circuit 20 for generating the C-PHY signal, and the photoelectric conversion module or signal conditioner can be combined according to application requirements to form different application forms, the specific details of which will not be elaborated further.

[0426] In summary, the present invention has the following advantages:

[0427] 1. Obtain the C-PHY line status, form a line status block, and map the line status block to a binary number that can uniquely identify the line status block. This eliminates the need to convert the line status to Symbol and combine 7 Symbols to map to 16 bits of data, reducing the complexity of the circuit used to encode C-PHY signals and maintaining the integrity of the encoded information. It contains all the information in the 7 Symbol to 16-bit mapping code table of the HS mode signals in the C-PHY protocol.

[0428] 2. Since only X bits of binary encoding are needed to achieve the encoding mapping of line status, the amount of data transmission is reduced and the encoding efficiency is improved.

[0429] 3. Set flags to distinguish between HS mode, LP mode and ALP mode, further reducing the number of bits in binary encoding and improving encoding efficiency.

[0430] 4. Line status sub-blocks can be set in the HS mode line status block. Encoding and decoding can be performed on each line status sub-block without waiting for all line status sub-blocks to be sent and received. This reduces the complexity of encoding and decoding and improves the efficiency and real-time performance of encoding and decoding.

[0431] Obviously, those skilled in the art will understand that the various units or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device, or alternatively, they can be implemented using computer-executable program code, thereby allowing them to be stored in a storage device for execution by the computing device. Alternatively, they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0432] The above description is a further detailed explanation of the present invention in conjunction with specific preferred embodiments. It should not be considered that the specific embodiments of the present invention are limited to this. For those skilled in the art, several simple deductions or substitutions can be made without departing from the concept of the present invention, and all such deductions or substitutions should be considered to fall within the scope of protection of the present invention as defined by the submitted claims.

Claims

1. A decoding method, characterized in that, Obtain an X-bit binary number and directly map the X-bit binary number to a line status block representing the line status; the binary number and the line status block correspond one-to-one; the line status block contains 1 or N line status values. as well as Based on the line status value of the line status block, the A, B, and C lines of the C-PHY are respectively in the line status corresponding to the line status value, wherein the line status is the voltage combination of the A, B, and C lines.

2. The decoding method according to claim 1, characterized in that, In response to the transmission channel of the C-PHY corresponding to the line status block being in HS mode, the binary number is mapped to the line status block representing the line status as the first line status block, and the X-bit binary number represents at least one real line status value of the HS mode. In response to the C-PHY's transmission channel being in LP mode corresponding to the line status block, the line status block representing the line status mapped by the binary number is the second line status block, and the X-bit binary number represents only one line status value in LP mode; In response to the line status block corresponding to the ALP mode, the line status block representing the line status mapped by the binary number is the third line status block, and the X-bit binary number represents only one line status value in the ALP mode.

3. The decoding method according to claim 2, characterized in that, The X = 1 + L, where, One bit in the X-bit binary number indicates whether the line status block is the first line status block, the second line status block, or the third line status block. The step of directly mapping the X-bit binary number to a line status block representing the line status includes: In response to the line status block being the first line status block, the flag bit in the X-bit binary number is removed, and the remaining L-bit binary number is mapped to the first line status block. In response to the line status block being the second line status block or the third line status block, the flag bit in the X-bit binary number is removed, and the remaining L-bit binary number is mapped to a line status value.

4. The decoding method according to claim 2, characterized in that, Where X=L, The step of directly mapping the binary number to a line status block representing the line status includes: The X-bit binary number is divided into k parts, each part containing p-bit binary numbers, where L = k × p.

5. The decoding method according to claim 4, characterized in that, The p-bit binary number is mapped to a first line status sub-block representing the line status; the first line status sub-block contains m line status values, where N = m × k; The first line state block is obtained by combining k consecutive line state sub-blocks, which drives the A, B and C lines of the C-PHY to be in the line state corresponding to the line state value.

6. The decoding method according to claim 3, characterized in that, Mapping the L-bit binary number to the first line status block also includes: The L-bit binary number is divided into k parts, each part containing p-bit binary numbers, where L = k × p.

7. The decoding method according to claim 6, characterized in that, The p-bit binary number is mapped to a first line status sub-block representing the line status; the first line status sub-block contains m line status values, where N = m × k; The first line state block is obtained by combining k consecutive line state sub-blocks, or the A, B and C lines of the C-PHY are driven to be in the line state corresponding to the line state value according to the line state value of the line state sub-block.

8. The decoding method according to any one of claims 1-7, characterized in that, The X-bit binary number is directly mapped to a line status block representing the line status; When the mode corresponding to the line status block is HS (high speed) mode, according to the first clock, the line status value of the line status block is used to drive the A line, B line and C line of the C-PHY to be in the line status corresponding to the line status value.

9. The decoding method according to claim 8, characterized in that, When the mode corresponding to the line status block is non-HS (non-high speed) mode, it is mapped to a line status value containing 1 bit according to the second clock and X bits of binary number. The A line, B line and C line of the C-PHY are respectively in the line status corresponding to the line status value. The second clock is obtained by dividing the first clock by N.

10. The decoding method according to claim 8, characterized in that, Extract or recover the first clock from the serial signal obtained from the transmission medium; The serial signal obtained from the transmission medium is converted from serial to parallel to generate parallel data containing the X-bit binary number.

11. A decoding method, characterized in that, Obtain an X-bit binary number and directly map the binary number to a line status block representing the transmission channel line status of the C-PHY; the binary number corresponds one-to-one with the line status block; the line status block contains 1 or N line status values.

12. The decoding method according to claim 11, characterized in that, In response to the transmission channel of the C-PHY corresponding to the line status block being in HS mode, the binary number is mapped to the line status block representing the line status as the first line status block, and the X-bit binary number represents at least one real line status value of the HS mode; the first line status block is a complete line status block or an incomplete line status block. In response to the C-PHY's transmission channel being in LP mode corresponding to the line status block, the line status block representing the line status mapped by the binary number is the second line status block, and the X-bit binary number represents only one line status value in LP mode; In response to the line status block corresponding to the ALP mode, the line status block representing the line status mapped by the binary number is the third line status block, and the X-bit binary number represents only one line status value in the ALP mode.

13. The decoding method according to claim 12, characterized in that, The X = 1 + L, where, One bit in the X-bit binary number indicates whether the line state block is a first line state block mode, a second line state block, or a third line state block. The step of directly mapping the binary number to a line status block representing the line status includes: In response to the line status block being the first line status block, the flag bit in the X-bit binary number is removed, and the remaining L-bit binary number is mapped to the first line status block. In response to the line status block being the second line status block or the third line status block, the flag bit in the X-bit binary number is removed, and the remaining L-bit binary number is mapped to a line status value.

14. The decoding method according to claim 12, characterized in that, The step of directly mapping the binary number to a line status block representing the line status includes: The X-bit binary number is divided into k parts, each part containing p-bit binary numbers, where X = k × p; The p-bit binary number is mapped to a first line status sub-block representing the line status; the first line status sub-block contains m line status values, where N = m × k; Based on the line status value of the line status sub-block, the A, B, and C lines of the C-PHY are respectively in the line status corresponding to the line status value.

15. The decoding method according to claim 13, characterized in that, The direct mapping of the L-bit binary number to the first line status block also includes... The L-bit binary number is divided into k parts, each part containing a p-bit binary number, where L = k × p; The p-bit binary number is mapped to a first line status sub-block representing the line status; the first line status sub-block contains m line status values, where N = m × k; Based on the line status value of the line status sub-block, the A, B, and C lines of the C-PHY are respectively in the line status corresponding to the line status value.

16. The decoding method according to any one of claims 11-15, characterized in that, The X-bit binary number is directly mapped to a line status block representing the line status; When the mode corresponding to the line status block is HS (high speed) mode, according to the first clock, the line status value of the line status block is used to drive the A line, B line and C line of the C-PHY to be in the line status corresponding to the line status value.

17. The decoding method according to claim 16, characterized in that, When the mode corresponding to the line status block is non-HS (non-high speed) mode, it is mapped to a line status value containing 1 bit according to the second clock and X bits of binary number. The A line, B line and C line of the C-PHY are respectively in the line status corresponding to the line status value. The second clock is obtained by dividing the first clock by N.

18. The decoding method according to claim 16, characterized in that, Extract or recover the first clock from the serial signal obtained from the transmission medium; The serial signal obtained from the transmission medium is converted from serial to parallel to generate parallel data containing the X-bit binary number.

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