A device for transmitting large-bandwidth data in multiple channels based on CPRI

Abstract

The application relates to the field of optical communication and discloses a device for transmitting large-bandwidth data in multiple channels based on CPRI; the device is divided into master and slave devices and can be remotely connected through optical fibers; a group of large-bandwidth data is transmitted in multiple channels; the data transmission delay is determined according to the characteristics of CPRI. The transmission steps include: calculating the data amount required by each channel according to the required transmission data size, modifying the interface bottom layer Serdes parameters to adapt to the sampling clock, and adjusting the CPRI minimum basic frame unit size. The master device converts the IQ data received by the radio frequency subcard from the link clock domain to the CPRI clock domain, divides the data into multiple channels, inserts the data into the corresponding transmission data frame according to the CPRI frame format, transmits the data to the slave device at the other end through the optical fiber, takes out the IQ data in the CPRI frame, aligns the data between the multiple channels according to the frame header, crosses the clock domain to the link clock, and finally sends the data to the radio frequency subcard of the slave device.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more specifically, to a device for multi-channel transmission of large bandwidth data based on CPRI. Background Technology

[0002] In traditional communication systems, high-capacity macrocell base stations are typically housed in a central equipment room, with baseband processing centralized. Fiber optic cables are used to extend radio frequency (RF) modules to remote RF units, distributed across sites determined by network planning. This addresses issues such as coverage blind spots or suboptimal equipment room conditions in practical applications. However, when transmitting data via optical signals to remote units, the fiber optic cable, being glass, expands and contracts with temperature changes, affecting the actual transmission distance. While this is manageable over short distances, significant variations occur over lengths of tens of kilometers, making accurate transmission latency difficult to predict. The CPRI protocol is an important wired transmission protocol, commonly used for time-domain data communication between base stations and remote RF units. Its master-slave synchronization mechanism allows for precise latency prediction, proving particularly effective in scenarios with high time accuracy requirements. However, commercially available CPRI interface IPs only support single-channel transmission, limiting bandwidth and offering limited selectable transmission rates due to basic frame limitations. Furthermore, cost constraints and specific application requirements also limit the use of higher-performance chips. When using CPRI to transmit data, the total transmission capacity and the utilization of the basic frame space need to be considered at the system level. Summary of the Invention

[0003] The purpose of this invention is to address, to some extent, the problem of limited transmission bandwidth and few selectable transmission rates associated with CPRI. It proposes a device for multi-channel transmission of large-bandwidth data based on CPRI, treating the multiple channels as a single unit; essentially, it is still point-to-point transmission, ultimately utilizing CPRI's ability to accurately predict transmission delays over long distances.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: a device for multi-channel transmission of high-bandwidth data based on CPRI, comprising a master device and a slave device, wherein the master device and the slave device communicate via two optical fibers, including 7 SerDes channels, of which 6 are used for CPRI interface transmission of IQ and Trigger signals with a line rate of 8.448Gbps, and 1 is used for Aurora interface transmission of control information with a line rate of 2.64Gbps, and the clock is shared among the multiple channels;

[0005] The master device and slave device each include two FPGA chips, two single-mode optical modules for receiving and transmitting light signals, an RF daughter card for receiving and transmitting RF data, a clock chip, and a local clock crystal oscillator;

[0006] In the master device, the clock chip locks to either the local crystal oscillator or an external clock source. In the slave device, when the slave device is used as an independent device, the clock chip can lock to the local crystal oscillator. When used as a synchronization device, the clock chip can only lock to the clock recovered from CPRI, and the frequency of the recovered clock is 52.8MHz.

[0007] As a preferred embodiment of the present invention, the two FPGA chips are a 45T-FPGA with an ARM core and a 690T-FPGA with only a logic side. The 690T-FPGA in the master device establishes communication with the RF daughter card through the Jesd204b interface, converts the electrical signal into an optical signal through a single-mode optical module, sends a set of high-bandwidth data signals received to multiple channels of the CPRI interface, transmits them through optical fiber to the slave device at the other end, extracts them according to the format for receiving and alignment processing, and finally sends them out at the RF daughter card at the slave end.

[0008] As a preferred embodiment of the present invention, the unused portion of the CPRI data frame can transmit other signals, including trigger signals; control information is transmitted via the Aurora protocol interface on a separate data channel, the operating clock of which comes from the CPRI module.

[0009] As a preferred embodiment of the present invention, inter-chip SPI communication is established between the 45T-FPGA and the 690T-FPGA to realize the ARM side's access and control of the registers of each interface on the 690T-FPGA, including initialization configuration and reset, and real-time calculation of latency based on the read latency-related registers.

[0010] As a preferred embodiment of the present invention, the following modules are included: Cpri_core, an interface IP module encapsulated according to the CPRI protocol; Axc_insert and Axc_extract, clock domain conversion modules; Mapping_tx and Mapping_rx, frame insertion and extraction modules; Alignment, a module for receiving multi-channel alignment; Jesd204b_tx and Jesd204b_rx, modules for establishing communication with the RF daughter card; and Aurora_core, an interface IP module for transmitting control information encapsulated according to the Aurora protocol.

[0011] As a preferred embodiment of the present invention, the Cpri_core module is based on the standard protocol line rate option8 of the Xilinx CPRI 8.9 version IP core, which is 10137.6 Mbit / s. By modifying the underlying Serdes parameters, the line rate is increased to 8.448 Gbps. At this time, the CPRI reference clock is 264 MHz, the recovery clock is 52.8 MHz, and the minimum basic frame unit rate is 3.2 MHz. This enables the conversion between high-speed interface data and CPRI frame format data, as well as the underlying synchronization and link establishment.

[0012] The clock domain conversion module has Axc_insert and Axc_extract. Axc_insert converts continuous link clock domain iq data into a discontinuous CPRI clock domain data stream, while Axc_extract restores the discontinuous CPRI clock domain data stream back into continuous link clock domain iq data.

[0013] The Mapping_tx and Mapping_rx of the frame insertion and frame extraction module are designed to fill and extract data with reference to the CPRI frame header, and at the same time realize the filling of the Trigger signal into the remaining frame space not occupied by IQ and the reverse extraction.

[0014] The Alignment module for receiving multi-channel alignment aims to use the CPRI frame header to align data from different channels and ensure the timing of complete data.

[0015] The modules Jesd204b_tx and Jesd204b_rx, which establish communication with the RF daughter card, are used to transmit and receive IQ data.

[0016] The module Aurora_core utilizes the clock shared by the CPRI module to achieve point-to-point transmission of control information.

[0017] As a preferred embodiment of the present invention, the clock domain mutual conversion module Axc_insert and Axc_extract, and the frame insertion and frame extraction module Mapping_tx and Mapping_rx work together to realize the filling of data in CPRI frames. According to different sampling rates, the amount of data to be carried by each channel is calculated in advance.

[0018] To ensure latency stability, data is converted across clock domains using RAM. The large bit-width data output by Axc_insert is evenly distributed across multiple Mapping_tx channels. The 1024M sampling rate data is evenly distributed across five channels, with each channel transmitting 204.8M sampling rate data.

[0019] As a preferred embodiment of the present invention, the Alignment module for receiving multi-channel alignment manually selects one channel and adds a fixed delay. The delay is greater than the possible delay jitter range between multiple channels. This fixed delay is remembered, and the remaining channels are delayed to the same position, ultimately achieving data alignment at the receiving end.

[0020] The transmission process includes the following steps: Calculate the amount of data required for each channel based on the desired data size; modify the underlying SerDes (serializer / deserializer) parameters of the interface to adapt to the sampling clock; and adjust the CPRI minimum basic frame unit size. The master device transfers the IQ data received from the RF daughter card from the link clock domain to the CPRI clock domain, distributes the data equally among multiple channels, and inserts it into the corresponding transmission data frame according to the CPRI frame format. This data is then transmitted via fiber optic cable to the slave device at the other end. The slave device extracts the IQ data from the CPRI frame, aligns the data between multiple channels according to the frame header, crosses the clock domain to the link clock, and finally sends it out from the slave device's RF daughter card.

[0021] Specifically:

[0022] The CPRI protocol consists of two layers and three data planes. Layer 1 is the physical layer, which mainly includes the specifications of optical / electrical ports, line transmission rates, line encoding / decoding, frame formats, and transmission distances. Layer 2 is the MAC layer, which specifies media access control, operation and maintenance data protection, and error detection functions.

[0023] The three data planes are the User Plane, the Control and Maintenance Plane (C&M Plane), and the Synchronization Plane. The User Plane primarily carries data transmitted between the base station and the terminal, i.e., IQ data. The C&M Plane primarily carries L1 and higher-layer operation and maintenance information. The Synchronization Plane primarily carries synchronization and timing information.

[0024] The 1024Mbps sampling rate IQ data from the RF interface is first segmented. Since the default basic frame rate of 3.84MHz (option8) cannot be uniformly sampled, the underlying SerDes parameters, primarily the clock parameters, need to be modified by manually adjusting the "size" of the basic frame. The basic frame rate is changed from 3.84MHz to 3.2MHz, allowing for uniform sampling, and the line rate is also changed from 10.1376G to 8.448G. The master device clock chip locks its local clock, and the slave device clock chip locks its restored clock. Using the PLL locking mechanism within the clock chip, clock synchronization between the master and slave devices is achieved.

[0025] Meanwhile, in order for CPRI Core to function properly, an SPI register read / write channel is established between the ARM and the logic side to enable CPRI power-on initialization configuration, reset, and real-time latency calculation.

[0026] Data transmission can only begin after CPRI successfully establishes synchronization between the master and slave ends.

[0027] The FPGA communicates with the RF daughter card through the Jesd204b interface, receiving 1024M sampling rate IQ data from the RF and sending it to the relevant modules of CPRI.

[0028] The Axc_insert module, which converts clock domains, works in conjunction with the Mapping_tx module. The former converts continuous link clock domain IQ data to discontinuous CPRI clock domain data, while the latter fills the data from Axc into the pre-defined transmission IQ position of the basic frame according to the CPRI frame format.

[0029] The high-speed interface IP encapsulating the CPRI protocol converts parallel data into serial data, and the optical module converts electrical signals into optical signals for transmission to the peer device.

[0030] The optical module of the slave device converts the optical signal into an electrical signal and sends it to the FPGA. Then, it outputs the signal via the CPRI interface, extracts it from the CPRI frame through the Mapping_rx interface, and then passes it through the Alignment module for multi-channel alignment. Using the CPRI frame header, one channel is artificially delayed, and the other channels are aligned to it, ultimately achieving consistency in the timing of multiple data streams. The aligned signal is then sent to the Axc_extract module to be converted into continuous IQ data, and finally, the data is sent to the RF daughter card via the Jesd204b interface of the slave device for transmission.

[0031] Compared with existing technologies, the present invention proposes a device for multi-channel transmission of large bandwidth data based on the CPRI protocol. The core of this device is to modify the underlying Serdes parameters to adapt to different sampling rates and to transmit a large set of data through multiple channels, so as to solve the problem of CPRI transmission bandwidth limitation and ultimately utilize the deterministic transmission delay of CPRI.

[0032] The device of this invention allows for greater focus on sampling rate in data transmission, while freeing up frame space for customer customization, such as using the device to transmit second pulses and triggers. Different protocol functions can also be implemented on other channels via a shared clock. This makes the device more flexible and improves development efficiency. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the device structure for multi-channel transmission of big data in the embodiment.

[0034] Figure 2 This is a schematic diagram of data communication between the master and slave devices in the embodiment.

[0035] Figure 3 This is a schematic diagram of the internal module structure on the logic side in the embodiment.

[0036] Figure 4This is a diagram showing the initialization configuration of CPRI in the example.

[0037] Figure 5 This is a schematic diagram of basic frame space utilization in the embodiment. Detailed Implementation

[0038] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0039] refer to Figure 1 A schematic diagram of a device for transmitting big data through multiple channels.

[0040] The device consists of two identical devices, a master and a slave. The main differences are the CPRI configuration and the clock source locked by the AU5508 clock chip. The master device locks the local clock crystal oscillator. When the slave device is used as an independent device, it can lock the local crystal oscillator. When used as a synchronization device, it needs to lock the recovery clock, which has a frequency of 52.8MHz.

[0041] The 690T main device establishes communication with the RF daughter card through the Jesd204b interface; it converts electrical signals into optical signals through a single-mode optical module, and then communicates with the interface of the slave device at the other end via optical fiber; the device's interface initialization and configuration, etc., are achieved by establishing inter-chip SPI communication between the 45T and 690T to realize the ARM side's register read and write access control to the logic side.

[0042] Communication between the master and slave devices relies on two optical fibers, including seven SerDes channels. Six of these channels are used for CPRI interface transmission of IQ and Trigger signals, with a line rate of 8.448 Gbps, while one channel is used for Aurora interface transmission of control information, with a line rate of 2.64 Gbps. Clocks are shared among the multiple channels.

[0043] refer to Figure 2 A schematic diagram of data communication between master and slave devices.

[0044] The signals received by the master device's RF daughter card are received into the FPGA via the Jesd204b interface. A total of 8 x 128Mbps sampling rate, 32-bit IQ data, are evenly distributed across five CPRI channels. Trigger signals are sent to the sixth CPRI core, and control information is sent to the Aurora core. The data is then transmitted via fiber optic cable to the slave device, where it is parsed by the FPGA. The IQ data is then sent back to the RF daughter card via the Jesd204b interface, while the trigger signals and control information are used as references by the slave device.

[0045] refer to Figure 3 A schematic diagram of the internal module structure on the logic side.

[0046] The RF received signal is received via Jesd, specifically the Jesd204b_rx interface. The 1024MHz sampling rate data is sent to the clock domain conversion module, the Axc_insert module. The converted data is then evenly distributed across five mapping modules, each transmitting an average of 204.8MHz sampling rate data per channel. Axc_insert converts the data from the link clock domain to the CPRI clock domain. The first five Mapping_tx modules process the converted IQ data according to the CPRI frame format and finally send it to the IP core for transmission via the high-speed interface. Multi-channel CPRI system IQ transmission is essentially point-to-point data transmission. The sixth Mapping_tx module is used to transmit the trigger signal.

[0047] Data output from the IP core to the link first passes through the mapping module (Mapping_rx) to extract the IQ data from the CPRI frame. Then, it passes through the alignment module (Alignment) to align the data across multiple channels, making it a unified whole. Next, it passes through the reverse cross-clock domain module (Axc_extract) to convert the data to the link clock domain. Finally, it is transmitted via the Jesd204b_tx interface through the RF daughter card, thus completing the IQ data transmission. The trigger signal is extracted in the fifth Mapping_rx.

[0048] The device also has a channel for transmitting control information, and the interface uses the Aurora protocol.

[0049] refer to Figure 4 CPRI initialization configuration diagram.

[0050] First, configure the master-slave mode and various CPRI parameters. These parameters include the preset value of the internal configuration transmission trigger signal offset and the CPRI control word transmission parameters. Then, reset the MMCM to obtain a stable clock. Finally, reset the high-speed interface SerDes and the CPRI core to facilitate the establishment of synchronization.

[0051] Because this project involves multiple channels, it can only be considered complete after all CPRI channels are synchronized.

[0052] The specific embodiments of the present invention have been described in detail above. These embodiments are merely some, not all, of the present invention and do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.

[0053] refer to Figure 5A schematic diagram of basic frame space utilization.

[0054] The IQ data mapping is based on a basic frame, with the total region starting at W=1 and Y=0, containing both IQ data and triggers.

[0055] The system transmits data at a sampling rate of 1024 Mbps, or 8 * 128 Mbps * 32 bits of data, through 5 channels for I and Q data transmission, with an average of 204.8 Mbps transmitted per channel. This occupies 4 / 5 of a basic frame space. The mapping distribution is as follows, with the bits of the I and Q data alternating. (Example:) Figure 5 As shown, the orange part represents the IQ data, and the blue part represents the Trigger signal.

[0056] It should be understood that although this specification describes the system according to embodiments, not every embodiment contains only one independent technical solution. This narrative style is only for clarity, and those skilled in the art should consider this specification as a whole. The technical features in each embodiment can also be reasonably combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A device for multi-channel transmission of high-bandwidth data based on CPRI, characterized in that: It includes master and slave devices, which communicate with each other via two optical fibers. It includes 7 SerDes channels, of which 6 are used for CPRI interface to transmit IQ and Trigger signals with a line rate of 8.448Gbps, and 1 is used for Aurora interface to transmit control information with a line rate of 2.64Gbps. The clock is shared among the multiple channels. The master device and slave device each include two FPGA chips, two single-mode optical modules for receiving and transmitting light signals, an RF daughter card for receiving and transmitting RF data, a clock chip, and a local clock crystal oscillator; In the master device, the clock chip locks to either the local crystal oscillator or an external clock source. In the slave device, when the slave device is used as an independent device, the clock chip can lock to the local crystal oscillator. When used as a synchronization device, the clock chip can only lock to the clock recovered from CPRI. The frequency of the recovered clock is 52.8MHz. The two FPGA chips are a 45T-FPGA with an ARM core and a 690T-FPGA with only a logic side. The 690T-FPGA in the master device establishes communication with the RF daughter card through the Jesd204b interface. It converts electrical signals into optical signals through a single-mode optical module, sends a set of high-bandwidth data signals received to multiple channels of the CPRI interface, transmits them through optical fiber to the slave device at the other end, extracts them according to the format, performs reception alignment processing, and finally sends them out through the RF daughter card of the slave device. The 690T-FPGA includes: The interface IP module Cpri_core is encapsulated according to the CPRI protocol; The Axc_insert and Axc_extract modules are used for clock domain conversion; the Mapping_tx and Mapping_rx modules are used for frame insertion and extraction; the Alignment module is used for receiving multi-channel alignment; the Jesd204b_tx and Jesd204b_rx modules are used to establish communication with the RF daughter card; and the Aurora_core module is used as the interface IP module for transmitting control information encapsulated according to the Aurora protocol. The module Cpri_core is based on the standard protocol line rate option8 of the Xilinx CPRI 8.9 version IP core, which is 10137.6 Mbit / s. By modifying the underlying parameters of Serdes, the line rate is increased to 8.448 Gbps. At this time, the CPRI reference clock is 264 MHz, the recovery clock is 52.8 MHz, and the minimum basic frame unit rate is 3.2 MHz. The clock domain conversion module has Axc_insert and Axc_extract. Axc_insert converts continuous link clock domain IQ data into a discontinuous CPRI clock domain data stream, while Axc_extract restores the discontinuous CPRI clock domain data stream back into continuous link clock domain IQ data. The Mapping_tx and Mapping_rx of the frame insertion and frame extraction module are designed to fill and extract data with reference to the CPRI frame header, and at the same time realize the filling of the Trigger signal into the remaining frame space not occupied by IQ and the reverse extraction. The Alignment module for receiving multi-channel alignment aims to use the CPRI frame header to align data from different channels and ensure the timing of complete data. The modules Jesd204b_tx and Jesd204b_rx, which establish communication with the RF daughter card, are used to transmit and receive IQ data. The module Aurora_core utilizes the clock shared by the CPRI module to achieve point-to-point transmission of control information.

2. The apparatus for multi-channel transmission of large bandwidth data based on CPRI according to claim 1, characterized in that: The unused portion of the CPRI data frame can be used to transmit other signals, including trigger signals; control information is transmitted via the Aurora protocol interface on a separate data channel, whose operating clock comes from the CPRI module.

3. The apparatus for multi-channel transmission of large bandwidth data based on CPRI according to claim 1, characterized in that: Inter-chip SPI communication is established between the 45T-FPGA and the 690T-FPGA to enable the ARM side to access and control the registers of various interfaces on the 690T-FPGA, including initialization configuration and reset, and to perform real-time delay calculation based on the read delay-related registers.

4. The apparatus for multi-channel transmission of large bandwidth data based on CPRI according to claim 1, characterized in that: The clock domain conversion modules Axc_insert and Axc_extract, along with the frame insertion and extraction modules Mapping_tx and Mapping_rx, work together to fill data in CPRI frames. Based on different sampling rates, the amount of data that each channel needs to handle is calculated and allocated in advance. To ensure latency stability, data is converted across clock domains using RAM. The large bit-width data output by Axc_insert is evenly distributed across multiple Mapping_tx channels. The 1024M sampling rate data is evenly distributed across five channels, with each channel transmitting 204.8M sampling rate data.

5. The apparatus for multi-channel transmission of large bandwidth data based on CPRI according to claim 1, characterized in that: The Alignment module receives multi-channel alignment by manually selecting one channel and adding a fixed delay. The delay is greater than the delay jitter range between multiple channels. This fixed delay is remembered, and the remaining channels are delayed to the same position, ultimately achieving data alignment at the receiving end.

6. A device for multi-channel transmission of high-bandwidth data based on CPRI according to any one of claims 1-5, characterized in that, The data transmission process in the device is as follows: Based on the required data size, calculate the amount of data allocated to each channel, modify the underlying Serdes parameters of the interface to adapt to the sampling clock, and adjust the CPRI minimum basic frame unit size. The master device transfers the IQ data received from the RF daughter card from the link clock domain to the CPRI clock domain, distributes the data equally among multiple channels, inserts it into the corresponding transmission data frame according to the CPRI frame format, and transmits it to the slave device at the other end through optical fiber. The master device extracts the IQ data from the CPRI frame, aligns the data between multiple channels according to the frame header, crosses the clock domain to the link clock, and finally sends it out from the RF daughter card of the slave device.

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