Large-size package substrate and method for manufacturing the same

Abstract

The application provides a large-size packaging substrate and a preparation method thereof, and the technical scheme is as follows: comprising the following steps: first core independent manufacturing: sequentially performing first layer lamination dielectric material construction and SAP patterning, second layer lamination dielectric material construction and SAP patterning on a first core base material; applying an encoder mask; second core independent manufacturing: performing second layer solder core construction on a second core base material; forming a through-hole structure, and completing line layer processing through an electroplating and patterning process; covering a solder mask and performing unit cutting; double-core coupling: mechanically connecting the first core and the second core through a coupling structure; and filling a bottom filling material at a coupling interface to solidify the structure. Through the double-core independent manufacturing and compression forming coupling process, in combination with the high modulus core body and the stress buffer layer design, the material stress caused interlayer misregistration and warping deformation are effectively inhibited, and the advantages of effectively reducing the substrate warping, improving the interlayer alignment accuracy and improving the manufacturing yield are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a large-size packaging substrate and a preparation method thereof. BACKGROUND

[0002] With the rapid development of semiconductor technology, especially the miniaturization of semiconductor processes and the widespread application of artificial intelligence (AI) technology, large chips have higher requirements for packaging materials, processes, and supply chains. Developing the preparation process of large-size packaging substrates needs to face the following challenges:

[0003] Manufacturing process complexity: Large-size chip carriers usually adopt a multi-layer laminated structure, and problems such as interlayer alignment deviation and uneven structure within the layer are prone to occur during the lamination process, which puts higher requirements on lamination equipment and process control. Since the stacking of multi-layer structure requires accurate positioning and adhesion, any slight deviation may cause signal transmission performance to decline or structure to fail.

[0004] Size accuracy and warpage control: The size error range of large-size carriers is usually in the micron level, and how to control the expansion and warpage of the substrate during the manufacturing process is a difficulty. In addition, large-size carriers are prone to warpage due to material stress or temperature changes during the manufacturing process, which will affect assembly and signal transmission performance. Warpage problems not only affect the subsequent chip mounting process, but also may cause the reliability of the packaging structure to decline.

[0005] Manufacturing yield and cost control: The manufacturing process of large-size carriers is complex, and any problem in any link may cause the entire carrier to be scrapped, so how to improve the yield is an important challenge. In addition, the production cost of large-size carriers is usually high, including material, equipment and process costs, and how to reduce costs while ensuring performance is a problem that enterprises need to solve.

[0006] Among the above problems, the warpage of the substrate is the most difficult to control and improve. Warpage not only affects the mechanical stability of the packaging substrate, but also causes the alignment accuracy to decline in the subsequent chip mounting process, and even causes welding defects. Therefore, an effective packaging substrate structure and preparation method for reducing the warpage of large-size substrates are needed to improve packaging reliability and production efficiency. SUMMARY

[0007] The purpose of the present application is to provide a large-size packaging substrate and a preparation method thereof, which has the advantages of effectively reducing substrate warpage, improving interlayer alignment accuracy, and improving manufacturing yield.

[0008] The application provides a preparation method of a large-size packaging substrate, comprising the following steps: (a) sequentially performing first layer lamination dielectric material construction and SAP patterning, and second layer lamination dielectric material construction and SAP patterning on the base material of the first core, wherein the lamination dielectric material includes but is not limited to photosensitive dielectric material or lamination insulation film; (b) second core independent manufacturing: performing second layer solder core construction on the base material of the second core; forming a through-hole structure, and completing the processing of the circuit layer through the plating and patterning process; covering a solder mask and performing unit cutting; (c) double-core coupling: mechanically connecting the first core and the second core through a coupling structure; and filling a bottom filling material at the coupling interface to solidify the structure.

[0009] Further, the application also proposes that the elastic modulus of the second core is higher than that of the first core, and the second core can adopt a glass core.

[0010] Further, the application also proposes that the thickness of the second core is smaller than that of the first core, and the lamination process after the independent manufacturing of the double core adopts a compression molding process to inhibit warping.

[0011] Further, the application also proposes that the number of layers of the first core is greater than that of the second core.

[0012] Further, the application also proposes that the bottom filling material is an epoxy resin-based polymer, and a stress buffer layer is formed after filling and solidification.

[0013] Further, the application also proposes a large-size packaging substrate, comprising: an independently manufactured first core, comprising at least two lamination dielectric material dielectric layers and SAP patterned circuit layers, wherein the lamination dielectric material includes but is not limited to photosensitive dielectric material or lamination insulation film; an independently manufactured second core, comprising a solder core layer, a through-hole structure and a plated circuit layer; a coupling structure: the first core and the second core are interconnected through a solder ball array coupling structure, and the coupling structure includes but is not limited to tin ball connection, blind hole plating connection, copper column connection and through connection, and the interface is filled with a bottom filling material layer.

[0014] Further, the application also proposes that the second core is a glass-based core body, the thickness of which is smaller than that of the first core, and the modulus value is 1.5-3 times the modulus of the first core.

[0015] The first core is a Core plate or a Coreless substrate, which is in the form of a symmetric substrate or an asymmetric substrate.

[0016] Further, the application also proposes that the through-hole structure comprises a first through-hole penetrating through the glass-based core body, the first through-hole is filled after the dielectric material is increased, the second through-hole is formed on the surface of the dielectric material after the increase, and the aperture of the first through-hole is greater than that of the second through-hole.

[0017] Furthermore, this application also proposes that the number of layers in the first core is greater than the number of layers in the second core.

[0018] The line width in the first core is less than the line width in the second core; the line spacing in the first core is less than the line spacing in the second core; the line thickness in the first core is less than the line thickness in the second core; the solder pad thickness in the first core is less than the solder pad thickness in the second core.

[0019] As can be seen from the above, the large-size packaging substrate and its fabrication method provided in this application have the following technical solutions: (a) Independent fabrication of the first core: sequentially constructing and patterning the first ABF layer and the second ABF layer on the substrate of the first core; applying an encoder mask; (b) Independent fabrication of the second core: constructing the second solder core on the substrate of the second core; forming a through-hole structure, and completing the circuit layer processing through electroplating and patterning processes; covering the solder mask and performing unit cutting; (c) Dual-core coupling: mechanically connecting the first core and the second core through a solder ball matrix; filling the coupling interface with bottom filler material to solidify the structure. Through the dual-core independent fabrication and compression molding coupling process, combined with the high-modulus core and stress buffer layer design, the interlayer misalignment and warpage deformation caused by material stress are effectively suppressed, which has the advantages of effectively reducing substrate warpage, improving interlayer alignment accuracy, and improving manufacturing yield. Attached Figure Description

[0020] Figure 1 A schematic diagram of an ink injection and patterning process for a large-size packaging substrate provided in this application;

[0021] Figure 2 This application provides a schematic diagram of the construction and SAP patterning process of the first insulating film ABF of a large-size packaging substrate.

[0022] Figure 3 A schematic diagram of the construction and SAP patterning process of the second insulating film ABF on a large-size packaging substrate provided in this application;

[0023] Figure 4 This application provides a schematic diagram of an encoder mask process applied to a large-size packaging substrate.

[0024] Figure 5 A schematic diagram of a process for constructing a second layer of solder core on a second core substrate, as provided in this application;

[0025] Figure 6 A schematic diagram of the circuit layer processing technology of a large-size packaging substrate provided in this application, which is completed by electroplating and patterning.

[0026] Figure 7 A schematic diagram of a large-size packaging substrate covered with a welding mask and subjected to cell cutting, as provided in this application;

[0027] Figure 8 A schematic diagram of the manufacturing process of a large-size packaging substrate for mechanically connecting a first core and a second core through a coupling structure, provided in this application;

[0028] Figure 9 A schematic diagram of the process of filling the coupling interface with bottom filler material for a large-size packaging substrate provided in this application;

[0029] Figure 10 This application provides a schematic diagram of a large-size packaging substrate structure.

[0030] In the diagram: 100, first core; 2, ink filling hole; 300, first ABF layer; 400, second ABF layer;

[0031] 500, Encoder mask; 600, Second core; 7, Through hole; 8, Welding mask; 9, Coupling structure;

[0032] 10. Bottom filling material. Detailed Implementation

[0033] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following drawings indicate similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0034] In existing technologies, with the increasing size of semiconductor chips, the lamination process of traditional packaging substrates faces severe challenges. Conventional methods employ a continuous lamination process, leading to stress accumulation between layers, which can easily cause substrate warping, especially during high-temperature processes. In existing technologies, the differences in the thermal expansion coefficients of the substrate layers are difficult to coordinate, and the internal stress generated by continuous lamination cannot be effectively released, ultimately resulting in irreversible deformation of large-size substrates.

[0035] To address the aforementioned issues, considering that stress accumulation in the overall manufacturing process is the primary cause of warpage, a split manufacturing strategy is proposed. By separating the substrate into independently manufactured first and second cores, and completing the internal structure processing separately before coupling, the stress range of different materials can be effectively isolated. Furthermore, a discretely distributed solder ball connection method is used to replace the traditional integral lamination, which can reduce the structural rigidity constraint. Finally, an interface filling material is introduced to form a stress buffer layer to absorb thermomechanical stress.

[0036] Therefore, this application proposes a method for fabricating a large-size packaging substrate, such as... Figures 1-9 As shown, it includes the following steps:

[0037] like Figure 1 This is a schematic diagram of the first core 100 after ink filling and patterning; where the first core 100 is a BT core and 2 is an ink filling hole;

[0038] On the first core 100 substrate, a first layer of laminated dielectric material is sequentially constructed and patterned using SAP, followed by a second layer of laminated dielectric material and SAP patterning. The laminated dielectric material includes, but is not limited to, photosensitive dielectric materials or laminated insulating films. In the SAP process, the ink injection holes 2 serve as entry points for chemical copper deposition, selectively depositing conductor patterns onto the substrate. In a specific embodiment, such as... Figure 2 The first layer of laminated insulating film, namely the first layer of ABF300, is constructed and patterned with SAP on the first core 100 substrate.

[0039] like Figure 3 The second layer of ABF400 is constructed and patterned with SAP.

[0040] ABF construction refers to the formation of a multilayer dielectric layer using a stacked thin film process, specifically achieved through vacuum lamination combined with laser drilling, to create an insulating layer with a low dielectric constant. SAP patterning refers to a semi-additive circuit forming process, specifically achieved through chemical copper plating and photolithography etching, to form high-precision conductive lines.

[0041] like Figure 4 Apply encoder mask 500; encoder mask 500 refers to a photolithographic mask with position calibration marks, which can be formed by laser etching to achieve interlayer alignment.

[0042] like Figure 5 A second layer of solder core is constructed on the second core 600 substrate.

[0043] Core bonding refers to the process of forming the core layer by welding, which can be achieved by copper foil lamination combined with etching process, and is used to build high-density interconnect structures.

[0044] This application further proposes that the elastic modulus of the second core 600 is higher than that of the first core 100, and that the second core 600 may be a glass core.

[0045] Elastic modulus refers to a material's ability to resist deformation during the elastic deformation stage. This can be achieved using glass or ceramic composite materials, enabling the second core 600 to form a rigid support framework during lamination. Specifically, it can be achieved using carbon fiber reinforced resin matrix composites or alumina ceramic substrates. This feature ensures that the second core 600 possesses sufficient structural stiffness to resist deformation during hot pressing.

[0046] The first core 100 is a coreless substrate with or without a core board, and can be in the form of a symmetrical substrate or an asymmetrical substrate.

[0047] Specifically, in the dual-core laminated structure, the second core 600 is configured as a support with a higher elastic modulus. When the first core 100 and the second core 600 expand due to heat during lamination, the high-modulus core, through its own rigidity, restricts the lateral expansion of the low-modulus core, thereby reducing the asymmetric deformation of the overall structure. Regarding interfacial stress distribution, the high stiffness of the second core 600 allows it to absorb and disperse the thermal expansion stress from the first core 100, preventing excessive stress concentration at the coupling interface. Application examples of glass cores demonstrate that their isotropic mechanical properties can effectively balance thermal deformation in different directions. In a specific embodiment, the elastic moduli of the first core 100 and the second core 600 are 25 GPa and 70 GPa, respectively.

[0048] Traditional packaging substrates often use stacked materials of the same or similar modulus, leading to cumulative deformation due to the synchronous expansion of each layer during hot pressing. This solution, however, constructs a modulus gradient structure, allowing the high-modulus core to actively constrain the plastic flow of the low-modulus core during lamination, thereby suppressing warpage at the material level. Compared to conventional metal-core substrates, glass cores or high-modulus composite materials reduce the difference in thermal expansion coefficients while maintaining the same stiffness, avoiding secondary deformation caused by thermal mismatch.

[0049] By setting the elastic modulus of the second core (600) to be higher than that of the first core (100), deformation control of the large-size packaging substrate during high-temperature lamination was achieved. The high-modulus core acts as a rigid support frame, effectively limiting the thermal expansion displacement of the low-modulus core and reducing the risk of interlayer misalignment. The differentiated configuration of material stiffness results in a more uniform distribution of interfacial stress, avoiding microcracks caused by localized stress concentration. The application of glass cores or high-modulus composite materials further enhances the dimensional stability of the substrate under thermal cycling conditions, ensuring the precision requirements of subsequent chip assembly.

[0050] This application further proposes that the thickness of the second core 600 is less than the thickness of the first core 100, and that the lamination process after the dual cores are manufactured independently adopts a compression molding process to suppress warping.

[0051] The thickness of the second core 600 being less than that of the first core 100 is achieved by adjusting the structural size ratio of the different core layers to achieve stress balance. Specifically, this can be achieved by reducing the proportion of high-modulus material. The thinner second core 600 reduces the impact of thermal expansion differences on the overall structure. The compression molding process refers to applying uniform mechanical pressure during lamination. This can be achieved using hydraulic molding equipment in conjunction with a temperature control module. Through the synergistic effect of pressure and heat, molecular-level bonding is achieved at the interface of the two cores.

[0052] like Figure 6 The through-hole 7 structure is formed, and the circuit layer is processed through electroplating and patterning processes.

[0053] The through-hole 7 structure includes a first through-hole penetrating the glass substrate core, which is filled after the dielectric material is added. A second through-hole is then formed on the surface of the added dielectric material. The diameter of the first through-hole is greater than the diameter of the second through-hole.

[0054] like Figure 7 Cover the welding mask 8 and perform unit cutting;

[0055] like Figures 8-9 The first core 100 and the second core 600 are mechanically connected by a coupling structure 9. The coupling structure 9 includes, but is not limited to, solder ball connection, blind hole electroplating connection, copper pillar connection and conductive connection. The coupling interface between the first core 100 and the second core 600 is filled with a bottom filler material 10 to form a bottom filler material layer.

[0056] In a specific embodiment, the coupling structure 9 refers to a discretely distributed array of micro solder balls, which can be implemented using a reflow soldering process to provide mechanical connection and electrical conduction.

[0057] Specifically, during the dual-core coupling process, the core layer structure with varying thicknesses can adjust the stiffness distribution of different materials. The thinner, high-modulus second core 600 generates a reaction force under pressure, counteracting the deformation tendency of the first core 100 due to thermal expansion. The compression molding process, through precise control of the pressure gradient, enables the filler material to form a uniform stress buffer layer in the interface region. The unique continuous pressure holding stage of this process eliminates interlayer gaps, mechanically constraining the difference in the expansion coefficients of the two cores during the curing process.

[0058] This application effectively suppresses warping deformation during the lamination process of large-size substrates, solves the problem of interfacial stress imbalance caused by the difference in thermal expansion coefficients of materials in dual-core structures, and ensures the dimensional accuracy and structural stability of multilayer stacked structures.

[0059] This application further proposes a layer-independent design for the first core 100 and the second core 600.

[0060] In this design, the independent layer design means that the number of dielectric and circuit layers for the first core 100 and the second core 600 are determined separately according to their respective functional requirements, with the first core 100 having more layers than the second core 600. For example, a 20-layer structure originally consisting of 9+2+9 layers. In this technical solution, after independent manufacturing, the layer designs for the first core 100 and the second core 600 are 6+2+6 layers and 2+2+2 layers, respectively. This can be achieved using different lamination process parameters and material combinations. The layer design for the first core 100 focuses on increasing wiring density by increasing the number of ABF dielectric layers, while the layer design for the second core 600 reduces the number of layers and strengthens the via 7 structure to enhance mechanical support.

[0061] Specifically, the first core 100 employs a combination of multi-layer ABF dielectric layers and SAP patterned circuit layers, achieving high-density interconnect functionality through layer-by-layer construction. The second core 600, based on a high-modulus material, has fewer layers, but utilizes a through-hole 7 electroplating process to form a vertical interconnect structure to enhance rigidity. During the independent manufacturing of the two cores, the lamination temperature and pressure parameters of the first core 100 can be optimized independently to reduce thermal stress in the dielectric layer, while the lamination parameters of the second core 600 are adjusted according to the characteristics of the high-modulus material to reduce deformation. When the two cores are coupled, the difference in the number of layers is compensated for by the elastic connection of the solder ball array, avoiding interface stress concentration caused by traditional layer matching.

[0062] By setting the independent layer design of the first core 100 and the second core 600, this application can reduce the stress transmission caused by the difference in the number of layers at the dual-core coupling interface, suppress the overall warping of large-size substrates during the lamination process, and at the same time take into account the requirements of high-density interconnection and high rigidity support.

[0063] It should be emphasized that, in this application, if Figure 9 The bottom filler material 10 is filled at the coupling interface to solidify the structure.

[0064] The bottom filler material 10 refers to a thermosetting polymer material, which can be achieved using a capillary flow filling process to form a stress buffer interface after curing.

[0065] This application further proposes that the bottom filler material 10 is an epoxy resin-based polymer, which is cured after filling to form a stress buffer layer.

[0066] Among them, epoxy resin-based polymers refer to polymeric materials with epoxy groups as reactive centers. Specifically, they can be achieved using a mixture of bisphenol A type epoxy resin and a curing agent. This material has low viscosity before curing, which can fully wet the gaps between solder balls. The stress buffer layer refers to a viscoelastic interfacial transition layer formed through a curing process. Specifically, it can be achieved using a stepped temperature curing process. This layer can absorb the difference in thermal expansion stress between heterogeneous materials through elastic deformation.

[0067] Specifically, during the dual-core coupling process, an epoxy resin-based polymer is injected into the gaps between the solder ball array. Its low viscosity ensures uniform material distribution and complete filling of interfacial voids. During curing, the material is gradually cross-linked by controlling the temperature gradient, forming a buffer layer that combines adhesive strength and elasticity. This layer forms a continuous transition at the interface. When shear stress occurs between the first core 100 and the second core 600 due to the difference in their coefficients of thermal expansion, the buffer layer absorbs energy through local slippage and deformation of molecular chain segments, thereby reducing interfacial stress concentration. Simultaneously, the cured material maintains appropriate stiffness, preventing plastic deformation during mechanical load transfer.

[0068] Traditional filler materials often use rigid polymers, resulting in a high degree of interface hardness after curing. This makes it difficult to effectively release thermal stress between dissimilar materials, leading to interface cracks or substrate warping. This solution, however, utilizes the viscoelastic properties of epoxy resin-based polymers to enable the interface layer to dynamically adjust stress, maintaining structural stability while suppressing stress accumulation.

[0069] By using epoxy resin-based polymer as the bottom filler material 10, this application can effectively reduce the interfacial shear stress caused by the difference in the thermal expansion coefficient of materials during the dual-core coupling process of large-size substrates, reduce the overall warping deformation of the substrate, and improve the fatigue resistance and long-term reliability of the interface structure.

[0070] In addition, the line width in the first core 100 is less than the line width in the second core 600; the line spacing in the first core 100 is less than the line spacing in the second core 600; the line thickness in the first core 100 is less than the line thickness in the second core 600; and the solder pad thickness in the first core 100 is less than the solder pad thickness in the second core 600.

[0071] In summary, in this invention, the layered ABF construction of the first core 100 forms a flexible multilayer structure by alternately depositing dielectric and conductive layers. The encoder mask 500 ensures the alignment accuracy between layers, avoiding the accumulated stress generated by traditional continuous lamination. The solder core construction of the second core 600 and the through-hole processing form a rigid interconnect structure. The unit cutting process releases residual stress in the substrate before coupling. The two cores are mechanically connected by a solder ball matrix. The discrete distribution reduces the rigidity constraint of the overall structure. The bottom filler material 10 compensates for the difference in thermal expansion at the interface during the curing process. The flexible dielectric layer of the first core 100 and the rigid substrate of the second core 600 form a modulus gradient. The distributed connection of the solder ball array allows for local stress release. The buffer layer formed by the filler material absorbs thermomechanical stress, ultimately achieving warpage suppression of large-size substrates.

[0072] In existing technologies, integral lamination processes are prone to interlayer stress concentration during high-temperature pressing, while split manufacturing processes isolate stress generation points at different manufacturing stages. In existing continuous lamination structures, alignment errors accumulate layer by layer, while the application of encoder masks allows for independent calibration of each layer's position. Conventional rigid connections limit stress release paths, while discrete connections in the solder ball matrix allow for localized deformation. Existing filler materials are only used for electrical protection, while in this solution, the filler material achieves active stress compensation through matching its coefficient of thermal expansion.

[0073] This invention effectively reduces the risk of warpage during the manufacturing of large-size substrates. The split manufacturing process reduces interlayer stress accumulation, the distributed connection of the solder ball matrix reduces structural rigidity constraints, the bottom filler material 10 absorbs interfacial thermal stress, and the modulus gradient design enhances overall structural stability. The synergistic effect of each process step enables deformation control of large-size substrates during high-temperature processing.

[0074] In specific embodiments, such as Figure 10 This application further proposes a large-size packaging substrate, including a separately manufactured first core 100, a separately manufactured second core 600, and a coupling structure 9. The first core 100 includes at least two ABF dielectric layers, namely a first ABF300 layer, a second ABF400 layer, and an SAP patterned circuit layer; the second core 600 includes a solder core layer, a via structure 7, and an electroplated circuit layer; in the coupling structure 9, the first core 100 and the second core 600 are interconnected by a solder ball matrix, and the interface is filled with an underfill material 10.

[0075] The ABF dielectric layer refers to an insulating dielectric layer constructed using a layer-by-layer method. Specifically, it can be formed by coating ABF material layer by layer and then curing it, reducing stress accumulation from a single lamination process. The SAP patterned circuit layer refers to conductive circuits formed using a semi-additive process, specifically achieved through a combination of chemical copper plating and photolithography, ensuring circuit accuracy and reducing processing deformation. The solder core layer refers to a rigid substrate supporting the through-hole 7 structure, specifically made of glass or high-modulus composite materials, suppressing overall substrate deformation through its high rigidity. The electroplated circuit layer refers to metal circuits formed through an electroplating process, specifically using copper electroplating to fill through-hole 7 and form an interconnect structure, enhancing the structural stability of the second core 600. The solder ball array refers to discretely distributed metal solder ball connection points, specifically achieved by tin-silver alloy balls arranged in a matrix, dispersing interface stress through discrete connections. The bottom filler material layer 10 refers to a polymer material that forms a continuous supporting interface after curing, specifically using epoxy resin-based materials for filling and curing, buffering the thermal expansion differences between the two cores.

[0076] Specifically, the first core 100 utilizes a layered ABF dielectric layer and SAP process to form high-precision circuitry, reducing stress concentration caused by single lamination. The second core 600 employs a high-elasticity modulus material to construct the solder core layer and via 7 structure; its rigidity counteracts the overall deformation tendency of the substrate. The two cores are mechanically interconnected via a solder ball array; the discrete connection method allows for localized stress release, avoiding stress concentration at continuous interfaces. The bottom filler material 10 forms a continuous support layer after curing, suppressing warping caused by temperature changes by matching the difference in thermal expansion coefficients between the two cores. The flexible dielectric layer of the first core 100 complements the high-modulus characteristics of the second core 600; the synergistic control of solder ball density and filler material shrinkage optimizes stress distribution, thus comprehensively addressing the structural stability issues of large-size substrates.

[0077] Traditional large-size substrates employ a single-core, multi-layer stacked structure, which is prone to stress accumulation during lamination and lacks rigid support, leading to uncontrollable warpage. This solution achieves layered stress management through independent manufacturing of two cores, providing rigid support for the high modulus characteristics of the second core (600). The solder ball array and filler material layer form a composite stress buffer mechanism, effectively overcoming the limitations of the single-core structure. Existing technologies do not employ a synergistic design of discrete interconnects and high-modulus cores, thus failing to simultaneously achieve the dual effects of stress dispersion and rigidity enhancement.

[0078] This invention significantly reduces warpage of large-size packaging substrates during manufacturing and use, improving interlayer alignment accuracy and structural stability. By employing a dual-core complementary design to suppress deformation caused by material stress, using interface filling materials to mitigate thermal expansion differences, and optimizing stress distribution with a solder ball array, the invention ensures dimensional consistency of the substrate under high-temperature processing conditions, thereby improving chip assembly yield and signal transmission reliability.

[0079] This application further proposes that the second core 600 is a glass-based core with a thickness less than that of the first core 100, and its modulus is 1.5-3 times that of the first core 100. In a specific embodiment, the elastic moduli of the first core 100 and the second core 600 are 25 GPa and 70 GPa, respectively.

[0080] The glass-based core refers to the use of glass as the matrix structure of the second core 600. Specifically, high-purity silicate glass or borosilicate glass can be used, providing structural support to resist deformation through high-rigidity materials. A thickness less than the first core 100 means that the vertical dimension of the second core 600 is smaller than the corresponding dimension of the first core 100. This can be achieved by adjusting the core lamination process parameters, reducing stress accumulation in the thickness direction while ensuring mechanical strength. A modulus value of 1.5-3 times that of the first core 100 means that the elastic modulus of the second core 600 is limited to between 1.5 and 3 times that of the first core 100. This can be achieved by selecting different glass materials or composite materials to balance the overall stiffness and stress distribution of the dual-core structure.

[0081] Specifically, the high modulus of the glass-based core effectively constrains the deformation tendency of the first core 100 under thermal stress. By controlling the thickness of the second core 600 to be less than that of the first core 100, excessive stress gradients in the thickness direction of the high-modulus material can be avoided. Simultaneously, the modulus ratio is limited to 1.5-3 times, ensuring that the rigidity of the second core 600 is sufficient to suppress the warping tendency of the first core 100, while also preventing localized stress concentration at the dual-core interface due to excessive modulus difference. This synergistic design of material and geometric parameters allows the internal stresses generated during thermal expansion of the dual-core structure to cancel each other out, thereby reducing overall warping.

[0082] By setting the second core 600 as a glass-based core with a thickness less than that of the first core 100 and a modulus value 1.5-3 times that of the first core 100, this application can effectively suppress the warping phenomenon caused by the difference in the thermal expansion coefficient of materials during the manufacturing process of large-size packaging substrates. Through the dual effects of rigid support and stress matching, the flatness of the substrate is improved and the interlayer alignment accuracy is guaranteed.

[0083] This application further proposes that the curing shrinkage rate of the bottom filler material 10 is controlled below 0.5%, and that its coefficient of thermal expansion matches the difference in the coefficient of thermal expansion between the first core 100 and the second core 600.

[0084] Among them, curing shrinkage rate refers to the ratio of volume change of a material during the curing process. This can be achieved by using a low-shrinkage epoxy resin system or adding inorganic fillers, such as modifying the resin matrix with silica powder to reduce shrinkage. This feature reduces internal stress at the interface caused by shrinkage deformation by limiting the volume shrinkage during curing. Matching thermal expansion coefficients means that the difference in thermal expansion coefficients between the filler material and the two core materials is on the same order of magnitude. This can be achieved by adjusting the proportion of toughening agents in the resin matrix or introducing a ceramic particle composite structure, such as using epoxy composites reinforced with alumina particles. This feature reduces the accumulation of thermomechanical stress at the interface by balancing the expansion differences of the materials during temperature changes.

[0085] Specifically, during the curing stage, the low-shrinkage filler material suppresses volume shrinkage, preventing a decrease in interfacial bonding strength or localized structural deformation due to excessive shrinkage. Under temperature cycling conditions, the difference in the coefficients of thermal expansion between the filler material and the two cores is controlled within a reasonable range, minimizing the difference in deformation caused by thermal expansion and thus reducing the tensile or compressive effects of thermal stress on the substrate structure. The dual control of curing shrinkage and thermal expansion forms a synergistic mechanism, reducing the risk of stress concentration from both the initial and service states of the material, thereby suppressing overall substrate warping.

[0086] The curing shrinkage rate of the bottom filler material 10 is controlled below 0.5%, and its coefficient of thermal expansion matches the difference in the coefficients of thermal expansion of the first core 100 and the second core 600. This effectively alleviates the stress concentration phenomenon at the interface caused by the difference in material shrinkage and thermal expansion, suppresses the warping deformation of large-size substrates during manufacturing and use, improves the dimensional stability and long-term reliability of the packaging structure, and reduces the risk of assembly failure caused by warping, thereby improving product yield.

[0087] This application further proposes that the first core 100 has a greater number of layers than the second core 600, and that the second core 600 contains at least 6 layers of high-density interconnect lines.

[0088] Specifically, this can be achieved by using two ABF dielectric layers and SAP-processed circuit layers for the first core 100, and four solder core layers and HDI-processed circuit layers for the second core 600. This ratio is achieved by increasing the rigidity level of the second core 600 to balance the thermal stress distribution between the two cores. High-density interconnect lines refer to fine circuit structures with a linewidth / spacing ≤10μm, which can be achieved by using a semi-additive process combined with laser drilling technology to form microvia structures. The stacking of multiple high-density interconnect lines forms a supporting framework, enhancing the structural strength of the second core 600.

[0089] Specifically, the first core 100 has fewer layers and primarily serves as a basic support and low-density signal transmission layer, while the second core 600, with a higher layer ratio, undertakes high-density interconnection and mechanical support functions. The first core 100 has more layers than the second core 600, and the increased proportion of rigid material in the second core 600 effectively counteracts the deformation stress generated by the first core 100 during thermal expansion. For example, a 20-layer structure originally consisting of 9+2+9 layers can be transformed in this technical solution by independently manufacturing the first core 100 and the second core 600 with core layer designs of 6+2+6 layers and 2+2+2 layers, respectively.

[0090] In some specific embodiments, the first core 100 may employ two ABF dielectric layers and a copper foil circuit layer, while the second core 600 employs eight glass fiber reinforced dielectric layers and an electroplated copper circuit layer. Microvias with a diameter ≤50μm are formed between the layers through laser drilling. In the circuit layer of the second core 600, the interconnection density between adjacent layers can reach more than 1000 connection points per square centimeter.

[0091] The above configuration reduces substrate deformation caused by differences in the coefficients of thermal expansion of materials, and suppresses warping of large-size substrates during high-temperature processes. Multilayer high-density interconnects improve signal transmission efficiency while enhancing the substrate's bending resistance through a three-dimensional stacking structure, ensuring the planarity stability of the packaging substrate during subsequent assembly and use.

[0092] This application further proposes that the arrangement density of the solder ball array is controlled within the range of 500-2000 balls / cm², and the height deviation of the solder balls is limited to within ±5μm.

[0093] The solder ball array density refers to the number of solder balls per unit area. This can be achieved through a combination of laser drilling and electroplating processes. By adjusting the pattern spacing of the exposure mask and the pad size, the solder ball distribution density can be made to meet a preset range. This density range balances the interface stress distribution and the material's thermal expansion compatibility. The solder ball height deviation refers to the dimensional difference of the solder balls in the vertical direction. This can be achieved using a precision reflow soldering process combined with an optical detection feedback system. By adjusting the welding temperature profile and pressure parameters in real time, the coplanarity of the solder balls can be made to meet the target requirements. This deviation limitation can prevent localized stress concentration caused by inconsistent heights.

[0094] Specifically, when the solder ball density is below the lower limit, insufficient interconnect points can lead to uneven stress distribution at the interface, while a density above the upper limit may exacerbate thermal expansion mismatch due to excessively small solder ball spacing. By controlling the density between 500-2000 balls / cm², sufficient interconnect points can be provided to distribute mechanical stress, while avoiding the superposition of thermal stress between adjacent solder balls caused by high density. Simultaneously, with solder ball height deviation strictly limited, each solder point can uniformly bear pressure during lamination, eliminating localized deformation caused by height differences, thereby ensuring the flatness and structural stability of the dual-core coupling interface.

[0095] By adjusting the solder ball array density, the alignment accuracy of large-size packaging substrates during lamination can be effectively improved, reducing the risk of interlayer misalignment caused by improper solder ball parameters. Simultaneously, the uniform distribution of interface stress suppresses differences in thermal expansion in localized areas of the substrate, reducing warpage and enhancing the long-term reliability of the packaging structure.

[0096] In addition, the line width in the first core 100 is less than the line width in the second core 600; the line spacing in the first core 100 is less than the line spacing in the second core 600; the line thickness in the first core 100 is less than the line thickness in the second core 600; and the solder pad thickness in the first core 100 is less than the solder pad thickness in the second core 600.

[0097] This application provides a large-size packaging substrate and its fabrication method, the technical solution of which includes the following steps: (a) Independent fabrication of the first core 100: On the substrate of the first core 100, the first layer ABF300 is constructed and patterned with SAP, and the second layer ABF400 is constructed and patterned with SAP in sequence; an encoder mask 500 is applied; (b) Independent fabrication of the second core 600: On the substrate of the second core 600, the second layer of solder core is constructed; a through-hole 7 structure is formed, and the circuit layer is processed by electroplating and patterning processes; a solder mask is covered and the unit is cut; (c) Dual-core coupling: The first core 100 and the second core 600 are mechanically connected by a solder ball matrix; a bottom filler material 10 is filled at the coupling interface to solidify the structure. Through the independent fabrication of the dual cores and the compression molding coupling process, combined with the design of a high-modulus core and a stress buffer layer, the interlayer misalignment and warpage deformation caused by material stress are effectively suppressed, which has the advantages of effectively reducing substrate warpage, improving interlayer alignment accuracy, and improving manufacturing yield.

[0098] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a large-size packaging substrate, characterized in that, Includes the following steps: S1: First chip independently manufactured: On the substrate of the first core, a first layer of stacked dielectric material is constructed and patterned with SAP, and a second layer of stacked dielectric material is constructed and patterned with SAP in sequence. The stacked dielectric material includes a photosensitive dielectric material or a stacked insulating film. Apply an encoder mask; the encoder mask is a photolithographic mask with position calibration marks. S2: Second core manufactured independently: A second layer of solder core is constructed on the substrate of the second core; A through-hole structure is formed, and the circuit layer is processed through electroplating and patterning processes; Cover the welding mask and perform unit cutting; S3: Dual-core coupling: The first core and the second core are mechanically connected by a coupling structure; Fill and cure the bottom filler material at the coupling interface; The coupling structure: the first core and the second core are interconnected through a coupling structure, which includes solder ball connection, blind hole electroplating connection or copper pillar connection and the interface is filled with a bottom filler material layer. The elastic modulus of the second core is higher than that of the first core, and the second core is made of glass. The thickness of the second core is less than that of the first core, and the lamination process for coupling the two cores after they are manufactured independently adopts a compression molding process.

2. The method for preparing a large-size packaging substrate according to claim 1, characterized in that: The first core has more layers than the second core.

3. The method for preparing a large-size packaging substrate according to claim 1, characterized in that: The bottom filler material is an epoxy resin-based polymer, which is cured after filling to form a stress buffer layer.

4. A large-size packaging substrate, characterized in that, include: The independently manufactured first core comprises at least two layers of stacked dielectric material and a SAP patterned circuit layer, wherein the stacked dielectric material includes photosensitive dielectric material or stacked insulating film; The independently manufactured second core includes a solder core layer, a through-hole structure, and an electroplated circuit layer; Coupling structure: The first core and the second core are interconnected through a coupling structure, which includes solder ball connection, blind hole electroplating connection or copper pillar connection and the interface is filled with a bottom filler material layer; The elastic modulus of the second core is higher than that of the first core, and the second core is made of glass. The thickness of the second core is less than that of the first core, and the lamination process for coupling the two cores after they are manufactured independently adopts a compression molding process.

5. The large-size packaging substrate according to claim 4, characterized in that: The elastic modulus of the second core is 1.5-3 times that of the first core; the first core is a coreless substrate with or without a core board, and can be in the form of a symmetrical substrate or an asymmetrical substrate.

6. The large-size packaging substrate according to claim 5, characterized in that: The through-hole structure includes a first through-hole penetrating the glass core, which is filled by a dielectric material layer, and a second through-hole is formed by further processing on the surface of the dielectric material after the layering. The diameter of the first through-hole is greater than the diameter of the second through-hole.

7. The large-size packaging substrate according to claim 4, characterized in that: The first core has more layers than the second core.

8. The large-size packaging substrate according to claim 4, characterized in that: The line width in the first core is less than the line width in the second core; the line spacing in the first core is less than the line spacing in the second core; the line thickness in the first core is less than the line thickness in the second core; the solder pad thickness in the first core is less than the solder pad thickness in the second core.

Images