MOS transistor and integrated circuit

Abstract

The invention relates to the technical field of semiconductors, particularly provides an MOS transistor and an integrated circuit, and aims to solve the technical problem of electric leakage of a GIDL of an existing high-voltage CMOS. To this end, the MOS transistor of the present application comprises: a semiconductor substrate; the source region and the drain region are arranged in the semiconductor substrate; the gate structure is arranged between the source region and the drain region and located on the semiconductor substrate, the gate structure comprises a gate insulating layer and a gate arranged above the gate insulating layer, the gate insulating layer comprises a first region close to the drain region and a second region close to the source region, and the physical thickness of the first region is larger than or equal to that of the second region; the first area at least comprises a first insulating layer and a second insulating layer which are sequentially stacked on the semiconductor substrate, the dielectric constant of the first insulating layer is larger than that of the second insulating layer, the GIDL leakage current can be effectively restrained, and the performance and reliability of the device are guaranteed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and specifically provides a MOS transistor and an integrated circuit. Background Technology

[0002] GIDL (Gate-Induced Drain Leakage) is a band-to-band tunneling effect induced when a gate electric field is applied to the drain depletion region. In high-voltage CMOS devices for display driving platforms, the drain needs to withstand a high operating voltage. This high drain voltage causes a sharp bending of the energy band in the drain depletion region, resulting in the valence band top being higher than the conduction band bottom. Electrons then transition from the valence band to the conduction band through quantum tunneling, forming electron-hole pairs. Electrons enter the drain or, under the influence of a strong electric field, enter the gate oxide, while holes are collected by the substrate, forming the GIDL leakage current (I0). GIDL ).

[0003] The GIDL effect leads to a degradation in the quality of the gate dielectric layer (gate insulating layer), adversely affecting device reliability and reducing device lifespan. Furthermore, for high-voltage CMOS in the display driver field, the GIDL phenomenon has multiple negative impacts on the performance and reliability of the display driver chip, including excessive leakage current leading to a significant increase in chip static power consumption, and voltage drops caused by pixel circuit leakage that may result in display anomalies such as flickering, image retention, and uneven brightness.

[0004] To address the aforementioned technical challenges in high-voltage CMOS fabrication, improvements can be made to the trap ion implantation method from a process perspective, or the device structure can be optimized. For example, by adjusting the tilt angle during ion implantation, a gradually varying doping morphology can be formed in the channel region, thereby reducing the drain electric field. Structurally, the vertical electric field intensity within the gate dielectric layer can be reduced by increasing the gate dielectric layer thickness or pushing the drain away from the gate, thus decreasing the GIDL leakage current. However, the improvement capabilities of these methods are limited, and they may also lead to side effects such as decreased device switching speed and increased device size. Summary of the Invention

[0005] To overcome the aforementioned deficiencies, this application is proposed to provide a technical solution to, or at least partially solve, the GIDL leakage problem in existing high-voltage CMOS transistors. This application provides a MOS transistor and an integrated circuit comprising the aforementioned MOS transistor.

[0006] In a first aspect, this application provides a MOS transistor, comprising:

[0007] Semiconductor substrate;

[0008] Source and drain regions disposed within the semiconductor substrate;

[0009] A gate structure is disposed between a source region and a drain region and located on a semiconductor substrate. The gate structure includes a gate insulating layer and a gate disposed on the gate insulating layer. The gate insulating layer includes a first region near the drain region and a second region near the source region. The physical thickness of the first region is greater than or equal to the physical thickness of the second region. The first region includes at least a first insulating layer and a second insulating layer sequentially stacked on the semiconductor substrate. The dielectric constant of the first insulating layer is greater than the dielectric constant of the second insulating layer.

[0010] In one embodiment of the MOS transistor of this application, the semiconductor substrate is a silicon layer or a silicon carbide layer, the first insulating layer is a silicon dioxide layer or a high-k dielectric layer, and the second insulating layer is a low-k dielectric layer.

[0011] In one embodiment of the MOS transistor of this application, the dielectric constant of the second region is equal to the dielectric constant of the first insulating layer, and further, the second region and the first insulating layer are made of the same material.

[0012] In one embodiment of the MOS transistor of this application, the first region further includes a third insulating layer stacked on the second insulating layer, wherein the dielectric constant of the third insulating layer is greater than the dielectric constant of the second insulating layer.

[0013] In one embodiment of the MOS transistor of this application, the gate is a polysilicon gate and the third insulating layer is a silicon dioxide layer; in another embodiment of the MOS transistor of this application, the gate is a metal gate and the third insulating layer is a high-k dielectric layer.

[0014] In one embodiment of the MOS transistor of this application, the semiconductor substrate is further provided with an adjacent first well region and a second well region, both of which extend inward from the surface of the semiconductor substrate to a predetermined depth.

[0015] The first well region and the second well region have the same doping type, and the doping concentration of the first well region is greater than that of the second well region. The drain region is located in the first well region, and the source region is located in the second well region. The gate structure spans the first well region and the second well region.

[0016] In one embodiment of the MOS transistor of this application, the boundary line between the first well region and the second well region is flush with the boundary line between the first region and the second region.

[0017] In one embodiment of the MOS transistor of this application, sidewalls are provided on both sides of the gate structure.

[0018] In one embodiment of the MOS transistor of this application, a lightly doped drain region located in the semiconductor substrate is also included.

[0019] In a second aspect, this application provides an integrated circuit including the MOS transistor described in the first aspect above.

[0020] The above-described technical solutions of this application have at least one or more of the following beneficial effects:

[0021] The MOS transistor in this application effectively reduces the longitudinal electric field strength when a high voltage is applied to the drain by adding a second insulating layer with a relatively low dielectric constant in the gate insulating layer near the drain region. This reduces the carrier tunneling probability, suppresses GIDL leakage current at the source, and ensures the performance and reliability of the device.

[0022] In particular, by specially designing the well regions, the first well region located below the gate structure and the second well region have the same doping type, and the doping concentration of the first well region corresponding to the drain region is greater than the doping concentration of the second well region corresponding to the source region. This well region structure with non-uniform doping concentration can ensure the stability of the threshold voltage. Attached Figure Description

[0023] The disclosure of this application will become more readily understood with reference to the accompanying drawings. It will be readily understood by those skilled in the art that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this application. Furthermore, similar numbers in the drawings are used to denote similar components, wherein:

[0024] Figure 1 This is a schematic diagram of the main structure of a MOS transistor in one embodiment of this application;

[0025] Figures 2 to 7 This is a schematic diagram of the main process structure for forming the gate insulating layer in one embodiment of this application;

[0026] Figures 8 to 9 This is a schematic diagram of the main process structure for forming the first and second well regions in one embodiment of this application. Detailed Implementation

[0027] Some embodiments of this application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of this application and are not intended to limit the scope of protection of this application.

[0028] To address, or at least partially address, the technical problem of GIDL leakage in existing high-voltage CMOS transistors that affects device performance, this application proposes a MOS transistor and integrated circuit.

[0029] Figure 1 This is a schematic diagram of the main structure of a MOS transistor according to one embodiment of this application. Figure 1As shown, the MOS transistor in this embodiment mainly includes: a semiconductor substrate 10, wherein an isolation structure 20 is provided, defining an active region by the isolation structure 20; a source region 30 and a drain region 40 located within the active region; and a gate structure 50 located between the source region 30 and the drain region 40 and on the surface of the semiconductor substrate 10. The gate structure 50 includes a gate insulating layer 51 and a gate 52 disposed above the gate insulating layer 51. The gate insulating layer 51 includes a first region 511 near the drain region 40 and a second region 512 near the source region 30. The first region 511 includes at least a first insulating layer 5111 and a second insulating layer 5112 stacked together. The dielectric constant of the first insulating layer 5111 is greater than the dielectric constant of the second insulating layer 5112.

[0030] Specifically, the semiconductor substrate 10 in the MOS transistor can be a substrate commonly used in the semiconductor field, such as a silicon substrate, a silicon carbide substrate, or SOI (silicon on insulator), or it can be an epitaxial wafer commonly used in the semiconductor field, which includes a substrate and an epitaxial layer stacked together, such as a silicon substrate and a silicon epitaxial layer.

[0031] The isolation structure 20 located within the semiconductor substrate 10 can effectively block electrical crosstalk between adjacent active regions, ensuring device stability. This application does not impose specific limitations on the specific form of the isolation structure 20; a suitable isolation method can be selected based on actual product requirements. In one embodiment, the isolation structure 20 is a shallow trench isolation (STI) structure. The core function of shallow trench isolation is to achieve the required electrical isolation effect by etching shallow trenches on the surface of the semiconductor substrate 10 and then filling them with insulating material.

[0032] The active region defined by the isolation structure 20 contains an active region 30 and a drain region 40, which serve as the injection and collection terminals for charge carriers. Their doping type and concentration need to be specifically designed according to the device type. For example, for NMOS, the source region 30 and drain region 40 can be heavily N-type doped with phosphorus or arsenic; for PMOS, the source region 30 and drain region 40 can be heavily P-type doped with boron or similar materials.

[0033] A gate structure 50 for implementing device switching control function is provided on the surface of the semiconductor substrate 10 between the source region 30 and the drain region 40. The gate structure 50 includes a gate insulating layer 51 located on the surface of the semiconductor substrate 10 and a gate 52 located on the gate insulating layer 51. The gate 52 is used to control the opening and closing of the conductive channel between the source region 30 and the drain region 40. The gate insulating layer 51 serves as an isolation medium between the gate 52 and the semiconductor substrate 10 and can regulate the channel carrier concentration. The gate insulating layer 51 is divided into two regions along the direction from source to drain. The region closer to the drain region 40 is designated as the first region 511, and the region closer to the source region 30 is designated as the second region 512. The physical thickness of the first region 511 is greater than or equal to the physical thickness of the second region 512.

[0034] In Embodiment 1, the first region 511 adopts a double-layer stacked design, which is formed by stacking a first insulating layer 5111 and a second insulating layer 5112, and the dielectric constant of the first insulating layer 5111 is greater than the dielectric constant of the second insulating layer 5112.

[0035] By providing a second insulating layer 5112 with a low dielectric constant in the gate insulating layer 51 near the drain region 40, and based on Gauss's law, it can be known that at the interface between the second insulating layer 5112 and the first insulating layer 5111, the electric displacement vector must satisfy the continuity condition, i.e. ,in The dielectric constant of the first insulating layer 5111 is... The electric field strength within the first insulating layer 5111; The dielectric constant of the second insulating layer 5112 is... This represents the electric field strength within the second insulating layer 5112. Because the second insulating layer 5112 has a relatively lower dielectric constant, therefore... Less than To maintain the continuity of the electric displacement vector at the interface, the electric field strength of the first insulating layer 5111 is... The electric field strength at the drain edge of the device will be reduced proportionally, ultimately achieving effective control and weakening of the electric field strength. The core cause of GIDL leakage is band-to-band tunneling induced by the strong vertical electric field at the drain edge. The reduction of the electric field strength here can directly weaken the vertical electric field required for band-to-band tunneling, significantly reducing the tunneling probability and suppressing the GIDL leakage current of the device from the root.

[0036] In the first embodiment of this application, by providing a second insulating layer 5112 with a lower dielectric constant on the first insulating layer 5111, the longitudinal electric field strength when a high voltage is applied to the drain can be effectively reduced, thereby reducing the carrier tunneling probability, suppressing GIDL leakage current from the source, and ensuring device performance and reliability.

[0037] In the above structure, the material of the first insulating layer 5111 should ideally be compatible with the material of the semiconductor substrate 10, in addition to considering the material of the second insulating layer 5112, to ensure the interface quality between the first region 511 and the semiconductor substrate 10. For example, if the semiconductor substrate 10 is a silicon substrate, silicon carbide substrate, SOI substrate, or silicon epitaxial wafer, then the first insulating layer 5111 can be silicon dioxide. Of course, if the semiconductor substrate 10 is made of other materials, the first insulating layer 5111 can also be made of other dielectric materials, such as high-k dielectric materials.

[0038] The second insulating layer 5112 can be made of a low-k dielectric material, such as Black Diamond I, nanoporous organosilicon glass, fluorine-doped silicon dioxide, or carbon-doped silicon dioxide. With the development of semiconductor process materials, other superior and more suitable low-k dielectric materials for this device may also emerge. In specific implementations, if the first insulating layer 5111 is silicon dioxide, the second insulating layer 5112 can be made of fluorine-doped silicon dioxide or carbon-doped silicon dioxide, mainly because these two materials have advantages such as good bonding with silicon dioxide, good density, and high compatibility with existing processes.

[0039] In one specific embodiment, the material of the second region 512 is the same as the material of the first insulating layer 5111. For example, the first insulating layer 5111 and the entire second region 512 are both made of silicon dioxide, or both are high-k dielectric materials. By setting the second region 512 in the gate insulating layer 51 near the source region 30 to use the same material as the first insulating layer 5111 of the first region 512, the fabrication process can be simplified and the production cost reduced.

[0040] Further reference Figure 1 In another embodiment of the MOS transistor of this application (referred to as Embodiment 2), the first region 511 further includes a third insulating layer 5113 disposed on the second insulating layer 5112, wherein the dielectric constant of the third insulating layer 5113 may be greater than the dielectric constant of the second insulating layer 5112.

[0041] Specifically, in Embodiment 1, the first region 511 is a double-layered structure composed of a first insulating layer 5111 and a second insulating layer 5112. In Embodiment 2, a third insulating layer 5113 is added to the side of the second insulating layer 5112 away from the semiconductor substrate 10, and the dielectric constants of both the third insulating layer 5113 and the first insulating layer 5111 are greater than the dielectric constant of the second insulating layer 5112. Thus, in Embodiment 2, the first region 511 is a sandwich-type three-layered composite structure composed of the first insulating layer 5111, the second insulating layer 5112, and the third insulating layer 5113, with the middle layer being the second insulating layer 5112 having a low dielectric constant, and the upper and lower layers being the first insulating layer 5111 and the third insulating layer 5113 having high dielectric constants, respectively. According to Gauss's law, the electric displacement vector at the interface of the insulating layer must remain continuous. Since the dielectric constant of the middle second insulating layer 5112 is lower than that of the upper and lower first insulating layers 5111 and third insulating layers 5113, in order to maintain the continuity of the electric displacement vector, the electric field strength inside the first insulating layer 5111 will be reduced proportionally, thereby weakening the electric field strength at the drain edge.

[0042] The material selection for the third insulating layer 5113 should not only have a higher dielectric constant than the second insulating layer 5112, but also ideally consider the interface quality between it and the gate 52. For example, if the gate 52 is a polysilicon gate, then silicon dioxide can be used for the third insulating layer 5113. Alternatively, if the gate 52 is a metal gate, then a high-k dielectric material can be used for the third insulating layer 5113. Furthermore, the first insulating layer 5111 and the entire second region 512 can also be made of high-k dielectric materials. By matching the materials of the third insulating layer 5113 and the gate 52, the quality of the third insulating layer 5113 itself, as well as the interface quality between the first region 511 and the gate 52, can be ensured, and the influence of work function changes can be suppressed.

[0043] In one feasible implementation, the semiconductor substrate 10 is a silicon substrate or a silicon epitaxial wafer, the gate 52 is a polysilicon gate, the first insulating layer 5111 and the third insulating layer 5113 are both silicon dioxide, and the second insulating layer 5112 uses a low-k dielectric, such as a single layer of fluorine-doped silicon dioxide, a single layer of carbon-doped silicon dioxide, or a stack of two low-k dielectric layers. In this way, the interface quality between the first insulating layer 5111 and the semiconductor substrate 10 is guaranteed, and the interface quality between the third insulating layer 5113 and the gate 52 is guaranteed and the influence of work function changes is suppressed.

[0044] It is understandable that a larger thickness of the first region 511 is more conducive to improving its effect on weakening the electric field and ensuring the electric field control effect. In a specific embodiment of the MOS transistor of this application, the thickness of the first region 511 is greater than or equal to the thickness of the second region 512, and preferably the thickness of the first region 511 is greater than the thickness of the second region 512. Here, thickness refers to physical thickness.

[0045] In one specific embodiment of the MOS transistor of this application, the well regions in the semiconductor substrate 10 include an adjacent first well region 101 and a second well region 102, both extending from the surface of the semiconductor substrate 10 into the semiconductor. The drain region 40 is located within the first well region 101, and the source region 30 is located within the second well region 102. The gate structure 50 spans the first well region 101 and the second well region 102, meaning the gate structure 50 covers both the first well region 101 and the second well region 102; or, in other words, the gate structure 50 covers the boundary between the first well region 101 and the second well region 102. The well regions can be formed by ion implantation or diffusion, with both having the same doping type, such as P-type doping, and the doping concentration of the first well region 101 being greater than that of the second well region 102.

[0046] Specifically, the asymmetric gate insulating layer 51 may cause a difference in the equivalent oxide thickness (EOT) between the first region 511 and the second region 512, which may lead to unstable threshold voltage. Therefore, by setting an asymmetric well structure, that is, the doping concentration of the first well region 101 is greater than the doping concentration of the second well region 102, the threshold voltage can be made as stable as possible.

[0047] In one embodiment, the boundary line between the first well region 101 and the second well region 102 is flush with the boundary line between the first region 511 and the second region 512.

[0048] In practice, when the physical thickness of the first region 511 is equal to the physical thickness of the second region 512, and the boundary line between the first well region 101 and the second well region 102 is flush with the boundary line between the first region 511 and the second region 512 (see...), Figure 1 The dashed line in the middle vertical direction can be used to conveniently and accurately calculate the doping concentration ratio between the first well region 101 and the second well region 102.

[0049] Let Tk be the physical thickness of the second insulating layer 5112 in the first region 511, Tox1 be the total physical thickness of the first insulating layer 5111 and the third insulating layer 5113, and Tox2 be the physical thickness of the second region 512. Then, Tk + Tox1 = Tox2. Let the doping concentration of the second well region 102 be denoted as... The doping concentration of the first well region 101 is denoted as Ignoring the effects of flat-band voltage, work function, and fixed charge within the dielectric, and without substrate bias voltage, calculations and derivations show that... and The ratio is the thickness of the oxide layer in the second region. With the thickness of the oxide layer in the first region The square of the ratio can be expressed by the following reference formula:

[0050] Since the equivalent oxide layer thickness EOT and the physical thickness of the gate insulating layer 51 can be related by the capacitance series formula, the ratio of doping concentration between the first well region 101 and the second well region 102 can be calculated once the physical thickness of the second insulating layer 5112 is determined (i.e., ...). and The ratio of the two values ​​is used to improve the GIDL leakage current of the device without reducing device performance such as threshold voltage as much as possible.

[0051] Of course, the above reference formula is roughly derived based on the premise that the physical thickness of the first region 511 is the same as that of the second region 512, the boundary line between the first well region 101 and the second well region 102 is flush with the boundary line between the first region 511 and the second region 512, and the material of the first insulating layer 5111 and the third insulating layer 5113 is silicon dioxide. In practical applications, the doping concentration ratio of the second well region 102 and the first well region 101 and the position of their boundary line can be determined according to the actual situation.

[0052] Further reference Figure 1 In some embodiments, sidewalls 60 are also provided on both sides of the gate structure 50, and the sidewalls 60 are arranged closely around the sidewalls of the gate insulating layer 51 and the gate 52.

[0053] like Figure 1 As shown, the MOS transistor may further include a lightly doped drain region 70 and an ohmic contact region 80 disposed in the semiconductor substrate 10. The lightly doped drain (LDD) region is a low-doped region disposed between the drain region 40 and the channel. This region is used to share some of the voltage stress, thereby reducing the peak electric field intensity near the drain region 40. The ohmic contact region 80 is used to implement the well region's extraction. Its doping type is consistent with the well region, but its doping concentration is much greater than that of the well region. For example, if the well region is P-type doped, then the ohmic contact region 80 is heavily P-type doped.

[0054] This application also provides a method for fabricating a MOS transistor. Figures 2 to 7 This is a schematic diagram of the main process structure for forming the gate insulating layer in one embodiment of this application; Figure 8 and Figure 9 This is a schematic diagram of the main process structure for forming the first and second well regions in one embodiment of this application. The following is combined with... Figures 2 to 7 , Figure 8 and Figure 9 The formation of asymmetric gate insulating layers and asymmetric well structures will be explained in detail.

[0055] First, a first insulating material layer 901 and a second insulating material layer 902 are sequentially formed on the surface of the semiconductor substrate 10 that has formed the STI isolation structure, wherein the dielectric constant of the first insulating material layer 901 is greater than the dielectric constant of the second insulating material layer 902.

[0056] Next, a first mask 903 is set at the location where the first region is to be formed, and the first insulating material layer 901 and the second insulating material layer 902 are etched to obtain the first insulating layer 5111 and the second insulating layer 5112 respectively. Then the first mask 903 is removed.

[0057] Subsequently, a third insulating material layer 904 is formed on the semiconductor substrate 10 and the surface of the second insulating layer 5112. A second mask 905 is provided at the location where the first region and the second region are to be formed, and the third insulating material layer 904 is etched to obtain the third insulating layer 5113 (and the first region 511) and the second region 512.

[0058] Then gate 52 is formed.

[0059] Specifically, during the formation of the gate structure, such as Figure 2 As shown, a first insulating material layer 901, such as a silicon dioxide layer, is first formed on the surface of the semiconductor substrate 10; as Figure 3 As shown, a second insulating layer 902 of a certain thickness is then deposited on the first insulating material layer 901 using plasma-enhanced chemical vapor deposition (PECVD), such as fluorine-doped silicon dioxide (SiOF) and carbon-doped silicon dioxide (SiCOH). Figure 4 As shown, the first mask 903 defines the range of the first region. The first insulating material layer 901 and the second insulating material layer 902 in other regions can be removed by dry etching or wet etching to expose the surface of the semiconductor substrate 10, and then the first mask 903 is removed.

[0060] Subsequently, as Figure 5 As shown, the third insulating material layer 904 is formed using methods such as atomic layer deposition (ALD). The purpose of using ALD here is to ensure the quality of the dielectric layer in the second region and to prevent the high temperature of the furnace tube and in-situ steam generation (ISSG) process from damaging the already formed second insulating layer 5112. To ensure the subsequent formation of a gate insulating layer of uniform thickness, the thickness of the third insulating material layer 904 should be greater than the sum of the thicknesses of the first insulating layer 5111 and the second insulating layer 5112. Figure 6As shown, the range of the first region 511 and the second region 512 is defined using a second mask 905. The third insulating material layer 904 in the other regions is removed, and then the second mask 905 is removed. Figure 7 As shown, after a planarization process, a gate insulating layer 51 with a relatively flat surface is obtained.

[0061] In another embodiment, after forming the third insulating material layer 904, the method further includes thinning the third insulating material layer 904 until the second insulating layer 5112 is exposed. This results in a first region 511 containing only the first insulating layer 5111 and the second insulating layer 5112, which also reduces GIDL leakage current in the device.

[0062] Using the above process route, a gate insulating layer of uniform thickness can be formed; in other embodiments, adjustments can be made to this process route to make the physical thickness of the first region greater than that of the second region.

[0063] In one specific embodiment of the method for fabricating a MOS transistor according to this application, the asymmetric well region structure can be formed before the gate structure 50 is formed. Specifically, the steps of forming the first well region 101 and the second well region 102 in the semiconductor substrate 10 may include:

[0064] A third mask 906 is set at the location where the first well region is to be formed, and a first ion implantation is performed at the location where the second well region is to be formed to obtain the second well region 102; a fourth mask 907 is set at the location where the second well region is to be formed, and a second ion implantation is performed at the location where the first well region is to be formed to obtain the first well region 101, wherein the doping concentration of the first ion implantation is less than the doping concentration of the second ion implantation.

[0065] Specifically, such as Figure 8 and Figure 9 As shown, photoresist is first coated on the semiconductor substrate 10 and exposed and developed. A third mask 906 is then placed over the location where the first well region is to be formed. Low-concentration ion implantation, such as boron ion implantation, is then performed at the location where the second well region is to be formed to obtain the second well region 102. After photoresist removal and cleaning, photoresist is coated again and exposed and developed. A fourth mask 907 is then placed over the location where the second well region 102 is to be formed. High-concentration ion implantation, such as boron ion implantation, is then performed at the location where the first well region is to be formed. Finally, after high-temperature annealing, a well region structure with uneven doping concentration is formed. The well region structure with uneven doping concentration can ensure the stability of the threshold voltage.

[0066] In one embodiment, the boundary line between the first well region 101 and the second well region 102 is aligned with the boundary line between the first region 511 and the second region 512. This is to facilitate the calculation of the EOT difference between the first region 511 and the second region 512, thereby simplifying the calculation process of the doping concentration of the first well region 101 and the second well region 102. In other embodiments, the boundary line between the first well region 101 and the second well region 102 may not be aligned with the boundary line between the first region 511 and the second region 512. In practice, whether the boundary lines coincide can be determined by considering factors such as the material and thickness of the gate dielectric layer in the two regions and the concentration of the two well regions.

[0067] Based on the aforementioned MOS transistor, this application also provides an integrated circuit in which the aforementioned MOS transistor is integrated. This integrated circuit may be, for example, a CMOS integrated circuit, including PMOS transistors and NMOS transistors, wherein at least one of the PMOS transistors and NMOS transistors uses the aforementioned MOS transistor. The integrated circuit may also be a BCD (Bipolar-CMOS-DMOS) product, wherein the CMOS includes the aforementioned MOS transistor.

[0068] The technical solution of this application has been described in conjunction with the specific embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.

Claims

1. A MOS transistor, characterized in that, include: Semiconductor substrate; Source and drain regions disposed within the semiconductor substrate; A gate structure disposed between the source region and the drain region and located on the semiconductor substrate, the gate structure including a gate insulating layer and a gate disposed on the gate insulating layer, wherein the gate insulating layer includes a first region near the drain region and a second region near the source region, the physical thickness of the first region being greater than or equal to the physical thickness of the second region; the first region includes at least a first insulating layer and a second insulating layer sequentially stacked on the semiconductor substrate, wherein the dielectric constant of the first insulating layer is greater than the dielectric constant of the second insulating layer.

2. The MOS transistor according to claim 1, characterized in that, The semiconductor substrate is a silicon layer or a silicon carbide layer, the first insulating layer is a silicon dioxide layer or a high-k dielectric layer, and the second insulating layer is a low-k dielectric layer.

3. The MOS transistor according to claim 1 or 2, characterized in that, The second region is made of the same material as the first insulating layer.

4. The MOS transistor according to any one of claims 1-3, characterized in that, The first region further includes a third insulating layer stacked on the second insulating layer, wherein the dielectric constant of the third insulating layer is greater than the dielectric constant of the second insulating layer.

5. The MOS transistor according to claim 4, characterized in that, The gate is a polysilicon gate, and the third insulating layer is a silicon dioxide layer; or, the gate is a metal gate, and the third insulating layer is a high-k dielectric layer.

6. The MOS transistor according to any one of claims 1-5, characterized in that, The semiconductor substrate is further provided with an adjacent first well region and a second well region, both of which extend inward from the surface of the semiconductor substrate to a predetermined depth. The first well region and the second well region have the same doping type, and the doping concentration of the first well region is greater than that of the second well region. The drain region is located in the first well region, and the source region is located in the second well region. The gate structure spans the first well region and the second well region.

7. The MOS transistor according to claim 6, characterized in that, The boundary line between the first and second well regions is flush with the boundary line between the first and second regions.

8. The MOS transistor according to claim 1, characterized in that, The gate structure is also provided with sidewalls on both sides.

9. The MOS transistor according to claim 1 or 8, characterized in that, It also includes lightly doped drain regions located in the semiconductor substrate.

10. An integrated circuit, characterized in that, The MOS transistor includes any one of claims 1-9.

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