Socket board and automatic testing device

Abstract

The invention provides a socket board which can be accurately managed. The socket board (210A) is provided with a socket printed board (214) and a socket (212) provided on the socket printed board (214). A non-volatile memory (240) is provided for each socket printed board (214), and is capable of storing information relating to the socket board (210A).

Description

Technical Field

[0001] This invention relates to socket boards. Background Technology

[0002] Automatic test equipment (ATE) is used in the inspection of various semiconductor devices such as memory and CPU (Central Processing Unit). The ATE supplies test signals to the semiconductor device under test (hereinafter referred to as the device under test (DUT)), measures the DUT's response to the test signals, determines whether the DUT is qualified or not, or identifies the defective parts.

[0003] In recent years, DRAM (Dynamic Random Access Memory) has continued to advance in terms of speed. In GDDR (Graphics Double Data Rate) memory integrated into graphics tablets, under the GDDR6X standard, a transfer speed of 21Gbps is achieved through NRZ (NonReturn to Zero) mode.

[0004] In the next generation of GDDR7, PAM4 (Pulse Amplitude Modulation 4) is adopted, increasing the transmission speed to 40Gbps. NRZ technology is also progressing towards higher speeds year by year, with the next generation reaching around 28Gbps.

[0005] Patent document 1 discloses an interface device and an automatic testing device capable of testing high-speed devices with high precision. In this interface device, the socket board and the pin electronic circuit are connected via an interlayer and wiring.

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2024-014522 Summary of the Invention

[0009] Summary of the invention

[0010] The problem that the invention aims to solve

[0011] In automated testing equipment, the management and use of socket boards are very important.

[0012] The present invention was made in view of such circumstances, and one of the exemplary objects of one of its solutions is to provide a socket board that can be accurately managed.

[0013] Solution for solving the problem

[0014] One embodiment of the present invention provides a socket board comprising: a socket printed circuit board; a socket guide disposed on the socket printed circuit board; and a non-volatile memory disposed on the socket printed circuit board, capable of storing information related to the socket board.

[0015] It should be noted that any combination of the above-mentioned constituent elements, or the substitution of constituent elements and descriptions among methods, apparatuses, systems, etc., are also valid solutions to this invention or disclosure. Furthermore, the description in this section (Solutions for Solving the Problem) does not represent all the essential features of this invention; therefore, sub-combinations of these described features may also constitute this invention. Attached Figure Description

[0016] Figure 1 This is a diagram representing the ATE implementation method.

[0017] Figure 2 This is a cross-sectional view of an interface device according to an embodiment.

[0018] Figure 3 This is a diagram illustrating a front-end module of one embodiment.

[0019] Figure 4 It means Figure 3 A three-dimensional diagram of the composition of a FEU.

[0020] Figure 5 It means Figure 3 A cross-sectional view of the components of a FEU.

[0021] Figure 6 This is a cross-sectional view showing an example of the connection between a pinned electronic IC and a socket (DUT).

[0022] Figure 7 This is a cross-sectional view of the socket plate according to the implementation method.

[0023] Figure 8 This is a diagram showing the layout of multiple second pads on the second side of the socket PCB.

[0024] Figure 9 This is a diagram showing a variation of the layout of multiple second pads on the second side of a socket PCB.

[0025] Figure 10 This is a perspective view showing the layout of the socket board in the implementation method.

[0026] Figure 11 This is a top view showing the layout of the socket panel in the embodiment.

[0027] Figure 12 This is a top view showing the layout of the socket panel for the comparative technology.

[0028] Figure 13This is a top view showing the layout of a modified socket panel.

[0029] Figure 14 This is a diagram showing a socket board according to one embodiment.

[0030] Symbol Explanation

[0031] 1DUT, 100ATE, 120 Tester, 130 Test Head, 200 Interface Device, 210 Socket Board, 212 Socket, 214 Socket PCB, P1 First Pad, P2 Second Pad, SIG Signal Pin, GND Ground Pin, 216 Socket Board Side Connector, 218 Intermediate Layer, 219 Cable Clip, 220 Wiring, 222 FPC Cable, 230 Motherboard, 240 Non-Volatile Memory, 300 Front-End Module, 400 Pin Electronic IC. Detailed Implementation

[0032] (Summary of the implementation method)

[0033] A summary of several exemplary embodiments of the present invention will be described. This summary serves as a prelude to the detailed description that follows, and aims to provide a basic understanding of the embodiments, simplifying the explanation of several concepts of one or more embodiments without limiting the breadth of the invention or disclosure. This summary is not an inclusive summary of all embodiments to be considered, nor does it define the scope of some or all of the embodiments by identifying the essential elements of all embodiments. For simplicity, "an embodiment" is sometimes used to indicate one or more embodiments (examples, variations) disclosed in this specification.

[0034] One embodiment of the present invention provides a socket board comprising a socket printed circuit board, a socket guide disposed on the socket printed circuit board, and a non-volatile memory disposed on the socket printed circuit board and storing information related to the socket board.

[0035] Based on this structure, instead of a DSA (Device Specific Adapter) unit composed of multiple socket boards, information can be managed within a single socket board unit. This enables testing applications that take into account the individual differences of each socket board.

[0036] In one embodiment, the non-volatile memory can be positioned along the outer periphery of the socket printed circuit board. By positioning the socket at the center of the socket printed circuit board and arranging the non-volatile memory along the outer periphery, the impact on the wiring layout of the DUT's signal lines and ground lines can be minimized.

[0037] In one embodiment, the non-volatile memory can be disposed at any of the four corners of the socket printed circuit board.

[0038] One embodiment of the automatic testing device may include the aforementioned socket board.

[0039] (Implementation Method)

[0040] Hereinafter, preferred embodiments will be described with reference to the accompanying drawings. Identical or equivalent constituent elements, components, and processes shown in the drawings will be labeled with the same symbols, and repetitive descriptions will be omitted where appropriate. Furthermore, the embodiments are illustrative rather than limiting the disclosure and invention; all features and combinations thereof described in the embodiments may not be essential features and combinations thereof of the disclosure and invention.

[0041] In addition, the dimensions (thickness, length, width, etc.) of the components shown in the accompanying drawings are sometimes appropriately enlarged or reduced for ease of understanding. Furthermore, the dimensions of multiple components do not necessarily indicate their size relationship; in the accompanying drawings, even if a component A is depicted as thicker than another component B, component A may actually be thinner than component B.

[0042] In this specification, "the state of connection between component A and component B" includes not only the case where component A and component B are physically directly connected, but also the case where component A and component B are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect performed by their combination.

[0043] Similarly, "the state in which component C is connected (set between) component A and component B" includes not only the case where component A and component C, or component B and component C are directly connected, but also the case where they are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect performed by their combination.

[0044] Figure 1 This is a diagram illustrating an implementation of ATE100. ATE100 includes a tester 120, a test head 130, a processor 150, and an interface device 200.

[0045] The tester 120 centrally controls the ATE100. Specifically, the tester 120 executes the test program, controls the test head 130 and the processor 150, and collects the measurement results.

[0046] The processor 150 supplies (loads) the DUT1 to the interface device 200 and unloads the tested DUT1 from the interface device 200. Furthermore, the processor 150 distinguishes the DUT1 into qualified and unqualified products.

[0047] The test head 130 has hardware that generates test signals to be supplied to the DUT1 and detects signals from the DUT1 (referred to as device signals). It may also include power supply circuitry that generates power supply voltages to be supplied to the DUT1 and the interface device 200.

[0048] The interface device 200 includes a socket board 210, wiring 220, and a front-end module 300.

[0049] In this embodiment, multiple pin-based electronic ICs (PE-ICs) 400 are disposed in the interface device 200 rather than within the test head 130. The pin-based electronic ICs 400 are application-specific integrated circuits (ASICs) that integrate a driver for generating test signals and a comparator for receiving device signals. The test signals and device signals are NRZ signals or PAM4 signals.

[0050] More specifically, the multi-pin electronic IC 400 is modularized. This module is referred to as the front-end module 300.

[0051] The socket board 210 has multiple sockets 212. The DUT1 is mounted on the socket 212. The front-end module 300 is connected to the socket 212 via wiring 220.

[0052] The above is the structure of ATE100.

[0053] According to the ATE100, a front-end module 300, which is modularly composed of multiple pin-based electronic ICs 400, is built into the interface device 200, thereby allowing the pin-based electronic ICs 400 to be positioned near the DUT1. As a result, the transmission distance of test signals and device signals can be significantly shortened compared to the past.

[0054] For example, in conventional ATEs, the pin-controlled electronic IC and the socket board are connected by a coaxial cable with a length of approximately 500mm to 600mm. However, in this embodiment, the length of the wiring 220 can be shortened to approximately 100mm to 150mm. This significantly reduces the loss of high-frequency components and enables the transmission of high-speed test signals and device signals. The ATE100 equipped with this interface device 200 can perform high-speed memory testing exceeding 20Gbps.

[0055] Figure 2 This is a cross-sectional view of an interface device 200A according to an embodiment. Figure 2Only the structure associated with one DUT is shown. In this embodiment, the interface device 200A includes a motherboard 230 and a socket board 210 that is detachable from the motherboard 230. The socket board 210 includes a socket (also called a socket guide) 212 as a mechanical component, a socket printed circuit board (socket PCB) 214, and a socket board side connector 216. It should be noted that the socket PCB itself is sometimes referred to as a socket board, and the socket PCB with the socket guide mounted is referred to as a DSA (Device Specific Adapter) or device board.

[0056] The front-end module 300A includes multiple printed circuit boards (PCBs) 310 for mounting multiple pin electronic ICs 400. The multiple pin electronic PCBs 310 are arranged in a direction perpendicular to the surfaces (surface and back) of the DUT, in other words, perpendicular to the surface S1 of the socket board 210. In this embodiment, the socket board 210 is parallel to the ground, therefore the multiple pin electronic PCBs 310 are arranged parallel to the direction of gravity.

[0057] The front-end module 300A also features a plate-shaped cooling device (hereinafter referred to as a cold plate) 320. The cold plate 320 has a flow path for refrigerant circulation.

[0058] Multiple pin electronic PCBs 310a and 310b and a cold plate 320 are stacked in a manner where the pin electronic IC 400 and the cold plate 320 are thermally coupled.

[0059] The motherboard 230 includes a socket board-side connector 232, a spacer frame 234, and a relay connector 236. The front-end module 300A is fixed to the spacer frame 234. The relay connector 236 is electrically and mechanically coupled to the test head-side connector 132.

[0060] As detailed below, wiring 220 can replace conventional coaxial cables with cables made of flexible printed circuits (FPCs) (also known as FPC cables).

[0061] On the other hand, the wiring 224 between the pin electronics PCB 310 and the relay connector 236 only transmits control signals for the pin electronics IC 400, and does not transmit test signals or device signals. Therefore, wiring 224 can utilize a coaxial cable.

[0062] Figure 3 This is a diagram illustrating a front-end module 300B according to one embodiment.

[0063] One DUT1 is assigned 2 × M (M≥1) pin electronic ICs 400. Multiple DUTs and pin electronic ICs 400 are labeled with A to D to distinguish them as needed. In this example, with DUT1 having 192 I / Os and pin electronic ICs 400 having 24 I / Os, each DUT is assigned 192 / 24 = 8 (i.e., M = 4) pin electronic ICs 400.

[0064] The front-end module 300B is configured such that each N (N≥2) DUT1 is divided into multiple units, and this division unit is called a front-end unit (FEU). In this example, the block corresponding to 4 DUTs constitutes 1 FEU, and 1 FEU has 2×M×N = 2×4×4 = 32 pins of electronic IC 400.

[0065] Figure 3 The diagram shows two FEUs, but in reality, the front-end module 300B can have more than two FEUs. For example, in an ATE capable of simultaneously measuring 64, setting 64 / 4 = 16 FEUs, as a whole, the front-end module 300B has 64 × 192 I / O = 12288 I / Os.

[0066] Figure 4 It means Figure 3 A perspective view of the configuration example of the FEU. The sockets 212A to 212D corresponding to the four DUTs are arranged in a matrix of two rows and two columns. Considering one DUT 1A, the eight-pin electronic IC 400A assigned to it is mounted in pairs on four pin electronic PCBs 310a to 310d arranged along the X direction. The socket PCB 214 for mounting the sockets 212 can be divided according to each DUT, or the socket PCBs 214 corresponding to the four DUTs can be integrally constructed as a single substrate.

[0067] Two pin-mounted electronic ICs 400A are arranged along the Y direction and mounted on a single-pin electronic PCB 310. The two pin-mounted electronic ICs 400A are positioned at equal distances from the DUT1A.

[0068] Figure 5 It means Figure 3 A cross-sectional view of the components of a FEU. For example... Figure 5 As shown, a cold plate 320 is placed between two pin electronics PCBs 310a and 310b. Similarly, a cold plate 320 is also placed between two pin electronics PCBs 310c and 310d. As described above, the pin electronics IC 400 is mounted on the pin electronics PCB 310 at a location close to the socket board 210. To improve cooling efficiency, the pin electronics IC 400 can be a bare chip, and the pin electronics IC 400 and the cold plate 320 are thermally coupled via a thermal interface material (TIM) 322.

[0069] In addition, when viewing the FEU from above along the Y-axis, the center of the DUT, namely the socket 212A, is located at the center of the four (M) pin electronic PCBs 310a to 310d stacked along the X-direction.

[0070] The above is the structure of FEU.

[0071] The advantages of this FEU are explained. Focusing on DUT1A marked with annotation A, multiple (eight in this example) pin-type electronic ICs 400A corresponding to one DUT1A are mounted in pairs on four pin-type electronic PCBs 310a-310d. This allows the distance from each of the eight pin-type electronic ICs 400A to the socket 212A to be uniform. Consequently, the transmission line loss from each pin-type electronic IC 400A to the socket 212A (DUT1A) is uniformized, enabling accurate testing.

[0072] Next, the electrical connection between the pin electronics IC400 and the socket 212 will be explained.

[0073] Figure 6 This is a cross-sectional view showing an example of the connection between the pin electronics IC and the socket (DUT1). The transmission path for test signals and device signals, i.e., the wiring 220 between the pin electronics PCB310 and the socket board 210, uses FPC cable 222.

[0074] If a coaxial cable is used as the wiring 220 between the pin electronics PCB 310 and the socket board 210, the minimum distance between them is limited due to the rigidity of the coaxial cable. In contrast, by using an FPC cable 222, the distance h between the pin electronics PCB 310 and the socket board 210 can be shortened compared to using a coaxial cable due to its flexibility, thus reducing the transmission distance of test signals and device signals.

[0075] In conventional testing setups, LIF (Low Insulation Force) connectors were typically used when it was desired to make the socket board 210 removable. These LIF connectors exhibit a non-negligible loss of approximately -3dB in frequency bands higher than 14GHz, which can cause waveform distortion at high-speed transmissions of 28Gbps or 40Gbps. By using FPC cable 222 via wiring 220 without requiring LIF connectors, waveform distortion caused by losses (attenuation in high-frequency bands) can be suppressed, enabling accurate testing.

[0076] More specifically, the socket board 210 includes a socket 212 and a socket PCB 214. The socket PCB 214 is a multilayer substrate including a wiring layer and an insulating layer. Wiring is formed in the wiring layer to allow signal paths to move horizontally, and vias VH are formed in the insulating layer to allow signal paths to move vertically. Test signals and device signals are preferably led out to the back of the socket board 210 as horizontally as possible (X and Y directions) without shifting. Conversely, power signals and low-frequency control signals can move horizontally throughout the interior of the socket PCB 214.

[0077] FPC cable 222 is connected to socket board 210 by socket board side connector 216. Socket board side connector 216 includes interposer 218 and cable clip 219.

[0078] Intermediate layer 218 and socket PCB 214 are detachable. The electrodes exposed on the surface of intermediate layer 218 are electrically connected to the electrodes exposed on the back of socket PCB 214. FPC cable 222 is clamped in by cable clip 219 in contact with the back electrode of intermediate layer 218.

[0079] Figure 7 This is a cross-sectional view of the socket board 210 according to the embodiment. A socket 212 is provided on the first side of the socket PCB 214 of the socket board 210, which is connected to the DUT. The second side of the socket board 210 is connected to the interposer layer 218 so that it can be detached.

[0080] Additionally, a surface mount device (SMD) 213 is mounted on the second side of the socket board 210. Examples of SMD 213 include chip capacitors, chip resistors, and chip inductors. Multiple first pads P1 for mounting the SMD 213 are formed on the second side of the socket PCB 214.

[0081] Additionally, a plurality of second pads P2 are formed on the second side of the socket PCB214 to serve as electrical contacts with the interposer layer 218. The second pads P2 are electrically connected to the corresponding contacts (pins) P3 of the interposer layer 218.

[0082] The first pad P1 has a thickness t1, and the second pad P2 has a thickness t2. The thicknesses t1 and t2 of the two pads P1 and P2 are different (t1 ≠ t2). Specifically, the relationship t2 > t1 holds true.

[0083] Preferably, the thickness t2 of the second pad P2 is more than twice the thickness t1 of the first pad P1. More preferably, the thickness t2 of the second pad P2 is more than five times the thickness t1 of the first pad P1. Even more preferably, the thickness t2 of the second pad P2 is more than eight times the thickness t1 of the first pad P1.

[0084] For example, the thickness t1 of the first pad P1 is 0.03 micrometers with a dimensional tolerance of ±30%. In contrast, the thickness t2 of the second pad P2 is 0.5 micrometers with a dimensional tolerance of ±30%. In this case, the thickness t2 of the second pad P2 is 16 times the thickness t1 of the first pad P1.

[0085] According to the socket board 210, the first pad P1 for component mounting and the second pad P2, which becomes the electrical contact with the interposer layer 218, have different thicknesses. As a result, the peel strength of the SMD 213 can be improved, the wear resistance of the electrical contact with the interposer layer 218 can be improved, and the long-term reliability can be improved.

[0086] Figure 8 This diagram shows the layout of multiple second pads P2 on the second side of the socket PCB 214. Multiple pins arranged in a matrix are provided on the surface of the interposer layer 218. Figure 7 P3), and corresponding to multiple pins P3, multiple second pads P2 are arranged in a matrix on the second side of the socket PCB214.

[0087] Multiple second pads P2 are alternately assigned signal pins SIG and ground pins GND in the row direction (top and bottom) and column direction (left and right). In other words, each signal pin SIG is assigned such that it is adjacent to the ground pin GND along both the row and column directions, and adjacent to each other along the diagonal direction. Furthermore, this can be understood as a structure where the two rows and two columns of second pins SIG are considered the smallest unit PU, and this smallest unit PU is arranged along the row and column directions. The smallest unit PU contains two diagonally arranged signal pins SIG and two diagonally arranged ground pins GND.

[0088] The above is the layout of the second pad P2 in the socket PCB214. Compared with the layout where the signal pins are completely surrounded by the ground pins in the row, column, and diagonal directions, this layout can increase the density of signal pins and reduce the area of ​​the socket printed circuit board.

[0089] Figure 9 This is a modified example of the layout of multiple second pads P2 on the second side of the socket PCB214. In this modified example, the ground pins GND in the multiple second pads P2 are formed continuously to each other.

[0090] According to this variation, the impedance of the ground pin GND can be reduced.

[0091] Next, the layout of the DUT and signals in the socket board will be explained.

[0092] Figure 10 This is a perspective view showing the layout of the socket board 210 according to the embodiment. Figure 11 This is a top view showing the layout of the socket panel 210 according to the embodiment.

[0093] The socket board 210 includes a socket PCB 214 and N socket guides (referred to as sockets) 212_1 to 212_N. In this example, N = 2.

[0094] N sockets 212_1 to 212_N are arranged on the first side (top surface in the figure) of socket PCB214.

[0095] On the second side (lower surface in the figure) of the socket PCB214, multiple pads P2 are formed, divided into a first region RGN1 and a second region RGN2. The multiple pads P2 become electrical contacts with the interposer layer 218.

[0096] The first region RNG1 and the second region RGN2 are rectangles with the same shape and size, with the first direction (y) as the longer side, and are separated from each other along the second direction (x).

[0097] N sockets 212_1 to 212_N are respectively located in the third region RNG3, which is sandwiched between the first region RGN1 and the second region RNG2 in the x direction, and are arranged adjacently in the y direction.

[0098] Each socket 212_1 to 212_N is electrically connected to a portion of the plurality of pads P2 contained in the first region RGN1 and a portion of the plurality of pads P2 contained in the second region RNG2. Each pin of socket 212 and its corresponding pad P2 are connected to wiring provided on socket PCB 214 via through-holes.

[0099] One socket 212_1 is positioned between y0 and y1 in the y direction, and the other socket 212_2 is positioned between y1 and y2 in the y direction. y0 is the coordinate of one end of the rectangular regions RGN1 and RGN2, y2 is the coordinate of the other end of the regions RGN1 and RGN2, and y1 is the coordinate of the center.

[0100] exist Figure 11 In the layout, Pa represents the farthest pad among the pads connected to socket 212_1, and Pb represents the nearest pad among the pads connected to socket 212_1.

[0101] The above describes the layout of the socket panel 210. The advantages of this socket panel 210 become clear through comparison with comparative technologies.

[0102] Figure 12 This is a top view showing the layout of the socket panel 210R of the comparative technology.

[0103] In this comparative technique, one socket 212_1 is connected to the pad P2 contained in the first region RNG1, and the other socket 212_2 is connected to the pad P2 contained in the second region RNG2.

[0104] exist Figure 12 In the layout, Pc represents the farthest pad among the pads connected to socket 212_1, and Pd represents the nearest pad among the pads connected to socket 212_1.

[0105] Will Figure 11 (Implementation Method) and Figure 12 (Comparative techniques) show that, Figure 11 (Implementation Method) The length of the wiring connecting the socket to the farthest pad can be shortened. As a result, parasitic impedance is reduced, thus widening the bandwidth and enabling the testing of higher speed signals.

[0106] Will Figure 11 (Implementation Method) and Figure 12 When making comparisons using (comparative techniques) Figure 11 In the (implementation method), the difference between the distance Pa to the farthest pad and the distance Pb to the nearest pad is less than [the required value]. Figure 12 The difference between the distance Pc to the farthest pad and the distance Pd to the nearest pad in the (comparative technique). That is, according to the implementation, the wiring length of up to multiple pins P2 can be made more uniform compared to the comparative technique.

[0107] Figure 13 This is a top view showing the layout of a modified socket panel 210. In this modified example, the number N of sockets 212 is 4. In this layout, regarding the two central sockets 212_2 and 212_3, in the y-direction, the range y0 to y2 of the rectangular regions RGN1 and RGN2 converge. Therefore, it is possible to enjoy the same... Figure 10 The layout has the same advantages.

[0108] Next, we will explain the management of the socket board.

[0109] Figure 14 This diagram illustrates a socket board 210A according to one embodiment. In addition to the socket PCB 214 and socket 212, the socket board 210A also includes a non-volatile memory 240. The non-volatile memory 240 can be read from the tester body. The non-volatile memory 240 is either an EEPROM (Electrically Erasable Programmable Read-Only Memory) or a flash memory.

[0110] The non-volatile memory 240 can be configured at a location along the outer periphery of the socket PCB 214, such as any of the four corners. A ground pattern 242 is formed along the outer periphery of the socket PCB 214, and the non-volatile memory 240 can be configured adjacent to the ground pattern 242.

[0111] Typically, multiple (e.g., 16) socket boards are connected by a mechanical component called a socket frame, forming a unit. This unit is sometimes referred to as a DSA or device board. Traditionally, each DSA was equipped with non-volatile memory, storing its inherent information.

[0112] The inventors, through research on previous DSA (Digital Subtraction Angiography) methods, independently recognized the following issues. In conventional ATE (Automatic Equipment) systems that process relatively low-speed signals, individual variations in the socket board were negligible or not a significant problem. However, in high-speed testing of memory, specifically exceeding 20Gbps, individual variations in the socket board cannot be ignored.

[0113] Therefore, in this embodiment, a non-volatile memory 240 is provided for each socket board 210A, and inherent information for each socket board 210 can be stored in the non-volatile memory 240. For example, the following information can be pre-stored in the non-volatile memory 240.

[0114] (i) Information related to socket 212 set on socket board 210A. Specifically, this may include the location of the socket board, pin configuration, etc. The tester body reads this information from socket board 210A and transmits it to the processor. As a result, the processor can place the DUT in the correct position on socket board 210A.

[0115] Furthermore, the precision of mechanical components changes due to temperature variations and the effects of time. By comparing the actual location of the processor placed in the DUT, i.e., the actual location of the socket, with the location information of the socket 212 stored in the non-volatile memory 240, the user of ATE100 can observe how the actual location of the socket 212 has shifted due to time-related or temperature changes.

[0116] (ii) Manufacturing serial number and management serial number of socket board 210A

[0117] (iii) It can manage information about the processor's contact with the socket board on a per-socket basis, such as the number of contacts and the depth of contact.

[0118] The above describes the structure of the socket board 210A. Based on this socket board 210A, various types of information can be managed at the socket board level, rather than at the DSA level. Therefore, testing applications that take into account individual differences in the socket board are possible, enabling accurate testing of high-speed memory devices exceeding 20Gbps. It should be noted that the system of this embodiment is also applicable to the inspection of memory devices with frequency bands lower than 20Gbps and other DUTs.

[0119] The interface device 200 can take many forms, but the present invention can be applied to any form.

[0120] • SBC (Socket Board Change) type

[0121] The SBC type is an interface device that replaces the socket board 210 type according to the type of DUT.

[0122] • CLS (Cable Less) type

[0123] The CLS type is an interface device 200 that can be separated into an upper DSA (Device Specific Adapter) and a lower motherboard, and the type of DSA can be replaced according to the type of DUT. When applying the interface device 200 of this embodiment to the CLS type, two methods can be considered.

[0124] One approach is to configure the front-end module 300 on the motherboard side. In this case, the front-end module 300 can be shared in tests of different DUTs, which is advantageous from a cost perspective.

[0125] Another approach is to configure the front-end module 300 on the DSA side. In this case, the front-end module 300 is set up for each DSA, thus increasing the cost of the device. On the other hand, since the front-end module 300 can be placed close to the DUT, it is advantageous from the viewpoint of high-speed testing.

[0126] • CCN (Cable Connection) type

[0127] The CCN type is an interface device in which the entire interface device 200 is replaced according to the type of DUT. If the interface device 200 of this embodiment is applied to the CCN type, the front-end module 300 can be brought closer to the limit of the DUT, which is advantageous from the point of view of high-speed testing.

[0128] • Wafer motherboard

[0129] The interface device 200 can be a wafer motherboard used in wafer-level testing. In this case, the interface device 200 can have a probe card instead of a socket board.

[0130] The above-described embodiments are illustrative, and it will be self-evident to those skilled in the art that the combination of the above-described components and processing techniques may include various modifications. Such modifications will be described below.

[0131] (Variation Example 1)

[0132] In one embodiment, the pin electronics IC 400 electrically connects the FPC to the printed circuit board using an interposer, but the present invention is not limited thereto. Wiring 220 may be used instead of the FPC cable 222, and may be other wiring methods such as the printed circuit board.

[0133] (Variation Example 2)

[0134] In this embodiment, an interface device 200 with the socket plate 210 parallel to the ground is described, but the invention is not limited thereto. For example, the socket plate 210 may be perpendicular to the ground. In this case, Figure 4 , Figure 5 In equations, the Y-direction becomes the direction of gravity.

[0135] While specific terminology has been used to describe embodiments of the present invention, this description is merely illustrative and does not limit the invention or the claims. The scope of the invention is defined by the claims; therefore, embodiments, examples, and modifications not described herein are also included within the scope of the invention.

Claims

1. A socket board, characterized in that, have: Socket printed circuit board; A socket guide, disposed on the socket printed circuit board; and A non-volatile memory, disposed on the printed circuit board of the socket, is capable of storing information related to the socket board.

2. The socket board according to claim 1, characterized in that, The non-volatile memory is positioned along the outer periphery of the socket printed circuit board.

3. The socket board according to claim 1, characterized in that, The non-volatile memory is disposed at any one of the four corners of the socket printed circuit board.

4. An automatic testing device, characterized in that, A socket board comprising any one of claims 1 to 3.

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