Instruction obtaining method, processor and storage medium

Abstract

The application provides an instruction obtaining method, a processor and a storage medium. The method comprises the following steps: obtaining an instruction fetch request of an IFU; in the case that an I-cache is in an off state, comparing an instruction address of the instruction fetch request with an extended address space of an ILM to obtain a first comparison result, the extended address space being mapped to a first storage space of the ILM and a second storage space of the I-cache; according to the first comparison result, obtaining a target instruction corresponding to the instruction fetch request in the first storage space, the second storage space or an external storage unit; and returning the target instruction to the IFU. Based on the application scheme, the storage space of the I-cache can be fully utilized to improve the instruction storage capacity of the ILM without increasing the hardware resource overhead, so that the efficient instruction fetch requirement of the processor can be met.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to an instruction fetching method, a processor, and a storage medium. Background Technology

[0002] In related technologies, some processors include Instruction Local Memory (ILM) as their instruction storage unit. ILM has advantages such as fast access speed and strong real-time performance, and is often used to store critical instructions. However, due to the limited storage space of ILM, the amount of instructions stored in ILM is relatively low, making it difficult to meet the processor's high-efficiency instruction fetching requirements. Summary of the Invention

[0003] This application provides an instruction fetching method, a processor, and a storage medium.

[0004] A first aspect of this application provides an instruction fetching method applied to a processor, the processor including an instruction fetch unit (IFU), an instruction local memory (ILM), and an instruction cache (I-Cache), and the processor is connected to external memory units; the method includes:

[0005] Obtain the instruction fetch request for the IFU;

[0006] When the I-Cache is off, the instruction address of the instruction fetch request is compared with the extended address space of the ILM to obtain the first comparison result. The extended address space is mapped to the first storage space of the ILM and the second storage space of the I-Cache.

[0007] Based on the first comparison result, the target instruction corresponding to the instruction fetch request is obtained from the first storage space, the second storage space, or the external storage unit.

[0008] Return the target instruction to the IFU.

[0009] In an optional embodiment of this application, obtaining the target instruction corresponding to the instruction fetch request from the first storage space, the second storage space, or the external storage unit according to the first comparison result includes: if the first comparison result indicates that the instruction address is in the extended address space, then obtaining the target instruction corresponding to the instruction fetch request from the first storage space or the second storage space; if the first comparison result indicates that the instruction address is outside the extended address space, then obtaining the target instruction corresponding to the instruction fetch request from the external storage unit.

[0010] In an optional embodiment of this application, if the first comparison result indicates that the instruction address is in the extended address space, then the target instruction corresponding to the instruction fetch request is obtained from the first storage space or the second storage space, including: if the first comparison result indicates that the instruction address is in the intrinsic address space of the ILM in the extended address space, then the target instruction corresponding to the instruction fetch request is obtained from the first storage space, and there is a mapping relationship between the intrinsic address space and the first storage space; if the first comparison result indicates that the instruction address is in the reused address space of the I-Cache in the extended address space, then the target instruction corresponding to the instruction fetch request is obtained from the second storage space, and there is a mapping relationship between the reused address space and the second storage space.

[0011] In an optional embodiment of this application, before obtaining the instruction fetch request of the IFU, the method further includes: configuring the I-Cache to a disabled state when the processor meets preset conditions; determining a first storage space from the ILM and determining the address space corresponding to the first storage space as the intrinsic address space of the ILM; determining a second storage space from the I-Cache and determining the address space corresponding to the second storage space as the reused address space of the I-Cache; and integrating the intrinsic address space and the reused address space into the extended address space of the ILM.

[0012] In an optional embodiment of this application, the method further includes: determining that the processor meets a preset first condition within a preset time range after the processor is powered on; or, determining that the processor meets a preset second condition when the processor enters a real-time response mode; wherein the preset first condition and the preset second condition are both preset conditions, and the processor disables the instruction caching mechanism of the I-Cache in the real-time response mode.

[0013] In an optional embodiment of this application, after obtaining the instruction fetch request from the IFU, the method further includes: when the I-Cache is enabled, comparing the instruction address of the instruction fetch request with the intrinsic address space of the ILM to obtain a second comparison result, wherein the intrinsic address space is mapped to the first storage space of the ILM; obtaining the target instruction corresponding to the instruction fetch request from the first storage space, the second storage space of the I-Cache, or an external storage unit according to the second comparison result; and returning the target instruction to the IFU.

[0014] In an optional embodiment of this application, retrieving the target instruction corresponding to the instruction fetch request from the first storage space, the second storage space of the I-Cache, or an external storage unit based on the second comparison result includes: if the second comparison result indicates that the instruction address is within the inherent address space, then retrieving the target instruction corresponding to the instruction fetch request from the first storage space; if the second comparison result indicates that the instruction address is outside the inherent address space, then determining the cache hit result of the instruction address according to the instruction caching mechanism of the I-Cache, wherein the cache hit result indicates that the instruction address hits the second storage space of the I-Cache or does not hit the second storage space; and retrieving the target instruction corresponding to the instruction fetch request from the second storage space or an external storage unit based on the cache hit result.

[0015] In an optional embodiment of this application, obtaining the target instruction corresponding to the instruction fetch request from the second storage space or the external storage unit according to the cache hit result includes: if the cache hit result indicates that the instruction address hits the second storage space, then obtaining the target instruction corresponding to the instruction fetch request from the second storage space; if the cache hit result indicates that the instruction address does not hit the second storage space, then obtaining the target instruction corresponding to the instruction fetch request from the external storage unit.

[0016] A second aspect of this application provides a processor, which includes an instruction fetch unit (IFU), an instruction local memory (ILM), and an instruction cache (I-Cache), and is connected to an external memory unit; the processor is configured to perform the steps of the method described in any of the above claims.

[0017] A third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the steps of the method as described in any of the above. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 A schematic diagram illustrating an example of instruction acquisition provided in one embodiment of this application;

[0020] Figure 2 A flowchart illustrating an instruction acquisition method provided in one embodiment of this application;

[0021] Figure 3 A schematic diagram illustrating an example of instruction acquisition provided in one embodiment of this application;

[0022] Figure 4A flowchart for obtaining a target instruction based on a first comparison result is provided as an embodiment of this application;

[0023] Figure 5 A flowchart for obtaining a target instruction based on a first comparison result is provided as an embodiment of this application;

[0024] Figure 6 A flowchart for determining the extended address space of the ILM provided in one embodiment of this application;

[0025] Figure 7 A flowchart illustrating the process of retrieving a target instruction when the I-Cache is enabled, as provided in one embodiment of this application;

[0026] Figure 8 This is a flowchart illustrating the process of obtaining a target instruction based on a second comparison result, provided as an embodiment of this application. Detailed Implementation

[0027] The technical solutions in this application will be clearly and thoroughly described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. "And / or" in the text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0028] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0029] Please see Figure 1 , Figure 1 This is an example diagram illustrating instruction acquisition provided in one embodiment of this application. Figure 1 The processor shown includes an Instruction Fetch Unit (IFU), an Instruction Memory Module (ILM), an Instruction Cache (I-Cache), and a Bus Control Unit. The ILM and I-Cache constitute the processor's instruction storage unit. Furthermore, the processor is connected to external memory to jointly complete instruction fetching and execution.

[0030] The Instruction Unit (IFU) is responsible for fetching instructions from memory and passing them to the processor's execution unit, serving as the starting point of the processor's instruction pipeline. The Instruction Memory Unit (ILM) is a high-speed local memory unit, typically constructed from Static Random-Access Memory (SRAM), used to store critical instructions, offering advantages such as fast access speed and strong real-time performance. The I-Cache implements its function based on an instruction caching mechanism, dynamically mapping instructions from external memory units to the processor's limited internal memory space to reduce latency when accessing external memory units. It should be noted that the I-Cache may also be constructed based on SRAM. External memory units are typically implemented using Dynamic Random-Access Memory (DRAM) or Flash Memory, offering larger capacity but slower access speeds, primarily used to store large amounts of program instructions and data. The bus control unit is responsible for data transmission between the IFU, ILM, I-Cache, and external memory units, ensuring the correct delivery of instructions and data. Figure 1 As shown, the ILM is connected to the bus control unit through the ILM interface, and the I-Cache is connected to the bus control unit through the I-Cache interface. The address space of the ILM and the address space of the I-Cache are mapped to the storage areas of the ILM and I-Cache, respectively.

[0031] In some possible instruction fetching methods, the processor issues an instruction fetch request via the IFU (Instruction Request Unit). The bus control unit determines the instruction's storage location based on the fetch address in the request. If the fetch address falls within the ILM (Instruction Library) address space, the instruction is fetched directly from the ILM; otherwise, the processor attempts to fetch the instruction from the I-Cache. If the I-Cache is hit, the instruction is retrieved from the I-Cache; if the I-Cache is missed, the instruction needs to be fetched from external memory.

[0032] While this instruction fetching method can meet the processor's needs to some extent, it has significant limitations in practical applications. First, the In-Memory Memory (ILM), due to its high-speed access and real-time performance, is used to store critical program instructions. However, the ILM implementation relies on SRAM technology, and the high cost of SRAM limits the ILM's storage capacity. Furthermore, the ILM typically requires pre-programming some power-on programs or other critical instructions, further consuming its limited storage space and further restricting its instruction storage capacity. Second, the I-Cache dynamically maps instructions from external memory to the processor's internal memory through a caching mechanism. While this can reduce access latency to some extent, its cache hit rate is limited by the cache capacity, and when a cache miss occurs, instructions must be fetched from external memory, resulting in additional latency. Finally, although external memory has a larger capacity, its access speed is far lower than that of the ILM and I-Cache, failing to meet the processor's demand for efficient instruction fetching, especially in scenarios with high real-time requirements, where this fetching method struggles to guarantee the processor's response speed.

[0033] In summary, existing instruction fetching methods, given the limited ILM storage capacity, the uncertainties of the I-Cache mechanism, and the slow access speed of external memory units, struggle to meet the processor's demand for efficient instruction fetching. Therefore, improving the processor's instruction storage capacity and fetching efficiency under limited hardware resources has become a pressing issue in current processor design.

[0034] To address the aforementioned issues, the solution provided in this application mainly includes: when the I-Cache is disabled, comparing the instruction address of the instruction fetch request with the extended address space of the ILM to obtain a first comparison result, wherein the extended address space is mapped to the first storage space of the ILM and the second storage space of the I-Cache. Then, based on the first comparison result, the target instruction corresponding to the instruction fetch request is retrieved from the first storage space, the second storage space, or an external storage unit, and the target instruction is returned to the IFU. This achieves reuse of the I-Cache storage space, effectively expanding the storage capacity of the ILM. Based on the first comparison result, the processor may directly retrieve the target instruction from the first storage space of the ILM or the second storage space of the I-Cache, avoiding the high latency of accessing external storage units; based on the first comparison result, the processor may also retrieve the target instruction from an external storage unit, ensuring the integrity of instruction fetching and the normal operation of the system. The solution provided in this application fully utilizes the storage space of the I-Cache without increasing hardware resource overhead, improving the instruction storage capacity of the ILM, thereby meeting the processor's high-efficiency instruction fetching requirements.

[0035] based on Figure 1The scene shown below is an illustration; the following will combine... Figure 2 - Figure 8 The method for obtaining instructions provided in the embodiments of this application will be described in detail.

[0036] Please see Figure 2 , Figure 2 This is a flowchart illustrating an instruction fetching method according to an embodiment of this application. The processor includes an IFU, an ILM, and an I-Cache, and is connected to an external memory unit; as shown... Figure 2 As shown, the method in this application embodiment may include the following steps S101-S103.

[0037] S101, Obtain the instruction fetch request for IFU.

[0038] Specifically, the IFU involved in this embodiment is the starting point of the processor instruction pipeline, which is responsible for fetching instructions from the memory unit and passing them to the processor's execution unit;

[0039] An instruction fetch request (IFU) refers to a request signal issued by the instruction fetch unit to retrieve a target instruction. This request includes the instruction address and related control information. The instruction address refers to the physical or logical address of the target instruction to be fetched, used to identify the specific location of the target instruction in the instruction memory or external memory.

[0040] In some possible implementations, the processor includes a bus control unit, and the instruction fetch request to obtain the IFU is manifested as follows: the instruction fetch unit generates an instruction fetch request according to the processor's instruction pipeline requirements, and sends the instruction fetch request to the memory unit through the bus control unit. The bus control unit triggers subsequent instruction fetch operations according to the instruction address in the instruction fetch request.

[0041] S102, when the I-Cache is in the off state, the instruction address of the instruction fetch request is compared with the extended address space of the ILM to obtain the first comparison result, and the extended address space is mapped to the first storage space of the ILM and the second storage space of the I-Cache.

[0042] Specifically, in this embodiment, the I-Cache being in a disabled state means that the instruction caching mechanism is disabled, and the processor no longer obtains instructions through the instruction caching mechanism, but directly obtains instructions through the ILM or external storage units; however, the second storage space of the I-Cache is still available, because the second storage space of the I-Cache is not completely disabled in hardware, but is reused as part of the extended storage space of the ILM through address mapping.

[0043] The extended address space of the ILM includes the ILM's intrinsic address space and the I-Cache's reused address space. The ILM's intrinsic address space is mapped to the ILM's first storage space, and the I-Cache's reused address space is mapped to the I-Cache's second storage space. It should be noted that the ILM's first storage space may be the entire ILM's storage space or only a portion of it; similarly, the I-Cache's second storage space may be the entire I-Cache's storage space or only a portion of it.

[0044] In some possible implementations, the step of comparing the instruction address of the instruction fetch request with the extended address space of the ILM is as follows: the bus control unit receives the instruction address of the instruction fetch request, compares the instruction address with the address range of the extended address space of the ILM, and determines whether the instruction address is located in the extended address space, and specifically whether it is located in the part of the extended address space corresponding to the ILM or the part corresponding to the I-Cache.

[0045] S103, based on the first comparison result, obtain the target instruction corresponding to the instruction fetch request from the first storage space, the second storage space, or the external storage unit;

[0046] S104, return the target instruction to the IFU.

[0047] Specifically, the first comparison result in this embodiment is used to indicate whether the instruction address is located within the extended address space, and specifically within which part of the extended address space. The extended address space includes the intrinsic address space of the ILM and the reused address space of the I-Cache.

[0048] In some possible implementations, the step of retrieving the target instruction corresponding to the instruction fetch request from the first storage space, the second storage space, or an external storage unit based on the first comparison result is as follows: If the first comparison result indicates that the instruction address of the instruction fetch request is within the extended address space of the ILM, then it is further determined which part of the extended address space the instruction address is located in. If the instruction address is within the intrinsic address space of the ILM, then the target instruction corresponding to the instruction fetch request is retrieved from the first storage space of the ILM; if the instruction address is within the multiplexed address space of the I-Cache, then the target instruction corresponding to the instruction fetch request is retrieved from the second storage space of the I-Cache. If the first comparison result indicates that the instruction address of the instruction fetch request is outside the extended address space of the ILM, then the target instruction corresponding to the instruction fetch request is retrieved from an external storage unit. After retrieving the target instruction, the target instruction is returned to the IFU.

[0049] In some possible implementations, the step of retrieving the target instruction from the first memory space of the ILM is as follows: the bus control unit accesses the memory location corresponding to the instruction address in the first memory space of the ILM according to the instruction address of the instruction fetch request, reads the target instruction, and returns the target instruction to the IFU.

[0050] In some possible implementations, the step of retrieving the target instruction from the second storage space of the I-Cache is as follows: the bus control unit accesses the storage location corresponding to the instruction address in the second storage space of the I-Cache according to the instruction address of the instruction fetch request, reads the target instruction, and returns the target instruction to the IFU.

[0051] In some possible implementations, the steps for retrieving the target instruction from the external storage unit are as follows: the bus control unit accesses the storage location corresponding to the instruction address in the external storage unit through the external bus according to the instruction address of the instruction fetch request, reads the target instruction, and returns the target instruction to the IFU.

[0052] For example, such as Figure 3As shown, the IFU is connected to the bus control unit via a bus. The bus control unit is connected to the ILM and I-Cache via the ILM interface and I-Cache interface, respectively. The IFU, as the starting point of the processor instruction pipeline, is responsible for generating instruction fetch requests and sending them to the bus control unit via the bus. The bus control unit, based on the instruction address in the fetch request and in conjunction with the I-Cache enable signal and address selection logic, determines whether the instruction address is located in the ILM address space or the I-Cache address space. If the I-Cache enable signal indicates that the I-Cache is disabled, the bus control unit compares the instruction address in the fetch request with the ILM's extended address space, which includes the ILM's intrinsic address space and the I-Cache's multiplexed address space. If the instruction address is within the ILM's intrinsic address space, the bus control unit accesses the ILM's first memory space through the ILM interface, retrieves the target instruction, and returns to the IFU. If the instruction address is within the I-Cache's multiplexed address space, the bus control unit accesses the I-Cache's second memory space through the I-Cache interface, retrieves the target instruction, and returns to the IFU. If the instruction address is outside the extended address space, the bus control unit accesses the external memory unit through the external bus, retrieves the target instruction, and returns to the IFU. If the I-Cache enable signal indicates that the I-Cache is enabled, the bus control unit first determines whether the instruction address hits the I-Cache's address space. If it does, it accesses the I-Cache's second memory space through the I-Cache interface, retrieves the target instruction, and returns to the IFU. If it does not hit, it further determines whether the instruction address is within the ILM's address space. If it is within the ILM's address space, it accesses the ILM's first memory space through the ILM interface, retrieves the target instruction, and returns to the IFU. If it is outside the ILM's address space, it accesses the external memory unit through the external bus, retrieves the target instruction, and returns to the IFU.

[0053] In this embodiment, when the I-Cache is disabled, the instruction address of the instruction fetch request is compared with the extended address space of the ILM to obtain a first comparison result, wherein the extended address space is mapped to the first storage space of the ILM and the second storage space of the I-Cache. Then, based on the first comparison result, the target instruction corresponding to the instruction fetch request is retrieved from the first storage space, the second storage space, or an external storage unit, and the target instruction is returned to the IFU. In this way, the I-Cache storage space is reused, effectively expanding the storage capacity of the ILM. Based on the first comparison result, the processor may directly retrieve the target instruction from the first storage space of the ILM or the second storage space of the I-Cache, avoiding the high latency of accessing external storage units; based on the first comparison result, the processor may also retrieve the target instruction from an external storage unit, ensuring the integrity of instruction fetching and the normal operation of the system. The solution provided by this application embodiment makes full use of the I-Cache storage space and improves the instruction storage capacity of the ILM without increasing hardware resource overhead, thereby meeting the processor's high-efficiency instruction fetching requirements.

[0054] Please see Figure 4 This is a flowchart illustrating a process for obtaining a target instruction based on a first comparison result, as provided in one embodiment of this application. Figure 4 As shown, the method in this embodiment may include the following steps S201-S202, and steps S201-S202 may be used as a method for... Figure 2 The detailed steps of step S103 in the illustrated embodiment.

[0055] S201, if the first comparison result indicates that the instruction address is in the extended address space, then the target instruction corresponding to the instruction fetch request is obtained from the first memory space or the second memory space;

[0056] S202, if the first comparison result indicates that the instruction address is outside the extended address space, then the target instruction corresponding to the instruction fetch request is obtained from the external memory unit.

[0057] Specifically, the first comparison result in this embodiment is used to indicate whether the instruction address of the instruction fetch request is located within the extended address space, and specifically in which part of the extended address space. The extended address space includes the intrinsic address space of the instruction ILM and the reused address space of the I-Cache. The intrinsic address space of the ILM is mapped to the first storage space of the ILM, and the reused address space of the I-Cache is mapped to the second storage space of the I-Cache. It should be noted that the first storage space of the ILM may be the entire storage space of the ILM or a portion thereof; similarly, the second storage space of the I-Cache may be the entire storage space of the I-Cache or a portion thereof.

[0058] In some possible implementations, step S201 is specifically implemented as follows: If the first comparison result indicates that the instruction address of the instruction fetch request is in the extended address space, then it is further determined which part of the extended address space the instruction address is located in. If the instruction address is located in the intrinsic address space of the ILM, then the target instruction corresponding to the instruction fetch request is obtained from the first storage space of the ILM; if the instruction address is located in the multiplexed address space of the I-Cache, then the target instruction corresponding to the instruction fetch request is obtained from the second storage space of the I-Cache. Specifically, the step of obtaining the target instruction from the first storage space of the ILM is as follows: the bus control unit accesses the storage location corresponding to the instruction address in the first storage space of the ILM according to the instruction address of the instruction fetch request, and reads the target instruction. The step of obtaining the target instruction from the second storage space of the I-Cache is as follows: the bus control unit accesses the storage location corresponding to the instruction address in the second storage space of the I-Cache according to the instruction address of the instruction fetch request, and reads the target instruction.

[0059] In some possible implementations, if the first comparison result indicates that the instruction address of the instruction fetch request is outside the extended address space, then the target instruction corresponding to the instruction fetch request is retrieved from the external memory unit. Specifically, the step of retrieving the target instruction from the external memory unit involves the bus control unit accessing the storage location corresponding to the instruction address in the external memory unit via the external bus, based on the instruction address of the instruction fetch request, and reading the target instruction.

[0060] For example, assume the processor's first ILM storage space is Storage_ILM, the second I-Cache storage space is Storage_ICache, the external storage unit is Storage_External, and the extended address space is AddressSpace_Extended, where AddressSpace_Extended includes the ILM's intrinsic address space AddressSpace_ILM and the I-Cache's shared address space AddressSpace_ICache. The processor retrieves an instruction fetch request (IFU) with the instruction address Address_X. If the I-Cache is disabled, Address_X is compared with AddressSpace_Extended. If Address_X is within AddressSpace_ILM, the target instruction is fetched from Storage_ILM; if Address_X is within AddressSpace_ICache, the target instruction is fetched from Storage_ICache; if Address_X is outside AddressSpace_Extended, the target instruction is fetched from Storage_External. For example, if Address_X = Address_ILM1 (Address_ILM1 is an address of AddressSpace_ILM), the target instruction is retrieved from Storage_ILM; if Address_X = Address_ICache1 (Address_ICache1 is an address of AddressSpace_ICache), the target instruction is retrieved from Storage_ICache; if Address_X = Address_External1 (Address_External1 is an address other than AddressSpace_Extended), the target instruction is retrieved from Storage_External.

[0061] In this embodiment, the first comparison result determines whether the instruction address of the instruction fetch request is located within the extended address space. Based on the determination result, the target instruction is retrieved from the first storage space of the ILM, the second storage space of the I-Cache, or an external storage unit. If the instruction address is located within the extended address space, the target instruction is directly retrieved from the first storage space of the ILM or the second storage space of the I-Cache, avoiding the high latency of accessing external storage units. If the instruction address is located outside the extended address space, the target instruction is retrieved from an external storage unit, ensuring the integrity of instruction fetching and the normal operation of the system. Through the above method, this embodiment realizes the reuse of the I-Cache storage space, effectively expanding the storage capacity of the ILM, thereby improving the processor's instruction storage capability and instruction fetching efficiency without increasing hardware resource overhead.

[0062] Please see Figure 5 This is a flowchart illustrating a process for obtaining a target instruction based on a first comparison result, as provided in one embodiment of this application. Figure 5 As shown, the method in this embodiment may include the following steps S301-S302, and steps S301-S302 may be used as a method for... Figure 4 The detailed steps of step S201 in the illustrated embodiment.

[0063] S301, if the first comparison result indicates that the instruction address is in the intrinsic address space of the ILM in the extended address space, then the target instruction corresponding to the instruction fetch request is obtained from the first memory space, and there is a mapping relationship between the intrinsic address space and the first memory space;

[0064] S302, if the first comparison result indicates that the instruction address is in the reused address space of the I-Cache in the extended address space, then the target instruction corresponding to the instruction fetch request is obtained from the second storage space, and there is a mapping relationship between the reused address space and the second storage space.

[0065] Specifically, in this embodiment, the intrinsic address space of the ILM refers to the address range directly mapped to the first storage space of the ILM, used to identify storage locations within the first storage space of the ILM. The reused address space of the I-Cache refers to the address range directly mapped to the second storage space of the I-Cache, used to identify storage locations within the second storage space of the I-Cache. It should be noted that the intrinsic address space of the ILM and the reused address space of the I-Cache together constitute the extended address space of the ILM, and the range of the extended address space is jointly determined by the capacities of the first storage space of the ILM and the second storage space of the I-Cache.

[0066] In some possible implementations, if the first comparison result indicates that the instruction address of the instruction fetch request is within the intrinsic address space of the ILM in the extended address space, then the target instruction corresponding to the instruction fetch request is retrieved from the first memory space of the ILM. Specifically, the step of retrieving the target instruction from the first memory space of the ILM involves the bus control unit accessing the memory location corresponding to the instruction address in the first memory space of the ILM according to the instruction address of the instruction fetch request, and reading the target instruction. It should be noted that the mapping relationship between the first memory space of the ILM and the intrinsic address space of the ILM can be a pre-configured static mapping relationship or a dynamically adjusted mapping relationship based on the processor's operating state.

[0067] In some possible implementations, if the first comparison result indicates that the instruction address of the instruction fetch request is within the reused address space of the I-Cache in the extended address space, then the target instruction corresponding to the instruction fetch request is retrieved from the second storage space of the I-Cache. Specifically, the step of retrieving the target instruction from the second storage space of the I-Cache involves the bus control unit accessing the storage location corresponding to the instruction address in the second storage space of the I-Cache according to the instruction address of the instruction fetch request, and reading the target instruction. It should be noted that the mapping relationship between the second storage space of the I-Cache and the reused address space of the I-Cache can be a pre-configured static mapping relationship or a dynamically adjusted mapping relationship based on the processor's operating state.

[0068] For example, assume the processor's ILM's first storage space is Storage_ILM, the I-Cache's second storage space is Storage_ICache, the ILM's intrinsic address space is AddressSpace_ILM, the I-Cache's multiplexed address space is AddressSpace_ICache, and the extended address space is AddressSpace_Extended. The processor retrieves an instruction fetch request from the instruction fetch unit, with the instruction address being Address_X. If the I-Cache is disabled, Address_X is compared with AddressSpace_Extended. If Address_X is located within AddressSpace_ILM, the target instruction is fetched from Storage_ILM; if Address_X is located within AddressSpace_ICache, the target instruction is fetched from Storage_ICache. For example, if Address_X = Address_ILM1 (Address_ILM1 is an address of AddressSpace_ILM), then the target instruction is retrieved from Storage_ILM; if Address_X = Address_ICache1 (Address_ICache1 is an address of AddressSpace_ICache), then the target instruction is retrieved from Storage_ICache.

[0069] In this embodiment, the first comparison result is used to further determine which part of the extended address space the instruction address of the instruction fetch request is located in, and the target instruction is fetched from the first storage space of the ILM or the second storage space of the I-Cache based on the determination result. If the instruction address is located in the inherent address space of the ILM, the target instruction is directly fetched from the first storage space of the ILM, making full use of the high-speed access characteristics of the ILM; if the instruction address is located in the reused address space of the I-Cache, the target instruction is directly fetched from the second storage space of the I-Cache, realizing the reuse of the I-Cache storage space. Through the above method, this embodiment effectively expands the storage capacity of the ILM when the I-Cache is in a disabled state, reduces the frequency of the processor's access to high-latency external storage units, thereby improving the efficiency and real-time performance of instruction fetching and meeting the processor's high-efficiency instruction fetching requirements.

[0070] Please see Figure 6 This is a flowchart illustrating a process for determining the extended address space of an ILM, as provided in one embodiment of this application. Figure 6 As shown, the method in this application embodiment may include the following steps S401-S404, and steps S401-S404 may be performed in... Figure 2The procedure is performed before step S101 in the illustrated embodiment.

[0071] S401, under the condition that the processor meets the preset conditions, configures the I-Cache to be in a disabled state;

[0072] S402, determine the first storage space from the ILM, and determine the address space corresponding to the first storage space as the inherent address space of the ILM;

[0073] S403, determine the second storage space from the I-Cache, and determine the address space corresponding to the second storage space as the reused address space of the I-Cache;

[0074] S404 integrates the intrinsic address space and the multiplexed address space into the extended address space of the ILM.

[0075] Specifically, the preset conditions involved in this embodiment refer to the conditions under which the processor triggers the I-Cache shutdown under a specific operating state. These conditions can be a preset time range after the processor powers on, the processor entering real-time response mode, or other conditions related to the processor's operating state. Configuring the I-Cache to be disabled means disabling the I-Cache's instruction caching mechanism. The processor no longer retrieves instructions through the I-Cache's caching mechanism but directly retrieves instructions through the ILM or external memory units. It should be noted that disabling the I-Cache does not affect the availability of its second storage space, because the I-Cache's second storage space is not completely disabled in hardware but is reused as part of the ILM's extended storage space through address mapping.

[0076] Determining the first memory space from the ILM refers to selecting a portion or all of the memory spaces from the ILM's total memory space as the first memory space based on the processor's operational requirements or configuration. The first memory space is used to store critical instructions or power-on programs, characterized by high-speed access and strong real-time performance. Determining the address space corresponding to the first memory space as the ILM's intrinsic address space means allocating a unique address range to the first memory space. This address range has a mapping relationship with the first memory space and is used to identify the storage locations within it. It should be noted that the ILM's intrinsic address space can be a pre-configured static address range or a dynamically adjusted address range based on the processor's operating state.

[0077] Determining the second storage space from the I-Cache refers to selecting a portion or all of the storage space from the entire I-Cache as the second storage space based on the processor's operational needs or configuration. When the I-Cache is disabled, the second storage space is reused as part of the ILM's extended storage space through address mapping. Determining the address space corresponding to the second storage space as the I-Cache's reused address space means allocating a unique address range to the second storage space; this address range has a mapping relationship with the second storage space and is used to identify the storage locations within it. It should be noted that the I-Cache's reused address space can be a pre-configured static address range or a dynamically adjusted address range based on the processor's operational state.

[0078] Integrating the intrinsic address space and the reused address space into the extended address space of the ILM refers to merging the ILM's intrinsic address space and the I-Cache's reused address space into a contiguous address range. This address range maps to the ILM's first memory space and the I-Cache's second memory space. The range of the extended address space is jointly determined by the capacities of the ILM's first memory space and the I-Cache's second memory space. It should be noted that the integration of the extended address space can be implemented through an address mapping table or hardware logic, ensuring the continuity and uniqueness of the address space.

[0079] In some possible implementations, the processor is determined to meet a preset first condition within a preset time range after power-on; or, the processor is determined to meet a preset second condition when entering real-time response mode. Both the preset first and preset second conditions are preset conditions, and the processor disables the instruction caching mechanism of the I-Cache in real-time response mode. The specific steps for configuring the I-Cache to be disabled are as follows: the processor generates a configuration signal according to the preset conditions and sends the configuration signal to the I-Cache control unit; the control unit disables the instruction caching mechanism of the I-Cache according to the configuration signal.

[0080] In some possible implementations, the processor selects a portion or all of the ILM's memory space as the first memory space based on operational needs or configuration. The specific steps for determining the address space corresponding to the first memory space as the ILM's intrinsic address space are: the processor allocates a unique address range to the first memory space and establishes a mapping relationship between this address range and the first memory space. It should be noted that the ILM's intrinsic address space can be a pre-configured static address range or a dynamically adjusted address range based on the processor's operating state.

[0081] In some possible implementations, the processor selects part or all of the memory space from the entire I-Cache as the second memory space based on operational needs or configuration. The specific steps for determining the address space corresponding to the second memory space as the reused address space of the I-Cache are: the processor allocates a unique address range to the second memory space and establishes a mapping relationship between this address range and the second memory space. It should be noted that the reused address space of the I-Cache can be a pre-configured static address range or a dynamically adjusted address range based on the processor's operating state.

[0082] In some possible implementations, the processor merges the intrinsic address space of the ILM and the multiplexed address space of the I-Cache into a contiguous address range, and maps this address range to the first memory space of the ILM and the second memory space of the I-Cache. The consolidation of the extended address space can be implemented through an address mapping table or hardware logic, ensuring the continuity and uniqueness of the address space.

[0083] For example, assume the processor's ILM's first storage space is Storage_ILM, the I-Cache's second storage space is Storage_ICache, the ILM's intrinsic address space is AddressSpace_ILM, the I-Cache's multiplexed address space is AddressSpace_ICache, and the extended address space is AddressSpace_Extended. Under preset conditions, the processor configures the I-Cache to be disabled. Then, it determines the first storage space Storage_ILM from the ILM and sets its corresponding address space to AddressSpace_ILM. Next, it determines the second storage space Storage_ICache from the I-Cache and sets its corresponding address space to AddressSpace_ICache. Finally, it merges AddressSpace_ILM and AddressSpace_ICache into the extended address space AddressSpace_Extended. For example, if the address range of AddressSpace_ILM is 0x0000-0x0FFF and the address range of AddressSpace_ICache is 0x1000-0x1FFF, then the address range of the extended address space AddressSpace_Extended is 0x0000-0x1FFF.

[0084] In this embodiment, by configuring the I-Cache to a disabled state when the processor meets preset conditions, and determining the first and second storage spaces from the ILM and I-Cache respectively, the address spaces corresponding to the first and second storage spaces are integrated into the extended address space of the ILM. This achieves the reuse of the I-Cache storage space, effectively expanding the storage capacity of the ILM. Through the above method, this embodiment fully utilizes the I-Cache storage space without increasing hardware resource overhead, improves the instruction storage capacity of the ILM, reduces the processor's access frequency to high-latency external memory units, thereby improving instruction fetching efficiency and real-time performance, and meeting the processor's high-efficiency instruction fetching requirements.

[0085] In one embodiment, based on Figure 6 In the illustrated embodiment, the instruction acquisition method further includes the following steps:

[0086] Within a preset time range after the processor is powered on, determine that the processor meets a preset first condition; or,

[0087] When the processor enters real-time response mode, it is determined that the processor meets the preset second condition;

[0088] Among them, the first preset condition and the second preset condition are both preset conditions, and the processor disables the instruction caching mechanism of I-Cache in real-time response mode.

[0089] Specifically, in this embodiment, the preset first condition refers to the condition that triggers I-Cache shutdown within a preset time range after the processor powers on, and the preset second condition refers to the condition that triggers I-Cache shutdown when the processor enters real-time response mode. Both the preset first condition and the preset second condition are preset conditions used to disable the I-Cache instruction caching mechanism in specific scenarios to optimize the processor's instruction fetching efficiency.

[0090] The preset time range after processor power-on refers to the period from processor startup to entering a stable operating state. During this period, the processor's instruction fetching needs are typically concentrated and have high real-time requirements. Within the preset time range, the processor may execute power-on initialization procedures or other critical tasks, the execution of which depends on fast and stable instruction fetching. Therefore, disabling the I-Cache instruction caching mechanism within the preset time range can reduce instruction fetching latency and ensure that the processor can quickly respond to power-on initialization requirements.

[0091] The processor entering real-time response mode refers to the processor's operating state when executing real-time tasks. Real-time tasks have high requirements for the real-time and deterministic nature of instruction fetching. In real-time response mode, disabling the I-Cache instruction caching mechanism can avoid additional latency caused by cache misses, ensuring that the processor can quickly fetch instructions and execute real-time tasks. It should be noted that real-time response mode can be a state that the processor automatically enters based on task requirements, or a state triggered by external configuration signals.

[0092] Within a preset time range after the processor powers on, the specific steps for determining that the processor meets a preset first condition are as follows: The processor starts a timer after power-on, and generates a first trigger signal when the timer reaches the preset time range. The first trigger signal indicates that the processor meets the preset first condition. The processor generates a configuration signal based on the first trigger signal and sends the configuration signal to the I-Cache control unit. The control unit disables the I-Cache instruction caching mechanism based on the configuration signal.

[0093] When the processor enters real-time response mode, the steps to determine if the processor meets the preset second condition are as follows: While executing a real-time task, the processor detects task attributes or receives an external configuration signal, and generates a second trigger signal upon determining that it has entered real-time response mode. This second trigger signal indicates that the processor meets the preset second condition. The processor generates a configuration signal based on the second trigger signal and sends it to the I-Cache control unit. The control unit disables the I-Cache instruction caching mechanism based on the configuration signal.

[0094] In some possible implementations, the preset time range can be a fixed period of time after the processor powers on, such as within 100 milliseconds after power-on; or it can be a dynamically adjusted period of time based on the processor's operating state, such as the time required for the processor to execute the initialization program after power-on. The preset time range can be determined using a hardware timer or a software timer.

[0095] In some possible implementations, the triggering condition for real-time response mode can be that the processor receives a real-time task request, such as an interrupt request or a high-priority task request; or it can be that the processor detects the execution requirement of a real-time task, such as a periodic task or a time-sensitive task. The triggering of real-time response mode can be implemented through hardware logic or software configuration.

[0096] In some possible implementations, disabling the I-Cache instruction caching mechanism involves the processor generating a configuration signal and sending it to the I-Cache control unit. The control unit then disables the I-Cache's caching function based on the configuration signal. It's important to note that disabling the I-Cache instruction caching mechanism does not affect the availability of the I-Cache's second storage space, because this second storage space is not completely disabled in hardware; rather, it is reused as part of the ILM's extended storage space through address mapping.

[0097] In this embodiment, by determining that the processor meets preset conditions within a preset time range after power-on or when the processor enters real-time response mode, and disabling the I-Cache instruction caching mechanism, the processor's instruction fetching efficiency is optimized. Disabling the I-Cache instruction caching mechanism within the preset time range reduces instruction fetching latency during power-on initialization, ensuring the processor quickly enters a stable operating state. Disabling the I-Cache instruction caching mechanism in real-time response mode avoids additional latency caused by cache misses, ensuring the processor quickly responds to real-time task requirements. Through the above methods, this embodiment improves the processor's instruction fetching efficiency and real-time performance without increasing hardware resource overhead, meeting the processor's high-efficiency instruction fetching requirements in specific scenarios.

[0098] Please see Figure 7 This is a schematic diagram illustrating a process for obtaining a target instruction when the I-Cache is enabled, as provided in one embodiment of this application. Figure 7 As shown, the method of this application embodiment may include the following steps S501-S503, and steps S501-S503 may be performed in... Figure 2 The example shown is executed after step S101.

[0099] S501, when the I-Cache is enabled, compares the instruction address of the instruction fetch request with the inherent address space of the ILM to obtain a second comparison result, and maps the inherent address space to the first storage space of the ILM;

[0100] S502, based on the second comparison result, retrieve the target instruction corresponding to the instruction fetch request from the first storage space, the second storage space of the I-Cache, or the external storage unit;

[0101] S503, return the target instruction to the IFU.

[0102] Specifically, in this embodiment, "I-Cache enabled" means that the instruction caching mechanism is activated, allowing the processor to fetch instructions and reduce latency when accessing external memory. The inherent address space of the ILM refers to the address range directly mapped to the first memory space of the ILM, used to identify storage locations within the first memory space of the ILM. It should be noted that the inherent address space of the ILM can be a pre-configured static address range or a dynamically adjusted address range based on the processor's operating state.

[0103] In some possible implementations, the step of comparing the instruction address of the instruction fetch request with the inherent address space of the ILM specifically involves: the bus control unit receiving the instruction address of the instruction fetch request and comparing it with the address range of the ILM's inherent address space to determine whether the instruction address is within the inherent address space. If the instruction address is within the inherent address space, the target instruction is fetched from the ILM's first memory space; if the instruction address is outside the inherent address space, the cache hit result of the instruction address is further determined through the I-Cache instruction caching mechanism.

[0104] In some possible implementations, the step of retrieving the target instruction corresponding to the fetch request from the first storage space, the second storage space of the I-Cache, or an external storage unit based on the second comparison result is as follows: if the second comparison result indicates that the instruction address of the fetch request is within the inherent address space of the ILM, then the target instruction corresponding to the fetch request is retrieved from the first storage space of the ILM; if the second comparison result indicates that the instruction address of the fetch request is outside the inherent address space of the ILM, then the cache hit result of the instruction address is determined according to the instruction caching mechanism of the I-Cache, wherein the cache hit result indicates that the instruction address hits the second storage space of the I-Cache or misses the second storage space; and the target instruction corresponding to the fetch request is retrieved from the second storage space of the I-Cache or an external storage unit based on the cache hit result.

[0105] In some possible implementations, the specific steps for retrieving the target instruction from the first memory space of the ILM are as follows: the bus control unit accesses the memory location corresponding to the instruction address in the first memory space of the ILM according to the instruction address of the instruction fetch request, and reads the target instruction.

[0106] In some possible implementations, the steps for determining the cache hit result of the instruction address based on the I-Cache instruction caching mechanism are as follows: The bus control unit accesses the I-Cache cache tag table based on the instruction address of the instruction fetch request, and determines whether the instruction address hits the second storage space of the I-Cache. If the instruction address hits the second storage space of the I-Cache, the target instruction is retrieved from the second storage space of the I-Cache; if the instruction address does not hit the second storage space of the I-Cache, the target instruction is retrieved from the external storage unit.

[0107] In some possible implementations, the specific steps for retrieving the target instruction from the second storage space of the I-Cache are as follows: the bus control unit accesses the storage location corresponding to the instruction address in the second storage space of the I-Cache according to the instruction address of the fetch request, and reads the target instruction.

[0108] In some possible implementations, the steps for retrieving the target instruction from the external storage unit are as follows: the bus control unit accesses the storage location corresponding to the instruction address in the external storage unit through the external bus according to the instruction address of the instruction fetch request, and reads the target instruction.

[0109] After acquiring the target instruction, the bus control unit returns the target instruction to the IFU.

[0110] In this embodiment, with the I-Cache enabled, the instruction address of the fetch request is compared with the intrinsic address space of the ILM to obtain a second comparison result, where the intrinsic address space is mapped to the first storage space of the ILM. Then, based on the second comparison result, the target instruction corresponding to the fetch request is retrieved from the first storage space, the second storage space of the I-Cache, or an external storage unit, and the target instruction is returned to the IFU. This achieves coordinated utilization of the ILM and I-Cache storage spaces, optimizing the processor's instruction fetching efficiency. Based on the second comparison result, the processor may directly retrieve the target instruction from the first storage space of the ILM, fully utilizing the high-speed access characteristics of the ILM; based on the second comparison result, the processor may also retrieve the target instruction from the second storage space of the I-Cache through the I-Cache's instruction caching mechanism, reducing the latency of accessing external storage units; based on the second comparison result, the processor may also retrieve the target instruction from an external storage unit, ensuring the integrity of instruction fetching and the normal operation of the system. The solution provided in this embodiment, with the I-Cache enabled, fully utilizes the storage spaces of the ILM and I-Cache, improving the processor's instruction storage capacity and fetching efficiency, thereby meeting the processor's high-efficiency instruction fetching requirements.

[0111] Please see Figure 8This is a flowchart illustrating a process for obtaining a target instruction based on a second comparison result, as provided in one embodiment of this application. Figure 8 As shown, the method in this embodiment may include the following steps S601-S603, and steps S601-S603 may be used as a method for... Figure 7 The detailed steps of step S502 in the illustrated embodiment.

[0112] S601, if the second comparison result indicates that the instruction address is in the inherent address space, then the target instruction corresponding to the instruction fetch request is obtained from the first memory space;

[0113] S602, if the second comparison result indicates that the instruction address is outside the inherent address space, then the cache hit result of the instruction address is determined according to the instruction caching mechanism of the I-Cache, wherein the cache hit result indicates that the instruction address hits the second storage space of the I-Cache or does not hit the second storage space.

[0114] S603 retrieves the target instruction corresponding to the instruction fetch request from the second storage space or external storage unit based on the cache hit result.

[0115] Specifically, the second comparison result involved in this embodiment is used to indicate whether the instruction address of the instruction fetch request is located within the intrinsic address space of the ILM. The intrinsic address space of the ILM refers to the address range directly mapped to the first storage space of the ILM, used to identify the storage location in the first storage space of the ILM. The instruction caching mechanism of the I-Cache refers to dynamically mapping instructions in external storage units to the second storage space of the I-Cache through a cache tag table to reduce the latency of accessing external storage units. The cache hit result refers to the result of determining whether the instruction address of the instruction fetch request hits the second storage space of the I-Cache through the instruction caching mechanism of the I-Cache, used to indicate whether the instruction address exists in the second storage space of the I-Cache.

[0116] In some possible implementations, if the second comparison result indicates that the instruction address of the instruction fetch request is within the ILM's intrinsic address space, then the target instruction corresponding to the instruction fetch request is retrieved from the ILM's first memory space. Specifically, the step of retrieving the target instruction from the ILM's first memory space involves the bus control unit accessing the memory location corresponding to the instruction address in the ILM's first memory space, reading the target instruction, and returning the target instruction to the IFU. It should be noted that the mapping relationship between the ILM's first memory space and the ILM's intrinsic address space can be a pre-configured static mapping relationship or a dynamically adjusted mapping relationship based on the processor's operating state.

[0117] In some possible implementations, if the second comparison result indicates that the instruction address requested for instruction fetching is outside the inherent address space of the ILM, then the cache hit result of the instruction address is determined according to the instruction caching mechanism of the I-Cache. Specifically, the steps for determining the cache hit result according to the instruction caching mechanism of the I-Cache are as follows: the bus control unit accesses the cache tag table of the I-Cache based on the instruction address requested for instruction fetching, and determines whether the instruction address hits the second storage space of the I-Cache. If the instruction address hits the second storage space of the I-Cache, the target instruction is retrieved from the second storage space of the I-Cache; if the instruction address does not hit the second storage space of the I-Cache, the target instruction is retrieved from the external storage unit. It should be noted that the cache tag table of the I-Cache is used to store the mapping relationship between instruction addresses in the external storage unit and the second storage space of the I-Cache.

[0118] In some possible implementations, if the cache hit result indicates that the instruction address hits the second storage space of the I-Cache, then the target instruction corresponding to the fetch request is retrieved from the second storage space of the I-Cache. Specifically, the steps for retrieving the target instruction from the second storage space of the I-Cache are as follows: the bus control unit accesses the storage location corresponding to the instruction address in the second storage space of the I-Cache according to the instruction address of the fetch request, reads the target instruction, and returns the target instruction to the IFU. It should be noted that the mapping relationship between the second storage space of the I-Cache and external storage units can be dynamically maintained through a cache tag table to ensure the consistency between the instruction address and the storage location.

[0119] In some possible implementations, if the cache hit result indicates that the instruction address does not hit the second storage space of the I-Cache, the target instruction corresponding to the fetch request is retrieved from the external storage unit. Specifically, the steps for retrieving the target instruction from the external storage unit are as follows: the bus control unit accesses the storage location corresponding to the instruction address in the external storage unit via the external bus, reads the target instruction, and returns the target instruction to the IFU. It should be noted that the external storage unit is typically implemented using Dynamic Random Access Memory (DRAM) or Flash Memory, which has a large capacity but slow access speed, and is mainly used to store large amounts of program instructions and data.

[0120] For example, assume the processor's ILM's first storage space is Storage_ILM, the I-Cache's second storage space is Storage_ICache, the external storage unit is Storage_External, and the ILM's intrinsic address space is AddressSpace_ILM. The processor retrieves an instruction fetch request from the instruction fetch unit, with the instruction address being Address_X. If the I-Cache is enabled, Address_X is compared with AddressSpace_ILM. If Address_X is within AddressSpace_ILM, the target instruction is fetched from Storage_ILM; if Address_X is outside AddressSpace_ILM, a cache hit result is determined according to the I-Cache's instruction caching mechanism. If the cache hit result indicates that Address_X hits Storage_ICache, the target instruction is fetched from Storage_ICache; if the cache hit result indicates that Address_X does not hit Storage_ICache, the target instruction is fetched from Storage_External. For example, if Address_X = Address_ILM1 (Address_ILM1 is an address of AddressSpace_ILM), the target instruction is retrieved from Storage_ILM; if Address_X = Address_ICache1 (Address_ICache1 is an address outside AddressSpace_ILM and hits Storage_ICache), the target instruction is retrieved from Storage_ICache; if Address_X = Address_External1 (Address_External1 is an address outside AddressSpace_ILM and does not hit Storage_ICache), the target instruction is retrieved from Storage_External.

[0121] In this embodiment, the second comparison result determines whether the instruction address of the instruction fetch request is within the intrinsic address space of the ILM, and the target instruction is retrieved from the first storage space of the ILM based on the determination result. If the instruction address is outside the intrinsic address space of the ILM, the cache hit result is determined according to the instruction caching mechanism of the I-Cache, and the target instruction is retrieved from the second storage space of the I-Cache or an external storage unit based on the cache hit result. If the instruction address is within the intrinsic address space of the ILM, the target instruction is directly retrieved from the first storage space of the ILM, making full use of the high-speed access characteristics of the ILM. If the instruction address is outside the intrinsic address space of the ILM but hits the second storage space of the I-Cache, the target instruction is retrieved from the second storage space of the I-Cache, reducing the latency of accessing external storage units. If the instruction address is outside the intrinsic address space of the ILM but does not hit the second storage space of the I-Cache, the target instruction is retrieved from an external storage unit, ensuring the integrity of instruction fetching and the normal operation of the system. In this embodiment, with the I-Cache enabled, the coordinated use of ILM and I-Cache storage space is achieved, optimizing the processor's instruction fetching efficiency and thus meeting the processor's high-efficiency instruction fetching requirements.

[0122] In one embodiment, for Figure 8 Step S603 of the illustrated embodiment can be further refined to include the following steps:

[0123] If the cache hit result indicates that the instruction address hits the second storage space, then the target instruction corresponding to the instruction fetch request is retrieved from the second storage space;

[0124] If the cache hit result indicates that the instruction address does not hit the second storage space, then the target instruction corresponding to the instruction fetch request is retrieved from the external storage unit.

[0125] Specifically, the cache hit result involved in this embodiment refers to the result of determining whether the instruction address of the instruction fetch request hits the second storage space of the I-Cache through the instruction caching mechanism of the I-Cache, which is used to indicate whether the instruction address exists in the second storage space of the I-Cache.

[0126] In some possible implementations, if a cache hit indicates that the instruction address hits the second storage space of the I-Cache, then the target instruction corresponding to the fetch request is retrieved from the second storage space of the I-Cache. Specifically, the steps for retrieving the target instruction from the second storage space of the I-Cache are as follows: the bus control unit accesses the storage location corresponding to the instruction address in the second storage space of the I-Cache based on the instruction address of the fetch request, reads the target instruction, and returns the target instruction to the IFU. It should be noted that the mapping relationship between the second storage space of the I-Cache and the external storage unit can be dynamically maintained through a cache tag table to ensure the consistency between the instruction address and the storage location. The cache tag table stores the mapping relationship between the instruction address in the external storage unit and the second storage space of the I-Cache. The bus control unit determines whether the instruction address hits the second storage space of the I-Cache by querying the cache tag table.

[0127] In some possible implementations, if the cache hit result indicates that the instruction address does not hit the second storage space of the I-Cache, the target instruction corresponding to the instruction fetch request is retrieved from the external storage unit. Specifically, the steps for retrieving the target instruction from the external storage unit are as follows: the bus control unit accesses the storage location corresponding to the instruction address in the external storage unit via the external bus, reads the target instruction, and returns the target instruction to the IFU. It should be noted that access to the external storage unit typically requires traversing the external bus, and the bandwidth and latency of the external bus affect the efficiency of instruction fetching. To improve the efficiency of external storage unit access, the processor may employ a prefetch mechanism or cache filling strategy to preload instructions from the external storage unit into the second storage space of the I-Cache, thereby reducing the latency of subsequent instruction fetching.

[0128] In some possible implementations, the steps for determining a cache hit result are as follows: The bus control unit accesses the I-Cache's cache tag table based on the instruction address of the fetch request, and determines whether the instruction address hits the second storage space of the I-Cache. If the instruction address hits the second storage space of the I-Cache, a hit signal is generated, indicating that the cache hit result is a hit; if the instruction address does not hit the second storage space of the I-Cache, a miss signal is generated, indicating that the cache hit result is a miss.

[0129] In some possible implementations, the step of retrieving the target instruction from the second storage space of the I-Cache specifically involves: the bus control unit accessing the storage location corresponding to the instruction address in the second storage space of the I-Cache according to the instruction address of the fetch request, and reading the target instruction. In some possible implementations, the step of retrieving the target instruction from an external storage unit specifically involves: the bus control unit accessing the storage location corresponding to the instruction address in the external storage unit via the external bus according to the instruction address of the fetch request, and reading the target instruction.

[0130] For example, assume the processor's second I-Cache storage space is Storage_ICache, the external storage unit is Storage_External, and the cache tag table is TagTable_ICache. The processor obtains an instruction fetch request from the instruction fetch unit, with the instruction address being Address_X. The bus control unit accesses TagTable_ICache based on Address_X to determine if Address_X hits Storage_ICache. If Address_X hits Storage_ICache, the target instruction is fetched from Storage_ICache; if Address_X misses Storage_ICache, the target instruction is fetched from Storage_External. For instance, if Address_X = Address_ICache1 (Address_ICache1 is an address of Storage_ICache), the target instruction is fetched from Storage_ICache; if Address_X = Address_External1 (Address_External1 is an address of Storage_External and misses Storage_ICache), the target instruction is fetched from Storage_External.

[0131] In this embodiment, the cache hit result is used to determine whether the instruction address of the instruction fetch request hits the second storage space of the I-Cache, and the target instruction is retrieved from the second storage space of the I-Cache or an external storage unit based on the determination result. If the instruction address hits the second storage space of the I-Cache, the target instruction is directly retrieved from the second storage space of the I-Cache, reducing the latency of accessing the external storage unit; if the instruction address does not hit the second storage space of the I-Cache, the target instruction is retrieved from the external storage unit, ensuring the integrity of instruction fetching and the normal operation of the system. Through the above method, this embodiment fully utilizes the caching mechanism of the I-Cache when the I-Cache is enabled, optimizes the processor's instruction fetching efficiency, and thus meets the processor's high-efficiency instruction fetching requirements.

[0132] It should be understood that although the steps in the flowchart are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0133] In one embodiment, a processor is provided that includes an IFU, an ILM, and an I-Cache, and the processor is connected to an external memory unit; the processor is configured to perform any step of the instruction fetching method described above.

[0134] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, can perform any of the steps in the instruction fetching method described above.

[0135] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0136] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0137] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0138] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0139] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0140] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for acquiring instructions, characterized in that, Applied to a processor, the processor including an instruction fetch unit (IFU), an instruction local memory (ILM), and an instruction cache (I-Cache), the processor being connected to external memory units; the method includes: Obtain the instruction fetch request of the IFU; When the I-Cache is in a disabled state, the instruction address of the instruction fetch request is compared with the extended address space of the ILM to obtain a first comparison result, and the extended address space is mapped to the first storage space of the ILM and the second storage space of the I-Cache; Based on the first comparison result, the target instruction corresponding to the instruction fetch request is obtained from the first storage space, the second storage space, or the external storage unit; Return the target instruction to the IFU; After obtaining the instruction fetch request of the IFU, the method further includes: When the I-Cache is enabled, the instruction address of the instruction fetch request is compared with the inherent address space of the ILM to obtain a second comparison result, and the inherent address space is mapped to the first storage space of the ILM; Based on the second comparison result, the target instruction corresponding to the instruction fetch request is obtained from the first storage space, the second storage space of the I-Cache, or the external storage unit; Return the target instruction to the IFU.

2. The method according to claim 1, characterized in that, The step of obtaining the target instruction corresponding to the instruction fetch request from the first storage space, the second storage space, or the external storage unit based on the first comparison result includes: If the first comparison result indicates that the instruction address is in the extended address space, then the target instruction corresponding to the instruction fetch request is obtained from the first storage space or the second storage space; If the first comparison result indicates that the instruction address is outside the extended address space, then the target instruction corresponding to the instruction fetch request is obtained from the external storage unit.

3. The method according to claim 2, characterized in that, If the first comparison result indicates that the instruction address is within the extended address space, then retrieving the target instruction corresponding to the instruction fetch request from the first storage space or the second storage space includes: If the first comparison result indicates that the instruction address is in the intrinsic address space of the ILM in the extended address space, then the target instruction corresponding to the instruction fetch request is obtained from the first memory space, and there is a mapping relationship between the intrinsic address space and the first memory space; If the first comparison result indicates that the instruction address is in the reused address space of the I-Cache in the extended address space, then the target instruction corresponding to the instruction fetch request is obtained from the second storage space, and there is a mapping relationship between the reused address space and the second storage space.

4. The method according to claim 3, characterized in that, Before obtaining the instruction fetch request for the IFU, the method further includes: If the processor meets the preset conditions, the I-Cache will be configured to be disabled; A first storage space is determined from the ILM, and the address space corresponding to the first storage space is determined as the inherent address space of the ILM; A second storage space is determined from the I-Cache, and the address space corresponding to the second storage space is determined as the reused address space of the I-Cache; The intrinsic address space and the reused address space are integrated into the extended address space of the ILM.

5. The method according to claim 4, characterized in that, The method further includes: Within a preset time range after the processor is powered on, it is determined that the processor meets a preset first condition; or, When the processor enters the real-time response mode, it is determined that the processor meets a preset second condition; Wherein, the preset first condition and the preset second condition are both one of the preset conditions, and the processor disables the instruction caching mechanism of the I-Cache in the real-time response mode.

6. The method according to claim 1, characterized in that, The step of obtaining the target instruction corresponding to the instruction fetch request from the first storage space, the second storage space of the I-Cache, or the external storage unit based on the second comparison result includes: If the second comparison result indicates that the instruction address is in the inherent address space, then the target instruction corresponding to the instruction fetch request is obtained from the first storage space; If the second comparison result indicates that the instruction address is outside the inherent address space, then the cache hit result of the instruction address is determined according to the instruction caching mechanism of the I-Cache, wherein the cache hit result indicates that the instruction address hits the second storage space of the I-Cache or does not hit the second storage space; Based on the cache hit result, the target instruction corresponding to the instruction fetch request is obtained from the second storage space or the external storage unit.

7. The method according to claim 6, characterized in that, The step of obtaining the target instruction corresponding to the instruction fetch request from the second storage space or the external storage unit based on the cache hit result includes: If the cache hit result indicates that the instruction address hits the second storage space, then the target instruction corresponding to the instruction fetch request is obtained from the second storage space; If the cache hit result indicates that the instruction address does not hit the second storage space, then the target instruction corresponding to the instruction fetch request is obtained from the external storage unit.

8. A processor, characterized in that, The processor includes an instruction fetch unit (IFU), an instruction local memory (ILM), and an instruction cache (I-Cache), and the processor is connected to an external memory unit. The processor is configured to perform the steps of the method as described in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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