Instruction processing method and apparatus, computer device, and storage medium

Abstract

The method comprises: obtaining a setting instruction and a vector calculation instruction from a preset instruction local storage or an instruction cache; updating a preset shadow register according to the setting instruction to obtain a first updated value; performing data recovery on the first updated value by using a preset real register to obtain a second updated value; and executing the vector calculation instruction according to the second updated value. The method uses the preset shadow register to perform instruction speculation according to a pipeline, and obtains an updated value in advance. When an instruction that needs to be flushed is executed, the incorrect updated value is backed up and recovered by using the preset real register, so that the values stored in the shadow register and the real register are consistent, thereby improving the performance and efficiency when the vector calculation instruction is executed.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and more specifically, to an instruction processing method, apparatus, computer device, and storage medium. Background Technology

[0002] Vector computation has always been a key part of operations across various fields, and RISC-V also has a corresponding basic vector extension, the V extension. Before using V instructions, it is usually necessary to use the VSET instruction to configure the vstart / vl / vtype registers to set the total length of the vector, the length of the vector computation, and the vector data type before performing the corresponding vector instructions such as vector multiplication and vector addition.

[0003] In existing technologies, a flushing pipeline approach is typically used for vector computations. This involves first fetching the VSET instruction, then performing a flushing operation after the instruction execution unit (IPU) has fetched the VSET instruction, causing the IPU to re-fetch instructions for subsequent vector computation. However, this approach results in a significant number of clock cycles being wasted on pipeline resets rather than actually executing useful instructions. Especially when VSET and Vector Processing Unit (VPU) instructions are frequently executed, this architecture causes the processor to spend most of its time processing pipeline flushing operations rather than effectively executing instructions. This significantly degrades the processor's overall performance during vector operations. Summary of the Invention

[0004] This application provides an instruction processing method, apparatus, device, and storage medium, aiming to solve the technical problem of how to improve the performance and efficiency of executing vector computation instructions.

[0005] A first aspect of the embodiments of this application provides an instruction processing method, the method comprising:

[0006] Retrieve setup instructions and vector calculation instructions from the preset instruction local memory or instruction cache;

[0007] The preset shadow register is updated according to the setting instruction to obtain the first update value;

[0008] The first updated value is recovered using a preset real register to obtain the second updated value;

[0009] The vector calculation instruction is executed based on the second updated value.

[0010] In an optional embodiment of this application, the step of updating the preset shadow register according to the setting instruction to obtain the first register value includes:

[0011] The preset pipeline level identifies and decodes the setting instructions, and extracts the address or identifier of the preset shadow register;

[0012] Locate the target shadow register based on its address or identifier;

[0013] Calculate the current value of the setting instruction and write the current value of the setting instruction into the target shadow register to obtain the first updated value.

[0014] In an optional embodiment of this application, the step of using a preset real register to recover data from the first updated value and obtain the second updated value includes:

[0015] The preset shadow register is restored by using the correct value in the preset real register to replace the first update value, the restored value of the preset shadow register is obtained, and the restored value of the shadow register is determined as the second update value.

[0016] In an optional embodiment of this application, the step of recovering data from the shadow register using the correct value in the real register to replace the first update value, obtaining the recovered value of the shadow register, and determining the recovered value of the shadow register as the second update value includes:

[0017] Read the correct value of the preset real register;

[0018] The incorrect values ​​in the preset shadow register are recovered based on the correct values ​​of the preset real register to obtain the preset shadow register after data recovery;

[0019] The recovered value is read from the preset shadow register and determined as the second updated value.

[0020] In an optional embodiment of this application, before the step of recovering the erroneous value in the preset shadow register based on the correct value of the preset real register to obtain the preset shadow register after data recovery, the method includes:

[0021] Monitor the execution status of the preset pipeline level. If the execution status of the preset pipeline level is detected to be abnormal, determine whether the setting instruction is an instruction that needs to be revoked due to the abnormal status.

[0022] If the setting instruction is one that needs to be revoked due to the abnormal state, then the current value of the preset shadow register is determined to be an error value.

[0023] In an optional embodiment of this application, the step of executing the vector calculation instruction based on the second updated value includes:

[0024] The second updated value is input into the preset vector decoder, and the vector calculation instruction is combined with it to perform a decoding operation to obtain the decoding information of the vector calculation instruction.

[0025] The decoded information is transmitted to a preset vector processing unit through a preset pipeline-level transmission mechanism, and the vector calculation instruction is performed using the second update value.

[0026] In an optional embodiment of this application, before the step of inputting the second updated value into a preset vector decoder, combining it with the vector calculation instruction, performing a decoding operation, and obtaining the decoding information of the vector calculation instruction, the method includes:

[0027] Verify whether the second updated value is consistent with the correct value of the actual register;

[0028] If they match, a status update signal is sent to the preset pipeline level;

[0029] Based on the status update signal, the pause state of the preset pipeline level is released and the instruction address is obtained;

[0030] Based on the instruction address, the second update value is input into the preset vector decoder to execute the vector calculation instruction.

[0031] A second aspect of this application provides an instruction processing apparatus, the apparatus comprising:

[0032] The acquisition module is used to acquire setting instructions and vector calculation instructions from a preset instruction local memory or instruction cache;

[0033] The update module is used to update the preset shadow register according to the setting instruction to obtain the first update value;

[0034] The recovery module is used to recover the data of the first updated value using a preset real register and obtain the second updated value;

[0035] An execution module is used to execute the vector calculation instruction based on the second updated value.

[0036] A third aspect of the present application provides a computer device, including: a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the instruction processing method as described above.

[0037] A fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the steps of the instruction processing method as described in any of the preceding claims. Attached Figure Description

[0038] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0039] Figure 1 A schematic diagram of a flushing process based on a multi-stage pipeline processor is provided for one embodiment of this application;

[0040] Figure 2 A flowchart of the instruction processing method provided in the first embodiment of this application;

[0041] Figure 3 A flowchart of the instruction processing method provided in the second embodiment of this application;

[0042] Figure 4 A flowchart of the instruction processing method provided in the third embodiment of this application;

[0043] Figure 5 A simplified flowchart illustrating the instruction processing method of this application;

[0044] Figure 6 A flowchart illustrating the process of restoring the value of the shadow register from the real register in the instruction processing method of this application;

[0045] Figure 7 This is a schematic diagram of the structure of an instruction processing method apparatus provided in one embodiment of this application;

[0046] Figure 8 This is a schematic diagram of a computer device structure provided in one embodiment of this application. Detailed Implementation

[0047] In the process of implementing this application, the inventors discovered that in the prior art, multi-stage pipelined processors are usually used to perform vector-related calculations in a flushing pipeline manner. That is, firstly, the instruction fetch stage reads the setting instruction, and after the instruction execution unit reads the setting instruction, the flushing pipeline operation is performed to allow the instruction fetch unit to fetch instructions again and read subsequent vector calculation instructions.

[0048] In multi-stage pipelined processor architectures, using a flushing pipeline approach to execute set instructions typically wastes a significant number of clock cycles, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a flushing pipeline process based on a multi-stage pipeline processor.

[0049] Depend on Figure 1As can be seen, the penultimate stage of a multi-stage pipelined processor is where registers reside. After a set instruction updates the registers, vector computation instructions are also executed within the execution unit. However, the vector computation unit needs to retrieve the set data from the decoding section of the execution unit and then send it to the vector processing unit for execution. Therefore, the registers need to undergo a flushing pipeline operation. Furthermore, all vector operation instructions require setting the vector-related registers using set instructions before computation. Figure 1 Taking a 5-stage pipelined processor as an example, the flushing pipeline costs 4 cycles. If a large number of setup instructions and vector calculation instructions are executed, a large number of processor clock cycles are spent processing the flushing pipeline, and very few instructions are actually executed. This architecture greatly affects the processor's vector operation performance.

[0050] To address the aforementioned problems, this application provides an instruction processing method, apparatus, computer device, and storage medium. The method includes: retrieving a setup instruction and a vector calculation instruction from a preset instruction local memory or instruction cache; updating a preset shadow register according to the setup instruction to obtain a first update value; restoring the first update value using a preset real register to obtain a second update value; and executing the vector calculation instruction based on the second update value. This method uses a preset shadow register to predict execution based on pipelined instructions, obtaining update values ​​in advance. When an instruction that needs to be flushed is executed, erroneous update values ​​are backed up and restored using the preset real register, ensuring consistency between the values ​​stored in the shadow register and the real register, thereby improving the performance and efficiency of executing vector calculation instructions.

[0051] The solutions in this application embodiment can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0052] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0053] The following is a brief description of the application environment of the instruction processing method provided in the embodiments of this application:

[0054] Please see Figure 2 The first embodiment provided in this application, wherein the instruction processing method includes steps S10 to S40:

[0055] Step S10: Retrieve the setup instruction and vector calculation instruction from the preset instruction local memory or instruction cache;

[0056] It should be noted that the VSET instruction is specifically designed for configuring the vector processing environment. It is typically used to initialize or adjust critical parameters of vector registers to ensure that subsequent vector operations can be executed correctly.

[0057] Vector computation instructions refer to a set of instructions that directly manipulate vector data. They rely on a vector environment pre-configured via the VSET instruction. Vector computation instructions include, but are not limited to, vector addition, vector subtraction, vector multiplication, and vector division.

[0058] Specifically, in this embodiment, during the instruction fetch stage of the preset multi-stage pipeline, an instruction fetch request is sent to the instruction local memory or instruction cache, and instructions are fetched from the instruction local memory or instruction cache based on the fetch request and sent to the instruction decoder. Then, the instruction decoder parses the type of each instruction, determines the setup instruction and vector calculation instruction, and transmits the setup instruction and vector calculation instruction to the execution unit of the preset multi-stage pipeline so that they can participate in the subsequent configuration of vector register parameters.

[0059] Step S20: Update the preset shadow register according to the setting instruction to obtain the first update value;

[0060] It should be noted that the shadow register is a special register designed in this embodiment, which is usually used to temporarily store or cache data in the real register.

[0061] The first updated value is the new value stored in the shadow register after executing a setup instruction (such as the VSET instruction). This value represents the latest change made to the vector register configuration based on the current setup instruction. Due to potential pipeline anomalies (such as jump prediction failures), this value may be incorrect, and therefore needs to be restored using the correct value from the real register.

[0062] Understandably, since the shadow register can quickly update its configuration without affecting the real register, executing step S20 can effectively reduce the possibility of pipeline flushing and improve system efficiency.

[0063] In one feasible embodiment, step S20 may include steps S21 to S23:

[0064] Step S21: The setting instruction is identified and decoded through a preset pipeline level to extract the address or identifier of the preset shadow register;

[0065] It should be noted that the preset pipeline level usually refers to a specific stage in the processor pipeline responsible for instruction decoding or execution (e.g., the decoding stage or the execution stage), ensuring that the processing of setup instructions (such as VSET) is synchronized with the execution of other instructions.

[0066] Specifically, firstly, in the preset pipeline-level instruction fetching or decoding stage, the instruction obtained in step S10 is identified as a setting instruction by the instruction opcode. For example, the instruction opcode of a setting instruction may be defined as 0x1A, distinguishing it from the instruction opcodes of other instructions (such as VADD, VMUL).

[0067] Then, the fields in the setting instruction are decoded to obtain the address or identifier of the shadow register that needs to be updated, as well as the new configuration values ​​(such as vector length and data type) provided in the setting instruction. Based on the decoding result, the identifier of the target shadow register is set. For example, if the shadow register group has 8 registers with an address range of 0x00 to 0x07, then the identifier SHADOW_REG_0 corresponds to address 0x00.

[0068] By using the above steps, setting instructions are processed at specific stages of the pipeline to ensure seamless integration between shadow register updates and the decoding and execution of vector computation instructions.

[0069] Step S22: Locate the target shadow register based on the address or identifier of the shadow register;

[0070] It should be noted that shadow registers are typically implemented as register files, containing multiple register units, each with a unique address or identifier. The target register is accessed directly via the address bus or control signals.

[0071] Specifically, the address or identifier extracted in step S21 is used as a strobe signal generated by the address decoder. For example, if the target address is 0x03, the fourth register in the shadow register group is strobe. Furthermore, it is checked whether the target shadow register is occupied by other instructions or is in a protected state. If a conflict exists, the current operation is paused or the priority issue is resolved through an arbitration mechanism.

[0072] Step S23: Calculate the current value of the setting instruction and write the current value of the setting instruction into the target shadow register to obtain the first updated value.

[0073] Specifically, if the set instruction provides an immediate value, that value is used directly as the new configuration value. If the set value needs to be based on the value of another register, data is read from the specified general-purpose register as the new value.

[0074] Then, the calculated new value is written to the target shadow register located in step S22 via the data bus. For example, if the target register address is 0x03, the new value is written to the register unit corresponding to that address. For example, if the target register address is 0x03, the new value is written to the register unit corresponding to that address, and this new value is used as the first update value.

[0075] By introducing a shadow register through the above steps, instruction updates can be written directly to the shadow register early in the pipeline, without waiting for the instruction to be committed to the real register. This allows vector computation instructions to be decoded and executed immediately using the latest configuration values, avoiding performance losses caused by pipeline flushing (such as jump prediction failures).

[0076] Step S30: Use a preset real register to recover the data of the first updated value and obtain the second updated value;

[0077] It should be noted that the real register is the authoritative value for storing vector configurations in the processor, and its contents are only updated after an instruction is successfully committed. It serves as a backup to the shadow register, used to restore the erroneous value of the shadow register to the correct value when pipeline anomalies are detected (such as jump prediction failures or pipeline flushing).

[0078] The second update value is a new value obtained by restoring the erroneous value of the shadow register to the correct value of the real register. This value ensures the correctness of the vector configuration, enabling subsequent instructions to execute based on a reliable configuration.

[0079] Understandably, since the shadow register is updated before the instruction is committed, and the instruction that updates this shadow register may not be committed at all due to pipeline flushing, the updated value of the shadow register is incorrect. Therefore, step S30 is executed to restore the incorrect value in the shadow register through the real register of the subsequent pipeline.

[0080] In one feasible embodiment, step S30 may include step S31:

[0081] Step S31: Restore the data of the preset shadow register using the correct value in the preset real register to replace the first update value, obtain the restored value of the preset shadow register, and determine the restored value of the shadow register as the second update value.

[0082] When a setup instruction is not committed due to a pipeline anomaly (such as jump prediction failure, interruption, or pipeline flushing), its updated shadow register value (first updated value) will become an error value, which may cause subsequent vector instructions to be executed based on the incorrect configuration.

[0083] Therefore, in this implementation, the correct value of the real register is used to overwrite the erroneous value of the shadow register to ensure system state consistency, and a second updated value is generated for use by subsequent instructions.

[0084] In another feasible embodiment, step S31 may further include steps S311 to S313:

[0085] Step S311: Read the correct value of the preset real register;

[0086] Specifically, the vector configuration values ​​(such as vector length and data type) currently stored in the real register are read. It is important to note that since the values ​​in the real registers are only updated after the instruction is successfully committed, they are unaffected by uncommitted instructions and are always valid values.

[0087] Step S312: Recover the erroneous value in the preset shadow register according to the correct value of the preset real register to obtain the preset shadow register after data recovery;

[0088] The erroneous value in the shadow register is restored based on the correct value of the real register. That is, the correct value of the real register is used to overwrite the current erroneous value (first update value) of the shadow register, resulting in the shadow register after data recovery.

[0089] Step S313: Read the recovered value from the preset shadow register after data recovery, and determine the recovered value as the second update value.

[0090] The correct recovered value is output through the shadow register after data recovery, and this recovered value is confirmed as the second updated value.

[0091] Through the above steps, the processor can efficiently utilize the collaborative working mechanism of shadow registers and real registers to quickly recover from misconfigurations caused by pipeline anomalies and ensure the continuity and correctness of vector operation instructions.

[0092] Step S40: Execute the vector calculation instruction based on the second updated value.

[0093] Understandably, since the restored value of the shadow register (i.e. the second updated value) has been verified and corrected by the correct value of the real register, ensuring the consistency and reliability of the vector configuration, executing step S40 can ensure that the system can seamlessly continue the vector operation task after the abnormal recovery.

[0094] In one feasible embodiment, step S40 may include steps S41 to S42:

[0095] Step S41: Input the second updated value into the preset vector decoder, and perform a decoding operation in conjunction with the vector calculation instruction to obtain the decoding information of the vector calculation instruction;

[0096] Specifically, after obtaining the second updated value (recovered value) output by the shadow register after data recovery in step S30, this second updated value is immediately transmitted to the vector decoder to participate in the decoding operation of the vector instruction, generating accurate decoding information. That is, the second updated value is used to parse information such as the operand range and data type of the vector calculation instruction. For example, if the second updated value indicates that the vector length is 256, the decoder will parse that the vector calculation instruction needs to process 256 elements. If the second updated value indicates that the data type is floating-point, the decoder will select the floating-point unit (FPU) for subsequent execution.

[0097] Step S42: The decoded information is transmitted to a preset vector processing unit through a preset pipeline-level transmission mechanism, and the vector calculation instruction is performed using the second update value.

[0098] It should be noted that pipelined transfer mechanisms refer to the hardware pathways and protocols for transferring data and control information between different stages of the processor pipeline. They typically include latches, buffers, bypass networks, and control signals.

[0099] Specifically, the decoded information (including the second update value) is sent to the vector processing unit without interruption through the pipeline execution stage via a preset pipeline-level transmission mechanism.

[0100] After receiving the decoded information, the vector processing unit determines the specific operation range and method based on the second update value (such as vector length and data type) in the decoded information. During vector computation, the number of iterations or the segmented processing range is determined based on the vector length. An appropriate computation unit is selected based on the data type. Data is loaded from the shadow register file based on the operand address.

[0101] By utilizing the collaborative working mechanism of shadow registers and real registers through the above embodiments, no pipeline flushing action can be generated. Vector instructions and set instructions are executed without interruption, and there is no pipeline flushing, thus avoiding the cost of pipeline flushing.

[0102] Please see Figure 3 The following embodiments use the aforementioned personal computer as the execution subject, and specifically illustrate the application of the method provided in the second embodiment of this application to an instruction processing method. The instruction processing method provided in this application, before step S312, further includes the following steps A1-A2:

[0103] Step A1: Monitor the execution status of the preset pipeline level. If the execution status of the preset pipeline level is detected to be abnormal, determine whether the setting instruction is an abnormal instruction.

[0104] Step A2: If the setting instruction is an abnormal instruction, then the current value of the preset shadow register is determined to be an error value.

[0105] Compared to the first embodiment, in this embodiment, by explicitly monitoring the pipeline status and determining the undo requirement of the set instruction, the affected shadow register can be identified more accurately, thereby reducing unnecessary recovery operations and improving the efficiency and flexibility of the system.

[0106] Specifically, firstly, the status of each stage of the pipeline is monitored in real time through hardware monitoring modules (such as pipeline state machines or anomaly detection units). Key states to be monitored include, but are not limited to, jump prediction failures, interrupt requests, and pipeline flushing requests. Furthermore, status registers are used to record the current operational status of multiple pipeline stages.

[0107] If a pipeline-level abnormal state is detected, query the instruction queue at the time of the abnormality to confirm whether there are any uncommitted configuration instructions, and determine whether the configuration instructions need to be revoked due to the abnormality.

[0108] If it is confirmed that the setting instruction needs to be revoked due to an error, the value updated by the instruction in the shadow register is marked as an "error value". Specifically, a flag (such as Error_Flag) is set in the shadow register file to indicate whether the current value is an error.

[0109] By using the methods described in the above embodiments, and by explicitly monitoring the pipeline status and determining the cancellation requirements of the setting instructions, the affected shadow registers can be identified more accurately, avoiding unnecessary recovery operations.

[0110] Please see Figure 4 The following embodiments use the aforementioned personal computer as the execution subject, and specifically illustrate the application of the method provided in the third embodiment of this application to an instruction processing method. The instruction processing method provided in this application embodiment further includes the following steps B1-B4 before step S41:

[0111] Step B1: Verify whether the second updated value is consistent with the correct value of the real register;

[0112] Step B2: If they match, send a status update signal to the preset pipeline level.

[0113] Step B3: Based on the status update signal, release the pause state of the preset pipeline level and obtain the instruction address;

[0114] Step B4: Based on the instruction address, input the second update value into the preset vector decoder to execute the vector calculation instruction.

[0115] Compared to the first and second embodiments, in this embodiment, by adding a verification mechanism and a state update signal design, the reliability of the system and the continuity of the pipeline can be significantly improved.

[0116] Specifically, after the operation to restore the erroneous value of the shadow register is completed, a hardware comparator is used to verify whether the second updated value is consistent with the correct value of the real register, ensuring the accuracy of the restoration result.

[0117] If verification fails, the system logs an error or triggers a reset to prevent the spread of incorrect configurations.

[0118] If verification is successful, an explicit status update signal is sent to lift the pipeline-level pause, ensuring the system can quickly resume normal operation. After lifting the pause, the instruction address is quickly obtained to ensure seamless follow-up instructions and avoid performance loss due to waiting.

[0119] Finally, based on the obtained instruction address, the second update value is input into the vector decoder to generate decoding information.

[0120] By introducing a verification mechanism and a state update signal, the accuracy of the recovery operation is ensured and the pipeline pause state is quickly lifted through the above-described embodiments, thereby significantly improving the overall performance and fault tolerance of the processor.

[0121] For example, to help understand the implementation flow of the instruction processing method obtained by combining this embodiment with the above embodiment one, please refer to... Figure 5 , Figure 5 A simplified flowchart of an instruction processing method is provided, specifically:

[0122] Based on the existing design, this embodiment designs a shadow register. The shadow register predicts the execution of pipeline instructions and obtains the latest value in advance. When an instruction that needs to be flushed is executed, the erroneous update value is backed up and restored using the real register to keep it consistent with the value of the real register.

[0123] like Figure 5As shown, a shadow register is designed in the next stage of the decoder pipeline. When the set instruction arrives at the pipeline containing the shadow register, it updates the register. At this time, the vector computation instruction is being decoded in the decoder pipeline of the execution unit. The updated register value can be immediately sent to the decoder to participate in the decoding operation of the vector instruction. The decoded information of the vector computation instruction can be sent to the vector processing unit for vector operation without interruption. No pipeline flushing occurs. The vector computation instruction and the set instruction are executed without interruption, and there is no pipeline flushing, thus avoiding the pipeline flushing cost.

[0124] However, since the shadow register is updated before the instruction is committed, and the instruction that updates this shadow register may not be committed at all due to pipeline flushing, the update of the shadow register is incorrect. In this case, the value of the shadow register needs to be restored using the real register of the subsequent pipeline. Figure 5 As shown, Figure 6 A flowchart illustrating the process of restoring the value of the shadow register to the real register.

[0125] Depend on Figure 6 As we can see, the shadow register has been modified by a set instruction, and the vector operation instruction is retrieving data from the shadow register. However, a pipeline flush occurs at this point. For example, if the set instruction was preceded by a jump instruction, and the jump prediction fails during execution, the pipeline needs to be flushed to redirect the instruction address. However, the next set instruction has already modified the shadow register. Therefore, the value of the shadow register used by subsequent vector instructions will be incorrect. The real register, on the other hand, is only updated by committed instructions and is always correct. When this happens, overwriting the shadow register with the real register restores the incorrectly updated shadow register to its correct value, allowing subsequent vector instructions to continue using the shadow register's value without error.

[0126] The above-described method not only improves performance by providing data for the arithmetic instructions in advance using the prediction mechanism of the preset shadow register, but also solves the problem of subsequent instruction execution errors caused by speculative execution errors that may occur due to the shadow register.

[0127] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0128] Please see Figure 7 One embodiment of this application provides an instruction processing apparatus, including:

[0129] The acquisition module 10 is used to acquire setting instructions and vector calculation instructions from a preset instruction local memory or instruction cache;

[0130] Update module 20 is used to update the preset shadow register according to the setting instruction to obtain the first update value;

[0131] Recovery module 30 is used to recover data from the first updated value using a preset real register and obtain the second updated value;

[0132] The execution module 40 is used to execute the vector calculation instruction according to the second updated value.

[0133] For specific limitations regarding the aforementioned instruction processing device, please refer to the limitations on the instruction processing method above, which will not be repeated here. Each module in the aforementioned instruction processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0134] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 8 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements one of the instruction processing methods described above. It includes: memory and a processor; the memory stores a computer program; and the processor executes the computer program to implement any step of the instruction processing method described above.

[0135] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, can perform any of the steps in the instruction processing method described above.

[0136] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0137] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0138] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0139] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0140] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0141] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An instruction processing method, characterized in that, The method includes: Retrieve setup instructions and vector calculation instructions from the preset instruction local memory or instruction cache; The preset shadow register is updated according to the setting instruction to obtain the first update value; The first updated value is recovered using a preset real register to obtain the second updated value; The vector calculation instruction is executed based on the second updated value.

2. The method as described in claim 1, characterized in that, The step of updating the preset shadow register according to the setting instruction to obtain the first update value includes: The preset pipeline level identifies and decodes the setting instructions, and extracts the address or identifier of the preset shadow register; Locate the target shadow register based on its address or identifier; Calculate the current value of the setting instruction and write the current value of the setting instruction into the target shadow register to obtain the first updated value.

3. The method as described in claim 1, characterized in that, The step of restoring the first updated value using a preset real register to obtain the second updated value includes: The preset shadow register is restored by using the correct value in the preset real register to replace the first update value, the restored value of the preset shadow register is obtained, and the restored value of the shadow register is determined as the second update value.

4. The method as described in claim 3, characterized in that, The step of restoring data to the shadow register using the correct value in the preset real register to replace the first update value, obtaining the restored value of the shadow register, and determining the restored value of the shadow register as the second update value includes: Read the correct value of the preset real register; The incorrect values ​​in the preset shadow register are recovered based on the correct values ​​of the preset real register to obtain the preset shadow register after data recovery; The recovered value is read from the preset shadow register after the data is recovered, and the recovered value is determined as the second update value.

5. The method as described in claim 4, characterized in that, Before the step of restoring the erroneous value in the preset shadow register based on the correct value of the preset real register to obtain the preset shadow register after data recovery, the following steps are included: Monitor the execution status of the preset pipeline level. If the execution status of the preset pipeline level is detected to be abnormal, determine whether the setting instruction is an abnormal instruction. If the setting instruction is an abnormal instruction, then the current value of the preset shadow register is determined to be an error value.

6. The method as described in claim 1, characterized in that, The step of executing the vector calculation instruction based on the second updated value includes: The second updated value is input into the preset vector decoder, and the vector calculation instruction is combined with it to perform a decoding operation to obtain the decoding information of the vector calculation instruction. The decoded information is transmitted to a preset vector processing unit through a preset pipeline-level transmission mechanism, and the vector calculation instruction is performed using the second update value.

7. The method as described in claim 6, characterized in that, Before the step of inputting the second updated value into the preset vector decoder and performing a decoding operation in conjunction with the vector calculation instruction to obtain the decoding information of the vector calculation instruction, the following steps are included: Verify whether the second updated value is consistent with the correct value of the actual register; If they match, a status update signal is sent to the preset pipeline level; Based on the status update signal, the pause state of the preset pipeline level is released and the instruction address is obtained; Based on the instruction address, the second update value is input into the preset vector decoder to execute the vector calculation instruction.

8. An instruction processing device, characterized in that, The instruction processing device includes: The acquisition module is used to acquire setting instructions and vector calculation instructions from a preset instruction local memory or instruction cache; The update module is used to update the preset shadow register according to the setting instruction to obtain the first update value; The recovery module is used to recover the data of the first updated value using a preset real register and obtain the second updated value; An execution module is used to execute the vector calculation instruction based on the second updated value.

9. An instruction processing device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the instruction processing method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the instruction processing method as described in any one of claims 1 to 7.

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