Ion trap chip and quantum computing device

Abstract

The application discloses an ion trap chip and a quantum computing device, and relates to the chip technical field.The ion trap chip comprises a radio frequency electrode and two direct current electrodes, the radio frequency electrode and the direct current electrodes are both configured as sheet electrodes, the radio frequency electrode is stacked between the two direct current electrodes and defines a hollow region together; wherein, each direct current electrode is provided with a direct current electrode introduction part, the radio frequency electrode is provided with a radio frequency electrode introduction part, the direct current electrode introduction part is used for introducing a direct current into the hollow region, the radio frequency electrode introduction part is used for introducing a radio frequency current into the hollow region, and ions are controlled in the hollow region. The ion trap chip of the embodiment of the application can reduce the distance between the direct current electrode and the radio frequency electrode, improve the sensitivity and speed of the electric potential control, and further improve the precision of ion control and the experimental rhythm, so as to facilitate the control of ions.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more particularly to an ion trap chip and a quantum computing device. Background Technology

[0002] A qubit is the basic unit of quantum computing, and increasing its number can significantly improve the computing power of a quantum computer. As the number of qubits increases, more demands are placed on ion trap chips. Furthermore, with the development of manipulation and applications, more experiments involving the manipulation of ions are needed. However, in related technologies, the distance between the DC electrode and the radio frequency electrode is relatively large. When adjusting the DC voltage, the ions respond slowly to voltage changes, affecting the experimental pace and indicating room for improvement. Summary of the Invention

[0003] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes an ion trap chip, which can effectively reduce the distance between the DC electrode and the radio frequency electrode, improve the sensitivity and speed of potential control, thereby improving the precision of ion manipulation, accelerating the experimental pace, and making it more conducive to ion manipulation.

[0004] An ion trap chip according to an embodiment of the present invention includes: a radio frequency electrode and two direct current electrodes, both of which are constructed as sheet electrodes. The radio frequency electrode is stacked between the two direct current electrodes and together defines a hollow region. Each direct current electrode has a direct current electrode introduction portion, and the radio frequency electrode has a radio frequency electrode introduction portion. The direct current electrode introduction portion is used to introduce direct current into the hollow region, and the radio frequency electrode introduction portion is used to introduce radio frequency current into the hollow region, and to manipulate ions within the hollow region.

[0005] According to the ion trap chip of the present invention, by setting a DC electrode and a radio frequency electrode, a hollow area can be defined to accommodate ions. By setting a DC electrode introduction part and a radio frequency electrode introduction part, DC current and radio frequency current can be introduced into the hollow area respectively to bind and manipulate ions. Moreover, by constructing both the DC electrode and the radio frequency electrode as sheet electrodes and stacking the radio frequency electrode between the two DC electrodes, the distance between the DC electrode and the radio frequency electrode can be effectively reduced, which can improve the sensitivity and speed of potential control, thereby improving the accuracy of ion manipulation, accelerating the experimental pace, and making it more conducive to ion manipulation.

[0006] According to some embodiments of the ion trap chip of the present invention, the DC electrode includes a first substrate layer, and the DC electrode introduction portion is configured as a first electroplated layer disposed on the surface of the first substrate layer; and / or, the RF electrode includes a second substrate layer, and the RF electrode introduction portion is configured as a second electroplated layer disposed on the surface of the second substrate layer.

[0007] According to some embodiments of the ion trap chip of the present invention, the first substrate layer has a first slope formed on the side away from the radio frequency electrode at the edge near the cutout region, the thickness of the first substrate layer at the first slope is set to gradually decrease along the direction near the cutout region, and the first electroplated layer includes a current-carrying section extending to the first slope.

[0008] According to some embodiments of the ion trap chip of the present invention, the first substrate layer has an introduction tooth formed on the end face near the hollow region, the introduction tooth protruding toward the hollow region, and the end of the current introduction segment extending to the surface of the introduction tooth toward the hollow region.

[0009] According to some embodiments of the ion trap chip of the present invention, the angle between the first inclined surface and the surface of the first substrate layer opposite to the radio frequency electrode is α, and satisfies: 20°≤α≤40°.

[0010] According to some embodiments of the ion trap chip of the present invention, the second substrate layer has a second inclined surface formed on both sides near the edge of the cutout region, and the thickness of the second substrate layer near the edge of the cutout region is set to gradually decrease in the direction near the cutout region, and the first substrate layer of each DC electrode is spaced apart from the corresponding second inclined surface to form a separation gap.

[0011] According to some embodiments of the ion trap chip of the present invention, the angle between the surface of the second substrate layer that is attached to the first substrate layer and the second inclined surface is β, and satisfies: 20°≤β≤40°.

[0012] According to some embodiments of the ion trap chip of the present invention, a first substrate layer of one of the two DC electrodes is provided with a clearance notch, and the radio frequency electrode introduction extends to the clearance notch and is adapted to be electrically connected to an external circuit at the clearance notch.

[0013] According to some embodiments of the ion trap chip of the present invention, the hollowed-out area includes a storage area, a control area and a temporary storage area, the storage area and the temporary storage area are respectively connected to the control area, and the DC current and the radio frequency current are adapted to be introduced into the control area for ion control.

[0014] According to some embodiments of the ion trap chip of the present invention, there is one storage area, two control areas, and two sets of temporary storage areas. The storage area is connected between the two control areas, and the two sets of temporary storage areas are respectively connected to the two control areas in a one-to-one correspondence; and / or, each control area is connected to three temporary storage areas, and the three temporary storage areas are arranged in a cross shape with the corresponding control area.

[0015] According to some embodiments of the ion trap chip of the present invention, a sealing gap is formed between the DC electrode and the RF electrode, and each DC electrode has at least one potting notch, the potting notch communicating with the sealing gap and being adapted to pot glue into the sealing gap through the potting notch.

[0016] The present invention also proposes a quantum computing device.

[0017] The quantum computing device according to embodiments of the present invention includes the ion trap chip described in any of the above embodiments.

[0018] The quantum computing device and the aforementioned ion trap chip have the same advantages over existing technologies, which will not be elaborated here.

[0019] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0021] Figure 1 This is a schematic diagram of the structure of an ion trap chip according to an embodiment of the present invention. Figure 1 ;

[0022] Figure 2 yes Figure 1 A magnified view of a section at point A in the middle;

[0023] Figure 3 This is a schematic diagram of the structure of an ion trap chip according to an embodiment of the present invention. Figure 2 ;

[0024] Figure 4 This is a schematic diagram of the structure of an ion trap chip according to an embodiment of the present invention. Figure 3 ;

[0025] Figure 5 yes Figure 4 A magnified view of a section at point B in the middle;

[0026] Figure 6 A cross-sectional schematic diagram of an ion trap chip according to an embodiment of the present invention;

[0027] Figure 7 This is a schematic diagram of the distribution of the hollowed-out areas according to an embodiment of the present invention. Figure 1 ;

[0028] Figure 8 This is a schematic diagram of the distribution of the hollowed-out areas according to an embodiment of the present invention. Figure 2 .

[0029] Figure label:

[0030] Ion trap chip 100,

[0031] RF electrode 1, RF electrode introduction portion 11, second substrate layer 12, second inclined surface 13.

[0032] DC electrode 2, DC electrode introduction section 21, current introduction section 211, first substrate layer 22, introduction tooth 221, first bevel 23, clearance notch 24, potting notch 25.

[0033] Hollowed-out area 3, storage area 31, control area 32, temporary storage area 33.

[0034] 4. Separation gap, 5. Sealing gap, 6. Mounting hole. Detailed Implementation

[0035] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0036] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, features defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0037] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0038] The following is for reference. Figures 1-8 The ion trap chip 100 according to an embodiment of the present invention is described in which both the DC electrode 2 and the radio frequency electrode 1 are constructed as sheet electrodes, and the radio frequency electrode 1 is stacked between the two DC electrodes 2. This can effectively reduce the distance between the DC electrode 2 and the radio frequency electrode 1, improve the sensitivity and speed of potential control, thereby improving the accuracy of ion manipulation, accelerating the experimental pace, and making it more conducive to ion manipulation.

[0039] like Figures 1-6 As shown, an ion trap chip 100 according to an embodiment of the present invention includes: a radio frequency electrode 1 and two DC electrodes 2.

[0040] Both the radio frequency electrode 1 and the DC electrode 2 are constructed as sheet electrodes. The radio frequency electrode 1 is stacked between the two DC electrodes 2 and together defines a hollow region 3. Each DC electrode 2 is provided with a DC electrode introduction part 21, and the radio frequency electrode 1 is provided with a radio frequency electrode introduction part 11. The DC electrode introduction part 21 is used to introduce DC current into the hollow region 3, and the radio frequency electrode introduction part 11 is used to introduce radio frequency current into the hollow region 3, and to manipulate ions within the hollow region 3.

[0041] Specifically, the ion trap chip 100 is a high-precision device that traps ions based on the synergistic effect of electromagnetic and laser fields. Its core function is to achieve quantum computing through precise manipulation of ions. The ion trap chip 100 includes a radio frequency electrode 1 and a DC electrode 2. The radio frequency electrode 1 is used to generate a high-frequency alternating electric field to form a dynamic trapping potential trap, while the DC electrode 2 is used to control the position and trajectory of ions through a static potential gradient. The two work together to achieve precise trapping and manipulation of ions.

[0042] The device comprises two DC electrodes 2, which are stacked to form a stable axial potential well, enabling precise control of the axial movement of ions. Furthermore, a radio frequency (RF) electrode 1 is stacked between the two DC electrodes 2, allowing the RF electrode 1 and the two DC electrodes 2 to jointly define a hollow region 3. This is achieved by hollowing out the middle of both the RF electrode 1 and the DC electrode 2, with the hollowed-out areas on the DC electrode 2 and the RF electrode 1 facing each other. This hollow region 3 provides space for ions to be stored or manipulated, and allows the RF electrode 1 to move closer to the DC electrode 2, reducing the distance between them and facilitating ion manipulation.

[0043] It should be noted that during the design phase, neither of the two DC electrodes 2 is polarized. In use, positive or negative voltages can be selectively applied to the two DC electrodes 2 to make them polarized. Moreover, the binding potential used to trap ions is formed by superimposing the radio frequency potential generated by the radio frequency electrode 1 and the DC potential generated by the DC electrode 2. To manipulate ions, it is necessary to regulate the entire binding potential of the trapped ions. This is mainly achieved by controlling the DC potential of the DC electrode 2. Changing the voltage applied to the DC electrode 2 can directly regulate the DC potential.

[0044] When the distance between DC electrode 2 and RF electrode 1 is closer, the DC potential has a greater impact on the overall binding potential. That is, the overall binding potential is more sensitive to DC voltage, which can improve the sensitivity and speed of potential control, thereby improving the accuracy of ion manipulation, accelerating the experimental pace, and making it more conducive to ion manipulation. Moreover, when the distance between DC electrode 2 and RF electrode 1 is closer, the potential field is deeper under the same RF voltage, and the external input RF power can be lower, which helps to reduce the impact of thermal effects on ion manipulation, can also bind ions more stably, enhance the resistance to background gas collisions, and help to extend the ion lifetime.

[0045] Furthermore, by constructing both the radio frequency electrode 1 and the two DC electrodes 2 as sheet-like electrodes, both the radio frequency electrode 1 and the DC electrodes 2 can be constructed as thin sheets, such as sheets with a thickness of 0.2 mm. This facilitates the stacking of the radio frequency electrode 1 between the two DC electrodes 2, and can further reduce the distance between the radio frequency electrode 1 and the DC electrodes 2, so as to better control the ions. It can also make the overall structure more compact, which is beneficial to reduce the size of the ion trap chip 100.

[0046] It should be noted that the distance between the DC electrode 2 and the RF electrode 1 in the ion trap chip 100 of the present invention can be 200-400 μm, which can effectively improve the ion response speed.

[0047] Furthermore, each DC electrode 2 is provided with a DC electrode introduction portion 21, which is used to introduce DC current into the hollow region 3. The DC electrode introduction portion 21 is configured to extend from the end of the DC electrode 2 away from the hollow region 3 toward the direction closer to the hollow region 3, so that the DC electrode introduction portion 21 can introduce external DC current into the hollow region 3. At the same time, the radio frequency electrode 1 is provided with a radio frequency electrode introduction portion 11, which is used to introduce radio frequency current into the hollow region 3. The radio frequency electrode introduction portion 11 is configured to extend from the end of the radio frequency electrode 1 away from the hollow region 3 toward the direction closer to the hollow region 3, so that the radio frequency electrode introduction portion 11 can introduce external radio frequency current into the hollow region 3. Thus, the DC current and the radio frequency current can jointly form an electric field in the hollow region 3 to precisely trap and manipulate ions.

[0048] According to the ion trap chip 100 of the present invention, by providing a DC electrode 2 and a radio frequency electrode 1, a hollow region 3 can be defined to accommodate ions. By providing a DC electrode introduction portion 21 and a radio frequency electrode introduction portion 11, DC current and radio frequency current can be introduced into the hollow region 3 respectively to bind and manipulate ions. Moreover, by constructing both the DC electrode 2 and the radio frequency electrode 1 as sheet electrodes and stacking the radio frequency electrode 1 between the two DC electrodes 2, the distance between the DC electrode 2 and the radio frequency electrode 1 can be effectively reduced, which can improve the sensitivity and speed of potential control, thereby improving the accuracy of ion manipulation, accelerating the experimental pace, and making it more conducive to ion manipulation.

[0049] In some embodiments, the DC electrode 2 includes a first substrate layer 22, and the DC electrode introduction portion 21 is configured as a first electroplated layer disposed on the surface of the first substrate layer 22; and / or, the RF electrode 1 includes a second substrate layer 12, and the RF electrode introduction portion 11 is configured as a second electroplated layer disposed on the surface of the second substrate layer 12.

[0050] In other words, the DC electrode 2 includes a first substrate layer 22 and a DC electrode introduction part 21. The first substrate layer 22 is the skeleton of the DC electrode 2 and can play a structural support role. The DC electrode introduction part 21 is constructed as a first electroplated layer on the surface of the first substrate layer 22. The DC electrode introduction part 21 can be attached to the surface of the first substrate layer 22 by electroplating. This can ensure that the DC current can be reliably introduced into the hollow area 3, and the DC electrode 2 can be a whole structure, which can improve its structural strength and operational reliability.

[0051] The DC electrode introduction part 21 is electroplated on the surface of the first substrate layer 22. The first substrate layer 22 can be used to withstand the mechanical stress of the first electroplated layer during processing, electrode assembly and experimentation. Therefore, the first substrate layer 22 needs to have high strength, high rigidity and low coefficient of thermal expansion. For example, it can be made of materials such as silicon or ceramic. The DC electrode introduction part 21 is used to introduce external DC current into the hollow area 3. That is, the DC electrode introduction part 21 needs to have good conductivity. For example, the first electroplated layer can be a gold plating layer, a silver plating layer or a copper plating layer, etc., to ensure the reliability of introducing DC current into the hollow area 3, and thus ensure the reliability of ion manipulation.

[0052] Meanwhile, the radio frequency electrode 1 includes a second substrate layer 12 and a radio frequency electrode introduction portion 11. The second substrate layer 12 is the skeleton of the radio frequency electrode 1 and can play a structural support role. The radio frequency electrode introduction portion 11 is constructed as a second electroplating layer on the surface of the second substrate layer 12. The radio frequency electrode introduction portion 11 can be attached to the surface of the second substrate layer 12 by electroplating. This can ensure that the radio frequency current can be reliably introduced into the hollow area 3, and the radio frequency electrode 1 can be a whole structure, which can improve its structural strength and operational reliability.

[0053] The radio frequency electrode introduction part 11 is electroplated on the surface of the second substrate layer 12. The second substrate layer 12 can be used to withstand the mechanical stress of the second electroplated layer during processing, electrode assembly and experimentation. Therefore, the second substrate layer 12 needs to have high strength, high rigidity and low coefficient of thermal expansion. For example, it can be made of materials such as silicon or ceramic. The radio frequency electrode introduction part 11 is used to introduce external radio frequency current into the hollow area 3. That is, the radio frequency electrode introduction part 11 needs to have good conductivity. For example, the second electroplated layer can be a gold plating layer, a silver plating layer or a copper plating layer, etc., to ensure the reliability of introducing radio frequency current into the hollow area 3, and thus ensure the reliability of ion manipulation.

[0054] It should be noted that both the first substrate layer 22 and the second substrate layer 12 can be made of ceramic material, and the ceramic material can be alumina, zirconium oxide, etc. The first electroplating layer and the second electroplating layer can be used to provide the binding potential of ions in a certain direction to manipulate the spatial position of ions such as transport, exchange, and turning.

[0055] In some embodiments, the first substrate layer 22 has a first slope 23 formed on the side away from the radio frequency electrode 1 near the edge of the cutout region 3. The thickness of the first substrate layer 22 at the first slope 23 is set to gradually decrease in the direction near the cutout region 3. The first electroplated layer includes a current-carrying section 211 extending to the first slope 23.

[0056] Specifically, the first inclined surface 23 is disposed at the edge of the first substrate layer 22 near the hollow area 3, so that the first inclined surface 23 faces the hollow area 3 and extends a certain distance from the edge of the first substrate layer 22 near the hollow area 3 in a direction away from the hollow area 3, so that the first inclined surface 23 can have a certain length. The thickness of the first substrate layer 22 at the first inclined surface 23 is set to gradually decrease along the direction near the hollow area 3, so that the first inclined surface 23 is constructed to extend inclinedly from the side of the first substrate layer 22 away from the radio frequency electrode 1 in a direction near the hollow area 3 towards the radio frequency electrode 1. In other words, the surface of the first substrate layer 22 away from the radio frequency electrode 1 moves closer to the radio frequency electrode 1 along the first inclined surface 23, so as to further reduce the distance between the DC electrode 2 and the radio frequency electrode 1, and allow the control laser to irradiate the hollow area 3 from a wider angle range, thereby improving the light transmission.

[0057] In other words, when the control laser irradiates the hollow area 3 from a direction that forms a certain angle with the surface of the first substrate layer 22, the first substrate layer 22 can avoid blocking the control laser, thereby improving the reliability of ion control by the control laser. It can also prevent the control laser from irradiating too much onto the surface of the ion trap chip 100, thereby preventing the accumulation of stray charges on the DC electrode 2 from affecting ion control and thus effectively ensuring the reliability of ion control.

[0058] Furthermore, the first electroplated layer includes a current-introducing section 211. By extending the current-introducing section 211 to the first inclined surface 23, an external DC current can be introduced into the hollow area 3 through the current-introducing section 211, so as to ensure that the DC current and the radio frequency current can jointly generate an electric field in the hollow area 3, and reliably control the ions. The current-introducing section 211 can be electroplated on the first inclined surface 23 to realize the setting of the current-introducing section 211 and ensure the reliable operation of the current-introducing section 211.

[0059] In some embodiments, the first substrate layer 22 has an introduction tooth 221 formed on the end face near the cutout region 3. The introduction tooth 221 protrudes into the cutout region 3, and the end of the current introduction section 211 extends to the surface of the introduction tooth 221 facing into the cutout region 3.

[0060] Specifically, the tooth 221 is formed on the end face of the first substrate layer 22 near the hollow region 3, and the tooth 221 protrudes into the hollow region 3. The tooth 221 extends the first substrate layer 22 into the hollow region 3, so that the first electroplated layer on the surface of the first substrate layer 22 can introduce DC current into the hollow region 3. Furthermore, the end of the current guiding section 211 extends to the surface of the tooth 221 facing the hollow region 3. The current guiding section 211 extends the first electroplated layer from the side surface of the first substrate layer 22 away from the radio frequency electrode 1 to the side surface facing the hollow region 3. Thus, the external DC current can be introduced from the outside of the ion trap chip 100 into the hollow region 3 through the first electroplated layer, so that the DC current and the radio frequency current can jointly generate an electric field in the hollow region 3 to reliably control the ions.

[0061] It should be noted that, as Figures 1-5 As shown, there are multiple introduction teeth 221, which are spaced apart along the extension direction of the hollow region 3. This allows the multiple introduction teeth 221 to introduce DC current to different positions within the hollow region 3. In this way, the DC voltage introduced by the multiple introduction teeth 221 can be controlled to reliably manipulate ions located at different positions within the hollow region 3. Moreover, the extension length of the hollow region 3 is relatively large, meaning that a large number of introduction teeth 221 can be set at the edge of the hollow region 3. Increasing the number of introduction teeth 221 can increase the amount of DC current that can be introduced, which is beneficial to improving the computing power of the quantum computing device.

[0062] In some embodiments, the angle between the first inclined surface 23 and the surface of the first substrate layer 22 facing away from the radio frequency electrode 1 is α, and satisfies: 20°≤α≤40°.

[0063] Specifically, such as Figure 6 As shown, the first inclined surface 23 is inclined relative to the side surface of the first substrate layer 22 facing away from the radio frequency electrode 1, and the angle between the first inclined surface 23 and the side surface of the first substrate layer 22 facing away from the radio frequency electrode 1 is α, and α is between 20° and 40°, such as 25°, 30° or 35°, etc., to avoid α being too large or too small. When α is too large, the extension length of the first inclined surface 23 is small, which may cause the first substrate layer 22 to block the control laser at the first inclined surface 23, which may lead to the accumulation of stray charges on the DC electrode 2, affecting ion control. When α is too small, the extension length of the first inclined surface 23 is large, which may increase the processing difficulty.

[0064] In some embodiments, the second substrate layer 12 has a second inclined surface 13 on both sides near the edge of the hollow region 3, and the thickness of the second substrate layer 12 near the edge of the hollow region 3 is set to gradually decrease in the direction near the hollow region 3. The first substrate layer 22 of each DC electrode 2 is spaced apart from the corresponding second inclined surface 13 to form a separation gap 4.

[0065] Specifically, the second inclined surface 13 is disposed at the edge of the second substrate layer 12 near the hollow area 3, so that the second inclined surface 13 faces the hollow area 3. The second inclined surface 13 is formed on both sides of the second substrate layer 12, so that the two second inclined surfaces 13 are symmetrically arranged, thus making the second substrate layer 12 a symmetrical structure. The second inclined surface 13 extends a certain distance from the edge of the second substrate layer 12 near the hollow area 3 in a direction away from the hollow area 3, so that the second inclined surface 13 can have a certain length. The thickness of the second substrate layer 12 near the edge of the hollow area 3 is set to gradually decrease in the direction of approaching the hollow area 3. Thus, the two second inclined surfaces 13 are constructed to extend inclinedly from both sides of the second substrate layer 12 in a direction of approaching each other in the direction of approaching the hollow area 3, so that the second substrate layer 12 moves away from the DC electrode 2 along the two second inclined surfaces 13.

[0066] This allows the first substrate layer 22 of each DC electrode 2 to be spaced apart from the corresponding second inclined surface 13 to form a separation gap 4. This creates a separation gap 4 between both DC electrodes 2 and the RF electrode 1. The separation gap 4 is used to prevent the second electroplated layer from contacting the DC electrode 2, thereby ensuring the reliability of the DC electrode 2 and the RF electrode 1 in introducing DC current and RF current into the hollow area 3, respectively, so as to jointly form an electric field in the hollow area 3 to reliably control the ions. Furthermore, the design of the separation gap 4 can prevent short circuits caused by gold plating overflow during the electroplating of the second electroplated layer.

[0067] It should be noted that by setting the first inclined plane 23 and the second inclined plane 13, the distribution of electric field lines can be changed, making the electric field more uniform and reducing electric field distortion. This results in a more stable trapping electric field, which can better trap ions, reduce the micro-movement of ions, and increase the effective length of the DC electrode introduction part 21 and the radio frequency electrode introduction part 11. This can increase the electric field strength under the same voltage, further enhancing the trapping electric field. Moreover, it can reduce stress concentration, improve the vibration resistance of the ion trap chip 100, and improve the installation accuracy, ensuring that the relative position and angle of the DC electrode 2 and the radio frequency electrode 1 meet the design requirements, thereby improving the quality of the trapping electric field.

[0068] In some embodiments, the angle between the surface of the second substrate layer 12 that is attached to the first substrate layer 22 and the second inclined surface 13 is β, and satisfies: 20°≤β≤40°.

[0069] Specifically, such as Figure 6 As shown, the second inclined surface 13 is inclined relative to the surface of the second substrate layer 12 near the DC electrode 2, so that the angle between the surface of the second substrate layer 12 that is in contact with the first substrate layer 22 and the second inclined surface 13 is β, that is, the angle between the second inclined surface 13 and the surface of the second substrate layer 12 near the DC electrode 2 is β, and β is between 20° and 40°, such as 25°, 30° or 35°, to avoid β being too large or too small. When β is too large, the extension length of the second inclined surface 13 is small, which may cause the second inclined surface 13 to contact the DC electrode 2, which may reduce the reliability of the DC electrode 2 and the RF electrode 1 in introducing DC current and RF current into the hollow area 3. When β is too small, the extension length of the second inclined surface 13 is large, which may reduce the connection area between the DC electrode 2 and the RF electrode 1, which may reduce the overall structural strength of the ion trap chip 100, which is not conducive to improving the reliability of the ion trap chip 100.

[0070] In some embodiments, the first substrate layer 22 of one of the two DC electrodes 2 is provided with a clearance notch 24, and the radio frequency electrode introduction portion 11 extends to the clearance notch 24 and is adapted to be electrically connected to an external circuit at the clearance notch 24.

[0071] Specifically, the radio frequency electrode 1 is located between two DC electrodes 2, and the radio frequency electrode 1 has a radio frequency electrode introduction portion 11. The radio frequency electrode introduction portion 11 is used to introduce radio frequency current into the hollow area 3. An avoidance notch 24 is provided on the first substrate layer 22 of one of the DC electrodes, so that the avoidance notch 24 can be selectively provided on any one of the first substrate layers 22, which can improve the flexibility of the setting. The avoidance notch 24 is used to avoid the radio frequency electrode introduction portion 11. Extending the radio frequency electrode introduction portion 11 to the avoidance notch 24, the radio frequency electrode introduction portion 11 can be exposed outward at the avoidance notch 24, so that the second electroplated layer can be electrically connected to the external circuit through the radio frequency electrode introduction portion 11, such as being electrically connected to the external circuit board, so that the second electroplated layer can reliably introduce the external radio frequency current into the hollow area 3 through the radio frequency electrode introduction portion 11.

[0072] like Figure 1 and Figure 4 As shown, the clearance notch 24 can be provided at the end of one of the first substrate layers 22, that is, the radio frequency electrode introduction part 11 can also be provided at the end of the second substrate layer 12, so as to connect the radio frequency electrode introduction part 11 to the external circuit at the end of the radio frequency electrode 1, and reduce the difficulty of providing the clearance notch 24 on the first substrate layer 22.

[0073] It should be noted that the DC electrode introduction section 21 and the radio frequency electrode introduction section 11 are respectively arranged facing different sides of the ion trap chip 100, so as to connect the DC electrode 2 and the radio frequency electrode 1 to the external circuit respectively, and to avoid interference between the DC electrode introduction section 21 and the radio frequency electrode introduction section 11, thereby improving the reliability of their respective electrical connections to the external circuit, and thus improving the reliability of ion manipulation.

[0074] In some embodiments, the hollowed-out area 3 includes a storage area 31, a control area 32, and a temporary storage area 33. The storage area 31 and the temporary storage area 33 are respectively connected to the control area 32, and the DC current and the radio frequency current are suitable for being introduced into the control area 32 for ion manipulation.

[0075] Specifically, storage area 31 is the region for loading ions, where ions can be captured and subsequently moved to other regions via ion transport technology. In other words, storage area 31 can be used to store ions before ion manipulation. Manipulation area 32 is the region for manipulating ions, including cooling, single-bit flipping, and two-bit gate manipulation. In other words, manipulation area 32 can provide space for ion manipulation. Temporary storage area 33 is the region for temporarily storing ions for use during the operation of the quantum circuit. During the operation of the circuit, ions storing quantum information can be transferred to temporary storage area 33 through ion exchange, transport, and other manipulations until the circuit needs to use the ions again or the circuit operation ends.

[0076] The hollowed-out area 3 is divided into different regions, each corresponding to a different function. This supports flexible large-scale ion manipulation and provides technical support for realizing large-scale quantum computing. Furthermore, the storage area 31 and the temporary storage area 33 are connected to the manipulation area 32, allowing ions to enter the manipulation area 32 from the storage area 31 or the temporary storage area 33 for ion manipulation, or vice versa, from the manipulation area 32 to the temporary storage area 33 for temporary storage, so that they can be manipulated again later.

[0077] Furthermore, DC current and RF current can be introduced into the manipulation area 32 so that DC current and RF current can jointly form an electric field to manipulate ions, thereby enabling quantum computing. DC current and RF current can also be introduced into the storage area 31 so that DC current and RF current can jointly form an electric field to capture ions, facilitating subsequent ion manipulation. Moreover, DC current and RF current can also be introduced into the temporary storage area 33 so that DC current and RF current can jointly form an electric field to temporarily store ions.

[0078] It should be noted that the first substrate layer 22 has a plurality of introduction teeth 221, which are spaced apart. The plurality of introduction teeth 221 can be extended to the storage area 31, the control area 32 and the temporary storage area 33 respectively. By controlling the voltage of the DC current introduced by the plurality of introduction teeth 221 corresponding to each area, different operations can be performed on ions located in different areas, ensuring the reliability of accurate ion control. There are also a plurality of corresponding DC electrode introduction parts 21, which correspond one-to-one with the plurality of introduction teeth 221. The plurality of introduction teeth 221 are electrically connected to external circuits through the plurality of DC electrode introduction parts 21, so that the voltage applied to the DC current introduced by the plurality of DC electrode introduction parts 21 can be controlled separately, thereby controlling the ions in different areas separately.

[0079] Furthermore, by functionally partitioning the hollowed-out region 3, a QCCD architecture can be realized, allowing ions to move between different functional regions and ensuring that the fidelity of each quantum operation does not decrease with the increase of the number of ions.

[0080] In some embodiments, there is one storage area 31, two control areas 32, and two sets of temporary storage areas 33. The storage area 31 is connected between the two control areas 32, and the two sets of temporary storage areas 33 are respectively connected to the two control areas 32 in a one-to-one correspondence; and / or, each control area 32 is connected to three temporary storage areas 33, and the three temporary storage areas 33 are arranged in a cross shape with the corresponding control area 32.

[0081] Specifically, such as Figures 7-8 As shown, a storage area 31 is set as one, through which ions can be captured. Two control areas 32 are set, each of which can independently control a group of ion chains. The two control areas 32 can realize the parallel operation of two groups of qubits, which can improve the computational efficiency of quantum computing devices. Two temporary storage areas 33 are set, and each group can include one or more temporary storage areas 33, which can effectively increase the number of temporary storage areas 33. Multiple ions can be temporarily stored at the same time, and different ion chains or qubits can be measured at the same time, so as to significantly shorten the overall calculation cycle.

[0082] Meanwhile, by connecting the storage area 31 to the two control areas 32, ions in the storage area 31 can enter one of the control areas 32 as needed, which can reduce the number of storage areas 31 and thus reduce the space occupied by the storage areas 31, which is beneficial to reduce the size of the ion trap chip 100. Furthermore, the two sets of temporary storage areas 33 are connected to the two control areas 32 one by one, that is, for each set of temporary storage areas 33, a control area 32 is provided to be connected to it, so that ions in the control area 32 can be reliably stored or ions in the temporary storage area 33 can be reliably controlled.

[0083] Or, such as Figures 1-4 and Figure 8 As shown, each control area 32 can also be connected to three temporary storage areas 33 simultaneously, which can temporarily store ions in multiple processes. The three temporary storage areas 33 and the corresponding control area 32 are arranged in a cross shape, which can separate the three temporary storage areas 33 to isolate the ions in different temporary storage areas 33. It can also make the three temporary storage areas 33 relatively close to the control area 32, so that the ions can move between the control area 32 and the temporary storage area 33.

[0084] It should be noted that when the hollow area 3 includes multiple temporary storage areas 33, the ions in one of the temporary storage areas 33 can be manipulated so that they can enter other temporary storage areas 33 for storage and use.

[0085] In some embodiments, a sealing gap 5 is formed between the DC electrode 2 and the RF electrode 1, and each DC electrode 2 has at least one potting notch 25, which is connected to the sealing gap 5 and is adapted to pot adhesive into the sealing gap 5 through the potting notch 25.

[0086] Specifically, the radio frequency electrode 1 is stacked between two DC electrodes 2, and a sealing gap 5 is formed between the DC electrodes 2 and the radio frequency electrode 1. The sealing gap 5 is used to allow adhesive to flow inside, so as to connect the radio frequency electrode 1 and the DC electrode 2 by adhesive bonding. This makes the ion trap chip 100 a whole structure, which can improve its structural strength and operational reliability. Moreover, the adhesive bonding method is simple, reliable and easy to operate. At the same time, each DC electrode 2 has at least one potting notch 25. That is, the number of potting notches 25 on each DC electrode 2 can be one, two or three, etc. The potting notch 25 is connected to the sealing gap 5, so that the user can pour adhesive into the sealing gap 5 through the potting notch 25 to realize the connection and fixation of the radio frequency electrode 1 and the DC electrode 2.

[0087] Furthermore, the potting notch 25 is recessed inward from the end of the DC electrode 2, so that glue can be poured into the sealing gap 5 from the potting notch 25. Through self-absorption and gravity, the glue can slowly seep into the sealing gap 5, thus completing the fixation of the RF electrode 1 and the DC electrode 2. At the same time, it can also prevent the glue from flowing to the outer surface of the ion trap chip 100.

[0088] like Figures 1-2As shown, each DC electrode 2 has two potting notches 25, and the four potting notches 25 are located at different positions of the ion trap chip 100. For example, the four potting notches 25 can be set at the four vertices of the ion trap chip 100, and glue can be potted from different positions at the same time, which improves the connection reliability between the RF electrode 1 and the DC electrode 2. Alternatively, two potting notches 25 can be set on the RF electrode 1, and the two potting notches 25 on the RF electrode 1 can be set opposite to the potting notch 25 on one of the DC electrodes 2, so as to increase the number of potting notches 25 and further improve the connection reliability between the RF electrode 1 and the DC electrode 2.

[0089] In addition, the ion trap chip 100 is provided with two spaced-apart mounting holes 6. The mounting holes 6 can be used to pass through connectors to realize the installation and fixation of the ion trap chip 100 to ensure its reliable operation. The electrode spacing of the ion trap chip 100 can be 50μm, and the electrode pad can be 50μm.

[0090] The present invention also proposes a quantum computing device.

[0091] The quantum computing device according to embodiments of the present invention includes an ion trap chip 100 of any of the above embodiments. DC current and radio frequency current can be introduced into the hollow region 3 through the DC electrode introduction portion 21 and the radio frequency electrode introduction portion 11 respectively to confine and manipulate ions. The radio frequency electrode 1 is stacked between two DC electrodes 2, which effectively reduces the distance between the DC electrode 2 and the radio frequency electrode 1. Simultaneously, the provision of the first inclined surface 23 and the second inclined surface 13 further reduces the distance between the DC electrode 2 and the radio frequency electrode 1, improving the sensitivity and speed of potential modulation, thereby enhancing the accuracy of ion manipulation, accelerating the experimental pace, and making ion manipulation more advantageous. Furthermore, the first substrate layer 22 has multiple introduction teeth 221. By increasing the number of introduction teeth 221, the amount of introduced DC current can be increased, which is beneficial for improving the computing power of the quantum computing device, and the quantum computing device can be a quantum computer.

[0092] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0093] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. An ion trap chip, characterized in that, include: The device includes a radio frequency (RF) electrode and two DC electrodes, both of which are constructed as sheet electrodes. The RF electrode is stacked between the two DC electrodes. The middle of both the RF electrode and the DC electrode is hollowed out, and the hollowed-out areas on the RF electrode and the DC electrode are aligned to jointly define the hollowed-out area. Each of the DC electrodes is provided with a DC electrode introduction portion, and the radio frequency electrode is provided with a radio frequency electrode introduction portion. The DC electrode introduction portion is used to introduce DC current into the hollow area, and the radio frequency electrode introduction portion is used to introduce radio frequency current into the hollow area, and to manipulate ions in the hollow area. The hollowed-out area includes a storage area, a control area, and a temporary storage area. The storage area and the temporary storage area are respectively connected to the control area, and the DC current and the radio frequency current are adapted to be introduced into the control area for ion manipulation.

2. The ion trap chip according to claim 1, characterized in that, The DC electrode includes a first substrate layer, and the DC electrode introduction portion is configured as a first electroplated layer disposed on the surface of the first substrate layer; And / or, the radio frequency electrode includes a second substrate layer, and the radio frequency electrode introduction portion is configured as a second electroplated layer disposed on the surface of the second substrate layer.

3. The ion trap chip according to claim 2, characterized in that, The first substrate layer has a first slope formed on the side away from the radio frequency electrode at the edge near the cutout area. The thickness of the first substrate layer at the first slope is set to gradually decrease along the direction near the cutout area. The first electroplated layer includes a current-carrying section extending to the first slope.

4. The ion trap chip according to claim 3, characterized in that, The first substrate layer has an introductory tooth formed on the end face near the cutout area. The introductory tooth protrudes into the cutout area, and the end of the current introductory section extends to the surface of the introductory tooth facing the cutout area.

5. The ion trap chip according to claim 3, characterized in that, The angle between the first inclined surface and the surface of the first substrate layer facing away from the radio frequency electrode is α, and satisfies: 20°≤α≤40°.

6. The ion trap chip according to claim 2, characterized in that, The second substrate layer has a second inclined surface formed on both sides near the edge of the hollow area, and the thickness of the second substrate layer near the edge of the hollow area is set to gradually decrease in the direction near the hollow area. The first substrate layer of each DC electrode is spaced apart from the corresponding second inclined surface to form a separation gap.

7. The ion trap chip according to claim 6, characterized in that, The angle between the surface of the second substrate layer that is bonded to the first substrate layer and the second inclined surface is β, and satisfies: 20°≤β≤40°.

8. The ion trap chip according to claim 2, characterized in that, One of the two DC electrodes has a clearance notch in its first substrate layer, and the radio frequency electrode introduction extends to the clearance notch and is adapted to be electrically connected to an external circuit at the clearance notch.

9. The ion trap chip according to claim 1, characterized in that, The storage area is one, the control area is two, and the temporary storage area is two groups. The storage area is connected between the two control areas, and the two groups of temporary storage areas are respectively connected to the two control areas one by one. And / or, each of the control areas is connected to three of the temporary storage areas, and the three temporary storage areas are arranged in a cross shape with the corresponding control area.

10. The ion trap chip according to claim 1, characterized in that, A sealing gap is formed between the DC electrode and the RF electrode. Each DC electrode has at least one potting notch, which communicates with the sealing gap and is adapted to pot glue into the sealing gap through the potting notch.

11. A quantum computing device, characterized in that, The ion trap chip includes any one of claims 1-10.

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