Control circuit based on shift register identification codes and control method thereof

Abstract

The invention discloses a control circuit based on shift register identification codes and a control method thereof.The control circuit comprises a register U1, a phase inverter U2, an AND gate U3 and an AND gate U4, specific coding signals are identified under excitation of clock signals, a post-stage circuit is driven to complete the functions of charging, discharging and the like, and the control circuit has the advantages of being simple in structure, low in cost and high in reliability. Different coding signals independently drive a post-stage circuit to achieve different functions and have uniqueness, the coding signals cannot drive the post-stage circuit to work when no clock signal exists, other coding signals except a specified coding signal are not responded, the safety of the control circuit is improved, meanwhile, software is not used, software engineering work is reduced, and the cost is reduced. The product development period is shortened.

Description

Technical Field

[0001] This invention relates to a control circuit and control method based on shift register recognition encoding. Background Technology

[0002] The main function of the detonation control circuit is to respond to charging and detonation commands, charge and store energy, then discharge and ignite to detonate the electric detonator and initiate the detonation sequence. During its operation, the detonation control circuit must be safe and reliable, and must not be accidentally charged or detonated due to environmental interference, which could lead to serious consequences. In detonation control circuits without microcontrollers, charging and detonation commands are typically single-level signals or pulse signals. These signals are easily interfered with during transmission, or the system containing the detonation control circuit may generate identical or similar pulse signals. Without a microcontroller, it is difficult to determine the authenticity of the charging or detonation commands, such as the amplitude and width of the pulse signal. This invention is a software-free, code-based detonation control circuit design. Driven by a clock signal, it identifies external input codes, and different codes drive different subsequent circuits to achieve the charging and detonation functions respectively.

[0003] Currently, the implementation method of detonation control circuit using microcontroller is as follows: Figure 2 As shown, the microcontroller identifies charging and detonation commands through an optocoupler receiving circuit, controlling the charging circuit to charge or the discharging circuit to discharge, outputting detonation energy, and igniting the electric detonator. Figure 3 The diagram shows a detonation control circuit implementation without a microcontroller. Charging and detonation commands are directly input to control the charging and discharging circuits, outputting detonation energy, and igniting the electric detonator. Using a microprocessor involves software engineering, increasing the engineering design workload and prolonging the development cycle. Furthermore, circuit design often requires consideration of power isolation, resulting in higher hardware costs. Summary of the Invention

[0004] The purpose of this invention is to address the problem of high cost of existing controllers by providing a control circuit that does not use software and is reliably identified by being driven by both clock signals and encoded signals.

[0005] The technical solution of the present invention: A control circuit and control method based on shift register identification encoding, including register U1, inverter U2, AND gate U3 and AND gate U4; The input ports of the register are connected to the clock signal and the encoded data respectively. The QA pin of the register is connected to pin 2 of AND gate U3 and pin 12 of AND gate U4. The QB pin is connected to pin 3 of AND gate U3 and pin 11 of AND gate U4. The QC pin is connected to pin 4 of AND gate U3 and pin 10 of AND gate U4. The QD pin is connected to pin 1 of inverter U2 and pin 9 of AND gate U4. The QE pin is connected to pin 9 of AND gate U3 and pin 9 of inverter U2. The QF pin is connected to pin 3 of inverter U2 and pin 5 of AND gate U4. The QG pin is connected to pins 5 and 11 of inverter U2. The QH pin is connected to pin 12 of AND gate U3 and pin 13 of inverter U2. Pin 2 of the inverter is connected to pin 5 of AND gate U3, pin 4 is connected to pin 10 of AND gate U3, pin 6 is connected to pin 11 of AND gate U3, pin 8 is connected to pin 2 of AND gate U4, pin 10 is connected to pin 3 of AND gate U4, and pin 12 is connected to pin 4 of AND gate U4. The output terminals of AND gates U3 and U4 respectively output pulse signals.

[0006] The register U1 is an eight-bit serial-in parallel-out shift register 74HC595M.

[0007] The inverter U2 is model 74HC04D.

[0008] The AND gate is model CD4068BM.

[0009] A control circuit and its control method based on shift register recognition encoding. (1) The host computer sends a time signal to excite the register; (2) The register reads the encoded signal transmitted by the host computer; (3) When the encoded signal is the same as the predetermined code, the inverter sets the data that is 0 to 1 and turns on the working circuit by outputting a pulse signal through the AND gate.

[0010] The encoded signal is an eight-bit binary encoded signal.

[0011] The rising edge of the clock signal is located in the middle of each bit of the encoded signal.

[0012] The frequency of the clock signal does not exceed 20MHz.

[0013] The beneficial effects of this invention are: Under the excitation of a clock signal, specific coded signals are identified to drive subsequent circuits to complete functions such as charging and discharging. Different coded signals independently drive subsequent circuits to achieve different functions and are unique. Without a clock signal, the coded signal cannot drive the subsequent circuit to work and does not respond to other coded signals besides the specified coded signal, which improves the safety of the control circuit. At the same time, no software is used, reducing software engineering work and shortening the product development cycle. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the control circuit.

[0015] Figure 2 This is a schematic diagram of an existing control circuit structure with a microprocessor.

[0016] Figure 3 This is a schematic diagram of an existing control circuit structure that does not have a microprocessor. Detailed Implementation

[0017] A control circuit and control method based on shift register identification encoding, including register U1, inverter U2, AND gate U3 and AND gate U4; The input ports of the register are connected to the clock signal and the encoded data respectively. The QA pin of the register is connected to pin 2 of AND gate U3 and pin 12 of AND gate U4. The QB pin is connected to pin 3 of AND gate U3 and pin 11 of AND gate U4. The QC pin is connected to pin 4 of AND gate U3 and pin 10 of AND gate U4. The QD pin is connected to pin 1 of inverter U2 and pin 9 of AND gate U4. The QE pin is connected to pin 9 of AND gate U3 and pin 9 of inverter U2. The QF pin is connected to pin 3 of inverter U2 and pin 5 of AND gate U4. The QG pin is connected to pins 5 and 11 of inverter U2. The QH pin is connected to pin 12 of AND gate U3 and pin 13 of inverter U2. Pin 2 of the inverter is connected to pin 5 of AND gate U3, pin 4 is connected to pin 10 of AND gate U3, pin 6 is connected to pin 11 of AND gate U3, pin 8 is connected to pin 2 of AND gate U4, pin 10 is connected to pin 3 of AND gate U4, and pin 12 is connected to pin 4 of AND gate U4. The output terminals of AND gates U3 and U4 respectively output pulse signals.

[0018] The register U1 is an eight-bit serial-in parallel-out shift register 74HC595M.

[0019] The inverter U2 is model 74HC04D.

[0020] The AND gate is model CD4068BM.

[0021] A control circuit and its control method based on shift register recognition encoding. (1) The host computer sends a time signal to excite the register; (2) The register reads the encoded signal transmitted by the host computer; multiple codes are identified by combining hardware circuits, so that this circuit can drive different subsequent circuits.

[0022] (3) When the encoded signal is the same as the predetermined code, the inverter sets the data that is 0 to 1 and turns on the working circuit by outputting a pulse signal through the AND gate. The encoded signal and the clock signal must be input at the same time to work, which ensures the safety of the circuit.

[0023] The encoded signal is an eight-bit binary encoded signal.

[0024] The rising edge of the clock signal is located in the middle of each bit of the encoded signal.

[0025] The frequency of the clock signal does not exceed 20MHz.

[0026] Example: Figure 1 As shown, the encoding recognition circuit mainly consists of an 8-bit serial-in parallel-out shift register 74HC595M, an inverter 74HC04D, and an AND gate CD4068BM. It can recognize the input encoded signal without software and will not misrecognize incorrect codes.

[0027] The 74HC595M in the encoding recognition circuit reads the charging signal code (11101101) and the discharging signal code (11110100) under clock signal excitation. After identifying and outputting bit by bit, the corresponding encoded signal is identified through the combined action of inverter 74HC04D and AND gate CD4068BM. The encoding recognition circuit uses an 8-bit serial-in parallel-out shift register U1 to identify the corresponding encoded data in each clock cycle under a specific frequency clock signal input, and shifts and outputs QA to QH. When the QA to QH data is the same as the predetermined code (11101101) / (11110100), inverter 74HC04D sets the data that is 0 to 1, and outputs a pulse signal through AND gate CD4068BM. The pulse signal width is the same as the clock cycle. The 8-bit serial-in parallel-out shift register U1 operates at a maximum clock frequency of approximately 20MHz under +5V power supply, so the encoding recognition circuit can reliably identify the encoded signal under a clock signal of ≤20MHz.

[0028] The charging signal is encoded as input, and the output pulse signal from the AND gate CD4068BM excites the charging circuit. The charging circuit is connected to the power supply (+22V~+32V), and the internal energy storage capacitor charges and stores energy. The discharging signal is encoded as input, and the output pulse signal from the AND gate CD4068BM excites the discharging circuit, opening the discharge path. The internal energy storage capacitor of the charging circuit discharges, and the electric detonator receives the energy and ignites.

[0029] Requirements for clock signal and encoded signal input: The rising edge of the clock signal should be in the middle of each encoding position, and it is only suitable for short-line transmission. When the distance is too long, the driving capability of the input end and the influence of parasitic inductance and parasitic capacitance on the transmission line should be considered, otherwise the signal is prone to distortion.

[0030] Input encoding combination method: The input encoding is confirmed through hardware circuit design without the need for software logic control. The encoding bit length is ≤8 bits. When multiple encodings are input, it should be considered in advance whether continuous input of encodings will generate other valid encodings, or each encoding should be separated by multiple bits of 0.

[0031] Clock signal frequency setting: Although the encoding recognition circuit can reliably recognize the encoding signal under a clock signal of ≤20MHz, the width of its output excitation signal (charging control signal / detonation control signal) is limited by the clock frequency. If the clock frequency is too high, it is necessary to consider whether it can drive the subsequent circuit.

[0032] Encoding recognition circuit response time: The recognition time of each code is limited by the number of bits in the code and the clock frequency. For example, if an 8-bit code is input under the excitation of a 500kHz clock signal, the minimum time of the encoding recognition circuit is ≥16µs.

[0033] In the design of the detonation control circuit, this invention eliminates the need for software design. The type of encoding can be determined during circuit design and can be combined in multiple ways, reducing the development cycle and cost. Two different signal inputs are required for driving the circuit, and neither can be omitted. Compared to single-level signals and pulse signals, the encoded signal has a lower probability of false charging and false detonation when affected by environmental interference, thus improving the safety of the detonation control circuit in production, testing, and operational use.

Claims

1. A control circuit based on shift register recognition encoding, characterized in that: This includes register U1, inverter U2, AND gate U3, and AND gate U4; The input ports of the register are connected to the clock signal and the encoded data respectively. The QA pin of the register is connected to pin 2 of AND gate U3 and pin 12 of AND gate U4. The QB pin is connected to pin 3 of AND gate U3 and pin 11 of AND gate U4. The QC pin is connected to pin 4 of AND gate U3 and pin 10 of AND gate U4. The QD pin is connected to pin 1 of inverter U2 and pin 9 of AND gate U4. The QE pin is connected to pin 9 of AND gate U3 and pin 9 of inverter U2. The QF pin is connected to pin 3 of inverter U2 and pin 5 of AND gate U4. The QG pin is connected to pins 5 and 11 of inverter U2. The QH pin is connected to pin 12 of AND gate U3 and pin 13 of inverter U2. Pin 2 of the inverter is connected to pin 5 of AND gate U3, pin 4 is connected to pin 10 of AND gate U3, pin 6 is connected to pin 11 of AND gate U3, pin 8 is connected to pin 2 of AND gate U4, pin 10 is connected to pin 3 of AND gate U4, and pin 12 is connected to pin 4 of AND gate U4. The output terminals of AND gates U3 and U4 respectively output pulse signals.

2. The control circuit based on shift register recognition encoding according to claim 1, characterized in that: The register U1 is an eight-bit serial-in parallel-out shift register 74HC595M.

3. The control circuit based on shift register recognition encoding according to claim 1, characterized in that: The inverter U2 is model 74HC04D.

4. The control circuit based on shift register recognition encoding according to claim 1, characterized in that: The AND gate is model CD4068BM.

5. The control circuit based on shift register recognition encoding according to claims 1-4, characterized in that: (1) The host computer sends a time signal to excite the register; (2) The register reads the encoded signal transmitted by the host computer; (3) When the encoded signal is the same as the predetermined code, the inverter sets the data that is 0 to 1 and turns on the working circuit by outputting a pulse signal through the AND gate.

6. The control method based on the shift register recognition encoding control circuit according to claim 1, characterized in that: The encoded signal is an eight-bit binary encoded signal.

7. The control method based on the shift register recognition encoding control circuit according to claim 1, characterized in that: The rising edge of the clock signal is located in the middle of each bit of the encoded signal.

8. The control method based on the shift register recognition encoding control circuit according to claim 1, characterized in that: The frequency of the clock signal does not exceed 20MHz.

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