GSM timing system and GSM timing method applied to O-RU

Abstract

The invention provides a GSM (Global System for Mobile Communications) timing system and a GSM timing method applied to an O-RU (Open Radio Access Unit), relates to the technical field of an O-RAN (Open Radio Access Network), and solves the problems of timing generation and synchronization when the GSM timing system is realized on an O-RU platform. The system is deployed in an O-RU under an O-RAN architecture, and generates a GSM frame / time slot timing signal according to a 1 PPS pulse per second and TOD information provided by a PTP protocol, so that the O-RU supports a 2G GSM system; the system comprises a GSM timing generator and a GSM timing regulator. The timing generator determines a timing reference starting point according to synchronization characteristics of a TOD second field and a 3-second period, and outputs a reference timing signal; the timing regulator generates independent uplink and downlink timing signals on the basis of a reference timing signal. According to the method, efficient implementation on an FPGA platform is supported, and a reliable basis is established for complete implementation of the GSM communication function in the O-RU.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of open radio access network (O-RAN), and particularly relates to a GSM timing system and a GSM timing method applied to an O-RU (open radio unit). BACKGROUND

[0002] The second generation mobile communication technology (2G GSM), represented by the global system for mobile communications (GSM), was the first globally unified digital mobile communication standard, widely deployed in the 1990s, and laid the foundation for the development of modern mobile communication. This technology not only promoted the popularization of mobile communication, but also introduced digital voice and short message services, becoming an important starting point for subsequent technology evolution. Although current 4G and 5G mobile communication technologies have become the global mainstream, providing high-speed data connections and enhanced features, GSM continues to operate in Europe, Africa, and some developing regions, supporting voice calls, text messages, and low-speed data transmission. These services not only serve a large number of existing users, but are also widely used in Internet of Things devices such as remote monitoring and simple sensor applications, so operators must maintain the stable operation of these networks to meet regional demand and ensure service continuity.

[0003] Open radio access network (O-RAN) is an emerging network architecture that promotes the decoupling and multi-vendor interoperability of radio access network (RAN) devices by defining open interfaces and standardized protocols, thereby enhancing the flexibility and scalability of network deployment. This architecture aims to break the limitations of traditional proprietary systems, reduce the dependence of operators on a single vendor, and promote innovation and cost optimization. Currently, the O-RAN Alliance has completed the standardization of front-haul interface specifications for 4G LTE and 5G NR, including protocols based on enhanced universal public radio interface (eUPi), which ensure interoperability between devices and efficient data transmission. The 4G / 5G dual-mode system based on open radio unit (O-RU) has been successfully deployed in multiple trial networks, demonstrating the potential of this architecture in supporting modern communication technologies and gradually transitioning to commercial applications.

[0004] However, the O-RAN protocol system mainly focuses on 4G / 5G technology and does not support 2G GSM system, especially the Global System for Mobile Communications (GSM). The key missing part is the definition of the GSM timing synchronization mechanism, which is a core element for the normal operation of the network and ensures the accuracy and reliability of signal transmission. For operators who still need to operate GSM networks, when using the O-RAN architecture, it is not possible to integrate multiple generations of communication systems on a unified platform. Existing O-RU devices only support 4G / 5G communication technology and cannot directly carry GSM services, which forces operators to maintain separate network infrastructure. This fragmentation of architecture not only increases hardware and software investment but also increases the complexity of operation and maintenance, such as device management, troubleshooting, and upgrade costs, limiting the improvement of network efficiency and the smooth transition to an open architecture.

[0005] Therefore, it is crucial for operators to integrate multiple generations of networks, reduce operating costs, and improve service continuity to implement GSM support within the O-RAN framework, especially to solve the problem of basic mechanisms such as timing synchronization. The industry needs an innovative technology to fill the gap in the protocol system to ensure that GSM functions can seamlessly integrate into existing architectures, thereby eliminating network fragmentation and promoting resource optimization and future technology evolution. SUMMARY

[0006] The purpose of the present application is to solve the problem of GSM timing generation and synchronization when implementing the GSM timing system on the O-RU platform. Therefore, a GSM timing system and method applied to O-RU are proposed. Based on the existing protocol framework, the present application divides GSM into three parts: timing system, uplink, and downlink. By multiplexing the existing PTP time synchronization in O-RU and combining the requirements of GSM frame structure, high-precision GSM frame timing generation is achieved. The present application supports efficient implementation on the FPGA platform and optimizes the design according to the timing characteristics and resource utilization of FPGA, thereby establishing a reliable foundation for the complete implementation of GSM communication functions in O-RU.

[0007] The present application adopts the following technical solutions to achieve the purpose: A GSM timing system applied to O-RU, which is deployed in O-RU under the O-RAN architecture, generates GSM frame / slot timing signals based on the 1 PPS second pulse and TOD information provided by the PTP protocol, enabling O-RU to support 2G GSM system. The system includes a GSM timing generator and a GSM timing regulator. The GSM timing generator is used to determine the GSM timing reference starting point based on the synchronization characteristics of the TOD second field and the 3-second period, and outputs the GSM reference timing signal. The GSM timing regulator is used to generate independent timing signals for uplink and downlink based on the GSM reference timing signal.

[0008] Specifically, the GSM timing generator outputs a GSM reference timing signal including a slot number, a slot head and a frame head.

[0009] Specifically, the GSM timing adjuster is further configured to directly use the slot number, the slot head and the frame head of the GSM reference timing signal as the slot number, the slot head and the frame head corresponding to the independent timing signal of the downlink, so as to generate the downlink timing signal.

[0010] Specifically, the GSM timing adjuster is further configured to perform a -3 offset operation on the slot number, the slot head and the frame head of the GSM reference timing signal, and take the operation result as the slot number, the slot head and the frame head corresponding to the independent timing signal of the uplink, so as to generate the uplink timing signal.

[0011] Preferably, the GSM timing adjuster is further configured to provide a configurable slot offset function, adjust the timing of the uplink or the downlink by receiving a slot number offset value issued by the baseband control unit, and adapt different channel types or network deployment scenarios through the timing adjustment mode; the slot number offset value is in units of GSM slots, and the numerical value corresponds to the number of GSM slots.

[0012] Further, the GSM timing generator is further configured to determine the 3-second period, perform a modulo 3 operation on a second field in the PTP TOD information, and when the operation result is 0, take a rising edge of a current 1 PPS second pulse as a starting point of a corresponding 3-second period, and in this way determine the starting point of each 3-second period, so as to determine a GSM timing reference starting point. According to the basis that the offset between the GSM time and the Unix time is an integer multiple of 3, the GSM timing generator is further configured to align the starting point of the first 3-second period with a GSM system time origin on a time axis.

[0013] Specifically, the GSM timing generator is further configured to divide the corresponding time into 5200 GSM slots in each 3-second period through a counter of the FPGA, and make the time step of each GSM slot be controlled under a system clock based on a preset frequency.

[0014] Preferably, the GSM timing generator is further configured to compensate for the non-integer characteristic of the GSM slot period, and apply a dynamic slot allocation strategy in the 26 GSM slots corresponding to each 15 ms period; the dynamic slot allocation strategy is to set 20 long-period slots and 6 short-period slots, so that the total length of each 15 ms period is exactly equal to the theoretically calculated integer value.

[0015] Specifically, the system is used for simultaneously running communication systems including 4G LTE, 5G NR and 2G GSM under the O-RAN architecture, so that corresponding wireless communication technologies are implemented in the same platform.

[0016] The application also provides a GSM timing method applied to the O-RU, which is based on the GSM timing system and includes the following steps: S1, receiving 1 PPS second pulses and 80-bit TOD information provided by a PTP protocol distribution; S2, extracting a second field from the 80-bit TOD information, and performing a modulo 3 operation on the 1 PPS second pulse every second; S3, when the result of the modulo 3 operation is 0, taking the rising edge of the current 1 PPS second pulse as the starting point of the corresponding 3-second period; S4, for each determined 3-second period, dividing 5200 GSM time slots in the corresponding time by a counter of the FPGA, taking every 26 GSM time slots as a measurement period, and allocating 20 long-period time slots and 6 short-period time slots; S5, for the GSM time slot division and allocation result of each determined 3-second period, determining a corresponding time slot number, a time slot header and a frame header for each GSM time slot, and outputting a GSM reference timing signal; S6, generating independent timing signals of uplink and downlink according to the GSM reference timing signal.

[0017] As described above, by adopting the technical solution, the application has the following beneficial effects: The application solves the problems of GSM timing generation and synchronization on the O-RU platform, and realizes compatible support for the 2G GSM system. The application reuses the existing PTP time synchronization mechanism in the O-RU, combines with the requirements of the GSM frame structure, generates a high-precision timing signal, and ensures the reliable operation of the GSM communication function under the O-RAN architecture. This not only fills the gap of existing protocols in GSM system support, but also optimizes the implementation efficiency of the FPGA platform, improves the resource utilization and timing performance.

[0018] The application enables operators to simultaneously deploy 2G, 4G and 5G networks under a unified O-RAN framework, significantly enhancing the flexibility and evolution capability of the network architecture. This avoids the drawbacks of isolated deployment of traditional systems, reduces operation and maintenance costs, and provides a seamless transition basis for future technology upgrades.

[0019] In addition, the application can help the smooth transition and coexistence of traditional 2G services, and support operators to continuously provide services in specific areas or user demands. This promotes the efficient integration of multiple generations of networks, and improves the stability and continuity of overall communication services. Attached Figure Description

[0020] The present invention further illustrates its embodiments and technical solutions in detail with reference to the following figures, specifically including 5 figures as follows: Figure 1 This is a schematic diagram of the functional architecture of the GSM timing system of the present invention; Figure 2 This is a schematic diagram of the traditional large-bit-width operation based on PTP TOD timestamps; Figure 3 This is a schematic diagram of the starting point detection of the 3-second cycle in this invention; Figure 4 This is a schematic diagram illustrating the distribution effect of the dynamic time slot allocation strategy in this invention after time slot allocation; Figure 5 This is an exemplary schematic diagram of the long-short cycle counter jump state machine in this invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0023] This embodiment provides a GSM timing system applied to O-RU. The architecture and functions of this system can be referred to in conjunction with the following description. Figure 1 The diagram illustrates that it is deployed in the O-RU under the O-RAN architecture. Based on the 1 PPS pulse and TOD information provided by the PTP protocol, it generates GSM frame / time slot timing signals, enabling the O-RU to support the 2G GSM standard.

[0024] In this embodiment, the system includes a GSM timing generator and a GSM timing regulator. The GSM timing generator determines the starting point of the GSM timing reference based on the synchronization characteristics of the TOD second field and the 3-second period, and outputs a GSM reference timing signal. The GSM timing regulator generates independent timing signals for the uplink and downlink respectively based on the GSM reference timing signal.

[0025] Before detailing the specific features of the system in this embodiment, it is necessary to further explain the relevant technical information in order to better understand the system technical solution of this embodiment.

[0026] First, although GSM (Global System for Mobile Communications) is a mature technology in traditional radio unit (RU), it has not yet been defined in the O-RAN (Open Radio Access Network) protocol system as 4G LTE and 5G NR become mainstream. Especially under the O-RU architecture, the lack of support for GSM timing mechanisms makes it difficult for operators to achieve coexistence of multiple generations of communication standards on a unified O-RAN platform. The GSM timing system in this implementation successfully solves this problem, enabling the O-RU to support the 2G GSM standard, thus allowing multiple generations of communication standards to coexist on the same platform.

[0027] GSM uses Time Division Multiple Access (TDMA), and its frame structure differs fundamentally from 4G / 5G. A GSM frame contains 8 timeslots, each lasting approximately 4.615 ms (120 / 26 ms), with each timeslot being approximately 577 μs. The specific multi-level frame structure is shown below: 26-frame traffic multiframe: used for traffic channels, with a period of 120 ms; 51-frame control multiframe: used for control channels, with a period of 244.615 ms; Superframe: Composed of 51 segments of 26 frames each, with a period of 6.12 seconds; Hyperframe: Composed of 2048 superframes, with a period of approximately 3 hours and 28 minutes, and its frame number (FN) ranges from 0 to 2,715,647.

[0028] In contrast, 4G / 5G systems use a 10 ms radio frame as the basic scheduling period, which is not an integer multiple of the 4.615 ms frame period of GSM. Therefore, the existing 10 ms timing mechanism of O-RU cannot be directly reused, and an independent GSM timing system must be designed.

[0029] In the O-RAN architecture, the timing of the O-RU relies on the PTP (Precision Time Protocol, IEEE 1588) protocol. The Open Distributed Unit (O-DU) distributes high-precision time information to the O-RU via a fronthaul network such as eCPRI or Ethernet. The O-RU then recovers 1 PPS (Pulse Per Second) pulses and 80-bit time and date information based on the PTP protocol stack; this time and date information is the TOD (Time of Day) information, conforming to the ITU-T G.8275.1 standard. Traditional 4G / 5G O-RUs can generate 10 ms frame timings using 1 PPS pulses, but this mechanism cannot directly support the non-integer multiple frame structure of GSM.

[0030] Therefore, the GSM timing system of this embodiment, through improved design, can be applied to the O-RU platform. Based on the 1 PPS pulse per second and 80-bit TOD information provided by PTP, it generates a high-precision GSM frame / time slot timing signal and has been deeply optimized for FPGA, thereby solving the resource consumption and timing problems caused by large bit width division and modulo operation in traditional solutions.

[0031] like Figure 1 As shown, the GSM timing generator in the GSM timing system of this embodiment is responsible for generating and outputting the GSM reference timing signal, including slot ID, slot start, and frame start, wherein the slot start and frame start are in the form of corresponding pulse signals.

[0032] Traditional implementations require large-bit-width calculations based on nanosecond-level PTP TOD timestamps; the process can be found in [link to documentation]. Figure 2 The steps can be briefly described as follows: a. Extract PTP TOD and separate the ptp_seconds and ptp_nanoseconds parts from the TOD information; b. Calculate the GSM time: gsm_seconds = ptp_seconds - 315532800; where the GSM time origin is 1980-01-06 00:00:00 UTC, and 315532800 is the offset of Unix time relative to the GSM time origin. c. Calculate the total nanoseconds: gsm_total_ns = gsm_seconds × 1e9 + nanoseconds; d. Calculate the frame number FN, FN=floor(gsm_total_ns / 4,615,384) % 2,715,648; e. Decompose T1 / T2 / T3; T1=floor(FN / (26*51)); T2=FN mod 26; T3=FN mod 51; f. GSM Slot / Frame output, generating slots and frames based on FN / T1 / T2 / T3.

[0033] The traditional implementation method described above requires division and modulo operations of more than 64 bits, which consumes high resources and has difficulty in timing convergence in FPGA, making it unsuitable for high-integration designs.

[0034] To overcome the above problems, this implementation method adopts a highly efficient timing generation method of "3-second cycle mapping", the theoretical basis of which is as follows: The GSM timeslot period is 15 / 26 ms≈577 μs, and 15 ms=26×(15 / 26) ms, meaning that every 15 ms contains exactly 26 GSM timeslots; Furthermore, 60 ms = 4 × 15 ms, which includes 104 GSM time slots; Therefore, 3 s = 50 × 60 ms, which contains a total of 50 × 10⁴ = 5200 GSM time slots.

[0035] According to relevant technical definitions, the GSM time origin is January 6, 1980, while the Unix time origin is January 1, 1970. The offset between the two is 315,532,800 seconds, which is a multiple of 3, i.e., 315,532,800 ÷ 3 = 105,177,600. This indicates that GSM time and Unix time are strictly aligned in a 3-second cycle.

[0036] Based on this characteristic, this implementation method can detect the start point of the 3-second cycle, which is performed by the GSM timing generator in the system and can be viewed synchronously. Figure 3 The illustration is as follows: Using the seconds field in the 80-bit TOD information provided by PTP, namely TOD[79:32], a modulo 3 operation is performed once per second, combining 1 PPS second pulse. When TOD[79:32] mod 3 == 0 is detected, the rising edge of the current 1 PPS pulse is determined to be the precise starting point of a 3-second cycle.

[0037] Once the starting point is determined, the system uses a fixed-step counter within each 3-second cycle to divide the corresponding time into 5200 GSM time slots, thus completely avoiding nanosecond-level large-bit-width operations. This implementation, through this timing synchronization mechanism based on modulo-3 cycle detection, is particularly suitable for achieving high-precision, low-complexity GSM frame timing generation on resource-constrained FPGA platforms. It significantly reduces the FPGA's logic resource consumption and design complexity while ensuring long-term timing accuracy and stability.

[0038] As a preferred embodiment of this method, the above process also needs to compensate for the non-integer characteristic of the GSM time slot period. Since 15,000,000 ns / 4 / 26≈144,230.769 is not an integer, direct counting will introduce accumulated errors. Therefore, this embodiment adopts a dynamic time slot allocation strategy, which can be referred to as... Figure 4 The illustration shows that it can also be done by a GSM timing generator.

[0039] Within each 26 GSM time slots, the following allocations are made: 20 long-cycle time slots: the counting period is 144,231 × 4 ns = 576,924 ns; Six short-cycle time slots: the counting period is 144,230 × 4 ns = 576,920 ns; Therefore, the total duration is: 20×576,924+6×576,920=15,000,000 ns=15 ms.

[0040] This dynamic time slot allocation strategy can control the counter step size through a state machine in the FPGA. (See also...) Figure 5 The exemplary illustration demonstrates how this achieves periodic cancellation of nanosecond-level errors, ensuring long-term timing accuracy. Furthermore, to improve counting accuracy, this embodiment preferably uses a 250 MHz system clock for the FPGA, with a period of 4 ns, enabling time slot boundary control accuracy to reach the 4 ns level, far exceeding the ±1 μs timing error requirement of the GSM system.

[0041] In this embodiment, the GSM timing regulator generates independent timing suitable for uplink and downlink based on the GSM reference timing signal output by the GSM timing generator, as follows: The GSM timing regulator directly uses the slot number, slot header, and frame header of the GSM reference timing signal as the slot number, slot header, and frame header corresponding to the independent timing signal of the downlink, thereby generating the downlink timing signal; According to the GSM protocol, uplink transmission lags behind downlink by 3 time slots, approximately 1.73 ms. Therefore, the GSM timing regulator performs a -3 offset operation on the time slot number, time slot header, and frame header of the GSM reference timing signal. The result of this operation is used as the time slot number, time slot header, and frame header corresponding to the independent timing signal of the uplink, thereby generating the uplink timing signal.

[0042] As a preferred embodiment, the GSM timing regulator also provides a configurable timeslot offset function. By receiving timeslot number offset values ​​from the baseband control unit, it performs additional timing adjustments on the uplink or downlink, and adapts to different channel types, such as TCH, SDCCH, or network deployment scenarios such as microcell synchronization, through this timing adjustment method. The timeslot number offset value is in units of GSM timeslots, and its magnitude corresponds to the number of GSM timeslots. In this way, the flexibility and adaptability of the GSM timing system are effectively improved.

[0043] In this embodiment, the introduction of the time slot offset function enables the GSM timing regulator to dynamically adjust the timing reference of signal processing according to actual communication needs. The baseband control unit can flexibly issue corresponding time slot offset values ​​based on the current service type or network environment. After receiving the offset value, the GSM timing regulator automatically fine-tunes the frame structure of the uplink and downlink. This adjustment does not change the basic frame period and time slot arrangement rules, but rather adds or subtracts a delay or advance of several time slot units on the original timing basis, thereby achieving fine control over the signal transmission and reception timing.

[0044] In different channel applications, such as voice service channels and signaling channels, the differences in data scheduling cycles and processing timing requirements mean that configuring appropriate time slot offsets can ensure precise time alignment between baseband processing and RF transceiver. In special deployment scenarios such as microcells, where signal propagation distances are short and latency is low, this function can also be used to optimize timing advance configuration and avoid signal interference between multiple cells. This mechanism requires no modification to the system hardware structure; switching between various timing strategies can be achieved solely through software configuration. This significantly enhances the compatibility and robustness of the GSM timing system in complex network environments, providing reliable timing guarantees for multi-scenario networking.

[0045] In practical applications, the GSM timing system of this embodiment can be summarized as a GSM timing method applied to O-RU. The key steps of the method can therefore be summarized as follows: S1. Receive 1 PPS pulse per second and 80-bit TOD information distributed by the PTP protocol; S2. Extract the seconds field from the 80-bit TOD information and perform a modulo-3 operation once per second, combining it with 1 PPS of second pulses. S3. When the result of the modulo 3 operation is 0, the rising edge of the current 1 PPS second pulse is taken as the starting point of the corresponding 3-second cycle. S4. For each defined 3-second period, 5200 GSM time slots are divided into the corresponding time period by the FPGA counter. Every 26 GSM time slots are used as a metering period, and 20 long period time slots and 6 short period time slots are allocated. S5. For each determined 3-second period of GSM time slot division and allocation result, determine the corresponding time slot number, time slot header and frame header for each GSM time slot, and then output the GSM reference timing signal. S6. Based on the GSM reference timing signal, generate independent timing signals for the uplink and downlink respectively.

[0046] Ultimately, through the application of its system and method, this implementation method can support the simultaneous operation of 4G LTE, 5G NR and 2G GSM communication standards under the O-RAN architecture, thereby realizing the common platform deployment of multiple generations of wireless communication technologies.

Claims

1. A GSM timing system applied to O-RU, characterized in that: The system is deployed in the O-RU under the O-RAN architecture. Based on the 1 PPS pulse and TOD information provided by the PTP protocol, it generates GSM frame / time slot timing signals, enabling the O-RU to support the 2G GSM standard. The system includes a GSM timing generator and a GSM timing regulator. The GSM timing generator is used to determine the GSM timing reference start point based on the synchronization characteristics of the TOD second field and the 3-second period, and output the GSM reference timing signal; the GSM timing adjuster is used to generate independent timing signals for the uplink and downlink respectively based on the GSM reference timing signal.

2. The GSM timing system according to claim 1, characterized in that: The GSM reference timing signal output by the GSM timing generator includes a timeslot number, a timeslot header, and a frame header.

3. The GSM timing system according to claim 2, characterized in that: The GSM timing regulator is also used to directly use the time slot number, time slot header, and frame header of the GSM reference timing signal as the time slot number, time slot header, and frame header corresponding to the independent timing signal of the downlink, thereby generating the downlink timing signal.

4. The GSM timing system according to claim 2, characterized in that: The GSM timing regulator is also used to perform a -3 offset operation on the time slot number, time slot header and frame header of the GSM reference timing signal, and use the operation result as the time slot number, time slot header and frame header corresponding to the independent timing signal of the uplink, thereby generating the uplink timing signal.

5. The GSM timing system according to claim 3 or 4, characterized in that: The GSM timing adjuster is also used to provide a configurable time slot offset function. By receiving the time slot number offset value issued by the baseband control unit, it performs timing adjustment on the uplink or downlink and adapts to different channel types or network deployment scenarios through this timing adjustment method. The time slot number offset value is in GSM time slots, and its value corresponds to the number of GSM time slots.

6. The GSM timing system according to claim 1, characterized in that: The GSM timing generator is also used to determine the 3-second cycle by performing a modulo-3 operation on the second field in the PTP TOD information. When the operation result is 0, the rising edge of the current 1 PPS second pulse is taken as the starting point of the corresponding 3-second cycle, and so on to determine the starting point of each 3-second cycle, thereby determining the GSM timing reference starting point. Based on the premise that the offset between GSM time and Unix time is an integer multiple of 3, the GSM timing generator is also used to align the starting point of the first 3-second cycle with the GSM system time origin on the time axis.

7. The GSM timing system according to claim 1 or 6, characterized in that: The GSM timing generator is also used to divide the corresponding time into 5200 GSM time slots within each 3-second cycle using an FPGA counter, and to control the time step of each GSM time slot under a system clock based on a preset frequency.

8. The GSM timing system according to claim 7, characterized in that: The GSM timing generator is also used to compensate for the non-integer characteristics of the GSM time slot period by applying a dynamic time slot allocation strategy within the 26 GSM time slots corresponding to each 15 ms period. This dynamic time slot allocation strategy makes the total duration of each 15 ms period exactly equal to the theoretically calculated integer value by setting 20 long-period time slots and 6 short-period time slots.

9. The GSM timing system according to claim 1, characterized in that: The system is used to simultaneously run communication standards including 4G LTE, 5G NR and 2G GSM under the O-RAN architecture, enabling the corresponding wireless communication technologies to be deployed on the same platform.

10. A GSM timing method for a GSM timing system according to claim 1, characterized in that, The method includes the following steps: S1. Receive 1 PPS pulse per second and 80-bit TOD information distributed by the PTP protocol; S2. Extract the seconds field from the 80-bit TOD information and perform a modulo-3 operation once per second, combining it with 1 PPS of second pulses. S3. When the result of the modulo 3 operation is 0, the rising edge of the current 1 PPS second pulse is taken as the starting point of the corresponding 3-second cycle. S4. For each defined 3-second period, 5200 GSM time slots are divided into the corresponding time period by the FPGA counter. Every 26 GSM time slots are used as a metering period, and 20 long period time slots and 6 short period time slots are allocated. S5. For each determined 3-second period of GSM time slot division and allocation result, determine the corresponding time slot number, time slot header and frame header for each GSM time slot, and then output the GSM reference timing signal. S6. Based on the GSM reference timing signal, generate independent timing signals for the uplink and downlink respectively.

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