IBGA packaging method and packaging structure of imaging module

Abstract

The invention belongs to the technical field of semiconductor packaging, and discloses an iBGA packaging method of an imaging module, which comprises the following steps: pasting an analysis chip on a substrate, and connecting a bonding pad of the analysis chip with a golden finger of the substrate through a first lead; a metal support is bonded, so that the analysis chip is accommodated between the metal support and the substrate; the imaging chip is bonded to the end face, away from the analysis chip, of the metal support; the bonding pad of the imaging chip and the golden finger of the substrate are connected through a second lead; a transparent cover plate is bonded to the end face, away from the metal support, of the imaging chip, and a semi-finished packaging piece is formed; the above processes are repeated, so that a plurality of semi-finished packaging pieces are arranged on the substrate at intervals, the substrate is filled with sealing glue, the side face of the transparent cover plate, the second lead, the metal support and the substrate are covered with the sealing glue, and baking and curing are carried out; the end face, away from the analysis chip, of the substrate is coated with scaling powder, and reflow soldering is carried out after ball mounting; and cutting the substrate according to a symmetric line of two adjacent semi-finished packaging pieces to form a plurality of packaging piece finished products.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to an iBGA packaging method and structure of an imaging module. BACKGROUND

[0002] The semiconductor packaging process is one of the more important processes in wafer processing, which is to use film technology and micro connection technology to arrange, fix and connect semiconductor components and other components on a frame or substrate, lead out the terminal, and through the insulation medium to form a whole main structure. In the packaging of the imaging module, the most common packaging technology is the carrier tape ball grid array packaging. The existing iBGA imaging module packaging method in the industry is to use the paving brick method to complete the packaging of the analysis chip and the imaging chip. This makes the size of the substrate larger, and further leads to the size of the packaging body being larger, and the packaging cost being higher and the packaging efficiency being lower.

[0003] The packaging process of the imaging module in the related art uses conductive glue to bond the readout chip to the substrate, and connects the sensor chip to the readout chip through the conductive glue film. However, the design of the substrate is complex, and the manufacturing process steps are many, resulting in high cost. In addition, the connection between the sensor chip and the readout chip has stress caused by the thermal expansion coefficient, increasing the difficulty of the packaging process.

[0004] Therefore, there is an urgent need for an iBGA packaging method and structure of an imaging module to solve the above problems. SUMMARY

[0005] One of the purposes of the present application is to provide an iBGA packaging method of an imaging module, which can reduce the size of the substrate, reduce the packaging size of the imaging module, and further reduce the packaging cost of the imaging module, reduce the difficulty of the packaging process, improve the yield of the chip packaging, and facilitate disassembly and maintenance.

[0006] The second purpose of the present application is to provide an iBGA packaging structure of an imaging module, which is made by the above-mentioned iBGA packaging method of an imaging module, can reduce the size of the substrate, reduce the packaging size of the imaging module, and facilitate disassembly and maintenance.

[0007] To achieve this purpose, the present application adopts the following technical solutions:

[0008] An iBGA packaging method of an imaging module, comprising the following steps:

[0009] Step S1: paste the analysis chip on the substrate, and connect the pads of the analysis chip and the gold fingers of the substrate through the first lead wire;

[0010] Step S2: bonding a metal bracket on the substrate, and containing the analysis chip between the metal bracket and the substrate;

[0011] Step S3: bonding the imaging chip on the end surface of the metal bracket away from the analysis chip;

[0012] Step S4: connecting the pads of the imaging chip and the gold fingers of the substrate through the second lead;

[0013] Step S5: bonding a transparent cover plate to the end surface of the imaging chip away from the metal bracket to form a semi-finished package;

[0014] Step S6: repeating the steps S1-S5 so that a plurality of semi-finished packages are arranged on the substrate in a spaced manner, pouring encapsulating glue on the substrate, the encapsulating glue covering the side surface of the transparent cover plate, the second lead, the metal bracket and the substrate, and baking and curing;

[0015] Step S7: applying flux on the end surface of the substrate away from the analysis chip, and then performing ball planting and reflow soldering;

[0016] Step S8: cutting the substrate along the symmetry line of the adjacent two semi-finished packages to form a plurality of finished packages.

[0017] As a preferred solution, the step S2 comprises:

[0018] Step S21: applying silver glue on the substrate in the circumferential direction of the analysis chip, the silver glue being arranged uniformly and at intervals, placing the metal bracket on the silver glue, and baking and curing;

[0019] Step S22: filling the first glue between the adjacent two silver glues after curing, and baking and curing to make the analysis chip located in the closed space surrounded by the metal bracket and the substrate.

[0020] As a preferred solution, in the step S3, the second glue is applied on the end surface of the metal bracket away from the analysis chip, and the imaging chip is pasted to the end surface of the metal bracket away from the analysis chip through the second glue.

[0021] As a preferred solution, the step S5 comprises:

[0022] Step S51: applying a layer of third glue on the upper surface of the imaging chip along the edge of the imaging chip in the circumferential direction of the imaging chip, and baking and curing to form a glue layer;

[0023] Step S52: Repeat step S51 until the second lead is located between two adjacent adhesive layers, apply the third adhesive to the top adhesive layer, bond the transparent cover to the end face of the imaging chip away from the metal bracket with the third adhesive, and bake to cure, forming the semi-finished package.

[0024] As a preferred embodiment, step S6 includes:

[0025] Step S61: Repeat steps S1-S5 so that a plurality of the semi-finished packages are arranged at intervals on the substrate;

[0026] Step S62: Apply the encapsulating adhesive to the substrate, covering the side of the transparent cover, the first lead, the second lead, the metal support, and the substrate, and bake and cure it. The height of the encapsulating adhesive is not higher than the upper surface of the transparent cover.

[0027] As a preferred embodiment, the step between step S61 and step S62 further includes:

[0028] Step S63: Along the circumferential direction of the substrate, a dam is formed on the substrate, and a plurality of semi-finished packaged parts arranged at intervals are located within the cavity formed by the dam and the substrate.

[0029] As a preferred embodiment, the method further includes the following step before step S1:

[0030] Step S0: Prepare an imaging wafer. The upper surface of the substrate of the imaging wafer has a sensing area. The substrate of the imaging wafer is ground by thinning technology. The ground imaging wafer is then divided into multiple imaging chips.

[0031] A resolution wafer is prepared, wherein the upper surface of the substrate of the resolution wafer has a resolution region. The substrate of the resolution wafer is ground by a thinning technique, and the ground resolution wafer is divided into multiple resolution chips.

[0032] As a preferred embodiment, the upper surface of the substrate is provided with an adhesive area and the gold fingers spaced apart, and the lower surface of the substrate is provided with solder pads. The solder pads and the gold fingers are electrically connected through the metal inside the substrate.

[0033] An iBGA packaging structure for an imaging module, characterized in that the iBGA packaging structure of the imaging module is manufactured using the iBGA packaging method for the imaging module as described above, and the iBGA packaging structure of the imaging module includes:

[0034] substrate;

[0035] Multiple analytical chips are attached to the substrate and connected to the gold fingers of the substrate via a first lead.

[0036] Multiple metal supports are attached to the substrate, and the analytical chip is located between the metal supports and the substrate;

[0037] Multiple imaging chips are attached to the end face of the metal bracket away from the analytical chip and connected to the gold fingers of the substrate through a second lead. A transparent cover plate is attached to the end face of the imaging chip away from the metal bracket to form a semi-finished package.

[0038] Multiple semi-finished packages are evenly spaced on the substrate, and encapsulating adhesive is applied to the substrate to cover the side of the transparent cover, the second lead, the metal support, and the substrate.

[0039] Solder balls are fixed to the end face of the substrate away from the analytical chip, and symmetrical lines are cut between two adjacent semi-finished packages.

[0040] As a preferred embodiment, the substrate is made of organic material.

[0041] The beneficial effects of this invention are:

[0042] This invention provides an iBGA packaging method for an imaging module, comprising the following steps: Step S1: attaching a resolution chip to a substrate and connecting the pads of the resolution chip to the gold fingers of the substrate via a first lead; Step S2: attaching a metal bracket to the substrate, with the resolution chip housed between the metal bracket and the substrate; Step S3: attaching an imaging chip to the end face of the metal bracket opposite to the resolution chip; Step S4: connecting the pads of the imaging chip to the gold fingers of the substrate via a second lead; Step S5: attaching a transparent cover to the end face of the imaging chip opposite to the metal bracket to form a semi-finished package; Step S6: repeating steps S1-S5, such that multiple semi-finished packages are spaced apart on the substrate, applying encapsulating adhesive to the substrate, covering the side of the transparent cover, the second lead, the metal bracket, and the substrate, and then baking and curing; Step S7: applying flux to the end face of the substrate opposite to the resolution chip, performing ball bonding, and then reflow soldering; Step S8: cutting the substrate along the symmetrical lines of two adjacent semi-finished packages to form multiple finished package products.

[0043] The iBGA packaging method for this imaging module stacks the resolution chip and imaging chip vertically along the substrate using a metal bracket, and connects the resolution chip and imaging chip to the gold fingers of the substrate using leads. This reduces the size of the substrate and the overall package size of the imaging module. The lead connection simplifies substrate fabrication, thereby reducing the packaging cost of the imaging module. Furthermore, the lead connection between the resolution chip and the substrate, as well as the imaging chip and the substrate, offers high flexibility and lowers the requirements for the packaging process, thus reducing the complexity of the packaging process and improving the chip packaging yield. The lead connection also facilitates disassembly and maintenance between the chip and the substrate.

[0044] The present invention also provides an iBGA packaging structure for an imaging module, which is made using the above-mentioned iBGA packaging method for an imaging module. This reduces the size of the substrate and the packaging size of the imaging module, and is easy to disassemble and maintain. Attached Figure Description

[0045] Figure 1 This is a first schematic diagram of the iBGA packaging method for the imaging module according to an embodiment of the present invention;

[0046] Figure 2 This is a second schematic diagram of the iBGA packaging method for the imaging module described in an embodiment of the present invention;

[0047] Figure 3 This is a third schematic diagram of the iBGA packaging method for the imaging module described in this embodiment of the invention;

[0048] Figure 4 This is a fourth schematic diagram of the iBGA packaging method for the imaging module described in this embodiment of the invention;

[0049] Figure 5 This is the fifth schematic diagram of the iBGA packaging method for the imaging module described in this embodiment of the invention;

[0050] Figure 6 This is the sixth schematic diagram of the iBGA packaging method for the imaging module described in this embodiment of the invention;

[0051] Figure 7 This is the seventh schematic diagram of the iBGA packaging method for the imaging module described in this embodiment of the invention;

[0052] Figure 8 yes Figure 7 A magnified view of a section at point A in the middle;

[0053] Figure 9 This is the eighth schematic diagram of the iBGA packaging method for the imaging module described in this embodiment of the invention;

[0054] Figure 10This is a schematic diagram of the iBGA packaging structure of the imaging module described in an embodiment of the present invention.

[0055] In the picture:

[0056] 10. Semi-finished packaged components;

[0057] 1. Substrate;

[0058] 2. Analyze the chip;

[0059] 3. First lead;

[0060] 4. Metal bracket;

[0061] 5. Imaging chip;

[0062] 6. Second lead;

[0063] 7. Transparent cover;

[0064] 8. Sealing adhesive;

[0065] 9. Dike;

[0066] 20. Finished packaged components. Detailed Implementation

[0067] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0068] In the description of this invention, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection or a detachable connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0069] In the description of this invention, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0070] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0071] This embodiment provides an iBGA packaging method for an imaging module, such as... Figures 1-9 As shown, the iBGA packaging method including the imaging module includes the following steps: S1: Attaching the resolution chip 2 to the substrate 1 and connecting the pads of the resolution chip 2 and the gold fingers of the substrate 1 through the first lead 3; S2: Attaching the metal bracket 4 to the substrate 1, with the resolution chip 2 housed between the metal bracket 4 and the substrate 1; S3: Attaching the imaging chip 5 to the end face of the metal bracket 4 away from the resolution chip 2; S4: Connecting the pads of the imaging chip 5 and the gold fingers of the substrate 1 through the second lead 6; S5: Attaching the transparent cover plate 7 to the end face of the imaging chip 5 away from the gold fingers. Step S6: Repeat steps S1-S5 to arrange multiple semi-finished packages 10 on the substrate 1 at intervals. Apply encapsulating glue 8 to the substrate 1. The encapsulating glue 8 covers the side of the transparent cover plate 7, the second lead 6, the metal support 4 and the substrate 1, and bake to cure. Step S7: Apply flux to the end face of the substrate 1 away from the analytical chip 2, and after ball mounting, perform reflow soldering. Step S8: Cut the substrate 1 along the symmetrical line of two adjacent semi-finished packages 10 to form multiple finished package products 20.

[0072] The iBGA packaging method of this imaging module stacks the resolution chip 2 and the imaging chip 5 vertically along the substrate 1 using a metal bracket 4, and connects the resolution chip 2 and the imaging chip 5 to the gold fingers of the substrate 1 using leads. This reduces the size of the substrate 1 and the packaging size of the imaging module. The lead connection simplifies the fabrication of the substrate 1, thereby reducing the packaging cost of the imaging module. At the same time, the lead connection between the resolution chip 2 and the substrate 1, as well as between the imaging chip 5 and the substrate 1, offers high flexibility and lower requirements for the packaging process, thus reducing the difficulty of the packaging process and improving the chip packaging yield. Furthermore, the lead connection facilitates disassembly and maintenance between the chip and the substrate 1.

[0073] Specifically, in this embodiment, the substrate 1 is made of an organic material. In other embodiments, the substrate 1 is made of a ceramic material or a glass material, etc. No limitation is made here. It should be noted that in this embodiment, the transparent cover 7 is glass. In other embodiments, the transparent cover 7 is an acrylic sheet, etc. No limitation is made here.

[0074] Optionally, the upper surface of the substrate 1 is provided with an adhesive area and gold fingers spaced apart, and the lower surface of the substrate 1 is provided with solder pads. The solder pads and gold fingers are electrically connected through the metal inside the substrate 1.

[0075] Optionally, such as Figure 1 and Figure 2 As shown, in this embodiment, the resolution chip 2 is adhered to the substrate 1 using an adhesive film. In other embodiments, the resolution chip 2 is adhered to the substrate 1 using a first glass adhesive, etc. No limitations are imposed here.

[0076] Specifically, such as Figure 1 and Figure 2 As shown, in this embodiment, two parsing chips 2 are provided, and the two parsing chips 2 are connected by an adhesive film. In other embodiments, there may be one, three, or four parsing chips 2, etc. No limitation is made here.

[0077] Specifically, in this embodiment, the first lead 3 is a first copper wire. Copper wire has excellent conductivity and low cost. In other embodiments, the first lead 3 is a first silver wire, etc. No limitations are imposed here.

[0078] Optionally, such as Figure 3 As shown, step S2 includes step S21: applying silver paste to the substrate 1 in the circumferential direction around the resolution chip 2, with the silver paste evenly spaced, placing the metal support 4 on the silver paste, baking and curing; step S22: filling the space between two adjacent silver pastes after curing with first glue, and baking and curing, so that the resolution chip 2 is located in the sealed space enclosed by the metal support 4 and the substrate 1. When bonding the metal support 4 to the substrate 1, spaced-apart silver paste is first used for bonding. During curing, the silver paste expands due to heat, and its internal volatiles are rapidly released, generating instantaneous pressure. The spaced-apart arrangement of the silver paste allows this pressure to dissipate between adjacent silver paste layers, preventing the silver paste from bursting apart as with continuous silver paste bonding of the metal support 4. This ensures the stability and reliability of the connection between the metal support 4 and the substrate 1, and also prevents the bursting silver paste from contaminating other areas of the substrate 1. Then, a first adhesive is used to cure and bond the metal support 4 and the substrate 1, further achieving a stable, fixed bond between them. This also isolates the external environment, protecting the analytical chip 2. It should be noted that both the baking and curing of the silver paste and the first adhesive are performed using ultraviolet light.

[0079] Specifically, in this embodiment, the first adhesive is a first UV adhesive. In other embodiments, the first adhesive is a second glass adhesive, etc. No limitation is made here.

[0080] Optionally, such as Figure 4 As shown, in step S3, a second adhesive is first applied to the end face of the metal bracket 4 facing away from the resolution chip 2, and the imaging chip 5 is then attached to the end face of the metal bracket 4 facing away from the resolution chip 2 using the second adhesive. This achieves a vertical stacking layout of the resolution chip 2, the metal bracket 4, and the imaging chip 5, maximizing the use of the longitudinal space of the substrate 1 and reducing the overall structural footprint.

[0081] Specifically, in this embodiment, the second adhesive is a second UV adhesive. In other embodiments, the second adhesive is a third glass adhesive, etc. No limitations are imposed here.

[0082] Specifically, such as Figure 5 As shown, the second lead 6 in step S4 is a second copper wire. Copper wire has excellent conductivity and low cost. In other embodiments, the second lead 6 is a second silver wire, etc. No limitation is made here.

[0083] Optionally, such as Figure 6 As shown, step S5 includes step S51: coating a layer of third adhesive on the upper surface of the imaging chip 5 along the edge of the imaging chip 5 in the circumferential direction, and baking to cure, forming an adhesive layer; step S52: repeating step S51 until the second lead 6 is located between two adjacent adhesive layers, coating the third adhesive onto the top adhesive layer, and bonding the transparent cover plate 7 to the end face of the imaging chip 5 away from the metal bracket 4 through the third adhesive, and baking to cure, forming a semi-finished package 10.

[0084] By baking and curing the adhesive layer by layer, the second lead 6 is wrapped in layers of cured third adhesive. Then, a transparent cover plate 7 is used to seal the upper surface of the imaging chip 5, forming a semi-finished package 10 that protects the internal structure of the chip while enabling its optical functions. By housing the second lead 6 in the adhesive layers formed by the third adhesive, the transparent cover plate 7 is prevented from sinking due to its own weight and coming into contact with the second lead 6, thus avoiding the open circuit or abnormal signal transmission caused by the deformation of the second lead 6 under pressure. At the same time, the adhesive layer has a fixing effect, enhancing the connection reliability between the transparent cover plate 7 and the imaging chip 5.

[0085] Specifically, in this embodiment, the third adhesive is a damming adhesive. In other embodiments, the third adhesive is an underfill adhesive, etc. No limitation is made here.

[0086] Optionally, such as Figures 7-9As shown, step S6 includes step S61: repeating steps S1-S5, so that multiple semi-finished packages 10 are arranged at intervals on the substrate 1; step S62: applying encapsulating adhesive 8 to the substrate 1, covering the side of the transparent cover plate 7, the first lead 3, the second lead 6, the metal support 4, and the substrate 1 with the encapsulating adhesive 8, and baking and curing it. The height of the encapsulating adhesive 8 is not higher than the upper surface of the transparent cover plate 7. By setting multiple semi-finished packages 10 on the substrate 1 and covering the exposed surface of each semi-finished package 10 with encapsulating adhesive 8, a dense protective layer is formed on the exposed surface of the semi-finished package 10. On the one hand, it fills the gap between the semi-finished package 10 and the substrate 1, and on the other hand, it wraps the exposed fragile structure, thus achieving the sealing, buffering, and fixing of the semi-finished package 10. It should be noted that in this embodiment, the encapsulating adhesive 8 is baked and cured with ultraviolet light after the encapsulation is completed.

[0087] Specifically, in this embodiment, the encapsulating adhesive 8 is an epoxy resin encapsulating adhesive. In other embodiments, the encapsulating adhesive 8 is a silicone resin encapsulating adhesive or a polyurethane encapsulating adhesive, etc. No limitation is made here.

[0088] Specifically, such as Figure 7 and Figure 8 As shown, step S63 is included between steps S61 and S62: a dam 9 is formed on the substrate 1 along the circumferential direction of the substrate 1, and multiple semi-finished packages 10 arranged at intervals are located within the cavity formed by the dam 9 and the substrate 1. The formation of the dam 9 makes the potting shape of the encapsulating adhesive 8 within the cavity more controllable. The dam 9 acts like a protective wall, surrounding the multiple semi-finished packages 10 within the cavity, preventing the highly fluid and low-viscosity encapsulating adhesive 8 from flowing out during potting, and preventing contamination of other non-target components, circuits, or solder joints on the substrate 1. At the same time, the cavity formed by the dam 9 and the substrate 1 is a relatively closed space, and the encapsulating adhesive 8 will not spread randomly during potting. Operators can more easily control the amount and speed of potting, ensuring the uniformity of encapsulation and reducing encapsulation defects of the semi-finished packages 10. Figure 9 This is a schematic diagram of a single semi-finished package 10 after encapsulation.

[0089] Optionally, before step S1, step S0 is further included: preparing an imaging wafer, wherein the upper surface of the substrate of the imaging wafer has a sensing area, and the substrate of the imaging wafer is ground using a thinning technique to divide the ground imaging wafer into multiple imaging chips 5; preparing a resolution wafer, wherein the upper surface of the substrate of the resolution wafer has a resolution area, and the substrate of the resolution wafer is ground using a thinning technique to divide the ground resolution wafer into multiple resolution chips 2. Preparing the required resolution chips 2 and imaging chips 5 before packaging provides a prerequisite for subsequent packaging and helps improve packaging efficiency.

[0090] Specifically, such as Figure 10As shown, in step S7, multiple solder balls are formed by reflow soldering on the end face of the substrate 1 away from the analytical chip 2.

[0091] Specifically, such as Figure 10 As shown, in step S8, laser cutting is used to cut the symmetry lines of two adjacent semi-finished packages 10 to form multiple finished packages 20. In other embodiments, blade cutting is used to cut the symmetry lines of two adjacent semi-finished packages 10, etc. No limitation is made here.

[0092] This embodiment also provides an iBGA packaging structure for an imaging module. The iBGA packaging structure of the imaging module is made using the iBGA packaging method for imaging modules. The iBGA packaging structure of the imaging module includes a substrate 1, multiple resolution chips 2, multiple metal supports 4, and multiple imaging chips 5. The resolution chips 2 are bonded to the substrate 1 and connected to the gold fingers of the substrate 1 through a first lead 3. The metal supports 4 are bonded to the substrate 1. The resolution chips 2 are located between the metal supports 4 and the substrate 1. The imaging chips 5 are bonded to the end face of the metal supports 4 away from the resolution chips 2 and connected to the gold fingers of the substrate 1 through a second lead 6. A transparent cover plate 7 is bonded to the end face of the imaging chips 5 away from the metal supports 4 to form a semi-finished package 10. Multiple semi-finished packages 10 are evenly spaced on the substrate 1. Encapsulating glue 8 is poured onto the substrate 1 to cover the side of the transparent cover plate 7, the second lead 6, the metal supports 4, and the substrate 1. Solder balls are fixed to the end face of the substrate 1 away from the resolution chips 2, and symmetrical lines are cut between adjacent semi-finished packages 10.

[0093] By using the iBGA packaging method to fabricate the iBGA packaging structure of the imaging module, the size of the substrate 1 is reduced, the packaging size of the imaging module is reduced, thereby reducing the packaging cost of the imaging module, and it is easy to disassemble and maintain.

[0094] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. An iBGA packaging method for an imaging module, characterized in that, Includes the following steps: Step S1: Attach the analytical chip (2) to the substrate (1) and connect the pads of the analytical chip (2) and the gold fingers of the substrate (1) through the first lead (3); Step S2: The metal bracket (4) is bonded to the substrate (1), and the analytical chip (2) is housed between the metal bracket (4) and the substrate (1); Step S3: Attach the imaging chip (5) to the end face of the metal bracket (4) away from the analytical chip (2); Step S4: Connect the pads of the imaging chip (5) and the gold fingers of the substrate (1) through the second lead (6); Step S5: Attach the transparent cover plate (7) to the end face of the imaging chip (5) away from the metal bracket (4) to form a semi-finished package (10). Step S6: Repeat steps S1-S5 so that multiple semi-finished packages (10) are arranged at intervals on the substrate (1), and encapsulating glue (8) is poured onto the substrate (1). The encapsulating glue (8) covers the side of the transparent cover plate (7), the second lead (6), the metal bracket (4) and the substrate (1), and is baked and cured. Step S7: Apply flux to the end face of the substrate (1) away from the analytical chip (2), and after ball placement, perform reflow soldering; Step S8: Cut the substrate (1) along the symmetrical line of two adjacent semi-finished packages (10) to form a plurality of finished package products (20).

2. The iBGA packaging method for the imaging module according to claim 1, characterized in that, Step S2 includes: Step S21: Apply silver paste to the substrate (1) around the circumferential direction of the analytical chip (2), and the silver paste is evenly spaced. Place the metal support (4) on the silver paste, bake and cure. Step S22: Fill the first glue between two adjacent silver pastes after curing and bake to cure, so that the analytical chip (2) is located in the sealed space formed by the metal support (4) and the substrate.

3. The iBGA packaging method for the imaging module according to claim 1, characterized in that, In step S3, a second adhesive is first applied to the end face of the metal bracket (4) away from the resolution chip (2), and the imaging chip (5) is then attached to the end face of the metal bracket (4) away from the resolution chip (2) using the second adhesive.

4. The iBGA packaging method for the imaging module according to claim 1, characterized in that, Step S5 includes: Step S51: A third adhesive is applied to the upper surface of the imaging chip (5) along the edge of the imaging chip (5) in the circumferential direction and baked to cure, forming an adhesive layer. Step S52: Repeat step S51 until the second lead (6) is located between two adjacent adhesive layers, apply the third adhesive to the topmost adhesive layer, and bond the transparent cover plate (7) to the end face of the imaging chip (5) away from the metal bracket (4) with the third adhesive, and bake and cure to form the semi-finished package (10).

5. The iBGA packaging method for an imaging module according to claim 1, characterized in that, Step S6 includes: Step S61: Repeat steps S1-S5 so that a plurality of the semi-finished package members (10) are arranged at intervals on the substrate (1). Step S62: Apply the encapsulating adhesive (8) to the substrate (1). The encapsulating adhesive (8) covers the side of the transparent cover plate (7), the first lead (3), the second lead (6), the metal bracket (4), and the substrate (1), and bakes and cures it. The height of the encapsulating adhesive (8) is not higher than the upper surface of the transparent cover plate (7).

6. The iBGA packaging method for an imaging module according to claim 5, characterized in that, Between step S61 and step S62, the following is also included: Step S63: Along the circumferential direction of the substrate (1), a dam (9) is made on the substrate (1), and a plurality of semi-finished packaged parts (10) arranged at intervals are located in the cavity formed by the dam (9) and the substrate (1).

7. The iBGA packaging method for an imaging module according to any one of claims 1-6, characterized in that, The steps preceding step S1 also include: Step S0: Prepare an imaging wafer. The upper surface of the substrate of the imaging wafer has a sensing area. The substrate of the imaging wafer is ground by thinning technology. The ground imaging wafer is then divided into multiple imaging chips (5). Prepare a resolution wafer. The upper surface of the substrate of the resolution wafer has a resolution region. The substrate of the resolution wafer is ground by thinning technology. The ground resolution wafer is then divided into multiple resolution chips (2).

8. The iBGA packaging method for an imaging module according to any one of claims 1-6, characterized in that, The upper surface of the substrate (1) is provided with an adhesive area and the gold finger spaced apart, and the lower surface of the substrate (1) is provided with a solder pad. The solder pad and the gold finger are electrically connected through the metal inside the substrate (1).

9. An iBGA packaging structure for an imaging module, characterized in that, The iBGA packaging structure of the imaging module is manufactured using the iBGA packaging method for the imaging module as described in any one of claims 1-8, and the iBGA packaging structure of the imaging module includes: substrate(1); Multiple analytical chips (2) are attached to the substrate (1) and connected to the gold fingers of the substrate (1) via a first lead (3); Multiple metal supports (4) are attached to the substrate (1), and the analytical chip (2) is located between the metal supports (4) and the substrate (1); Multiple imaging chips (5) are attached to the end face of the metal bracket (4) away from the analytical chip (2) and connected to the gold fingers of the substrate (1) through the second lead (6). A transparent cover plate (7) is attached to the end face of the imaging chip (5) away from the metal bracket (4) to form a semi-finished package (10). Multiple semi-finished packages (10) are evenly spaced on the substrate (1), and encapsulating glue (8) is applied to the substrate (1) to cover the side of the transparent cover plate (7), the second lead (6), the metal bracket (4) and the substrate (1). Solder balls are fixed on the end face of the substrate (1) away from the analytical chip (2), and the symmetrical lines of two adjacent semi-finished packages (10) are cut.

10. The iBGA packaging structure of the imaging module according to claim 9, characterized in that, The substrate (1) is made of organic material.

Images