Chip packaging method and related device

Abstract

The invention discloses a chip packaging method and a related device, and the method comprises the steps: determining an overlapping region, a reference region and a shielding boundary curve according to imaging data, and obtaining interconnection nodes and rigidity constraint data in the overlapping region; acquiring polarization intensity data in the overlapping region, and obtaining a surface slope field through a dual-band intensity ratio and multidirectional fusion conversion; taking the reference area as a Dirichlet boundary condition, taking a normal derivative of the shielding boundary curve as a Noiemann boundary condition, and carrying out Poisson integration on the surface slope field to obtain a relative height map of the upper chip; and solving low-order deformation parameters of the lower-layer chip through elastic constraint energy minimization according to displacement observation and interconnection rigidity constraint of the relative height map at interconnection nodes. According to the scheme, the technical problems that in a traditional method, geometric benchmark missing exists in an overlapping band, and a shielded layer cannot be observed can be solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging and testing technology, and in particular to a chip packaging method and related apparatus. Background Technology

[0002] With the development of heterogeneous integration and system-in-package (SiP), the juxtaposition, overlapping, and projection overlap of multiple bare dies on the same packaging substrate have gradually become common structural forms. Taking two-chip overlap as an example, the typical process is as follows: the first chip is attached to the packaging substrate in a positive orientation with an adhesive layer, and the second chip is electrically interconnected with the first chip and the packaging substrate respectively through bumps in a flip-chip manner. After reflow and cleaning, it can enter subsequent processes such as molding, dicing, and balling.

[0003] Regarding the aforementioned process nodes, existing inspection technologies mainly fall into two categories. The first is two-dimensional appearance inspection based on visible light imaging, relying on the stable extraction of the chip's outer edge, corner points, or reference baseline. It indirectly indicates warping or pose anomalies through geometric quantities such as angle measurement, anomaly measurement, or contour consistency (e.g., the method described in patent application number 202311535173.9). The second is evaluation through explicit acquisition of three-dimensional topography, such as focused or defocused scanning, structured light and phase shift measurement, confocal or interferometric contour acquisition, etc., using multiple frames or dedicated optical paths to reconstruct the height field of the measured surface. In traditional single-chip, unobstructed, and well-defined baseline scenarios, these methods exhibit good repeatability and engineering usability, meeting conventional coplanarity and appearance requirements.

[0004] When the structure transitions to multi-chip overlap, the key premise of the above methods is systematically weakened. Because the upper-layer chip obscures the lower-layer boundary in projection, it is difficult to obtain clear outer edges or corners that can serve as geometric references within the overlap region, and boundary-based geometric criteria lose stable support in this area. The strong reflection and depolarization effects brought about by the combination of materials such as mirrored metal, passivation films, and resins make binarization and fringe phase unfolding increasingly sensitive to illumination, attitude, and depth of field, leading to detection threshold drift and inconsistent results. Furthermore, the multi-frame focal scanning or complex 3D optical paths introduced to compensate for insufficient observable information are difficult to reconcile with production line cycle time, cost, and maintenance constraints. In addition, existing methods typically only obtain local, projection-based geometric surrogate quantities in the overlap region, lacking the ability to stably and quickly output attitude-independent global surface shape quantities without increasing hardware complexity. They also cannot effectively constrain the deformation of the obscured layer within the overlap band, resulting in detection blind spots for typical defect morphologies induced by overlap, such as symmetrical arching and localized pulling. Summary of the Invention

[0005] The main objective of this invention is to solve the technical problems of existing multi-chip overlapping packaging detection methods, which cannot stably obtain the overall scene shape under overlapping and occlusion conditions and are difficult to apply effective constraints to the occluded layer.

[0006] To achieve the above objectives, embodiments of this application provide a chip packaging method, including: Based on the imaging data, the overlapping region, the reference region outside the overlapping region, and the occlusion boundary curve formed by the outer edge of the upper chip are determined, and the interconnect nodes and their stiffness constraint data within the overlapping region are obtained to obtain the interconnect constraint data. Polarization intensity data is acquired in the overlapping region, and the surface slope field covering the overlapping region is calculated based on the polarization intensity data. Using the reference region as the zero-height boundary and the normal derivative of the occlusion boundary curve as the boundary condition, the surface slope field is integrated to obtain the relative height map of the upper chip in the overlapping region. Based on the relative height map and interconnection constraint data, the low-order deformation parameters of the lower-layer chip in the overlapping region are solved.

[0007] To achieve the above objectives, embodiments of this application also propose a chip packaging apparatus, comprising: The scene recognition module is used to determine the overlapping area, the reference area outside the overlapping area, and the occlusion boundary curve formed by the outer edge of the upper chip based on the imaging data, and to obtain the interconnection nodes and their stiffness constraint data within the overlapping area to obtain interconnection constraint data. The polarization detection module is used to acquire polarization intensity data in the overlapping region and calculate the surface slope field covering the overlapping region based on the polarization intensity data. The integral reconstruction module is used to integrate the surface slope field with the reference region as the zero-height boundary and the normal derivative of the occlusion boundary curve as the boundary condition to obtain the relative height map of the upper chip in the overlapping region. The cross-layer inversion module is used to solve the low-order deformation parameters of the lower-layer chip in the overlapping region based on the relative height map and interconnection constraint data.

[0008] To achieve the above objectives, this application also proposes a chip packaging device, including: a memory and at least one processor, wherein the memory stores instructions, and the memory and the at least one processor are interconnected via a circuit; the at least one processor invokes the instructions in the memory to cause the chip packaging device to perform the steps of the chip packaging method described above.

[0009] To achieve the above objectives, embodiments of this application also propose a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the steps of the chip packaging method described above.

[0010] The technical solution provided in this application determines the overlapping area between chips using imaging data. This clearly marks areas that were originally obscured by the upper chip, while simultaneously finding a still visible reference area outside the overlapping area and extracting the outer edge of the uppermost chip to form the obscuration boundary curve. The purpose of this is to establish a geometric reference even without the lower chip boundary as a direct reference.

[0011] Next, polarization intensity data is acquired in the overlapping region, and the surface slope field is obtained through calculation. The relationship between polarization intensity and material properties allows for the acquisition of surface tilt information in this region even when traditional optical methods fail. In this way, the optical signal is essentially converted into data related to the chip surface morphology.

[0012] After obtaining the slope field, the slope field is integrated using the reference region as the zero-height boundary and the normal derivative on the occlusion boundary curve as the boundary condition. The result of the integration is the relative height distribution map of the upper-layer chip within the overlapping region. This step is equivalent to restoring the three-dimensional topography that cannot be directly observed using a finite reference region and boundary constraints.

[0013] Finally, this relative height map is combined with the interconnect constraint data. At the interconnect nodes, the upper-layer displacement can be linked to the mechanical constraints of the nodes, and the low-order deformation parameters of the lower-layer chip can be deduced from these mechanical constraints. In this way, even if the lower-layer chip is completely obscured, its deformation in the overlapping region can still be obtained using the mechanical relationships of the interconnects. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of one embodiment of the chip packaging method in this invention; Figure 2 This is a schematic diagram of one embodiment of the chip packaging device in this invention; Figure 3 This is a schematic diagram of one embodiment of the chip packaging device in this invention.

[0016] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0018] In chip packaging, wafers are diced into individual dies, which are then combined with packaging substrates, electrical connections, and protective materials to form devices ready for board mounting. With the increasing prevalence of heterogeneous integration and system-in-package (SiP), a single die often cannot simultaneously meet the multiple functional requirements of computing power, storage, analog interfaces, and RF front-ends. Therefore, juxtaposing or stacking multiple dies has become a common practice. Taking two-chip stacking as an example, the first chip is first fixed to the packaging substrate with an adhesive layer, and the second chip then forms electrical connections and supports with the first chip and the substrate through bumps. The reasons for stacking the second chip on the first chip and using a bump method are: firstly, to shorten the signal path, reduce interconnect resistance and parasitic effects; secondly, to significantly improve input / output density and functional integration; and thirdly, to utilize the bumps and the underlying adhesive layer to form a controlled gap, providing both mechanical support and facilitating stress and thermal path design. After reflow and cleaning, the device undergoes processes such as molding, dicing, and balling. These thermo-mechanical processes can easily cause upper layer warpage, lower layer pulling, and localized deformation within the overlap zone, ultimately affecting the coplanarity and reliability of subsequent solder balls. Therefore, rapid detection is required in overlapping areas on the mass production line: it is necessary to obtain the true shape of the upper layer in the occluded area and to make a quantitative judgment on the deformation state of the lower layer, so as to provide a basis for release and traceability.

[0019] Traditional detection paths mainly fall into two categories. Visible light 2D appearance relies on outer edges, corner points, or reference baselines for angle measurement, anomaly and profile comparison; 3D measurement reconstructs the height field through dedicated optical paths such as focal scanning, structured light, phase shifting, confocal, or interferometry. In single-chip unobstructed scenarios, these methods are repeatable and usable. However, once two chips overlap, key prerequisites are weakened: upper layer occlusion leads to a lack of reliable geometric references within the overlap zone; the combination of metal mirrors, passivation films, and resin brings strong reflection and depolarization, making binarization and phase unwrapping extremely sensitive to illumination and attitude; and the multi-frame focal scanning or complex 3D optical paths introduced to compensate for information gaps are incompatible with cycle time and cost. To address this contradiction, this paper proposes a method that uses overlapping scenarios as the entry point: first, it clarifies the overlapping region, the reference region, and the occlusion boundary formed by the outer edge of the upper layer from the imaging data; then, it calculates the surface slope field within the overlapping zone using few-frame polarization observations; using the reference region as a zero-height reference, it transforms the occlusion boundary into a normal derivative constraint to complete the integration, obtaining an attitude-independent upper-layer relative height map; simultaneously, it links height information with equivalent stiffness at interconnect nodes to deduce the lower-order deformation of the lower layer under occlusion. The entire link does not rely on complex 3D optical paths and is designed specifically for overlapping occlusion, enabling it to provide the true morphology and cross-layer deformation within the overlapping zone within mass production cycles, thus mitigating risks and guiding process parameter tuning.

[0020] One embodiment of this application provides a chip packaging method. Figure 1 This is a flowchart illustrating a chip packaging method provided in an embodiment of this application. In this embodiment, the method includes: Please see Figure 1 S1. Based on the imaging data, determine the overlapping area, the reference area outside the overlapping area, and the occlusion boundary curve formed by the outer edge of the upper chip, and obtain the interconnection nodes and their stiffness constraint data within the overlapping area to obtain interconnection constraint data. In one embodiment of the present invention, S1 includes: S11. Based on the material spectral differences in the imaging data, the chip projection is segmented, and the overlapping area of ​​multiple chips projected onto the plane is determined. S12. Divide the overlapping area into a fully occluded sub-region and a partially occluded sub-region, and perform extension fitting based on the visible lower chip boundary in the partially occluded sub-region to reconstruct the lower chip boundary of the fully occluded sub-region. S13. When the lower chip is partially exposed, the reference area is determined based on the exposed area; when the lower chip is completely covered, the reference area is determined based on the peripheral structure. S14. Within the overlapping area, extract the outer edge line segment that intersects with the overlapping area from the outer edge of the uppermost chip and splice them together to obtain the occlusion boundary curve.

[0021] The following is a detailed description of the steps involved in the above embodiments: Specifically, material spectral differences refer to the differences in reflectivity or absorptivity of materials such as metal layers, passivation layers, resins, and silicon across two or more spectral bands. Chip projection refers to the two-dimensional connected region formed by a single chip on the imaging plane. In practice, the imaging intensity matrix of two or more spectral bands is first acquired, and the intensity ratio or normalized difference between band pairs is calculated pixel-by-pixel to generate a material spectral difference map. Thresholding is performed on the material spectral difference map, with the threshold derived from the upper-calibrated gray-level valley value or Otsu's Adaptive Thresholding method. Subsequently, morphological opening and closing operations are performed to remove isolated noise, and chip projection candidates are output through connected component labeling. The candidates are matched with the chip outline polygons in the design data using affine or homography transformations to eliminate noise blocks with areas smaller than the minimum process feature size, obtaining the chip projection for each chip. Finally, the intersection of different chip projections is calculated to obtain the overlapping region. The input is multi-band imaging data and the design outline; the output is the chip projection and the overlapping region. The band selection prioritizes coverage of the visible and near-infrared regions to utilize the contrast between the metal, organic layers, and silicon. The threshold is set at a grayscale valley to avoid the effects of material drift. The minimum area of ​​the connected regions is set on the order of interconnect spacing to ensure effective feature preservation. This segmentation method achieves stable chip projection even with weak outer edge texture or image contrast affected by pose. In an equivalent implementation, when the production line only has single-band imaging, polarization degree or S / P intensity ratio can be used to replace material spectral differences. Overlapping areas are then obtained through connected regions and intersections, maintaining consistency throughout the overall processing chain.

[0022] A fully occluded sub-region refers to a sub-region within the overlapping area where no pixels of the underlying chip are visible. A partially occluded sub-region refers to a sub-region where visible boundary pixels of the underlying chip still exist. In implementation, within the overlapping area, the region is divided into two types of sub-regions based on the material label and visibility mask from the previous step. For partially occluded sub-regions, directed boundary lines are extracted along the pixel sequence of the underlying chip boundary. Local tangent and curvature are calculated, and cubic splines are used for extrapolation in the tangential direction. The extrapolation step size is controlled by curvature continuity and residual constraints, allowing the fitted boundary to extend to the adjacent fully occluded sub-region. In the fully occluded sub-region, the reconstructed estimated boundary of the underlying chip is thus obtained. The input is the visibility mask of the overlapping area, and the output is the estimated boundary of the two sub-regions and the fully occluded sub-region. The spline smoothing coefficient is adaptively adjusted according to the fitting residual, and the extrapolation step size is limited to one to two times the interconnect spacing to avoid excessive overshooting. When the residual exceeds the threshold, piecewise fitting and short-step extrapolation are automatically triggered. This continuous extrapolation guided by visible boundaries allows geometric continuity to be transferred from the visible zone to the invisible zone, providing closed boundary conditions for subsequent integration. In an equivalent implementation, linear extrapolation can be used when the boundary is close to a straight line; circular extrapolation can be used when it is close to an arc; if the design data provides the lower-level shape, the imaging result can also be directly clipped with the design shape within the completely occluded sub-region, all of which can output estimated boundaries that can be used for subsequent steps.

[0023] The reference region refers to a visible, connected block located outside the overlapping region, connected to the underlying chip, and used to set the zero height during subsequent integration. The peripheral structure refers to alignment marks on the substrate or the outer edge of the peripheral chip within the non-overlapping region. In practice, when the underlying chip is exposed, the reference region is selected outside the estimated boundary or the actual boundary of the underlying chip based on connectivity. Isolated areas with an area smaller than the minimum process feature size are eliminated, and a safe distance is maintained between the reference region and the overlapping region. This safe distance is one to two times the interconnect spacing to avoid interference between boundaries. When the underlying chip is completely covered by the overlapping region, a connected block with geometric similarity to the underlying chip can be selected as the reference region outside the overlapping region based on the geometric correspondence between the alignment marks and the design layout, or the correspondence between the outer edge of the peripheral chip and the design shape. The input is the estimated boundary or actual boundary and the peripheral structure; the output is the reference region. The reference region serves as a zero-height anchor point in subsequent integration, ensuring that the height constant of the integration result is determined by the physically connected visible area, thus avoiding overall height drift. In an equivalent implementation, when the package design has solder mask openings or metal reference bands, the openings or reference bands that are connected to the underlying chip can be directly selected as the reference area. The zero-height anchor point provided is more direct, and the integral stability is comparable to the method described above.

[0024] The outer edge of the topmost chip refers to the projected boundary of the chip on the imaging plane above the overlapping area. The occlusion boundary curve refers to the outer edge curve that intersects with the overlapping area and is used to set boundary conditions in subsequent integration. In implementation, within the overlapping area, candidate outer edge segments are first extracted using material spectral differences and gradient responses. The Canny Edge Detector or Sobel Operator, combined with non-maximum suppression, is used to obtain refined edges. Then, valid line segments intersecting the overlapping area are selected and sorted and stitched according to endpoint distance, tangential consistency, and curvature continuity. A maximum allowable gap is set during the stitching process to bridge breaks; if continuity constraints are not met, piecewise curves are retained and the line segment sequence is recorded. The input is the overlapping area and candidate outer edge segments; the output is the occlusion boundary curve or its segment set. Regarding parameters, the minimum line segment length is set to the level of the interconnect spacing to filter out burrs; the upper limit of the stitching gap is one-tenth to one-quarter of the interconnect spacing corresponding to the pixel resolution; the tangential deviation and curvature jump thresholds are determined based on the upper limit calibration. Through this screening and physical constraint-based stitching, even if there are breaks at the outer edge, an occlusion boundary curve that meets the requirements of the subsequent Poisson integral can be generated. In an equivalent implementation, when the outer edge is a regular polygon, the polygon can be directly reconstructed based on the vertex order without curve stitching; when the boundary texture is weak, morphological closing operations can be performed on candidate pixels to connect gaps before stitching. Both methods can output an occlusion boundary curve that meets the requirements of subsequent steps.

[0025] In one embodiment of the present invention, S1 further includes: S15. Determine the interconnect nodes located in the overlapping area based on the design data, and determine the connection relationship between the interconnect nodes in the multilayer chips; S16. Based on the structural and material properties of the interconnecting nodes, calculate the equivalent vertical stiffness and shear stiffness of each interconnecting node. S17. Perform equivalent vertical stiffness and shear stiffness correction on interconnecting nodes located near the boundary of the overlapping region, and remove disconnected interconnecting nodes. S18. Organize the interconnected nodes and their corrected equivalent vertical stiffness and shear stiffness, along with the connection relationships, into interconnection constraint data.

[0026] The following is a detailed description of the steps involved in the above embodiments: Specifically, interconnect nodes refer to discrete connection units located within the overlapping region, used to achieve electrical connections between chips or between a chip and the packaging substrate, and to bear the force transmission. These include solder balls, microbumps, and copper pillars. Connection relationships refer to the continuous conductive paths of interconnect nodes along the interlayer direction and their hierarchical order, used to describe the connection links between upper-layer chips, adhesive layers, lower-layer chips, and the packaging substrate. In implementation, the bump coordinates, outline, and conductivity netlist in the design data are read. Registration from the design coordinate system to the imaging coordinate system is completed using alignment markers, resulting in transformation T. All interconnect node coordinates are projected onto the imaging coordinate system via T, and intersection with the obtained overlapping region polygon is calculated to filter out the set of interconnect nodes located within the overlapping region. For each interconnect node in the set, based on the conductivity netlist and the layer stack description, its connection relationship between multiple layers of chips is traced (e.g., upper-layer chip solder ball—adhesive layer—lower-layer chip pad—trace—via—substrate pad), recording the hierarchical order and path segment attributes. The inputs are design data, transformation T, and the overlapping region; the output is a set of interconnect nodes with connection relationship annotations. The registration tolerance can be set on the order of a few micrometers according to the visual resolution and interconnect spacing to balance recognition rate and mismatch risk. This process clarifies the spatial location of interconnect nodes and interlayer links, providing reliable input for subsequent stiffness calculations and boundary corrections. An equivalent implementation is as follows: when design data is not directly available, interconnect node coordinates can be identified in mass production images using raster fitting and template matching. The connection relationships are then completed by combining the process configuration list and standard stack description, resulting in a node set and connection relationships equivalent to the above process.

[0027] Equivalent vertical stiffness refers to the equivalent linear stiffness of the interconnect node in the interlayer normal (vertical direction), and equivalent shear stiffness refers to the equivalent linear stiffness of the interconnect node in the planar tangential (in-plane) direction. During implementation, for each interconnect node, its structural and material properties are collected, including the diameter of the solder ball or copper pillar, effective load-bearing area, adhesive layer thickness, elastic modulus and shear modulus of each material, and the parallel or series relationship of the path segments. Vertical paths are equivalent in series and parallel: segments in series (such as solder ball segments and adhesive layer segments) are equivalent by adding their reciprocals; segments in parallel (such as multiple points in the same position) are equivalent by adding their stiffnesses. Shear paths are equivalent after being converted according to the shear area and thickness of each segment. The input is the geometric and material parameters of the nodes and their connection relationships; the output is the equivalent vertical stiffness and equivalent shear stiffness of each interconnect node. Parameters can be obtained from mass production process cards and incoming material specifications. Thickness and dimensions are taken from the median or process control target values ​​within the tolerance range to reduce the impact of batch fluctuations on stiffness estimation. By providing equivalent vertical stiffness and equivalent shear stiffness at the node level, the mechanical transfer capability is quantitatively expressed, facilitating the consistency of upper and lower layer displacements with physical weights in subsequent deformation inversion. The equivalent implementation method is as follows: when geometric or material parameters are difficult to obtain completely, an offline calibration can be used to establish a material-geometry-equivalent stiffness lookup table, and values ​​can be assigned according to node type and size, still obtaining equivalent stiffness that meets the accuracy requirements of subsequent solutions.

[0028] Interconnected nodes near the boundary of the overlapping region refer to nodes whose shortest distance to the shading boundary curve is less than a distance threshold d. The distance threshold d can be one to two times the interconnection spacing, reflecting the reduction of parallel load paths and weakening of constraints at the boundary. In implementation, the distance from each interconnected node to the shading boundary curve is calculated, and the number of effective neighbors within its neighborhood radius r is counted. The neighborhood radius r can be the interconnection spacing. Based on the distance and the number of neighbors, vertical and shear correction coefficients are constructed to reduce or fine-tune the equivalent vertical stiffness and equivalent shear stiffness, respectively. Simultaneously, combining the connection relationships and the conduction netlist, disconnected interconnected nodes are removed, including nodes not designed to be connected to the lower-level conduction net and mis-matched nodes that fall into the padless area after registration. The inputs are the initial value of the equivalent stiffness, the shading boundary curve, and the connection relationships; the outputs are the corrected equivalent vertical stiffness and equivalent shear stiffness, as well as the cleaned set of interconnected nodes. Linking the distance threshold to the neighborhood radius and interconnection spacing ensures that the correction only applies to nodes affected by boundary effects. The fewer the number of neighbors or the closer the node is to the boundary, the stronger the reduction, reflecting the objective phenomenon of weakened edge constraints. Through boundary correction and the removal of disconnected nodes, the mechanical constraints of the node set more closely resemble the actual stress state, avoiding the introduction of excessively strong or ineffective constraints during inversion. An equivalent implementation method is to apply anisotropic reduction only to the shear stiffness along the missing half-plane direction outside the overlapping region, thus more closely resembling the boundary situation of insufficient unilateral support.

[0029] Interconnection constraint data refers to a structured data set consisting of the spatial coordinates, hierarchical identifiers, connection relationships, and corrected equivalent vertical and shear stiffness of interconnection nodes. This data serves as the mechanical constraint input for subsequent deformation solutions. In implementation, a record is generated for each interconnection node, containing the node coordinates in the imaging coordinate system, its hierarchical level, connection relationship identifier, and two types of equivalent stiffness. For multi-layered serial paths, a summary of the serial and parallel connections of the path segments can be included for auditing purposes. For nodes that have undergone boundary correction, the distance threshold, neighborhood radius, and correction coefficient range are recorded to ensure traceability. The input is the corrected set of interconnection nodes, and the output is the interconnection constraint data. To facilitate alignment with the relative height map's grid, the coordinate units are consistent with the pixel resolution, and the scaling factor from coordinates to physical length is recorded to support conversion between deformation parameter space and pixel space. Through this organization, the interconnection constraint data can be directly used to sample the relative height map at the interconnection node locations and construct the mechanical terms in the energy function, allowing cross-layer constraints to be integrated into the numerical solution process with minimal interface cost. The equivalent implementation is as follows: the interconnection constraint data can be stored as a columnar table or as a key-value mapping; when the sparse linear algebra library is used for subsequent solving, the index and weight array in compressed sparse row format can also be output in node order, without changing the meaning and usage of the constraints.

[0030] Please continue reading. Figure 1 S2. Obtain polarization intensity data in the overlapping region, and calculate the surface slope field covering the overlapping region based on the polarization intensity data. In one embodiment of the present invention, S2 includes: S21. Within the preset incident angle range, the overlapping area is illuminated with s-polarization and p-polarization, and polarization intensity data are obtained in the two different bands respectively. S22. Calculate the dual-band intensity ratio for the polarization intensity data at each pixel location, and convert the intensity ratio into a local incident angle by looking up a table based on the material band response. S23. Employ multiple azimuth angles to illuminate overlapping areas, perform polarization degree weighted fusion on the incident angle results under each azimuth angle, and output a stable local incident angle distribution; S24. Based on the lighting geometry and local incident angle distribution, the surface normal slope at each location within the overlapping area is calculated to form a surface slope field covering the overlapping area.

[0031] The following is a detailed description of the steps involved in the above embodiments: It should be noted that s-polarization refers to the linear polarization of the electric field vector perpendicular to the incident plane (s-polarization), while p-polarization refers to the linear polarization of the electric field vector parallel to the incident plane (p-polarization). The incident angle refers to the angle between the incident ray and the local surface normal; the azimuth angle refers to the plane rotation angle of the incident plane relative to the imaging coordinate system. In practice, the overlapping area is sequentially illuminated with s-polarization and p-polarization within a preset incident angle range, and polarization intensity data is collected at two different wavelengths to obtain polarization intensity data organized by pixel, wavelength, polarization state, and azimuth angle. The preset incident angle range preferably avoids the sensitivity trough near the Brewster angle of the material, for example, between 35° and 65°, to obtain stable reflection differences; the wavelength combination preferably covers the visible and near-infrared regions to simultaneously utilize the spectral contrast of the metal / organic layer and silicon. The input is the overlapping area and illumination geometry, and the output is the polarization intensity data covering the overlapping area. This step decomposes the coupling between material and geometry for reflection into resolvable intensity changes through orthogonal polarization and dual-band acquisition, thereby reducing ambiguity caused by attitude or material in single-band and single-polarization scenarios. In an equivalent implementation, a fixed incident and rotating analyzer approach can also be used to obtain an equivalent S / P component sequence at the imaging end, still outputting polarization intensity data equivalent to that in this step.

[0032] Material band response lookup table refers to the process of calibrating the correspondence between the intensity ratio and the incident angle of common exposed materials (such as metal layers, passivation layers, resins, and silicon) in two selected bands and two polarization states using standard samples before mass production, thus forming a lookup table. In practice, for each pixel location, the dual-band intensity ratio R is first calculated. R can be defined as the ratio of the intensities of two bands under the same polarization state or a monotonic mapping of the normalized difference. Then, the local incident angle is obtained by interpolation in the lookup table using material type or material combination as the index and R as the independent variable. If materials are mixed within a pixel, multiple lookup table outputs can be linearly combined according to the prior material proportions. The input is the aforementioned polarization intensity data and the material band response lookup table; the output is the initial value of the local incident angle grouped by azimuth. The reason for choosing the preset dual bands is to suppress albedo and light source inhomogeneity using the ratio, making the inversion of the incident angle insensitive to the brightness baseline. In an equivalent implementation, if the production line is limited to a single band, the ratio of s to p intensity can be used as the independent variable to look up a table and calculate the incident angle, or a combination of narrowband near-infrared and visible light can be used to achieve the same brightness normalization effect.

[0033] The degree of polarization (DoP) refers to the difference in polarization components after reflection, and can be defined as: Degree of Polarization (DoP) = |Is - Ip| / (Is + Ip), where Is and Ip are the intensities of s-polarization and p-polarization, respectively. In practice, for each azimuth angle, the initial local incident angle value is used to calculate the corresponding pixel's degree of polarization and incident angle sensitivity index (obtainable from the local slope of the curve in a lookup table). Based on this, the initial incident angle values ​​for each azimuth angle are weighted and fused to output a stable local incident angle distribution. The weighting design ensures that azimuth angles with higher polarization degrees and greater curve sensitivity contribute more, thereby suppressing unstable solutions caused by Brewster's angle neighborhood and weakly polarized echoes. The input is the initial local incident angle value grouped by azimuth angle and the corresponding polarization intensity; the output is the local incident angle distribution covering the overlapping area. The significance of this step is to transform redundant observations from multiple azimuths into statistically robust single incident angle estimates, reducing the angular dead zone caused by a single incident plane. In an equivalent implementation, a regularization term for azimuth coverage uniformity can be added to the weights, or a confidence lower limit can be introduced to eliminate azimuth angles with excessively low weights, thus obtaining a robust incident angle distribution equivalent to polarization degree weighted fusion.

[0034] The surface normal slope refers to the tangential amount of the surface normal in the x and y directions of the imaging coordinate system, denoted as sx and sy respectively. It can be obtained from the normal vector n = (nx, ny, nz) using sx = nx / nz and sy = ny / nz, where nx, ny, and nz represent the components of the normal in the x, y, and z directions of the imaging coordinate system, respectively. In implementation, the known incident direction vector lφ from the illumination geometry and the fused local incident angle α satisfy the relationship cosα = n·lφ. Constraints are established for each pixel under at least two distinct azimuth angles, and the unit normal vector n is calculated (using the least squares solution with constraint ‖n‖ = 1). The surface normal slope components sx and sy for that pixel are then calculated, forming a surface slope field covering the overlapping region. The input is the local incident angle distribution and illumination geometry parameters, and the output is the surface slope field. Using multi-azimuth angles to solve for the normal can avoid the underdetermined problem of "solving three components with one equation" in single-azimuth scenarios. Using the slope field as the input for subsequent integration can directly address mixed boundary conditions and reduce altitude constant drift. In an equivalent implementation, if there are many azimuth angles, the signal-to-noise ratio can be improved by averaging the symmetrical azimuths before solving for the normal; or in small-tilt scenarios, a small-tilt angle approximation can be used to simplify the normal solution into a linear problem to further enhance computational stability and speed.

[0035] In one embodiment of the present invention, S23 includes: S231. Set multiple lighting azimuth angles around the overlapping area according to a preset angle interval, and calculate the angle difference between each azimuth angle position and Brewster's angle. S232. For each pixel position, calculate the degree of polarization and the incident angle sensitivity gradient value under each azimuth angle, and determine the fusion weight of each azimuth angle based on the angle difference. S233. When the angle difference is less than the preset angle threshold, reduce the fusion weight of the corresponding azimuth angle; when the intensity of the reflected signal from the material interface exceeds the preset intensity threshold, increase the fusion weight of the corresponding azimuth angle. S234. Based on the fusion weight, the incident angle results of each azimuth angle are weighted and averaged to output the local incident angle distribution in the overlapping area.

[0036] The following is a detailed description of the steps involved in the above embodiments: It should be noted that the Brewster angle refers to the angle of incidence at which the p-polarization reflection coefficient reaches its minimum value at the interface of the medium. The preset angle interval refers to a set of illumination azimuth angles arranged at fixed intervals around the overlapping area, for example, one azimuth angle every 30° or 45°, ensuring at least four distinct azimuth angles to cover the in-plane direction. During implementation, based on the material-band library calibrated on the production line, the initial value of the current incident angle for each pixel at each azimuth angle is taken, and the difference is calculated with the Brewster angle of the corresponding material in that band to obtain the angle difference value. The inputs are the set of azimuth angles at the preset angle interval, the initial value of the local incident angle, and the Brewster angle corresponding to the material-band; the output is an angle difference map organized by pixel and azimuth angle. The reason for setting the preset angle interval is to cover the complete in-plane direction with fewer azimuth angles, while ensuring sufficient redundancy between adjacent azimuth angles to suppress local instability in subsequent fusion; the angle difference is used to identify observations close to the Brewster angle, preventing the excessive participation of low signal-to-noise and low-robust samples in the fusion process. In an equivalent implementation, an equivalent azimuth sequence can also be synthesized at the imaging end by rotating the analyzer, and then the angle difference can be calculated according to the above process to keep the input and output consistent.

[0037] The incident angle sensitivity gradient value refers to the magnitude of the local slope of the intensity comparison of the incident angle in the lookup table mapping at the current pixel and current azimuth angle. It is used to measure the degree of response of the inverted incident angle to changes in the observation at that azimuth angle. In practice, for each pixel location, the degree of polarization (DoP) and the incident angle sensitivity gradient value are calculated at each azimuth angle. The degree of polarization is calculated from the s-polarization and p-polarization intensities and is used to measure the availability of polarization information. Subsequently, initial fusion weights are constructed based on the angle difference: the larger the angle difference and the further away from the Brewster angle, the higher the initial weight. Based on this, the degree of polarization and the incident angle sensitivity gradient value are normalized to the same dimension interval and then multiplied or a weighted geometric mean is taken to obtain the initial draft of the fusion weights for each azimuth angle. The inputs are polarization intensity, initial incident angle value, and angle difference; the output is the initial draft of the fusion weights for each pixel and each azimuth angle. The significance of this approach lies in simultaneously utilizing the coupling of physical stability (distance from Brewster's angle), information sufficiency (polarization degree), and inversion sensitivity (gradient) to avoid bias caused by a single dominant indicator. In an equivalent implementation, the three indicators can also be written as piecewise scoring functions and linearly superimposed, and finally normalized to obtain an equally usable initial draft of the fusion weights.

[0038] The preset angle threshold refers to the upper limit of the angle difference closest to Brewster's angle, and the preset intensity threshold refers to the lower limit of the intensity of the interface reflection signal to ensure it is sufficiently reliable. In implementation, for each pixel and azimuth angle, if the angle difference is less than the preset angle threshold, the fusion weight of the corresponding azimuth angle is reduced or zeroed. This threshold is taken from the width of the low robust region closest to Brewster's angle in the material-band library to ensure the removal of unstable observations. Subsequently, the interface reflection signal intensity at that azimuth angle is calculated (e.g., the sum of s and p intensities or the larger of them). If the intensity exceeds the preset intensity threshold, a gain is applied to the fusion weight, but an upper limit is set to avoid dominance by a single azimuth angle. The inputs are the initial draft of the fusion weight, the angle difference, and the reflection intensity; the output is the fusion weight corrected by the threshold rule. Both the angle threshold and the intensity threshold are derived from upper limit calibration and signal-to-noise ratio requirements. The former is used to shield physical lows, and the latter is used to encourage high signal-to-noise observations to participate in the fusion. In an equivalent implementation, a robust statistical quantile threshold can be used instead of the fixed threshold, supplemented by median absolute deviation to remove abnormal azimuth angles, achieving the same weight correction effect.

[0039] The incident angle result refers to the initial local incident angle value obtained by table lookup at each azimuth angle. The local incident angle distribution refers to the pixel-level incident angle field after weighting these initial values ​​according to the fusion weights. In practice, for each pixel, the incident angle results of all azimuth angles are weighted and averaged with the corresponding fusion weights to obtain the final local incident angle of that pixel. To prevent bias caused by extreme weights, the weights can be normalized and an upper limit ratio can be set. At the same time, a robust aggregation is performed on the incident angle results (e.g., azimuth angle results exceeding a certain range of the weighted median) before weighting. The input is the corrected fusion weights and the incident angle results of each azimuth angle, and the output is the local incident angle distribution covering the overlapping area. This step gathers redundant information from multiple azimuths into a single-value estimate, significantly reducing the estimation fluctuations caused by material properties or geometric conditions at individual azimuth angles, and providing stable input for subsequent normal calculation and slope field formation. In an equivalent implementation, the weighted average can be replaced with weighted least squares fitting or weighted quantile aggregation, which performs the same or is more robust when there is slight tail noise or a small number of outliers in the incident angle results.

[0040] Please continue reading. Figure 1 S3. Using the reference region as the zero-height boundary and the normal derivative of the occlusion boundary curve as the boundary condition, integrate the surface slope field to obtain the relative height map of the upper chip in the overlapping region. In one embodiment of the present invention, S3 includes: S31. Set the reference region boundary as a Dirichlet boundary condition and assign it a zero height. Calculate the normal derivative on the shading boundary curve based on the surface slope field and set it as a Neumann boundary condition. S32. When the overlapping region contains multiple disconnected sub-regions, solve the Poisson integral independently for each sub-region and apply continuity constraints to the common boundary of adjacent sub-regions. S33. Introduce a first-order smoothing regularization term during the integral solution process to suppress the cumulative diffusion of slope field noise into the height field. S34. Based on the Dirichlet boundary conditions, Neumann boundary conditions, and regularization constraints, solve the Poisson equation to obtain the relative height map of the upper-layer chip within the overlapping region.

[0041] The following is a detailed description of the steps involved in the above embodiments: Specifically, the Dirichlet boundary condition refers to directly specifying the height value at the boundary; the Neumann boundary condition refers to specifying the derivative of the height along the outward normal at the boundary. The reference region boundary refers to the outer edge of the reference region; the shading boundary curve refers to the outer edge formed by the uppermost chip within the overlapping region. In implementation, the height at the reference region boundary is assigned to zero as the benchmark for subsequent integration; then, the normal derivative at the shading boundary curve is calculated based on the surface slope field. The normal derivative is calculated by multiplying the boundary outward normal unit vector by the slope field: at each discrete point of the shading boundary curve, the boundary tangent is obtained and rotated 90° to obtain the outward normal unit vector nb; the tangent of the surface slope field at that point is taken as g = (sx, sy), and let... , where h is the desired height, and sx and sy are the surface normal slopes in the x and y directions, respectively. The inputs are the reference region boundary, the occlusion boundary curve, and the surface slope field. The outputs are the Dirichlet boundary set with zero height and the Neumann boundary set with normal derivative. The reason for assigning zero height to the reference region is to eliminate the uncertainty of the integral constant; the reason for using the slope field projection as the normal derivative is to transform the observable slope information into physical boundary constraints. In an equivalent implementation, a narrow band of one to two pixels wide can be taken along the normal direction outside the occlusion boundary curve, and the normal derivative can be obtained by performing a moving average along the boundary on g·nb to improve robustness under noise conditions; the reference region can also have zero height applied to several anchor points inside the reference region and extended to its outer edge through boundary Laplacian interpolation to obtain an equivalent Dirichlet boundary set.

[0042] Disconnected sub-regions refer to several non-overlapping integral sub-domains obtained by decomposing overlapping regions in the sense of pixel connectivity. In practice, connected component decomposition is performed on the overlapping regions to obtain a set of sub-regions Ωk. Discrete meshes and corresponding boundary sets are prepared within each Ωk: the intersection of the reference region boundary and the occlusion boundary curve within Ωk. The right-hand side of the Poisson equation and boundary conditions are independently established and solved for each Ωk (the explanation of the Poisson equation is described later), yielding the local height distribution hk. Geometrically shared or nearest-neighbor boundary segments of adjacent sub-regions are denoted as Γc. Continuity constraints are applied along Γc: the height difference term and gradient difference term of adjacent solutions are added to their respective least-squares systems in the form of soft-constraint penalties, ensuring that the height at the seam is consistent with the first derivative. The input is Ωk obtained from the connected component decomposition and their respective boundary sets; the output is a multi-sub-region height field with seam continuity. The significance of splitting the large region for solution lies in reducing the scale of a single solution and avoiding cross-domain numerical ill-conditioning; continuity constraints are used to eliminate relative drift at the seams after independent integration of sub-regions. In an equivalent implementation, Ωk can be retained as a global domain at the computational level, and continuity can be achieved by iterating the conjugate gradient of the block diagonal preconditions and adding Lagrange multipliers to the interface determinant. The numerical effect is equivalent to the domain-splitting method. Alternatively, bidirectional least squares registration of overlapping regions can be used to eliminate gaps between sub-regions with small geometric overlap.

[0043] The first-order smooth regularization term refers to Tikhonov regularization, which penalizes the squared integral of the height field gradient to suppress the accumulation and spread of slope field noise during the integration process. In implementation, a term λ‖▽h‖² is introduced into the discrete least squares objective, where ▽h is the height field gradient and λ is the regularization weight. The value of λ can be determined based on the noise level and pixel resolution of the online calibration samples: a larger λ is used when the slope measurement noise is large or the boundaries are incomplete to smooth high-frequency artifacts; a smaller λ is used when structural details need to be preserved to avoid over-smoothing out small fluctuations. The input is the discrete gradient of the slope field and the regularization weights, and the output is a system of linear equations containing the regularization term. The significance of introducing first-order smooth regularization is to transform height recovery from a strict integral to a robust fit, preventing local noise and isolated measurement errors from propagating significantly along the integration path. In an equivalent implementation, when stronger edge preservation is required, first-order smoothing regularization can be replaced with total variation (TV) regularization, which suppresses noise while preserving step edges by penalizing the first norm of ‖▽h‖; alternatively, anisotropic weights can be added to the regularization term to make the smoothness along the tangent of the occlusion boundary slightly stronger than that along the normal, thereby weakening the striping caused by the uncertainty of the normal derivative.

[0044] In this implementation, the Poisson equation is presented in the least squares form: for the known surface normal slope fields sx and sy, a discrete divergence is constructed. And solve within the overlapping region Ω Combining the aforementioned Dirichlet and Neumann boundary conditions with first-order smooth regularization constraints, the relative height map h of the upper-layer chip within the overlapping region is obtained. In implementation, Ω is discretized into a pixel grid; a five-point Laplacian operator is used for discretization. The right-hand side b is obtained using a forward-backward difference hybrid method; the boundary conditions are written into the system equations (direct assignment in Dirichlet rows, approximation in Neumann rows using normal difference), and λ‖▽h‖ is added. 2 The corresponding discrete terms are solved using preconditional conjugate gradients or multigrid iterations, with the iteration stopping criterion being a relative residual less than 10. -6 Or the gain is below a threshold. The input is a slope field, boundary conditions, and regularization weights; the output is a relative height map. This process integrates the slope constraint with the height using divergence least squares, and with mixed boundary and regularization terms, a stable surface shape can be obtained under occlusion and noise conditions. In an equivalent implementation, a Poisson solver based on fast Fourier transform can be used in the rectangular extended domain, and boundary and regularization can be implemented with masks and penalty terms, or a finite element triangular mesh can be used to better fit the complex shape. The solution results are consistent with those of the finite difference method in this scenario.

[0045] In one embodiment of the present invention, S32 includes: S321. Based on the topological characteristics of the occlusion boundary curve, identify each disconnected sub-region within the overlapping area and assign an independent integration domain identifier to each sub-region. S322. For each disconnected sub-region, the local height distribution of each sub-region is obtained by independently solving the Poisson equation based on the Dirichlet conditions and Neumann conditions on its boundary. S323. Identify the common boundary segments between adjacent unconnected sub-regions and set high continuity and gradient continuity constraints on the common boundaries.

[0046] The following is a detailed description of the steps involved in the above embodiments: It should be noted that the topological characteristics of the occlusion boundary curve refer to the closure relationship, branching relationship, number of holes, and relative positional relationships of line segments within the overlapping region. Disconnected sub-regions refer to integral sub-domains that are inaccessible to each other under pixel connectivity after being segmented by the occlusion boundary curve; the integral domain identifier is a unique number assigned to each sub-domain for subsequent independent solution and stitching. In implementation, the occlusion boundary curve and overlapping region are unified to the imaging coordinate system, sub-pixel rasterization is performed, and the data is written into the mask. The rasterization bandwidth is set to one to two pixels to ensure continuous obstruction. The mask is decomposed into sub-domains using four-adjacent connected component analysis, and holes are marked as prohibited areas according to the even-odd fill rule or winding number to avoid incorrect integration. To suppress minor boundary breaks caused by imaging noise, an upper limit for bridging gaps is set; gaps exceeding the upper limit are not merged, and gaps below the upper limit are filled with a one-pixel virtual edge. Subsequently, an integral domain identifier is assigned to each connected component, and the adjacency graph between sub-domains is recorded. The input consists of overlapping regions and occlusion boundary curves, and the output is a set of disconnected sub-regions with unique integration domain identifiers and their adjacency relationships. Four-adjacency is preferred over eight-adjacency because it avoids false connectivity caused by diagonal omissions; the upper limit of bridging gaps should ideally be one-tenth to one-quarter of the interconnect spacing corresponding to the pixel resolution to achieve a balance between real breakpoints and minor gap repair. In other embodiments, polygon Boolean segmentation can be performed directly on the overlapping regions and occlusion boundaries at the vector level, and then the sub-polygons can be projected back into the pixel domain, resulting in higher shape fidelity and an output equivalent to the above process.

[0047] For each disconnected sub-region, Dirichlet boundary conditions and Neumann boundary conditions are collected point-by-point along its boundary. Boundary points falling on the reference region boundary are assigned zero height, and boundary points falling on the occlusion boundary curve are written into the constraint using the projection of the surface slope field onto the outward normal direction as the normal derivative. Within the sub-domain, a slope divergence term on the right-hand side of the Poisson equation is constructed using a five-point Laplace discretization method. A linear equation system is independently assembled on the sub-domain grid and solved iteratively using the preconditioned conjugate gradient (PCG) method or the multigrid method. The iteration stopping threshold can be set to a relative residual less than 1 x 10^-6, or a gain below a set value for several consecutive steps. For sub-domains with excessively small areas or extreme aspect ratios, lower limits can be set for area and minimum width; those below the lower limits are merged into adjacent sub-domains to reduce the severity of the problem. The input is the boundary conditions and slope divergence of each sub-domain, and the output is the local height distribution of each sub-domain and the corresponding index from the boundary to the solution. This domain-independent solution breaks down large problems into several smaller subproblems with better condition numbers, and naturally supports parallelism, adapting to mass production cycles. In other embodiments, discrete equations with a block-by-block diagonal structure can be assembled in the global domain at once, and the equation blocks of each subdomain can be solved in parallel, or finite element triangular mesh discretization can be used to fit complex boundaries, and the physical meaning of the solution is consistent with the pixel mesh finite difference method.

[0048] A common boundary segment refers to a set of shared boundaries between two geometrically adjacent, non-occluding sub-regions. During identification, candidate boundary pairs are located using the aforementioned adjacency relationship. Segments coinciding with occluding boundary curves are eliminated, while seams originating from the same physical surface are retained. For each common boundary segment, two types of constraints are applied to the corresponding solutions on both sides: a height continuity constraint requires the height difference between corresponding pixel positions to approach zero; a gradient continuity constraint requires the first derivatives of the normal and tangential directions along the common boundary to be consistent on both sides. The assembly method can employ soft constraint penalties, adding the difference between the variables on both sides as a weighted residual term to their respective least-squares systems. Weights can be set hierarchically, with height continuity weights greater than gradient continuity weights to avoid over-smoothing of real microsteps. When the common boundary crosses a reference region, height continuity is prioritized, and gradient weights are appropriately reduced to avoid conflict with zero-height anchor points. The input is the sub-domain height distribution and the set of common boundary segments; the output is the assembled solution after applying continuity constraints or a line of coupled equations for global fine-tuning. This processing suppresses relative drift and corner mismatch at the seams, ensuring that the final relative height map remains visually and physically continuous. In other embodiments, strips one to two pixels wide can be taken on both sides of the common boundary, and weighted least squares translation and tilt registration can be performed. The registration parameters are then fed back into the solutions of adjacent subdomains to achieve a stitching effect equivalent to the continuity penalty constraint.

[0049] Please continue reading. Figure 1 S4. Based on the relative height map and interconnection constraint data, solve for the low-order deformation parameters of the lower-layer chip in the overlapping region.

[0050] In one embodiment of the present invention, S4 includes: S41. Discretely sample the relative height map at the locations of interconnecting nodes to obtain the upper-level displacement observations at each interconnecting node. S42. Calculate the theoretical displacement values ​​of the lower layer at each interconnect node based on the parameterized deformation model of the principal curvature and torsional curvature of the lower layer chip. S43. The difference between the observed displacement value of the upper layer and the theoretical displacement value of the lower layer is used as the interconnection deformation. Combined with the equivalent vertical stiffness and shear stiffness of the interconnection nodes, the elastic constraint energy of each node is calculated. S44. Solve for the principal curvature and torsional curvature parameters of the lower-layer chip by minimizing the objective function of the elastic constraint energy and deformation parameter regularization term.

[0051] The following is a detailed description of the steps involved in the above embodiments: Specifically, the relative height is denoted as h. u (x, y) represents the relative height distribution of the upper-layer chip in pixels within the overlapping region; interconnect nodes refer to discrete connection units that undertake electrical connections and mechanical transmission, and the position of the i-th interconnect node in the imaging coordinate system is (x, y).i ,y i During implementation, the coordinates of interconnected nodes are aligned with the pixel grid of the relative height map, in (x i ,y i Interpolation is performed at point ) to obtain the upper-level displacement observation value w. u (x i ,y i Interpolation is preferably bilinear or cubic spline; to suppress single-point noise, a mean or Gaussian smoothing can be performed first within the neighborhood scaled by the interconnect spacing before sampling; when nodes fall on pixel boundaries or grid gaps, spline interpolation is used to avoid quantization errors. The input is a relative height map h. u With the set of interconnected node coordinates The output is the observation sequence. This approach maps continuous surface quantities to the same coordinate set of the interconnected network, facilitating parallel solution by assembling constraints only at nodes. In an equivalent implementation, if the height is stored as a vector surface, it can be directly mapped in (x... i ,y i The surface at point ) is evaluated to obtain w u No pixel-domain interpolation is required, and the input and output remain consistent.

[0052] The low-order deformation of the lower-layer chip within the overlapping region is parameterized using quadratic surfaces. The principal curvatures along the x and y directions are k and k, respectively. x k y The curvature of the distortion is k xy In the lower reference coordinate system, the lower theoretical displacement is written as: ; Where t x , t y The overall slightly tilted term is eliminated by the zero-height constraint of the reference region. Substituting the interconnect node coordinates yields... The input consists of node coordinates and the parameters to be determined. The output is a sequence. This low-order representation covers the main deformation forms such as arching, saddle-shaped, and twisted forms with very few parameters, suppressing ill-conditioned degrees of freedom while maintaining the convexity of the subsequent objective function. When the area is large and shows signs of cubic warping, a small-weighted cubic residual basis function can be added, but the principal solution remains k. x k y k xy Additional items are only for fine-tuning.

[0053] The interconnect deformation is determined by the difference between upper-level observations and lower-level theory at the nodes. Vertical deformation: .

[0054] Considering tangential shear, let the effective interlayer height be... The vertical distance from the lower bearing surface to the upper bearing surface is approximately represented by the in-plane relative displacement vector as follows: .

[0055] The equivalent vertical stiffness of the i-th node is The equivalent shear stiffness matrix is When isotropic When they are anisotropic Therefore, the nodal elastic constraint energy is obtained: .

[0056] Input is The output is The vertical term reflects the mismatch between bulges or depressions, while the shear term reflects the mismatch between in-plane stretching and twisting. Both constrain the upper-layer surface shape information to the lower-layer curvature parameters via an interconnected network. In an equivalent implementation, weights can also be included according to the orthogonal tangential direction, i.e., the second term can be rewritten as... It is used for long and short axis solder joints or asymmetric adhesive layers.

[0057] The deformation parameters are obtained by minimizing the overall objective function. The objective function consists of regularization terms for the elastic properties and parameters of all nodes: .

[0058] in For curvature regularization weights, The relative weights of the distortion terms, This represents the weight of the skewed term. Because... It is a quadratic function and Depends on The first derivative, For about For convex quadratic forms, the solution can be obtained directly using weighted least squares or through preconditional conjugate gradient iteration. The termination criterion is a relative residual of less than 10. -6 Or the parameter increment norm is below the threshold. A larger value is taken when the number of interconnects is sparse or the overlap band is narrow. Stabilize the solution; decrease when observations are sufficient and uniformly distributed. To preserve true low-order deformation; Based on the statistical settings of the distortion amplitude of the material anisotropy or historical samples; It reflects the expected range of the assembly posture.

[0059] The chip packaging method in the embodiments of the present invention has been described above. The chip packaging apparatus in the embodiments of the present invention will be described below. Please refer to [link / reference]. Figure 2 One embodiment of the chip packaging apparatus of the present invention includes: The scene recognition module 101 is used to determine the overlapping area, the reference area outside the overlapping area, and the occlusion boundary curve formed by the outer edge of the upper chip based on the imaging data, and to obtain the interconnection nodes and their stiffness constraint data located in the overlapping area to obtain interconnection constraint data. The polarization detection module 102 is used to acquire polarization intensity data in the overlapping region and calculate the surface slope field covering the overlapping region based on the polarization intensity data. The integral reconstruction module 103 is used to integrate the surface slope field with the reference area as the zero-height boundary and the normal derivative of the occlusion boundary curve as the boundary condition to obtain the relative height map of the upper chip in the overlapping area. The cross-layer inversion module 104 is used to solve the low-order deformation parameters of the lower-layer chip in the overlapping region based on the relative height map and interconnection constraint data.

[0060] above Figure 2 The chip packaging device in the embodiments of the present invention will be described in detail from the perspective of modular functional entities. The chip packaging equipment in the embodiments of the present invention will be described in detail from the perspective of hardware processing.

[0061] Figure 3 This is a schematic diagram of a chip packaging device 200 provided in an embodiment of the present invention. The chip packaging device 200 can vary significantly due to different configurations or performance characteristics. It may include one or more processors 210 (e.g., one or more processors) and a memory 220, and one or more storage media 230 (e.g., one or more mass storage devices) for storing application programs 233 or data 232. The memory 220 and storage media 230 can be temporary or persistent storage. The program stored in the storage media 230 may include one or more modules (not shown in the diagram), each module including a series of instruction operations on the chip packaging device 200. Furthermore, the processor 210 may be configured to communicate with the storage media 230 and execute a series of instruction operations on the storage media 230 on the chip packaging device 200 to implement the steps of the aforementioned chip packaging method.

[0062] The chip packaging device 200 may also include one or more power supplies 240, one or more wired or wireless network interfaces 250, one or more input / output interfaces 260, and / or one or more operating systems 231, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. Those skilled in the art will understand that... Figure 3The chip packaging device structure shown does not constitute a limitation on the chip packaging device provided by the present invention. It may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0063] The present invention also provides a computer-readable storage medium, which can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium, wherein the computer-readable storage medium stores instructions that, when the instructions are executed on a computer, cause the computer to perform the steps of the chip packaging method.

[0064] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system, device, or unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0065] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0066] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A chip packaging method, characterized in that, include: Based on the imaging data, the overlapping region, the reference region outside the overlapping region, and the occlusion boundary curve formed by the outer edge of the upper chip are determined, and the interconnect nodes and their stiffness constraint data within the overlapping region are obtained to obtain the interconnect constraint data. Polarization intensity data is acquired in the overlapping region, and the surface slope field covering the overlapping region is calculated based on the polarization intensity data. Using the reference region as the zero-height boundary and the normal derivative of the occlusion boundary curve as the boundary condition, the surface slope field is integrated to obtain the relative height map of the upper chip in the overlapping region. Based on the relative height map and interconnection constraint data, the low-order deformation parameters of the lower-layer chip in the overlapping region are solved.

2. The chip packaging method according to claim 1, characterized in that, The process of determining the overlapping region, the reference region located outside the overlapping region, and the occlusion boundary curve formed by the outer edge of the upper chip based on imaging data includes: Based on the differences in material spectra in the imaging data, the chip projection is segmented, and the overlapping area of ​​multiple chips projected onto the plane is determined. The overlapping region is divided into a fully occluded sub-region and a partially occluded sub-region. The lower chip boundary of the fully occluded sub-region is reconstructed by extending and fitting the visible lower chip boundary in the partially occluded sub-region. When the lower chip is partially exposed, the reference area is determined based on the exposed area; when the lower chip is completely covered, the reference area is determined based on the surrounding structure. Within the overlapping area, the outer edge line segment intersecting the overlapping area is extracted from the outer edge of the uppermost chip and spliced ​​together to obtain the occlusion boundary curve.

3. The chip packaging method according to claim 1, characterized in that, Obtain the interconnection nodes and their stiffness constraint data located within the overlapping region to obtain interconnection constraint data, including: Based on the design data, determine the interconnect nodes located within the overlapping area, and determine the connection relationship of the interconnect nodes between the multi-layer chips; Based on the structural and material properties of the interconnecting nodes, calculate the equivalent vertical stiffness and shear stiffness of each interconnecting node; Equivalent vertical stiffness and shear stiffness correction are performed on interconnected nodes located near the boundary of the overlapping region, and disconnected interconnected nodes are eliminated. The interconnecting nodes and their corrected equivalent vertical and shear stiffnesses are organized with the connection relationships into interconnecting constraint data.

4. The chip packaging method according to claim 1, characterized in that, The step of acquiring polarization intensity data in the overlapping region and calculating the surface slope field covering the overlapping region based on the polarization intensity data includes: Within a preset incident angle range, the overlapping area is illuminated with s-polarization and p-polarization, and polarization intensity data are acquired in two different bands. The intensity ratio of the two bands is calculated for the polarization intensity data at each pixel location, and the intensity ratio is converted into a local incident angle by looking up a table based on the material band response. By employing multiple azimuth angle illumination overlapping areas, polarization degree weighted fusion is performed on the incident angle results under each azimuth angle to output a stable local incident angle distribution; Based on the lighting geometry and local incident angle distribution, the surface normal slope at each location within the overlapping area is calculated, forming a surface slope field covering the overlapping area.

5. The chip packaging method according to claim 4, characterized in that, The method employs multiple azimuth angles to illuminate overlapping areas, performs polarization degree weighted fusion on the incident angle results at each azimuth angle, and outputs a stable local incident angle distribution, including: Multiple lighting azimuth angles are set around the overlapping area according to a preset angle interval, and the angle difference between each azimuth angle position and Brewster angle is calculated. For each pixel location, the degree of polarization and the incident angle sensitivity gradient value are calculated at each azimuth angle, and the fusion weight of each azimuth angle is determined based on the angle difference; When the angle difference is less than the preset angle threshold, the fusion weight of the corresponding azimuth angle is reduced; when the intensity of the reflected signal from the material interface exceeds the preset intensity threshold, the fusion weight of the corresponding azimuth angle is increased. The incident angle results of each azimuth angle are weighted and averaged according to the fusion weight, and the local incident angle distribution in the overlapping area is output.

6. The chip packaging method according to claim 1, characterized in that, The process of integrating the surface slope field using a reference region as the zero-height boundary and the normal derivative of the occlusion boundary curve as the boundary condition to obtain the relative height map of the upper chip within the overlapping region includes: Set the reference region boundary as a Dirichlet boundary condition and assign it a zero height. Calculate the normal derivative on the shading boundary curve based on the surface slope field and set it as a Neumann boundary condition. When the overlapping region contains multiple disconnected sub-regions, the Poisson integral is solved independently for each sub-region, and a continuity constraint is applied to the common boundary of adjacent sub-regions. A first-order smoothing regularization term is introduced during the integral solution process to suppress the cumulative diffusion of slope field noise into the height field; Based on the Dirichlet boundary conditions, Neumann boundary conditions, and regularization constraints, the Poisson equation is solved to obtain the relative height map of the upper-layer chip within the overlapping region.

7. The chip packaging method according to claim 6, characterized in that, When the overlapping region contains multiple disconnected sub-regions, the Poisson integral is solved independently for each sub-region, and a continuity constraint is applied to the common boundary of adjacent sub-regions, including: Based on the topological characteristics of the occlusion boundary curve, identify each disconnected sub-region within the overlapping area and assign an independent integral domain identifier to each sub-region. For each disconnected subregion, the local height distribution of each subregion is obtained by independently solving the Poisson equation based on the Dirichlet conditions and Neumann conditions on its boundary. Identify common boundary segments between adjacent disconnected sub-regions and set high continuity and gradient continuity constraints on the common boundaries.

8. The chip packaging method according to claim 1, characterized in that, The step of solving for the low-order deformation parameters of the lower-layer chip in the overlapping region based on the relative height map and interconnect constraint data includes: The relative height map is discretized at the locations of interconnection nodes to obtain the upper-level displacement observations at each interconnection node. Based on the parameterized deformation model of the principal curvature and torsional curvature of the lower-layer chip, the theoretical displacement value of the lower layer at each interconnect node is calculated. The difference between the observed displacement value of the upper layer and the theoretical displacement value of the lower layer is used as the interconnection deformation. Combined with the equivalent vertical stiffness and shear stiffness of the interconnection nodes, the elastic constraint energy of each node is calculated. The principal curvature and torsional curvature parameters of the lower-layer chip are solved by minimizing the objective function of the elastic constraint energy and the deformation parameter regularization term.

9. A chip packaging device, characterized in that, The chip packaging device includes: The scene recognition module is used to determine the overlapping area, the reference area outside the overlapping area, and the occlusion boundary curve formed by the outer edge of the upper chip based on the imaging data, and to obtain the interconnection nodes and their stiffness constraint data within the overlapping area to obtain interconnection constraint data. The polarization detection module is used to acquire polarization intensity data in the overlapping region and calculate the surface slope field covering the overlapping region based on the polarization intensity data. The integral reconstruction module is used to integrate the surface slope field with the reference region as the zero-height boundary and the normal derivative of the occlusion boundary curve as the boundary condition to obtain the relative height map of the upper chip in the overlapping region. The cross-layer inversion module is used to solve the low-order deformation parameters of the lower-layer chip in the overlapping region based on the relative height map and interconnection constraint data.

10. A chip packaging device, characterized in that, The chip packaging device includes: a memory and at least one processor, wherein the memory stores instructions; The at least one processor invokes the instructions in the memory to cause the chip packaging device to perform the steps of the chip packaging method as described in any one of claims 1 to 8.

Images