Power semiconductor package

Abstract

A power semiconductor package includes a substrate; a chip, wherein the chip is fixed on the substrate through a double-layer sintered silver joint structure; and an epoxy molding compound at least molding the chip and a portion of the double-layer sintered silver bonding structure. The double-layer sintered silver joint structure comprises a first sintered silver layer and a second sintered silver layer, wherein the first sintered silver layer is positioned on the substrate; and the second sintered silver layer is positioned on the first sintered silver layer, and the chip is positioned on the second sintered silver layer. The first sintered silver layer has a low porosity of less than 5% and the second sintered silver layer has a low Young's modulus of less than 20 GPa.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a power semiconductor package. Background Technology

[0002] In the field of electronics manufacturing, especially for the bonding of discrete components (such as the process of fixing chips onto substrates), the current mainstream practice is to use high-lead tin for bonding because it is less expensive. Furthermore, the heat dissipation efficiency of traditional high-lead tin bonding methods is approximately 45 W / m·K.

[0003] With the increasing application of high-power chips (such as GaN / SiC MOSFETs), the requirements for heat dissipation performance are also increasing. In order to further improve the heat dissipation performance of chips, it is necessary to consider using materials with better heat dissipation performance than high-lead tin, and sintered silver technology has been proposed as an alternative for this reason.

[0004] However, when applied to chip bonding, existing pressureless sintering silver technology still faces some technical challenges. Its main drawback is that pressureless sintering silver paste may crack and delamination at certain critical locations, such as the interface between the silver paste and the substrate (or support) or the interface between the silver paste and the chip sidewall. These interface problems directly affect the reliability of the product. Summary of the Invention

[0005] The main objective of this invention is to provide an improved high-power semiconductor package and its manufacturing method to overcome the shortcomings or defects of the prior art.

[0006] This invention provides a power semiconductor package comprising a substrate; a chip fixed to the substrate by a double-layer sintered silver bonding structure; and an epoxy molding compound (EMC) that at least encapsulates the chip and a portion of the double-layer sintered silver bonding structure. The double-layer sintered silver bonding structure includes a first sintered silver layer on the substrate; and a second sintered silver layer on the first sintered silver layer, with the chip located on the second sintered silver layer.

[0007] According to an embodiment of the present invention, the first sintered silver layer has a low porosity of less than 5%, and the second sintered silver layer has a low Young's modulus of less than 20 GPa.

[0008] According to an embodiment of the present invention, the first sintered silver layer has uniform spherical particles at the nanometer to submicrometer level.

[0009] According to an embodiment of the present invention, the second sintered silver layer has columnar or blocky distributed particles.

[0010] According to an embodiment of the present invention, the Young's modulus of the second sintered silver layer is less than that of the first sintered silver layer.

[0011] According to an embodiment of the present invention, the adhesion between the first sintered silver layer and the substrate is greater than 15 MPa.

[0012] According to an embodiment of the present invention, the chip is a power chip.

[0013] According to an embodiment of the present invention, the substrate is a ceramic substrate.

[0014] According to an embodiment of the present invention, the ceramic substrate has a coating, wherein the first sintered silver layer is disposed on the coating.

[0015] According to an embodiment of the present invention, the coating is selected from the group consisting of copper, gold and silver.

[0016] According to an embodiment of the present invention, the first sintered silver layer is used to resist the transverse shear force caused by the mismatch in the coefficients of thermal expansion between the epoxy molding compound and the substrate.

[0017] According to an embodiment of the present invention, the second sintered silver layer is used to buffer the positive shear force caused by the mismatch in the coefficients of thermal expansion between the epoxy molding compound and the chip edge.

[0018] According to an embodiment of the present invention, when a crack begins to appear, the second sintered silver layer is used to prevent the crack from expanding.

[0019] Another aspect of the present invention provides a method for forming a power semiconductor package. First, a substrate is provided; a first silver paste is applied to the substrate; then a second silver paste is applied to the first silver paste; a chip is disposed on the second silver paste; the first and second silver pastes are sintered to form a double-layer sintered silver bonding structure that fixes the chip to the substrate; and the chip is encapsulated with an epoxy molding compound. The double-layer sintered silver bonding structure includes a first sintered silver layer and a second sintered silver layer.

[0020] According to an embodiment of the present invention, the first sintered silver layer has a low porosity of less than 5%.

[0021] According to an embodiment of the present invention, the first sintered silver layer comprises uniform spherical particles at the nanometer to submicrometer scale.

[0022] According to an embodiment of the present invention, the second sintered silver paste layer comprises columnar or blocky distributed particles, and its Young's modulus is less than 20 GPa.

[0023] According to an embodiment of the present invention, the Young's modulus of the second sintered silver layer is less than that of the first sintered silver layer.

[0024] According to an embodiment of the present invention, the adhesion between the first sintered silver layer and the substrate is greater than 15 MPa.

[0025] According to an embodiment of the present invention, the chip is a power chip.

[0026] According to an embodiment of the present invention, the substrate is a ceramic substrate.

[0027] According to an embodiment of the present invention, the ceramic substrate has a coating, wherein the first sintered silver layer is disposed on the coating.

[0028] According to an embodiment of the present invention, the coating is selected from the group consisting of copper, gold and silver. Attached Figure Description

[0029] Figures 1 to 7 This is a schematic diagram illustrating a method for manufacturing a power semiconductor package according to an embodiment of the present invention.

[0030] The reference numerals in the attached figures are explained as follows:

[0031] 1 Power semiconductor packaging

[0032] 10 chips

[0033] 10S sidewall

[0034] 100 substrates

[0035] 101 First plating layer

[0036] 102 Second coating

[0037] 200 Double-layer sintered silver bonded structure

[0038] 201 First Silver Glue

[0039] 201S First Sintered Silver Layer

[0040] 202 Second Silver Glue

[0041] 202S Second Sintered Silver Layer

[0042] 30 Epoxy molding compound

[0043] SP sintering process

[0044] WB Connecting Wire Detailed Implementation

[0045] The following specific embodiments illustrate the implementation of the "power semiconductor packaging and manufacturing method thereof" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions; this is stated beforehand. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention.

[0046] It should be understood that while terms such as "first," "second," and "third" may be used in this document to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one signal from another. Furthermore, the term "or" as used herein should, as appropriate, include any combination of one or more of the associated listed items.

[0047] Please see Figures 1 to 7 This is a schematic diagram illustrating a method for manufacturing a power semiconductor package according to an embodiment of the present invention. Figure 1 As shown, firstly, a substrate 100 is provided, for example, the substrate may be a ceramic substrate. According to embodiments of the present invention, the aforementioned ceramic substrate includes, for example, a direct plated copper (DPC) ceramic substrate, a direct bonded copper (DBC) ceramic substrate, or an active metal brazing (AMB) ceramic substrate, but is not limited thereto. According to another embodiment of the present invention, the substrate 100 may be a leadframe.

[0048] According to an embodiment of the present invention, the substrate 100 includes at least one first plating layer 101 and at least one second plating layer 102. According to an embodiment of the present invention, for example, the first plating layer 101 may be selected from the group consisting of copper, gold, and silver, but is not limited thereto. According to an embodiment of the present invention, for example, the second plating layer 102 may be selected from the group consisting of copper, gold, and silver, but is not limited thereto.

[0049] The bonding process involves applying a first silver paste 201 onto the first plating layer 101 using a dispensing process. According to an embodiment of the present invention, the first silver paste 201 can be a pressureless sintered silver paste, which must meet the following three requirements: (1) small, uniform particles; (2) low porosity; and (3) free of columnar or blocky silver particles. According to an embodiment of the present invention, for example, the first silver paste 201 comprises uniform spherical particles at the nanometer to submicron level. According to an embodiment of the present invention, for example, the first silver paste 201 has a low porosity of less than 5%. Subsequently, a baking process can be performed on the first silver paste 201 to bring it to a semi-cured state.

[0050] like Figure 2 As shown, after bonding, a second dispensing process is performed to apply a second silver paste 202 onto the first silver paste 201. According to an embodiment of the present invention, the area of ​​the second silver paste 202 can be less than or equal to the top surface area of ​​the first silver paste 201. According to an embodiment of the present invention, the first silver paste 201 can be a pressureless sintered silver paste, which must meet the following two requirements: (1) it contains columnar or blocky silver particles; and (2) the Young's modulus after sintering is less than 20 GPa.

[0051] like Figure 3 As shown, a chip 10 is placed on a second silver paste 202. According to an embodiment of the invention, the chip 10 is, for example, a power chip. According to an embodiment of the invention, the chip 10 is a high-power chip, for example comprising a gallium nitride metal-oxide-semiconductor field-effect transistor (GaN MOSFET) or a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET), but is not limited thereto. According to an embodiment of the invention, the second silver paste 202 contacts the sidewall 10S of the chip 10. According to an embodiment of the invention, the chip 10 does not directly contact the first silver paste 201.

[0052] Then, as Figure 4 As shown, for Figure 3 The stacked structure is subjected to a sintering process SP, which sintersects the first silver paste 201 and the second silver paste 202 to form a double-layer sintered silver bonding structure 200 that fixes the chip 10 to the substrate 100. According to an embodiment of the present invention, the double-layer sintered silver bonding structure 200 includes a first sintered silver layer 201S and a second sintered silver layer 202S. According to an embodiment of the present invention, the chip 10 does not directly contact the first sintered silver layer 201S.

[0053] According to an embodiment of the present invention, the first sintered silver layer 201S comprises uniform spherical particles at the nanometer to submicron level and has a low porosity of less than 5%. According to an embodiment of the present invention, the second sintered silver paste layer 202S comprises columnar or blocky particles at the nanometer to micron level, and its Young's modulus is, for example, less than 20 GPa. According to an embodiment of the present invention, the Young's modulus of the second sintered silver layer 202S is less than the Young's modulus of the first sintered silver layer 201S. According to an embodiment of the present invention, the adhesion between the first sintered silver layer 201S and the substrate 100 is greater than 15 MPa.

[0054] According to an embodiment of the present invention, the silver content of the first sintered silver layer 201S is, for example, about 91-93% by weight, and the silver content of the second sintered silver paste layer 202S is, for example, about 85-90% by weight. According to an embodiment of the present invention, the coefficient of thermal expansion of the first sintered silver layer 201S is, for example, about 20-25 PPM / ℃, and the coefficient of thermal expansion of the second sintered silver paste layer 202S is, for example, about 26-40 PPM / ℃. According to an embodiment of the present invention, the Young's modulus of the first sintered silver layer 201S is, for example, about 17.5-21 GPa, and the Young's modulus of the second sintered silver paste layer 202S is, for example, about 8-17.5 GPa. According to an embodiment of the present invention, the porosity of the first sintered silver layer 201S is, for example, less than 5%, and the porosity of the second sintered silver paste layer 202S is, for example, 10-20%.

[0055] like Figure 5 As shown, bonding is performed using a wire bonding process, whereby the chip 10 is electrically connected to the second plating layer 102 using bonding wires WB. According to an embodiment of the present invention, the bonding wires WB may contain copper or gold, but are not limited thereto.

[0056] like Figure 6 As shown, a molding process is performed to form an epoxy molding compound (EMC) 30, which at least molds a portion of the chip 10, the bonding wires WB, and the double-layer sintered silver bonding structure 200. According to an embodiment of the present invention, the epoxy molding compound 30 directly contacts the sidewalls 10S, the first sintered silver layer 201S, and the second sintered silver layer 202S of the chip 10.

[0057] Finally, as Figure 7As shown, after encapsulation, the semiconductor is cut, for example, by mechanical cutting or laser cutting, to form a plurality of power semiconductor packages 1. According to an embodiment of the present invention, the first sintered silver layer 201S is composed of uniform spherical silver paste particles at the nanometer to submicron level with a dense and continuous structure, and has low porosity. Furthermore, its adhesion to the substrate 100 is greater than 15 MPa to resist the lateral shear force generated by the mismatch in the coefficient of thermal expansion (CTE) between the first plating layer 101 and the epoxy molding compound 30, thus preventing cracking at the interface between the first sintered silver layer 201S and the substrate 100. The second sintered silver layer 202S has a low modulus, and its silver paste particles are blocky and columnar, thus it can be used to buffer the positive shear force caused by the mismatch in the coefficient of thermal expansion between the epoxy molding compound 30 and the chip 10. Moreover, if conventional nanoscale spherical sintered silver paste is used as the material for linking the chip 10, cracking may occur at the interface between the sintered silver paste and the sidewall of the chip 10. In a preferred embodiment of the present invention, a second sintered silver layer 202S comprising columnar or blocky particles at the nanometer to micrometer scale is used as the material for linking the chip 10. Because the silver particles of the second sintered silver layer 202S are distributed in a columnar or blocky shape and have a low Young's modulus, cracks can be prevented from expanding when they begin to appear in the second sintered silver layer 202S, thus avoiding cracking at the interface between the second sintered silver layer 202S and the chip 10.

[0058] This invention combines two pressureless silver pastes with different properties to solve the problem of cracking that may occur at different locations in power semiconductor packaging. The advantages of this invention are that it maintains high heat dissipation efficiency, reduces the possibility of cracking between the silver paste and the chip side, and preserves the high reliability and performance of the power semiconductor package.

[0059] Structurally, such as Figure 7 As shown, the power semiconductor package 1 of the present invention includes a substrate 100 and a chip 10, which is fixed to the substrate 100 by a double-layer sintered silver bonding structure 200. According to an embodiment of the present invention, the chip is a power chip. According to an embodiment of the present invention, the substrate 100 includes, for example, a ceramic substrate, but is not limited thereto. According to an embodiment of the present invention, the ceramic substrate has a first plating layer 101, wherein a first sintered silver layer 201S is disposed on the first plating layer 101. According to an embodiment of the present invention, the first plating layer 101 is selected from the group consisting of copper, gold, and silver.

[0060] According to an embodiment of the present invention, the power semiconductor package 1 further includes an epoxy molding compound 30 to mold a chip 10 and a portion of a double-layer sintered silver bonding structure 200. According to an embodiment of the present invention, the double-layer sintered silver bonding structure 200 includes a first sintered silver layer 201S located on a substrate 100; and a second sintered silver layer 202S located on the first sintered silver layer 201S.

[0061] According to an embodiment of the present invention, the chip 10 is fixed on the second sintered silver layer 202S, and the chip 10 does not directly contact the first sintered silver layer 201S.

[0062] According to an embodiment of the present invention, the first sintered silver layer 201S has a low porosity of less than 5%, and the second sintered silver layer 202S has a low Young's modulus of less than 20 GPa. According to an embodiment of the present invention, the Young's modulus of the second sintered silver layer 202S is less than the Young's modulus of the first sintered silver layer 201S.

[0063] According to an embodiment of the present invention, the first sintered silver layer 201S has uniform spherical particles at the nanometer to submicron level. According to an embodiment of the present invention, the second sintered silver layer 202S has columnar or blocky distributed particles.

[0064] According to an embodiment of the present invention, the adhesion between the first sintered silver layer 201S and the substrate 100 is greater than 15 MPa.

[0065] According to an embodiment of the present invention, the first sintered silver layer 201S is used to resist the transverse shear force caused by the mismatch in the coefficients of thermal expansion between the epoxy molding compound 30 and the substrate 100.

[0066] According to an embodiment of the present invention, the second sintered silver layer 202S is used to buffer the positive shear force caused by the mismatch in the coefficients of thermal expansion between the epoxy molding compound 30 and the chip 10.

[0067] According to an embodiment of the present invention, when a crack begins to appear, a second sintered silver layer 202S is used to prevent the crack from expanding.

[0068] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

Claims

1. A power semiconductor package, characterized by, Comprising: a substrate; a chip secured to the substrate by a dual layer sintered silver joint structure; and an epoxy molding compound encapsulating at least the chip and a portion of the dual layer sintered silver joint structure; wherein the dual layer sintered silver joint structure comprises: a first sintered silver layer on the substrate; and a second sintered silver layer on the first sintered silver layer and on which the chip is located; wherein the first sintered silver layer has a low porosity of less than 5% and the second sintered silver layer has a low Young's modulus of less than 20 GPa.

2. The power semiconductor package of claim 1, wherein, The first sintered silver layer has uniform spherical particles in the nano to sub-micron range.

3. The power semiconductor package of claim 1, wherein, The second sintered silver layer has columnar or block-shaped distributed particles.

4. The power semiconductor package of claim 1, wherein, The Young's modulus of the second sintered silver layer is less than that of the first sintered silver layer.

5. The power semiconductor package of claim 1, wherein, The adhesion between the first sintered silver layer and the substrate is greater than 15 MPa.

6. The power semiconductor package of claim 1, wherein, The substrate is a ceramic substrate and the chip is a power chip.

7. The power semiconductor package of claim 6, wherein the power semiconductor package is a power MOSFET package. The ceramic substrate has a plating layer, wherein the first sintered silver layer is disposed on the plating layer.

8. The power semiconductor package of claim 7, wherein the die attach film is a polyimide film. The plating layer is selected from the group consisting of copper, gold and silver.

9. The power semiconductor package of claim 1, wherein, The first sintered silver layer is used to resist lateral shear force generated by the coefficient of thermal expansion mismatch between the epoxy molding compound and the substrate.

10. The power semiconductor package of claim 1, wherein, The second sintered silver layer is used to buffer the positive shear force caused by the coefficient of thermal expansion mismatch between the epoxy molding compound and the chip.

Images