Semiconductor package structure and assembly structure

Abstract

The invention relates to a semiconductor package structure and an assembly structure. A semiconductor package structure includes a vapor chamber, a plurality of electrical contacts, a semiconductor die, and a package. The vapor chamber defines a closed chamber for containing a working liquid. The electrical contacts surround the vapor chamber. The semiconductor die is disposed on the vapor chamber and electrically connected to the electrical contacts by a plurality of bond wires. The package covers a portion of the vapor chamber, a portion of the electrical contact, the semiconductor die, and the bonding wire.

Description

[0001] Related application of division

[0002] This application is a divisional application of the application with the application number “201910950784.7” and the title “Semiconductor Package Structure and Assembly Structure” filed on October 8, 2019, which claims the benefit of and priority to U.S. Provisional Application No. 62 / 742,239 filed on October 5, 2018, and U.S. Non-Provisional Application No. 16 / 579,345 filed on September 23, 2019, the contents of which are incorporated by reference in their entirety.

[0003] Cross-reference to related applications

[0004] This application claims the benefit of and priority to U.S. Provisional Application No. 62 / 742,239 filed on October 5, 2018, and U.S. Non-Provisional Application No. 16 / 579,345 filed on September 23, 2019, the contents of which are incorporated by reference in their entirety. TECHNICAL FIELD

[0005] The present disclosure relates to semiconductor package structures and assembly structures, and to semiconductor package structures and assembly structures that include a vapor cavity. BACKGROUND

[0006] Specifications for semiconductor package structures can include high-speed data transmission capability, high data capacity, and small footprint. Heat dissipation is also an issue for such semiconductor package structures. During operation, high-speed data transmission can cause a large amount of heat to be generated and can increase the temperature of the semiconductor package structure. Because the semiconductor package structure is small in size, heat dissipation is difficult. If efficient heat dissipation is not performed, the performance of the semiconductor package structure can be reduced, or the semiconductor package structure can malfunction or fail to operate. SUMMARY

[0007] In some embodiments, a semiconductor package structure includes a vapor cavity, a plurality of electrical contacts, a semiconductor die, and a package. The vapor cavity defines an enclosed cavity for containing a working liquid. The electrical contacts surround the vapor cavity. The semiconductor die is disposed on the vapor cavity and is electrically connected to the electrical contacts by a plurality of wirebonds. The package covers a portion of the vapor cavity, portions of the electrical contacts, the semiconductor die, and the wirebonds.

[0008] In some embodiments, an assembly includes a host substrate and a semiconductor package structure. The semiconductor package structure is thermally connected to the host substrate. The semiconductor package structure includes a vapor cavity, a semiconductor die, and a package. The semiconductor die is thermally connected to the vapor cavity. The package covers a portion of the vapor cavity and the semiconductor die. The vapor cavity is disposed between the semiconductor die and the host substrate and forms a thermal transfer path from the semiconductor die to the host substrate. BRIEF DESCRIPTION OF DRAWINGS

[0009] When read in conjunction with the accompanying Figure One Aspects of embodiments of the present disclosure can be readily understood by considering the following detailed description in conjunction with the accompanying drawings. It should be noted that the various structures can not be drawn to scale and the dimensions of the various structures can be arbitrarily increased or decreased for the sake of discussion.

[0010] Figure 1 An exploded perspective view of an assembled structure is shown in accordance with some embodiments of the present disclosure.

[0011] Figure 2 A bottom perspective view of a leadframe and a vapor cavity is shown in accordance with some embodiments of the present disclosure. Figure 1

[0012] Figure 3 A bottom perspective view of an assembled leadframe, vapor cavity, and bottom encapsulation is shown in accordance with some embodiments of the present disclosure. Figure 2

[0013] Figure 4 A top perspective view of an assembled leadframe, vapor cavity, and semiconductor die is shown in accordance with some embodiments of the present disclosure. Figure 1

[0014] Figure 5 A top perspective view of an assembled leadframe, vapor cavity, semiconductor die, and wirebonds is shown in accordance with some embodiments of the present disclosure. Figure 1

[0015] Figure 6 A perspective view of an assembled structure is shown in accordance with some embodiments of the present disclosure. Figure 1

[0016] Figure 7 A cross-sectional view of an assembled structure is shown in accordance with some embodiments of the present disclosure. Figure 6

[0017] Figure 8 An enlarged view of the area "A" shown in FIG. 1 is shown in accordance with some embodiments of the present disclosure. Figure 7

[0018] Figure 9 An exploded perspective view of an assembled structure is shown in accordance with some embodiments of the present disclosure.

[0019] Figure 10 A perspective view of a leadframe is shown in accordance with some embodiments of the present disclosure. Figure 9

[0020] A perspective view of an assembled leadframe, vapor cavity, and bottom encapsulation is shown in accordance with some embodiments of the present disclosure. Figure 11 Figure 9 A bottom perspective view of an assembled leadframe, vapor cavity, and bottom encapsulation is shown in accordance with some embodiments of the present disclosure.

[0021] Figure 12 Figure 11 A bottom perspective view of an assembled leadframe, vapor cavity, and bottom encapsulation is shown in accordance with some embodiments of the present disclosure.

[0022] ​​​​​​​​​Figure 13 An assembled top perspective view of the leadframe, vapor cavity, semiconductor die, and wirebonds of Figure 9

[0023] Figure 14 An assembled perspective view of the assembled structure of Figure 9

[0024] Figure 15 A cross-sectional view of the assembled structure of Figure 14

[0025] Figure 16 An exploded perspective view of the assembled structure according to some embodiments of the disclosure.

[0026] Figure 17 A perspective view of the leadframe and vapor cavity of Figure 16

[0027] Figure 18 An assembled top perspective view of the leadframe, vapor cavity, and semiconductor die of Figure 16

[0028] Figure 19 An assembled top perspective view of the leadframe, vapor cavity, semiconductor die, and wirebonds of Figure 16

[0029] Figure 20 An assembled perspective view of the assembled structure of Figure 16

[0030] Figure 21 A cross-sectional view of the assembled structure of Figure 20

[0031] Figure 22 An exploded perspective view of the assembled structure according to some embodiments of the disclosure.

[0032] Figure 23 An assembled top perspective view of the semiconductor package structure of the assembled structure of Figure 22

[0033] A bottom perspective view of the semiconductor package structure of Figure 24 Figure 23 An assembled cross-sectional view of the assembled structure of

[0034] Figure 25 Figure 22 An example of one or more stages of a method for manufacturing a semiconductor package structure according to some embodiments of the disclosure.

[0035] Figure 26 An example of one or more stages of a method for manufacturing a semiconductor package structure according to some embodiments of the disclosure. ​​​​​​​​​​

[0036] Figure 27 One or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the present disclosure are shown.

[0037] Figure 28 One or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the present disclosure are shown.

[0038] Figure 29 An exploded perspective view of an assembled structure according to some embodiments of the present disclosure is shown.

[0039] Figure 30 An assembled top perspective view of a semiconductor package structure of the assembled structure of Figure 29 is shown.

[0040] Figure 31 A bottom perspective view of the semiconductor package structure of Figure 30 is shown.

[0041] Figure 32 An assembled cross-sectional view of the assembled structure of Figure 29 is shown.

[0042] Figure 33 One or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the present disclosure are shown.

[0043] Figure 34 One or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the present disclosure are shown.

[0044] Figure 35 One or more stages of an example of a method for fabricating a semiconductor package structure according to some embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0045] Throughout the drawings and detailed description, identical or similar reference numbers represent identical or similar components. Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.

[0046] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed or arranged in direct contact, and may also include embodiments in which additional features may be formed and arranged between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0047] To meet specifications for increased functionality, the number of devices integrated into the semiconductor package structure must be increased. This increases power density and the number of heat sources, resulting in relatively high thermal resistance. Furthermore, it is difficult to dissipate heat generated by the devices at the center of the semiconductor package structure. To address these issues, in some comparative embodiments, a fan is incorporated. The fan is attached to the semiconductor package structure to dissipate heat at the periphery of the semiconductor package structure through airflow. However, this fan cannot dissipate heat generated by the devices at the center of the semiconductor package structure. In some comparative embodiments, the number of substrate vias or the thickness of the metal layer are increased. However, the improvement in heat dissipation efficiency is negligible. In some comparative embodiments, a thermal interface material (TIM) is used as an intercalation between the device and the package substrate. However, this does not significantly reduce the device temperature at the center of the semiconductor package structure.

[0048] At least some embodiments of this disclosure provide semiconductor package structures and assembly structures with significantly improved heat dissipation efficiency. In some embodiments, the semiconductor package structure includes a vapor chamber for dissipating heat generated by the semiconductor die of the semiconductor package structure.

[0049] Figure 1 An exploded perspective view of an assembly structure 9 according to some embodiments of the present disclosure is shown. Figure 2 Showing Figure 1 Bottom perspective view of lead frame 3 and vapor chamber 12. Figure 3 Showing Figure 2 A three-dimensional view of the bottom of the assembled lead frame 3 and vapor chamber 12. Figure 4 Showing Figure 1 Top perspective view of the assembled lead frame 3, vapor chamber 12 and semiconductor die 14. Figure 5 ShowingFigure 1 an assembled top perspective view of the leadframe 3, the vapor cavity 12, the semiconductor die 14, and the bonding wires 15. Figure 6 an assembled perspective view of Figure 1 an assembled structure 9. Figure 7 an assembled perspective view of Figure 6 a cross-sectional view of the assembled structure 9.

[0050] As shown in Figure 1 , Figure 6 and Figure 7 , the assembled structure 9 includes the main substrate 2 and the semiconductor package structure 1. As shown in Figure 1 and Figure 7 , the main substrate 2 (e.g., a printed circuit board (PCB)) has a first surface 21 (e.g., a top surface) and a second surface 22 (e.g., a bottom surface) opposite the first surface 21, and includes a main body 24, a first protective layer 26, a second protective layer 28, and a plurality of thermal vias 29. The main body 24 has a first surface 241 (e.g., a top surface) and a second surface 242 (e.g., a bottom surface) opposite the first surface 241. The main body 24 can include a plurality of passivation layers (not shown) and a plurality of circuit layers (not shown) interposed between the passivation layers. The first protective layer 26 and the second protective layer 28 can be solder resist layers. The first protective layer 26 is disposed on the first surface 241 of the main body 24. The first protective layer 26 can define a central opening 261 and a plurality of outer openings 262 extending through the first protective layer 26 to expose portions of the circuit layers of the main body 24. The second protective layer 28 is disposed on the second surface 242 of the main body 24. The thermal vias 29 can extend through the main substrate 2, and one end of each of the thermal vias 29 can be exposed from the first surface 241 in the central opening 261.

[0051] The semiconductor package structure 1 is electrically connected to the first surface 21 of the main substrate 2. The semiconductor package structure 1 can be a Quad Flat No leads (QFN) package. The semiconductor package structure 1 includes a leadframe 3, a vapor cavity 12, a thermal paste 13, at least one semiconductor die 14, a plurality of bonding wires 15, an encapsulant 16, a central connection element 17, and a plurality of outer connection elements 18.

[0052] As shown in Figure 2As shown, the lead frame 3 includes a frame 30, four connecting strips 32, and a plurality of electrical contacts 34 (e.g., strip leads) surrounding the frame 30. The frame 30 may include four inner strips 31 connected to each other to form a ring structure and define a central opening 33. The four connecting strips 32 connect the four corners of the frame 30 and extend outward. The electrical contacts 34 (e.g., strip leads) are disposed around the frame 30. The electrical contacts 34 (e.g., strip leads) are not connected to the frame 30 and extend outward. In one embodiment, a protrusion pad 341 may be further disposed on the bottom surface of the end portion of the electrical contacts 34 (e.g., strip leads). Additionally, the frame 30 includes a plurality of retaining pins 36 extending inward. That is, the retaining pins 36 extend from the inner strips 31 of the frame 30 toward the central opening 33. The lead frame 3 (including frame 30, connecting strip 32, electrical contact 34 (e.g., strip lead), protruding pad 341, and retaining pin 36) may be made of copper. The thickness of frame 30, connecting strip 32, and electrical contact 34 is substantially equal to that of each other (about 0.2 mm), and they may be mounted on the same horizontal plane.

[0053] like Figure 2 , Figure 3 and Figure 7 As shown, the vapor chamber 12 is disposed in the central opening 33 of the frame 30. The vapor chamber 12 includes a top wall 121, a bottom wall 122, side walls 123, a top wick structure 124, a bottom wick structure 125, multiple wick bars 126, a peripheral edge 127, and a working fluid 128. The materials of the top wall 121, bottom wall 122, and side walls 123 may be copper, copper alloy, aluminum alloy, stainless steel, or other suitable metals. The top wall 121, bottom wall 122, and side walls 123 are connected or sealed together to define an enclosed chamber for containing the working fluid 128. The material of the working fluid 128 may be water, ethanol, acetone, isopropanol, chlorofluorocarbon (CFC), or other suitable materials. The top wick structure 124 is disposed on the inner surface (i.e., the bottom surface) of the top wall 121. The bottom wick structure 125 is disposed on the inner surface (i.e., the top surface) of the bottom wall 122. Core rods 126 are disposed in a closed cavity, and each core rod 126 is connected at both ends to a top wall 121 and a bottom wall 122, respectively. The thickness of the vapor chamber 12 can be approximately 0.4 mm to 0.6 mm. In some embodiments, the peripheral edge 127 extends horizontally outward from the sidewall 123.

[0054] A peripheral edge 127 of the vapor cavity 12 is disposed on a top surface of the inner bar 31 of the frame 30. That is, the top surface of the inner bar 31 of the frame 30 is used to support the peripheral edge 127 of the vapor cavity 12, and a bottom portion of the vapor cavity 12 is positioned within the central opening 33 of the frame 30. In addition, the vapor cavity 12 can further define a plurality of recessed portions 129 at the sidewall 123. The number and location of the recessed portions 129 of the vapor cavity 12 correspond to the number and location of the fixation pins 36 of the frame 30. Thus, upon assembly, the fixation pins 36 of the frame 30 are disposed in corresponding ones of the recessed portions 291 of the sidewall 123 of the vapor cavity 12 to prevent a shift between the vapor cavity 12 and the frame 30 of the lead frame 3 during a molding process.

[0055] As shown in Figure 4 and Figure 7 , the semiconductor die 14 is disposed on the vapor cavity 12. In one embodiment, the semiconductor die 14 is thermally and physically connected to the top wall 121 of the vapor cavity 12 by the thermal paste 13. The thermal paste 13 can be a thermal interface material (TIM) having a thermal conductivity of about 30 W / mK to about 40 W / mK. The semiconductor die 14 has a first surface 141 (e.g., an active surface) and a second surface 142 (e.g., a back surface) opposite the first surface 141. The semiconductor die 14 can have a thickness of about 0.5 mm to about 0.6 mm. The second surface 142 of the semiconductor die 14 is adhered to the top wall 121 of the vapor cavity 12 by the thermal paste 13.

[0056] As shown in Figure 5 and Figure 7 , the semiconductor die 14 is electrically connected to the electrical contacts 34 (e.g., bar leads) of the lead frame 3 by the wire bonds 15. In one embodiment, the first surface 141 of the semiconductor die 14 is electrically connected to a top surface of the electrical contacts 34 (e.g., bar leads) of the lead frame 3 by the wire bonds 15. The material of the wire bonds 15 can be gold or copper.

[0057] As shown in Figure 6 and Figure 7As shown, the encapsulant 16 (e.g., a molding compound) covers a portion of the vapor cavity 12, portions of the electrical contacts 34 (e.g., strip leads) of the leadframe 3, the semiconductor die 14, and the wire bonds 15. That is, the vapor cavity 12, the electrical contacts 34 (e.g., strip leads), the semiconductor die 14, and the wire bonds 15 are embedded in the encapsulant 16. The encapsulant 16 has a top surface 161, a bottom surface 162 opposite the top surface 161, and side surfaces 163 extending between the top surface 161 and the bottom surface 162. The side surfaces 163 of the encapsulant 16 can be inclined surfaces, and can not cover the outermost ends of the electrical contacts 34 (e.g., strip leads). That is, the outermost ends of the electrical contacts 34 (e.g., strip leads) can be exposed from the encapsulant 16. In addition, the bottom surfaces of the protruding pads 341 of the electrical contacts 34 (e.g., strip leads) of the leadframe 3 and the bottom surface of the bottom wall 122 of the vapor cavity 12 can be substantially coplanar with the bottom surface 162 of the encapsulant 16. That is, the bottom surfaces of the protruding pads 341 of the electrical contacts 34 (e.g., strip leads) of the leadframe 3 and the bottom surface of the bottom wall 122 of the vapor cavity 12 can be exposed from the bottom surface 162 of the encapsulant 16. As shown, the bottom surface 162 of the encapsulant 16 can be substantially coplanar with the first surface 21 of the main substrate 2. Figure 7 As shown, there can be a gap between the bottom surface 162 of the encapsulant 16 and the first surface 21 of the main substrate 2.

[0058] The center connecting element 17 (e.g., a solder material, such as a solder bump) is disposed adjacent to the bottom surface of the bottom wall 122 of the vapor cavity 12. A bottom portion of the center connecting element 17 is disposed in the center opening 261 of the first protective layer 26 to cover and contact one end of the thermal via 29. Thus, the bottom wall 122 of the vapor cavity 12 is mounted or attached to the body 24 of the main substrate 2 by the center connecting element 17. The center connecting element 17 can be a thermal interface material (TIM) having a thermal conductivity of about 30 W / mK to about 40 W / mK. Thus, the vapor cavity 12 of the semiconductor package structure 1 is thermally connected to the thermal via 29 of the main substrate 2, and heat from the vapor cavity 12 can be dissipated to the second surface 22 of the main substrate 2 through the thermal via 29. That is, the vapor cavity 12 is disposed between the semiconductor die 14 and the main substrate 2, and forms or provides a heat transfer path (or a heat dissipating path) from the semiconductor die 14 to the main substrate 2.

[0059] Meanwhile, the outer connecting elements 18 (e.g., a solder material, such as solder bumps) are disposed adjacent to the bottom surfaces of the protruding pads 341 of the electrical contacts 34 (e.g., strip leads) of the leadframe 3. Bottom portions of the outer connecting elements 18 (e.g., solder bumps) are disposed in the outer openings 262 of the first protective layer 26 such that the electrical contacts 34 (e.g., strip leads) of the leadframe 3 are electrically connected to the circuit layer of the body 24 of the main substrate 2.

[0060] Figure 8 Showing Figure 7 An enlarged view of region "A" shown. During operation of the semiconductor die 14, the heat generated by the semiconductor die 14 is absorbed by the working liquid 128 on the top core structure 124 of the vapor chamber 12, heating the working liquid 128 into a high-temperature fluid or high-temperature vapor. The heated working liquid 128 (i.e., the high-temperature fluid or high-temperature vapor) moves downward to the bottom core structure 125, as shown in the first path 41. Then, the heated working liquid 128 (i.e., the high-temperature fluid or high-temperature vapor) is cooled through the heat passage 29 to become a low-temperature liquid or low-temperature vapor, and then moves horizontally to the bottom portion of the core bar 126, as shown in the second path 42. Then, the working liquid 128 moves upward along the core bar 126 to the top core structure 124, as shown in the third path 43. Then, the working liquid 128 on the top core structure 124 moves horizontally, as shown in the fourth path 44. Then, the working liquid 128 on the top core structure 124 can absorb the heat generated by the semiconductor die 14. Therefore, the circulation of the working fluid 128 and its vapor forms a thermal conduction loop. The vapor chamber 12 can conduct heat uniformly and rapidly, thereby obtaining a uniform temperature distribution.

[0061] Figure 9 An exploded perspective view of an assembly structure 9a according to some embodiments of the present disclosure is shown. Figure 10 Showing Figure 9 A three-dimensional view of the lead frame 3a. Figure 11 Showing Figure 9 A three-dimensional view of the assembled lead frame 3a, vapor chamber 12a and bottom package 16b. Figure 12 Showing Figure 11 Bottom perspective view of lead frame 3a, vapor chamber 12a and bottom package 16b. Figure 13 Showing Figure 9 Top perspective view of the assembled lead frame 3a, vapor chamber 12a, semiconductor die 14 and bonding wire 15. Figure 14 Showing Figure 9 The three-dimensional view of the assembled structure 9a. Figure 15 Showing Figure 14 A cross-sectional view of the assembly structure 9a.

[0062] Figures 9 to 15 Assembly structure 9a and Figures 1 to 8The assembly structure 9a is similar to that of the semiconductor package structure 1a, with the differences described below. The semiconductor package structure 1a of the assembly structure 9a includes a lead frame 3a, a vapor chamber 12a, a bottom package 16b, thermal paste 13, at least one semiconductor die 14, multiple bonding wires 15, a top package 16a, a central connecting element 17, and multiple external connecting elements 18.

[0063] like Figure 10 As shown, the lead frame 3a includes a plurality of electrical contacts 34 (e.g., strip leads) surrounding a central opening 33. In one embodiment, the electrical contacts 34 can be separated and spaced apart from each other. That is, the lead frame 3a does not include Figure 2 The frame 30 (i.e., four inner strips 31) and four connecting strips 32. In one embodiment, a protruding pad 341 may be further disposed on the bottom surface of the end portion of the electrical contact 34 (e.g., a strip lead).

[0064] like Figure 11 As shown, the vapor chamber 12a is placed in the central opening 33 of the lead frame 3a. Figure 9 and Figure 11 The vapor chamber 12a and Figures 1 to 8 Similar to the semiconductor vapor chamber 12, except Figure 9 and Figure 11 The vapor chamber 12a does not include the recessed portion 129 at the sidewall 123. The bottom package 16b (e.g., a pre-mold) covers a portion of the vapor chamber 12a and a portion of the electrical contacts 34 (e.g., strip leads). Figure 11 , Figure 12 and Figure 15 As shown, the bottom package 16b has a top surface 161b and a bottom surface 162b opposite to the top surface 161b. The top surface of the electrical contact 34 (e.g., a strip lead) is substantially coplanar with the top surface 161b of the bottom package 16b. The top surface of the vapor chamber 12a protrudes from the top surface 161b of the bottom package 16b. In one embodiment, the top wall 121 of the vapor chamber 12a protrudes from the top surface 161b of the bottom package 16b. Therefore, the top surface of the electrical contact 34 (e.g., a strip lead) and the top wall 121 of the vapor chamber 12a are exposed from the top surface 161b of the bottom package 16b.

[0065] like Figure 12 and Figure 15As shown, the bottom surface of the protruding pad 341 of the electrical contact 34 (e.g., strip lead) of the lead frame 3a and the bottom surface of the bottom wall 122 of the vapor chamber 12a can be substantially coplanar with the bottom surface 162b of the bottom package 16b. That is, the bottom surface of the protruding pad 341 of the electrical contact 34 (e.g., strip lead) of the lead frame 3a and the bottom surface of the bottom wall 122 of the vapor chamber 12a can be exposed from the bottom surface 162b of the bottom package 16b.

[0066] like Figure 13 and Figure 15 As shown, a semiconductor die 14 is disposed in a vapor chamber 12a. In one embodiment, the semiconductor die 14 is thermally bonded and physically attached to the top wall 121 of the vapor chamber 12a via hot paste 13. The semiconductor die 14 has a first surface 141 (e.g., an active surface) and a second surface 142 (e.g., a back surface) opposite the first surface 141. The second surface 142 of the semiconductor die 14 is adhered to the top wall 121 of the vapor chamber 12a via hot paste 13. Then, the first surface 141 of the semiconductor die 14 is electrically connected to the top surface of the electrical contacts 34 (e.g., strip leads) of the lead frame 3a via bonding wires 15.

[0067] like Figure 14 and Figure 15As shown, the top encapsulant 16a (e.g., a molding compound) is disposed on the bottom encapsulant 16b to cover a portion of the vapor cavity 12a, portions of the electrical contacts 34 (e.g., strip leads) of the leadframe 3a, the bottom encapsulant 16b, the semiconductor die 14, and the wire bonds 15. The side surfaces of the top encapsulant 16a can be inclined surfaces and can not cover the outermost ends of the electrical contacts 34 (e.g., strip leads). That is, the outermost ends of the electrical contacts 34 (e.g., strip leads) can be exposed from the top encapsulant 16a. In addition, there can be a boundary between the top encapsulant 16a and the bottom encapsulant 16b. The center connecting element 17 (e.g., a solder material such as a solder bump) is disposed adjacent to the bottom surface of the bottom wall 122 of the vapor cavity 12a. A bottom portion of the center connecting element 17 is disposed in the center opening 261 of the first protective layer 26 to cover and contact one end of the thermal via 29. Thus, the bottom wall 122 of the vapor cavity 12a is mounted or attached to the body 24 of the main substrate 2 by the center connecting element 17. Thus, the vapor cavity 12a of the semiconductor package structure la is thermally connected to the thermal via 29 of the main substrate 2, and heat from the vapor cavity 12a can be dissipated to the second surface 22 of the main substrate 2 through the thermal via 29. Meanwhile, the outer connecting element 18 (e.g., a solder material such as a solder bump) is disposed adjacent to the bottom surface of the protruding pad 341 of the electrical contacts 34 (e.g., strip leads) of the leadframe 3a. A bottom portion of the outer connecting element 18 (e.g., a solder bump) is disposed in the outer opening 262 of the first protective layer 26 such that the electrical contacts 34 (e.g., strip leads) of the leadframe 3a are electrically connected to the circuit layer of the body 24 of the main substrate 2.

[0068] Figure 16 An exploded perspective view of the assembled structure 9b according to some embodiments of the present disclosure is shown. Figure 17 A perspective view of the leadframe 3b and the vapor cavity 12b of Figure 16 Figure 18 An assembled top perspective view of the leadframe 3b, the vapor cavity 12b, and the semiconductor die 14 of Figure 16 Figure 19 An assembled top perspective view of the leadframe 3b, the vapor cavity 12b, the semiconductor die 14, and the wire bonds 15 of Figure 16 Figure 20 An assembled perspective view of the assembled structure 9b according to some embodiments of the present disclosure is shown. Figure 16 Figure 21 A cross-sectional view of the assembled structure 9b according to some embodiments of the present disclosure is shown. Figure 20 Figures 16 to 21 The assembled structure 9b according to some embodiments of the present disclosure is similar to the assembled structure 9 except for the structure of the leadframe 3b and the vapor cavity 12b of the semiconductor package structure lb. Figures 1 to 8 As shown in FIG. 1, the semiconductor package structure la includes a leadframe 3a, a semiconductor die 14, a wire bond 15, a vapor cavity 12a, a top encapsulant 16a, a bottom encapsulant 16b, a center connecting element 17, and an outer connecting element 18.

[0069] Figure 17 ​​​​​​As shown, the lead frame 3b includes a frame 30, four connecting strips 32, and a plurality of electrical contacts 34 (e.g., strip leads) surrounding the frame 30. The frame 30 may include four inner strips 31 connected to each other to form a ring structure and define a central opening 33. The four connecting strips 32 connect the four corners of the frame 30 and extend outward. The electrical contacts 34 (e.g., strip leads) are disposed around the frame 30. The electrical contacts 34 (e.g., strip leads) are not connected to the frame 30 and extend outward. In one embodiment, a protruding pad 341 may be further disposed on the bottom surface of the end portion of the electrical contacts 34 (e.g., strip leads).

[0070] Additionally, the frame 30 includes a plurality of upwardly extending protrusions 37. That is, the protrusions 37 are disposed on the top surface of the inner strip 31 of the frame 30. The vapor chamber 12b can be disposed in the central opening 33 of the frame 30. The vapor chamber 12b includes a top wall 121, a bottom wall 122, side walls 123, a top core structure 124, a bottom core structure 125, a plurality of core rods 126, a peripheral edge 127, and a working fluid 128. The top wall 121, bottom wall 122, and side walls 123 are connected or sealed together to define a closed cavity for containing the working fluid 128. The top core structure 124 is disposed on the inner surface (i.e., the bottom surface) of the top wall 121. The bottom core structure 125 is disposed on the inner surface (i.e., the top surface) of the bottom wall 122. The core rods 126 are disposed in the closed cavity, and each core rod 126 has its two ends connected to the top wall 121 and the bottom wall 122, respectively. In some embodiments, the peripheral edge 127 extends horizontally outward from the sidewall 123.

[0071] The outer edge 127 of the vapor cavity 12b is disposed on the top surface of the inner strip 31 of the frame 30. That is, the top surface of the inner strip 31 of the frame 30 is used to support the outer edge 127 of the vapor cavity 12b, and the bottom portion of the vapor cavity 12b is positioned within the central opening 33 of the frame 30. In addition, the vapor cavity 12b may further define a plurality of openings 1271 at the outer edge 127. It should be noted that the openings 1271 may not extend through the outer edge 127. The number and position of the openings 1271 of the vapor cavity 12b correspond to the number and position of the protrusions 37 of the frame 30. Therefore, after assembly, the protrusions 37 of the frame 30 are disposed or inserted into the corresponding openings in the openings 1271 of the outer edge 127 of the vapor cavity 12b to prevent displacement between the vapor cavity 12b and the frame 30 of the lead frame 3b during molding.

[0072] like Figure 18 and Figure 21As shown, a semiconductor die 14 is disposed on a vapor chamber 12b. In one embodiment, the semiconductor die 14 is thermally bonded and physically attached to the top wall 121 of the vapor chamber 12b via hot paste 13. The semiconductor die 14 has a first surface 141 and a second surface 142 opposite to the first surface 141. The second surface 142 of the semiconductor die 14 is adhered to the top wall 121 of the vapor chamber 12b via hot paste 13.

[0073] like Figure 19 and Figure 21 As shown, the semiconductor die 14 is electrically connected to the electrical contacts 34 (e.g., strip leads) of the lead frame 3b via bonding wires 15. In one embodiment, the first surface 141 of the semiconductor die 14 is electrically connected to the top surface of the electrical contacts 34 (e.g., strip leads) of the lead frame 3b via bonding wires 15.

[0074] like Figure 20 and Figure 21 As shown, the package 16 (e.g., a molding compound) covers a portion of the vapor chamber 12b, a portion of the electrical contacts 34 (e.g., strip leads) of the lead frame 3b, the semiconductor die 14, and the bonding wire 15. The package 16 has a top surface 161, a bottom surface 162 opposite to the top surface 161, and a side surface 163 extending between the top surface 161 and the bottom surface 162. The side surface 163 of the package 16 may be a sloped surface and may not cover the outermost end of the electrical contacts 34 (e.g., strip leads). That is, the outermost end of the electrical contacts 34 (e.g., strip leads) may be exposed from the package 16. Additionally, the bottom surface of the protruding pads 341 of the electrical contacts 34 (e.g., strip leads) of the lead frame 3b and the bottom surface of the bottom wall 122 of the vapor chamber 12b may be substantially coplanar with the bottom surface 162 of the package 16. That is, the bottom surface of the protruding pad 341 of the electrical contact 34 (e.g., strip lead) of the lead frame 3b and the bottom surface of the bottom wall 122 of the vapor chamber 12b can be exposed from the bottom surface 162 of the package 16.

[0075] A central connecting element 17 (e.g., soldering material, such as solder bumps) is disposed adjacent to the bottom surface of the bottom wall 122 of the vapor chamber 12b. The bottom portion of the central connecting element 17 is disposed in the central opening 261 of the first protective layer 26, such that the vapor chamber 12b is mounted to the main substrate 2, and heat from the vapor chamber 12b can be dissipated to the second surface 22 of the main substrate 2 through the heat via 29. Simultaneously, an external connecting element 18 (e.g., solder bumps) is disposed adjacent to the bottom surface of the protruding pads 341 of the electrical contacts 34 (e.g., strip leads) of the lead frame 3b. The bottom portion of the external connecting element 18 (e.g., soldering material, such as solder bumps) is disposed in the external opening 262 of the first protective layer 26, such that the electrical contacts 34 (e.g., strip leads) of the lead frame 3b are electrically connected to the circuit layer of the body 24 of the main substrate 2.

[0076] Figure 22 An exploded perspective view of an assembly structure 9c according to some embodiments of the present disclosure is shown. Figure 23 Showing Figure 22 The top three-dimensional view of the assembled semiconductor packaging structure 1c after the assembly of the 9c assembly structure. Figure 24 Showing Figure 23 The bottom perspective view of the semiconductor packaging structure 1c. Figure 25 Showing Figure 22 The assembled cross-sectional view of the assembly structure 9c. Figures 22 to 25 The assembly structure 9c and Figures 1 to 8 The assembly structure is similar to 9, with the differences described below.

[0077] The semiconductor package structure 1c of the assembly structure 9c includes multiple electrical contacts 50 (e.g., dots), a vapor chamber 12c, thermal paste 13, at least one semiconductor die 14, multiple bonding lines 15, a package body 16c, a central connecting element 17, and multiple external connecting elements 18.

[0078] like Figure 22 As shown, each electrical contact 50 is a dottype that can be formed by electroplating. Electrical contacts 50 can be isolated or separated from each other. In one embodiment, each electrical contact 50 (e.g., a dot) can comprise multiple metal layers. For example, each electrical contact 50 (e.g., a dot) can comprise a gold layer with a thickness of about 0.03 μm to about 0.08 μm, a first palladium layer with a thickness of about 0.1 μm to about 1.0 μm, a nickel layer with a thickness of about 10 μm, and a second palladium layer with a thickness of about 0.05 μm. The thickness of the vapor chamber 12c can be greater than 10 times the thickness of the electrical contacts 50. For example, the thickness of the vapor chamber 12c can be 15, 20, 30, or more times greater than the thickness of the electrical contacts 50. In one embodiment, two turns of electrical contacts 50 (e.g., dots) can be present. However, in other embodiments, three, four, five, or more turns of electrical contacts 50 (e.g., dots) can be present.

[0079] like Figure 23 , Figure 24 and Figure 25As shown, electrical contacts 50 (e.g., dots) surround the vapor chamber 12c. That is, the vapor chamber 12c is disposed in a space surrounded by multiple turns of electrical contacts 50 (e.g., dots). The vapor chamber 12c includes a top wall 121, a bottom wall 122, side walls 123, a top core structure 124, a bottom core structure 125, a plurality of core rods 126, a peripheral edge 127, and a working fluid 128. The top wall 121, bottom wall 122, and side walls 123 are connected or sealed together to define a closed cavity for containing the working fluid 128. The top core structure 124 is disposed on the inner surface (i.e., the bottom surface) of the top wall 121. The bottom core structure 125 is disposed on the inner surface (i.e., the top surface) of the bottom wall 122. The core rods 126 are disposed in the closed cavity, and each core rod of the core rods 126 is connected at both ends to the top wall 121 and the bottom wall 122, respectively.

[0080] like Figure 23 As shown, semiconductor die 14 is thermally bonded and physically connected to the top wall 121 of vapor chamber 12c via thermal paste 13. A first surface 141 of semiconductor die 14 is electrically connected to electrical contact 50 (e.g., a point) via bonding wire 15. Package 16c (e.g., a molding compound) covers a portion of vapor chamber 12c, a portion of electrical contact 50 (e.g., a point), semiconductor die 14, and bonding wire 15. Package 16c has a top surface 161c, a bottom surface 162c opposite to the top surface 161c, and a side surface 163c extending between the top surface 161c and the bottom surface 162c.

[0081] like Figure 24 As shown, the bottom surface of the electrical contact 50 (e.g., a dot) and the bottom surface of the bottom wall 122 of the vapor chamber 12c can be substantially coplanar with the bottom surface 162c of the package 16c. That is, the bottom surface of the electrical contact 50 (e.g., a dot) and the bottom surface of the bottom wall 122 of the vapor chamber 12c can be exposed from the bottom surface 162c of the package 16c.

[0082] like Figure 25 As shown, the central connecting element 17 (e.g., solder material, such as solder bumps) is disposed adjacent to the bottom surface of the bottom wall 122 of the vapor chamber 12c. The bottom portion of the central connecting element 17 is disposed in the central opening 261 of the first protective layer 26, such that the vapor chamber 12c is mounted to the main substrate 2, and heat from the vapor chamber 12c can be dissipated to the second surface 22 of the main substrate 2 through the heat via 29. Meanwhile, the external connecting element 18 (e.g., solder material, such as solder bumps) is disposed adjacent to the bottom surface of the electrical contact 50 (e.g., a dot). The bottom portion of the external connecting element 18 (e.g., solder bumps) is disposed in the external opening 262 of the first protective layer 26, such that the electrical contact 50 (e.g., a dot) is electrically connected to the circuit layer of the body 24 of the main substrate 2.

[0083] Figures 26 to 28Methods for manufacturing semiconductor package structures according to some embodiments of the present disclosure are illustrated. In some embodiments, the methods are used to manufacture, for example, Figures 22 to 25 The semiconductor packaging structure shown is 1c and other semiconductor packaging structures.

[0084] Reference Figure 26 A carrier 52 is provided. The carrier 52 has a top surface 521 and a bottom surface 522 opposite to the top surface 521. The material of the carrier 52 may be a metal such as copper. A plurality of electrical contacts 50 (e.g., dots) can then be formed by electroplating on the top surface 521 of the carrier 52. The electrical contacts 50 may be isolated from each other or separated. In one embodiment, each of the electrical contacts 50 (e.g., dots) may comprise a plurality of metal layers. For example, each of the electrical contacts 50 (e.g., dots) may comprise a gold layer with a thickness of about 0.03 μm to about 0.08 μm, a first palladium layer with a thickness of about 0.1 μm to about 1.0 μm, a nickel layer with a thickness of about 10 μm, and a second palladium layer with a thickness of about 0.05 μm. In one embodiment, a two-turn circuit of electrical contacts 50 (e.g., dots) may be present. However, in other embodiments, three, four, five, or more turns of electrical contacts 50 (e.g., dots) may be present.

[0085] Then, the vapor chamber 12c is placed on the top surface 521 of the carrier 52 and within a space surrounded by multiple turns of electrical contacts 50 (e.g., dots). Thus, the electrical contacts 50 (e.g., dots) surround the vapor chamber 12c. The thickness of the vapor chamber 12c can be greater than 10 times the thickness of the electrical contacts 50. For example, the thickness of the vapor chamber 12c can be 15, 20, 30, or more times greater than the thickness of the electrical contacts 50.

[0086] like Figure 27 As shown, the first surface 141 of the semiconductor die 14 is electrically connected to the electrical contact 50 (e.g., a point) via bonding wire 15. Then, an encapsulation 16c (e.g., a molding compound) is formed on the top surface 521 of the carrier 52 to cover a portion of the vapor chamber 12c, a portion of the electrical contact 50 (e.g., a point), the semiconductor die 14, and the bonding wire 15.

[0087] like Figure 28 As shown, carrier 52 is removed. Then, a single-cutting process is performed to form... Figure 25 The semiconductor package structure 1c shown. The bottom surface of the electrical contact 50 (e.g., a dot) and the bottom surface of the bottom wall 122 of the vapor chamber 12c can be substantially coplanar with the bottom surface 162c of the package body 16c. That is, the bottom surface of the electrical contact 50 (e.g., a dot) and the bottom surface of the bottom wall 122 of the vapor chamber 12c can be exposed from the bottom surface 162c of the package body 16c.

[0088] Figure 29An exploded perspective view of an assembly structure 9d according to some embodiments of the present disclosure is shown. Figure 30 Showing Figure 29 The assembly structure is shown in 9d, and the semiconductor packaging structure is shown in 1d. The top three-dimensional view after assembly is shown. Figure 31 Showing Figure 30 A 1D bottom perspective view of the semiconductor packaging structure. Figure 32 Showing Figure 29 The assembled cross-sectional view of the 9d assembly structure. Figures 29 to 32 The assembly structure 9d and Figures 22 to 25 The assembly structure is similar to that of 9c, with the differences described below.

[0089] The semiconductor package structure 1d of the assembly structure 9d includes multiple electrical contacts 54 (e.g., pillar leads), a vapor chamber 12d, thermal paste 13, at least one semiconductor die 14, multiple bonding wires 15, a package body 16d, a central connecting element 17, and multiple external connecting elements 18.

[0090] like Figure 29 As shown, each electrical contact in electrical contact 54 is a columnar lead formed by etching. Electrical contacts 54 may be isolated or separated from each other. In one embodiment, each electrical contact in electrical contact 54 (e.g., columnar leads) may include a surface finish layer on its top surface. The material of electrical contact 54 may be copper. The surface finish layer may comprise multiple metal layers. For example, the surface finish layer may comprise a gold layer with a thickness of about 0.03 μm to about 0.08 μm, a first palladium layer with a thickness of about 0.1 μm to about 1.0 μm, a nickel layer with a thickness of about 10 μm, and a second palladium layer with a thickness of about 0.05 μm. The thickness of vapor chamber 12d may be less than 5 times the thickness of electrical contact 54. For example, the thickness of vapor chamber 12d may be less than 4 times, 3 times, 2 times, or less than the thickness of electrical contact 54. In one embodiment, two turns of electrical contact 54 (e.g., columnar leads) may be present. However, in other embodiments, there may be three, four, five or more turns of electrical contact 54 (e.g., post leads). In one embodiment, the height of electrical contact 54 may be greater than the width of electrical contact 54.

[0091] like Figure 30 , Figure 31 and Figure 32As shown, electrical contacts 54 (e.g., cylindrical leads) surround a vapor chamber 12d. That is, the vapor chamber 12d is disposed within a space surrounded by multiple turns of electrical contacts 54 (e.g., cylindrical leads). The vapor chamber 12d includes a top wall 121, a bottom wall 122, side walls 123, a top core structure 124, a bottom core structure 125, multiple core rods 126, a peripheral edge 127, and a working fluid 128. The top wall 121, bottom wall 122, and side walls 123 are connected or sealed together to define a closed cavity for containing the working fluid 128. The top core structure 124 is disposed on the inner surface (i.e., the bottom surface) of the top wall 121. The bottom core structure 125 is disposed on the inner surface (i.e., the top surface) of the bottom wall 122. The core rods 126 are disposed within the closed cavity, and each core rod 126 has its two ends connected to the top wall 121 and the bottom wall 122, respectively.

[0092] like Figures 30 to 32 As shown, semiconductor die 14 is thermally bonded and physically connected to the top wall 121 of vapor chamber 12d via thermal paste 13. A first surface 141 of semiconductor die 14 is electrically connected to electrical contact 54 (e.g., columnar lead) via bonding wire 15. Package 16d (e.g., molding compound) covers a portion of vapor chamber 12d, a portion of electrical contact 54 (e.g., columnar lead), semiconductor die 14, and bonding wire 15. Package 16d has a top surface 161d, a bottom surface 162d opposite to the top surface 161d, and a side surface 163d extending between the top surface 161d and the bottom surface 162d.

[0093] like Figures 33 to 35 As shown, the bottom surface of the electrical contact 54 (e.g., a columnar lead) and the bottom surface of the bottom wall 122 of the vapor chamber 12d can be substantially coplanar with the bottom surface 162d of the package 16d. That is, the bottom surface of the electrical contact 54 (e.g., a columnar lead) and the bottom surface of the bottom wall 122 of the vapor chamber 12d can protrude from or be exposed to the bottom surface 162d of the package 16d.

[0094] like Figures 29 to 32 As shown, the central connecting element 17 (e.g., solder material, such as solder bumps) is disposed adjacent to the bottom surface of the bottom wall 122 of the vapor chamber 12d. The bottom portion of the central connecting element 17 is disposed in the central opening 261 of the first protective layer 26, such that the vapor chamber 12d is mounted to the main substrate 2, and heat from the vapor chamber 12d can be dissipated to the second surface 22 of the main substrate 2 through the heat via 29. Meanwhile, the external connecting element 18 (e.g., solder material, such as solder bumps) is disposed adjacent to the bottom surface of the electrical contact 54 (e.g., columnar lead). The bottom portion of the external connecting element 18 is disposed in the external opening 262 of the first protective layer 26, such that the electrical contact 54 (e.g., columnar lead) is electrically connected to the circuit layer of the body 24 of the main substrate 2.

[0095] Figure 33 Methods for manufacturing semiconductor package structures according to some embodiments of the present disclosure are illustrated. In some embodiments, the methods are used to manufacture, for example, Figure 34 The semiconductor packaging structure shown is 1d and other semiconductor packaging structures.

[0096] Reference Figure 35 A carrier 55 is provided. The carrier 55 has a top surface 551 and a bottom surface 552 opposite to the top surface 551. A base metal 56 is then formed or disposed on the top surface 551 of the carrier 55. The material of the base metal 56 may be copper. A first etching process is then performed on the top surface of the base metal 56 to form a connecting plate portion 561 and a plurality of protrusions 562. That is, the connecting plate portion 561 and the protrusions 562 are formed simultaneously and integrally. The protrusions 562 protrude from the connecting plate portion 561. In one embodiment, two rings of protrusions 562 may be present. However, in other embodiments, three, four, five, or more rings of protrusions 562 may be present. Furthermore, the central portion of the connecting plate portion 561 is completely etched to define a central through-hole 563, thereby exposing a portion of the top surface 551 of the carrier 55. A vapor chamber 12d is then disposed on the top surface 551 of the carrier 55 and within the central through-hole 563 of the connecting plate portion 561. Therefore, the protruding portion 562 surrounds the vapor chamber 12d.

[0097] like Figure 32 As shown, the first surface 141 of the semiconductor die 14 is electrically connected to the protrusion 562 via bonding line 15. Then, an encapsulation 16d (e.g., a molding compound) is formed on the top surface of the substrate metal 56 to cover a portion of the vapor chamber 12d, the bonding plate portion 561, the protrusion 562, the semiconductor die 14, and the bonding line 15.

[0098] like ​ As shown, the carrier 55 is removed. Then, a second etching process is performed on the bottom surface of the base metal 56 to completely remove the connecting plate portion 561. Simultaneously, the protrusion 562 becomes an electrical contact 54 (e.g., a columnar lead), which protrudes from the package 16d. The electrical contacts 54 (e.g., columnar leads) can be isolated or separated from each other. Then, a single-cut process is performed to form... ​ The semiconductor package structure 1d is shown.

[0099] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “above,” and “below” are indications of the orientation shown in the accompanying drawings. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that such arrangement does not deviate from the advantages of the embodiments of this disclosure.

[0100] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurred precisely or instances where the event or situation was close to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value may be considered “substantially” the same as or equal to the second numerical value. For example, "basically" vertical can refer to an angle variation range of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0101] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, the surface can be considered substantially flat.

[0102] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may contain plural referents.

[0103] As used herein, the terms “conductive,” “electrically conductive,” and “electrical conductivity” refer to the ability to conduct electric current. Conductive materials generally refer to those materials that offer little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than about 10. 4 S / m, such as at least 10 5 S / m or at least 10 6 Conductive materials with conductivity of S / m. The conductivity of the material may sometimes vary with temperature. Unless otherwise stated, the conductivity of the material is measured at room temperature.

[0104] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that this range format is used for convenience and brevity and should be flexibly interpreted to include not only the numerical values ​​that are explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0105] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes may be made and equivalents may be substituted without departing from the spirit and scope of this disclosure as defined by the claims. Illustrations may not necessarily be drawn to scale. There may be differences between artistic representations in this disclosure and actual devices due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically shown. The specification and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless expressly indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A semiconductor package structure comprising: A vapor chamber is defined as a closed chamber used to contain the working fluid. as well as A semiconductor die is disposed above the vapor chamber, the semiconductor die having an active surface and a back surface opposite to the active surface, the back surface of the semiconductor die facing the top wall of the vapor chamber.

2. The semiconductor packaging structure according to claim 1, wherein the width of the semiconductor die is greater than the width of the vapor chamber.

3. The semiconductor packaging structure according to claim 1, wherein the active surface of the semiconductor die is electrically connected to the top surface of the electrical contact via a bonding wire.

4. The semiconductor package structure according to claim 3, wherein the top surface of the electrical contact is lower than the active surface of the semiconductor die.

5. The semiconductor package structure of claim 4, wherein the top surface of the electrical contact is lower than the back surface of the semiconductor die.

6. The semiconductor packaging structure according to claim 1, further comprising a copper layer disposed beneath the semiconductor die and in contact with the vapor chamber.

7. The semiconductor package structure according to claim 6, wherein the active surface of the semiconductor die is electrically connected to the top surface of the electrical contact via a bonding wire, wherein the thickness of the copper layer is equal to the thickness of the electrical contact.

8. The semiconductor packaging structure according to claim 7, wherein the copper layer and the electrical contacts are disposed on the same horizontal plane.

9. The semiconductor packaging structure of claim 8, wherein the electrical contacts are disposed around the copper layer and are not connected to the copper layer.

10. The semiconductor packaging structure according to claim 1, further comprising: A main substrate is thermally connected to the vapor chamber, wherein the vapor chamber and the main substrate jointly support the semiconductor die, and wherein the vapor chamber and the main substrate are configured to jointly dissipate the heat generated by the semiconductor die.

11. A semiconductor package structure comprising: Main substrate; A vapor chamber, which defines a closed chamber for containing the working fluid and is thermally connected to the main substrate; as well as A semiconductor die is disposed above the vapor chamber and the main substrate, wherein the vapor chamber and the main substrate jointly support the semiconductor die, and wherein the heat generated by the semiconductor die is absorbed by the working fluid on the top core structure of the vapor chamber, thereby heating the working fluid into a high-temperature fluid.

12. The semiconductor packaging structure of claim 11, wherein the vapor chamber and the main substrate are configured to dissipate heat generated by the semiconductor die downwards.

13. The semiconductor packaging structure of claim 11, wherein the vapor chamber is attached to the main substrate.

14. The semiconductor package structure of claim 11, wherein the semiconductor die has an active surface and a back surface opposite to the active surface, the back surface of the semiconductor die facing the top wall of the vapor chamber, wherein the top core structure is disposed on the inner surface of the top wall.

15. The semiconductor package structure of claim 14, wherein the active surface of the semiconductor die is electrically connected to the top surface of an electrical contact via a bonding wire, wherein the electrical contact perpendicularly overlaps the main substrate.

16. A semiconductor package structure comprising: A vapor chamber is defined as a closed chamber used to contain the working fluid. as well as A semiconductor die is disposed above the vapor chamber, the semiconductor die having a first surface and a second surface opposite to the first surface, wherein the first surface of the semiconductor die is electrically connected to an electrical contact via a bonding wire, and wherein the second surface of the semiconductor die is attached to the vapor chamber.

17. The semiconductor package structure of claim 16, wherein a portion of the vapor chamber is disposed below the bonding line.

18. The semiconductor package structure of claim 17, wherein said portion of the vapor chamber is disposed outside the vertical projection range of the semiconductor die.

19. The semiconductor package structure of claim 16, wherein the vapor chamber includes a top wall, a bottom wall, a side wall, a top core structure, and the working fluid, wherein the top wall, the bottom wall, and the side wall are connected together to define the enclosed chamber, the top core structure is disposed on an inner surface of the top wall, and wherein the back surface of the semiconductor die is adhered to the top wall of the vapor chamber.

20. An assembly structure comprising: Main substrate; as well as A semiconductor package structure, thermally connected to the main substrate, includes: A vapor chamber having a peripheral edge, the vapor chamber defining a plurality of recessed portions on its sidewalls; A frame comprising a plurality of retaining pins, wherein the retaining pins of the frame are disposed in corresponding recesses in the recesses of the sidewall of the vapor chamber; Multiple connecting strips connecting the frame; and An encapsulation that covers a portion of the vapor chamber, wherein the top surface of the vapor chamber protrudes from the top surface of the encapsulation.

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