A time-axis phase unwrapping method and system based on FPGA

Abstract

This invention belongs to the field of signal technology for distributed optical fiber sensing (DAS) systems, and discloses a time-axis phase unwrapping method and system based on FPGA. The method includes phase data acquisition, stable group formation, phase progressive unfolding, pipelined and buffered collaborative processing, and quality metric closed-loop correction. The system achieves real-time phase extraction of interference signals through an FPGA demodulation unit, dynamically unfolds phase changes using a reliable periodic screening unit and a phase progressive unfolding unit, and forms an adaptive unwrapping mechanism by combining anomaly detection and threshold update logic. Parallel data transmission and timing synchronization are achieved through a circular buffer and a three-stage pipelined comparator design. This method can effectively improve the accuracy and stability of phase unwrapping in complex noise environments and significantly reduce hardware latency and resource consumption, making it suitable for real-time signal unwrapping processing in high-precision distributed optical fiber sensing systems.

Description

Technical Field

[0001] This invention belongs to the field of signal technology for distributed optical fiber sensing (DAS) systems, specifically a time-axis phase unwrapping method and system based on FPGA. Background Technology

[0002] Distributed fiber acoustic sensing (DAS) systems are a detection technology based on backscattered Rayleigh signals from optical fibers. They are widely used in scenarios such as safety monitoring of oil and gas pipelines, health monitoring of bridge structures, and early warning of geological disasters. In such systems, the phase change of the interference signal is used to reflect the external disturbance. Therefore, phase unwrapping is an important step in restoring the true phase change from the wrapped phase data, and its processing accuracy is directly related to the system's spatial positioning capability and monitoring sensitivity.

[0003] Existing DAS systems mostly use digital signal processors or general-purpose central processing units for phase demodulation and unwrapping operations. While this offers some flexibility, it suffers from significant computational latency and insufficient response speed under conditions of high sampling rates and multi-channel real-time monitoring. To improve processing efficiency, some systems have attempted to implement phase unwrapping functionality using field-programmable gate arrays (FPGAs). They output phase data through the CORDIC algorithm and unwrap the data on the time axis based on the phase difference between adjacent sampling periods, thereby achieving high-speed parallel computation at the hardware level.

[0004] However, in practical applications under complex environments, the above-mentioned technologies still have certain limitations. The method of using a fixed threshold to determine phase transitions is difficult to adapt to different noise levels and signal strength changes, and noise fluctuations are easily misjudged as real transitions, leading to an increase in unwrapping errors. In phase data processing, the reliability of different sampling periods is not identified, and local anomalies are difficult to correct in a timely manner, which can easily cause errors to spread along the time axis. At the same time, there is a lack of an effective synchronous feedback mechanism between data storage and computation paths. The high utilization of FPGA on-chip resources makes the processing timing easily restricted, affecting the continuity and stability of the unwrapping process. Summary of the Invention

[0005] The purpose of this invention is to provide a time-axis phase unwrapping method and system based on FPGA to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a time-axis phase unwrapping method based on FPGA, which completes initial phase acquisition, stable reference selection, progressive development, pipeline processing, and quality closed-loop correction within the same clock domain, specifically including the following steps:

[0007] First, phase data acquisition: The interference signal collected by the distributed fiber optic sensing system is orthogonally demodulated, and the initial phase data of the time axis is obtained by using the CORDIC algorithm. The data is then written into the FPGA input buffer at a fixed sampling rate, which is synchronized with the system clock to ensure the timing consistency and data continuity of subsequent processing.

[0008] Secondly, stable group formation: The phase stability index and amplitude stability index of continuous periods are jointly determined within the FPGA; when the phase stability index is lower than the first threshold and the amplitude stability index is not lower than the second threshold, the period is marked as a reliable period point; when the number of consecutive reliable period points is not less than the preset group length, a stable group is formed as the reference interval for subsequent expansion, thereby selecting a relatively stable and reliable phase reference on the time axis.

[0009] Secondly, phase progressive expansion: Starting from the last period of the stable group, the process proceeds periodically along the time axis. When the phase difference between adjacent periods is lower than the third threshold, cumulative expansion is performed. When the phase difference is not lower than the third threshold, the phase change trend index and amplitude change rate index of several adjacent periods are combined for joint judgment. If the preset anomaly judgment condition is met, the phase of that period is corrected by ±2π. Otherwise, the current phase value is kept unchanged to reduce the interference of isolated anomalies on the entire phase sequence.

[0010] Then, the pipeline and buffer work together: three pipeline comparators, namely the input stage, the comparison stage and the decision stage, are set up in the FPGA. The phase data and the decision result are read and written in parallel and stored in a circular buffer composed of dual-port BRAM. The read and write pointers are managed in a circular manner by the control logic according to a preset update strategy, so that the data input, calculation and output flow continuously in the same clock domain and meet the real-time processing requirements.

[0011] Finally, the quality metric closed-loop correction is performed: the quality metric (including the mean square error) is calculated for the unfolded phase sequence. When the metric exceeds the fourth threshold, the control logic issues a recalculation trigger signal, clears the buffered intermediate result partitions and retains the input partition data, and returns to the stable group formation and phase progression opening link for re-screening and unfolding, forming an error feedback closed loop for phase unwrapping oriented towards the time axis. This improves the reliability and continuity of phase unwrapping for long time sequences while ensuring real-time performance.

[0012] Furthermore, the specific steps for acquiring the phase data are as follows:

[0013] The FPGA demodulation unit receives the in-phase and orthogonal channel voltage values ​​of the interference signal output by the distributed optical fiber sensing system, generates orthogonal and in-phase components respectively through on-chip multiply-add logic, and then uses the CORDIC algorithm to perform polar coordinate transformation on the components to obtain the instantaneous phase of each sampling point.

[0014] The instantaneous phase is temporarily stored in the first-level cache register and then written into the FPGA's internal input buffer. The input buffer is composed of dual-port storage units. The writing end is driven by the sampling clock, and the reading end works synchronously with the subsequent phase filtering unit under the same system clock domain. The sampling clock and the system clock are phase-locked through the clock distribution network to ensure that the sampling interval is constant and that data writing and reading are performed under the same timing reference.

[0015] Furthermore, the specific steps for forming the stable group are as follows:

[0016] The decision logic circuit set up inside the FPGA receives phase data and obtains the phase data and amplitude data from the input buffer of the output;

[0017] The phase change and corresponding amplitude change of several adjacent cycles are extracted sequentially according to the preset sampling window. The phase stability index and amplitude stability index of each cycle are obtained by the statistical calculation unit, and the values ​​of the two indices are compared in parallel with the first threshold and the second threshold stored in the threshold register.

[0018] When the phase stability index of a certain period is less than the first threshold and the amplitude stability index is not lower than the second threshold, the control logic writes a reliable flag bit at the address position of that period; when the number of consecutive reliable flag bits reaches the preset group length, the control logic identifies the data of the consecutive address segment as a stable group and records its start address and end address in the group index register. The stable group index information serves as the input reference for subsequent phase expansion units.

[0019] Furthermore, the specific steps for the phase progression are as follows:

[0020] Using the last period of the stable group as the starting period of the expansion, the phase data of adjacent periods are read sequentially along the time axis, the phase difference between adjacent periods is calculated and compared with the third threshold stored in the threshold register.

[0021] When the phase difference is less than the third threshold, the phase value is accumulated in chronological order; when the phase difference is not less than the third threshold, the phase change trend data and amplitude change rate data of several previous and subsequent cycles are read, and a joint judgment is made according to the preset trend judgment condition and amplitude change condition: if the judgment result meets the correction condition, the phase value of the current cycle is corrected by a cycle jump; if the judgment result does not meet the correction condition, the phase value of the current cycle remains unchanged.

[0022] The expanded phase data is output to the buffer in chronological order for subsequent quality measurement and closed-loop correction.

[0023] Furthermore, the specific steps of the pipeline and cache co-processing are as follows:

[0024] A three-stage pipeline structure is formed within the FPGA, consisting of an input stage, a comparator stage, and a decision stage connected sequentially.

[0025] Phase data is sequentially processed in the input stage, then the comparison stage, and finally the decision stage. Data is passed sequentially between stages via registers to maintain timing consistency.

[0026] The phase data and judgment result output by the judgment stage are written into a ring buffer composed of dual-port BRAM. The buffer is equipped with a read pointer and a write pointer. The read and write pointers move cyclically according to the clock cycle according to the preset update rules. When the interval between the write pointer and the read pointer reaches the preset buffer depth, it automatically enters the cyclic overwrite mode, thereby realizing the parallel reading and writing and continuous storage of phase data and judgment result.

[0027] The output of the buffer synchronously transmits the expanded phase data of the current cycle to subsequent quality metrics and closed-loop corrections to ensure sequential transmission and continuous processing of data under a unified clock domain.

[0028] Furthermore, the specific steps of the closed-loop correction of the quality metric are as follows:

[0029] The unfolded phase sequence output from the buffer is read sequentially according to a preset sampling window. The phase difference data within the window is obtained by the statistical calculation unit, and the corresponding quality metric parameters are calculated. The quality metric parameters include an error assessment quantity that reflects the phase unwrapping accuracy.

[0030] When the calculated quality metric parameter exceeds the fourth threshold stored in the threshold register, the control logic generates a recalculation trigger signal and sends the signal to the cache management unit. After receiving the recalculation trigger signal, the cache management unit clears the intermediate results in the temporary storage partition, retains the original phase data of the input partition and the threshold setting in the parameter register, so that the system re-executes the process of stable group formation and phase progression within the same clock domain.

[0031] After the recalculation is completed, the new phase expansion result replaces the original temporary data and is output to the buffer, thus forming a continuous feedback loop between data acquisition, unwrapping calculation and error assessment.

[0032] This invention also proposes a time-axis phase unwrapping system based on FPGA, which is based on the above method and includes:

[0033] Phase demodulation module: used to perform orthogonal demodulation on interference signals and output initial phase data of the time axis;

[0034] FPGA unwrapping module: includes a reliable periodic screening unit, a phase progressive development unit, an anomaly detection unit, a quality measurement and recalculation control unit, and a three-stage pipeline comparator coupled thereto;

[0035] Ring buffer module: Composed of on-chip dual-port BRAM of FPGA, including input partition, temporary storage partition and output partition, used to perform parallel reading and writing and cyclic storage of phase data and judgment results during unwrapping process;

[0036] Control and Clock Module: Used to provide system clock, threshold and window parameters, recalculation trigger signals, and to perform timing synchronization control on read / write pointers and pipeline stage registers;

[0037] Among them, the FPGA unwrapping module and the ring buffer module are bidirectionally coupled through correction signals and holding signals: the anomaly judgment result is used to guide the phase correction of the unfolding unit, and at the same time, it is output to the quality measurement and recalculation control unit to participate in the online adjustment of threshold and window parameters, forming an algorithm-hardware collaborative closed loop.

[0038] Furthermore, the phase demodulation module performs orthogonal demodulation on the interference signal to obtain the initial phase data of the time axis, the FPGA unwrapping module receives the initial phase data and performs phase filtering, unwinding and correction processing, the ring buffer module stores and retrieves the phase data and judgment results during the unwrapping process, and the control and clock module provides a unified clock signal and threshold parameters for each module and realizes overall timing synchronization.

[0039] Furthermore, the FPGA unwrapping module includes a reliable periodic screening unit, a phase progressive development unit, an anomaly detection unit, a quality measurement and recalculation control unit, and a three-stage pipeline comparator connected in sequence with the units;

[0040] The reliable periodic screening unit is used to continuously screen the input phase data. The phase progressive expansion unit performs phase expansion calculations based on the screening results. The anomaly judgment unit judges the phase change trend and amplitude change rate. The quality measurement and recalculation control unit calculates quality parameters and generates recalculation trigger signals based on the judgment results. The three-stage pipeline comparator sequentially transmits comparison results between the units to ensure consistent data processing timing.

[0041] Furthermore, the FPGA unwrapping module and the ring buffer module are bidirectionally connected through correction signals and hold signals. The correction signal output by the anomaly determination unit is used to guide the phase adjustment of the phase progressive unfolding unit. At the same time, the hold signal and correction signal are synchronously input to the quality measurement and recalculation control unit to update the real-time parameters in the threshold register and window parameter register, so as to form a collaborative feedback loop between the algorithm and the hardware in the phase screening, unfolding and quality measurement process.

[0042] The beneficial effects of this invention are as follows:

[0043] 1. This invention constructs a dynamic threshold and window adaptive control mechanism within the FPGA, enabling the phase unwrapping process to automatically adjust the judgment parameters according to the real-time signal quality. When electromagnetic interference or noise fluctuations caused by structural vibration occur in the monitoring environment, the system can quickly adjust the judgment threshold and window length in the on-chip logic, thereby distinguishing between real phase changes and random noise disturbances, and realizing phase unwrapping with adaptive noise response. Compared with the fixed threshold method, this mechanism significantly improves the stability and accuracy of the unwrapping algorithm under complex noise conditions.

[0044] 2. This invention sets up a reliable period selection unit and a phase progressive unfolding unit in the FPGA unwrapping module to perform stability assessment and hierarchical processing on phase data with different sampling periods. The system uses window statistics and parallel comparison methods to identify reliable period points, and triggers phase correction operations on abnormal points through anomaly detection logic to prevent local errors from spreading along the time axis. Through this mechanism, the system can effectively suppress the accumulation of unwrapping errors, maintain the continuity and error convergence of the phase unfolding process, and improve the overall data reliability.

[0045] 3. This invention establishes a real-time feedback path between data acquisition, phase operation, and quality assessment by utilizing a ring buffer module and a three-stage pipeline structure. The unwrapping result and the judgment signal are read and written in parallel through a dual-port buffer. The correction signal and the hold signal are transmitted synchronously between modules, enabling data processing to be performed continuously in the same clock domain. This design effectively reduces on-chip data latency and logic occupancy, enabling the system to achieve low-latency, high-precision real-time phase unwrapping under high-speed sampling conditions. Attached Figure Description

[0046] Figure 1 This is a flowchart illustrating the stable group formation process of the present invention;

[0047] Figure 2 This is a flowchart of the quality measurement and recalculation process of the present invention. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] like Figures 1 to 2 As shown, this embodiment of the invention provides a time-axis phase unwrapping method based on FPGA to complete phase data access, stable reference selection, phase progressive development, pipeline processing, and quality measurement and recalculation control within the same FPGA chip. The processing flow can be executed sequentially according to the following steps.

[0050] First, in the phase data acquisition stage, the interference signal collected by the distributed fiber optic sensing system is orthogonally demodulated, and the initial phase data arranged along the time axis is obtained by using the CORDIC algorithm. The initial phase data is written into the input buffer of the FPGA at a fixed sampling rate. The sampling rate is set synchronously with the system clock so that the input data and subsequent processing logic work in the same clock domain, avoiding timing inconsistencies between sampling and operation.

[0051] Secondly, in the stable group formation stage, the phase stability index and amplitude stability index of continuous periods are jointly determined within the FPGA. The phase stability index and amplitude stability index are calculated based on the phase change and amplitude change within each period. When the phase stability index of a certain period is lower than the first threshold and the amplitude stability index is not lower than the second threshold, the period is marked as a reliable period point. When the number of consecutive reliable period points on the time axis is not less than the preset group length, the continuous interval is defined as a stable group, and the stable group is used as the reference for subsequent phase expansion.

[0052] Then, in the phase progression unfolding stage, starting from the last period of the stable group, subsequent periods are processed one by one along the time axis. When the phase difference between two adjacent periods is lower than the third threshold, the phase difference is unfolded in an accumulative manner. When the phase difference is not lower than the third threshold, the phase change trend index and amplitude change rate index of several adjacent periods are called in the FPGA to jointly determine whether the current period belongs to an abnormal change: if the preset abnormal judgment condition is met, the phase of the current period is corrected by ±2π; if the abnormal condition is not met, the phase value of the current period is kept unchanged, thereby reducing the impact of a single abnormal period on the entire phase sequence.

[0053] In the pipeline and cache co-processing stage, a three-stage pipeline comparator consisting of an input stage, a comparison stage, and a decision stage is set up in the FPGA. The phase data and the decision result are read, written, and stored in a circular cache composed of a dual-port BRAM in parallel. The read and write pointers are managed cyclically by the control logic according to a preset update strategy, so that the input of phase data, comparison calculation, and decision output can flow continuously in the same clock domain. At the same time, the read and write order of data in the cache of the previous and next cycles is guaranteed, providing data support for phase progression and anomaly detection.

[0054] Finally, in the quality metric closed-loop correction stage, a quality metric is calculated for the unfolded time-axis phase sequence. This quality metric includes an error assessment quantity, such as the mean square error. When the quality metric exceeds a fourth threshold, the control logic within the FPGA generates a recalculation trigger signal to clear the partition in the circular buffer used to store intermediate calculation results, while retaining the input data partition unchanged. This causes the system to return to the stable group formation stage and the phase progression unfolding stage to re-perform reliable periodic screening and phase unfolding processing. Through the aforementioned quality metric-driven recalculation control, the phase unwrapping process is recalculated as needed without changing the original input phase data, forming an error feedback closed loop oriented towards time-axis phase unwrapping.

[0055] The specific steps for acquiring phase data are as follows:

[0056] The so-called FPGA demodulation unit refers to the circuit unit deployed in the logic area on the FPGA chip for orthogonal demodulation of interference signals. It includes multiply-accumulate operation logic, CORDIC algorithm core and register array, and can output continuous instantaneous phase data of the time axis at a fixed sampling frequency.

[0057] The interference signal acquired by the distributed fiber optic sensing system is converted into two voltage signals after photoelectric conversion: the in-phase channel voltage. With positive traffic channel voltage All units are volts (V);

[0058] To achieve high-speed real-time demodulation, two signals are directly input to the on-chip demodulation unit of the FPGA. The demodulation unit consists of multiply-accumulate operation logic, CORDIC algorithm core and register array, and is deployed in the logic area on the FPGA.

[0059] Generation of in-phase and quadrature components

[0060] The FPGA demodulation unit performs on-chip multiply-add logic on the input voltage signal to generate normalized in-phase and quadrature components.

[0061] The normalization coefficients are taken as the maximum amplitude of the input signal. This ensures that the numerical range is between [-1, 1].

[0062] The multiply-accumulate logic employs a two-stage pipelined architecture, processing one sampling point per system clock cycle, with a sampling frequency of... Not higher than the system clock Half of it, to ensure timing stability;

[0063] CORDIC polar coordinate transformation

[0064] The in-phase and quadrature components of the output from the multiply-accumulate logic are fed into CORDIC (Coordinate Rotation).

[0065] DiqitalComputer) algorithm kernel;

[0066] The CORDIC module iteratively calculates the phase angle through shift and table lookup operations, with the following relationship:

[0067] In the formula, This represents the instantaneous phase value at the corresponding sampling time, in radians (rad).

[0068] The CORDIC algorithm core within the FPGA employs 16 iterations to achieve phase accuracy. The output results are obtained on-chip, without the need for CPU or DSP, thus avoiding external bus latency;

[0069] Cache structure and timing synchronization

[0070] To ensure the temporal continuity of the phase data, the instantaneous phase data is first temporarily stored in a primary register, and then written to the FPGA's internal input buffer.

[0071] The input buffer consists of a dual-port RAM (BlockRAM), with one port for writing and one port for reading. The storage depth is N = 2^10 sampling points, and the bit width is W = 16 bits.

[0072] The write port is controlled by the sampling clock. The driver reads the port via the system clock. control;

[0073] The sampling clock and the system clock are synchronized in phase through the FPGA's built-in phase-locked loop (PLL), and the phase-locking deviation is controlled. Keep it within 10^-6 radians.

[0074] The clock frequency difference satisfies: This design ensures that write and read operations are completed under a unified timing reference, eliminating the risk of phase drift caused by cross-clock domains;

[0075] Data transfer and collaboration logic

[0076] The output of the input buffer is connected to the phase filtering unit (subsequent stable group formation module); when the amount of data in the buffer reaches the preset sampling window length... Nw=1024 When a sampling point is reached, the read pointer is activated, and data is sequentially fed into the subsequent logic.

[0077] This architecture allows phase demodulation, buffer writing, and phase filtering to flow continuously within the same clock domain.

[0078] A data stream-level collaborative processing mechanism is established to ensure that the overall system data latency does not exceed two sampling cycles;

[0079] The core hardware implementation of the CORDIC algorithm is carried out on an FPGA chip, and combined with on-chip multiply-accumulate logic and dual-port BRAM cache, it realizes a fully hardware pipelined processing from input signal to instantaneous phase output.

[0080] Furthermore, by using PLL phase-locked loop and unified clock domain design, data sampling and processing are ensured to be performed under the same phase reference, avoiding the phase jitter and data delay problems that occur in traditional systems with multiple clock domains.

[0081] The specific steps for the formation of a stable group are as follows:

[0082] The decision logic circuit inside the FPGA performs statistical calculations and parallel comparisons on phase and amplitude data to identify continuous and stable segments of the signal on the time axis, forming a reference group for subsequent phase expansion.

[0083] Input data and unit composition

[0084] The input buffer sequential output sampling window length is Phase data sequence With amplitude data sequence ,

[0085] in Here is the sampling point index, and the sampling interval is... The unit is seconds. The decision logic circuit inside the FPGA consists of the following units:

[0086] Statistical calculation unit: calculates the phase change and amplitude change between adjacent sampling points;

[0087] Threshold comparison unit: compares the calculated result with the first threshold in the register. With the second threshold Perform parallel comparisons;

[0088] Control logic unit: Generates a reliable flag bit based on the comparison result and monitors continuity;

[0089] Group Index Register: Records the starting address of each stable group. and end address ;

[0090] All of the above units are fixed-point logic structures and operate in the same clock domain as the demodulation module;

[0091] Calculation of phase and amplitude stability indices

[0092] The statistical calculation unit performs the following calculations within each sampling window:

[0093] , ,

[0094] And calculate the phase and amplitude stability indices:

[0095] , ,

[0096] In the formula, the summation symbol is... This indicates that the data is accumulated point by point within the sampling window, using 16-bit fixed-point precision. : No. The instantaneous phase of each sampling point, in rad; : No. Amplitude at each sampling point, in V; Phase change, in rad; : Amplitude change, unit V; Phase stability index, unit: rad²; Amplitude stability index, unit V²; Threshold parameter, same unit as above; ; Sampling window length, unit, number of sampling points; Stable group length threshold, in units of sampling points;

[0097] The smaller the value, the more stable the phase. A smaller value indicates smaller amplitude fluctuations and higher signal quality; threshold determination and reliability flag generation are calculated as follows. and The data are respectively sent to the threshold comparison unit and compared with the data in the threshold register. , Compare;

[0098] when and At that time, the control logic identifies the current sampling point as a reliable point. ;

[0099] Otherwise, it is marked as an unreliable point. ;

[0100] all The data are sequentially written into the reliability register array to form a reliability flag sequence;

[0101] Stable group detection and indexing records

[0102] When the number of consecutive "1"s detected reaches the preset group length threshold (Typical values ​​range from 16 to 64 sampling points);

[0103] The control logic triggers the group index register to record the starting address of the segment. and end address ;

[0104] The address is in units of sampling point number, with a counting step of 1;

[0105] The group index table also includes a validity flag, which indicates the validity of the current group data;

[0106] Timing coordination and output interface

[0107] The statistical calculation, threshold comparison, and group detection units operate in a pipelined manner under a unified system clock.

[0108] Each time a new set of stable group index information is generated, the control logic synchronously sends the index information to the input register of the phase progressive expansion unit through the bus, forming a continuous data flow path from input buffer → decision logic → group index → ​​expansion unit;

[0109] By employing a joint determination of phase stability and amplitude stability indices and implementing parallel comparison logic within the FPGA, stable group indices can be generated in real time at the hardware level, eliminating software processing latency. Furthermore, by setting a group index register in the FPGA, stable groups can be directly addressed, thereby forming an automatic data transfer mechanism in the hardware pipeline and improving the determinism and real-time performance of the overall system.

[0110] The specific steps for phase progression are as follows:

[0111] The phase progression unfolding unit inside the FPGA takes the phase value at the end of the stable group as the unfolding starting point and continuously unfolds the phase data along the time axis cycle by cycle to restore the phase continuity across cycles.

[0112] Expand starting point and input data

[0113] The end address recorded in the stable group index register is loaded into the phase progressive expansion unit as the expansion starting point. The phase expansion unit sequentially reads the phase data and amplitude data of the sampled sequence from the input buffer. Each period corresponds to a sample point index, and the time interval is the sampling period. (Unit: seconds) The phase expansion logic operates independently inside the FPGA, and its inputs and outputs are phase-locked synchronized with the previous module.

[0114] Phase difference calculation and determination

[0115] The phase expansion unit calculates the phase difference between two adjacent sampling periods and compares it with the third threshold stored in the threshold register. The third threshold is used to determine whether the phase difference spans one period (usually π radians).

[0116] When the phase difference is less than the third threshold, the system considers the phase change of the current cycle to be continuous with that of the previous cycle.

[0117] The phase difference is then added to the expanded phase sequence, so that the phase value continues to increase continuously along the time axis;

[0118] When the phase difference is not less than the third threshold, the system considers that the phase has changed and triggers the anomaly detection logic.

[0119] Anomaly detection and correction

[0120] When the anomaly detection logic is triggered, the phase progression development unit reads the phase data and amplitude data of the three cycles before and after the current cycle from the buffer, calculates the trend of change and the amplitude change rate. When the phase change direction is consistent and the amplitude change rate does not exceed the amplitude change threshold, it is considered that the jump belongs to the cycle reversal. The control logic corrects the phase value of the current cycle, that is, adds or subtracts a full cycle angle (2π radians) on the basis of the original phase value, so as to ensure the continuity of the phase curve on the time axis. If the trend does not meet the correction condition, the current phase value remains unchanged.

[0121] Expanded result output and cache connection

[0122] The phase data, after being expanded and corrected, is output to the output partition of the buffer according to the sampling order.

[0123] The output partition adopts a dual-port RAM structure and is written by the expansion unit. The subsequent quality measurement and closed-loop correction modules read the expansion results from this buffer for quality calculation. To ensure timing consistency, buffer read and write operations are run under a unified system clock.

[0124] Module timing coordination

[0125] The phase difference calculation, transition determination and correction logic are formed into a three-stage pipeline in the FPGA in sequence. Each stage is delayed by one clock cycle to realize continuous data flow expansion. All operation logic is in the same clock domain to avoid phase drift caused by cross-domain delay. Each threshold parameter and trend determination condition can be configured through registers, so that the system can dynamically adjust the expansion sensitivity and accuracy according to the signal-to-noise ratio of the interference signal.

[0126] A dual-dimensional joint judgment mechanism and hardware-level correction logic are implemented within the FPGA. The nature of the jump is judged by the trend and amplitude changes of the previous and next cycles, reducing false corrections. The correction operation is completed at the hardware logic layer without the need for software intervention, and the response speed reaches the nanosecond level. The parameter threshold can be configured in real time, enabling the system to adapt to different signal conditions.

[0127] To achieve high-speed streaming unwrapping and real-time synchronization of phase data within the FPGA, this invention constructs a three-stage pipeline structure in the FPGA logic and combines it with a dual-port ring buffer to achieve parallel reading, writing and cyclic storage of phase data and judgment results, ensuring that all processing steps run continuously within a unified clock domain.

[0128] Three-stage assembly line structure

[0129] The pipeline structure includes an input stage, a comparator stage, and a decision stage sequentially along the data path. Each stage is connected by a register, which is used to latch data at each clock edge to maintain timing continuity.

[0130] Input stage: Responsible for receiving the phase data stream from the phase progression module, latching the data, and passing it to the next stage;

[0131] Comparative stage: Performs phase difference calculation and critical determination between adjacent cycles, providing input for subsequent determination logic;

[0132] Decision level: Generates a decision signal (including two flags: "stable" and "needs correction") based on the comparison results, and outputs it synchronously with the phase data;

[0133] All three stages of the pipeline operate under a unified system clock, with each stage delayed by one clock cycle, enabling continuous data stream processing.

[0134] Structure and operation logic of the circular buffer

[0135] The phase data output by the decision stage and the corresponding decision result are simultaneously written into a ring buffer composed of on-chip dual-port BRAM of the FPGA.

[0136] The cache is divided into an input partition, a temporary storage partition, and an output partition, and each partition can be accessed through an independent address pointer.

[0137] The buffer has a read pointer (ReadPtr) and a write pointer (WritePtr), which increment independently under a unified clock control;

[0138] At each rising edge of the system clock, the write pointer moves to the next memory address to receive new phase data;

[0139] The read pointer moves in sync with subsequent modules to output data. When the interval between the write pointer and the read pointer reaches the cache depth minus one, the write pointer returns to the starting address to overwrite the old data, thus achieving cyclic writing.

[0140] The cache management logic monitors the pointer spacing in real time. When it detects that a data range that has not yet been read is approached by the write pointer, it automatically pauses the write operation to prevent data overwriting.

[0141] Through this mechanism, phase data and determination results can be read and written in parallel in the same storage, forming a continuously flowing data path.

[0142] Data synchronization and module integration

[0143] The output of the buffer is connected to the quality measurement and closed-loop correction module;

[0144] Under a unified clock domain, the phase data and decision flags output from the buffer are synchronously read by subsequent modules and used for error measurement calculations.

[0145] Ensure that phase unwrapping, data caching, and error correction operate continuously in the time dimension, forming a real-time feedback closed loop;

[0146] All signal transmission is completed inside the FPGA, avoiding external bus transmission delays, which enables the system to maintain the stability and lossless phase unwrapped data stream even under high sampling rate conditions;

[0147] Parallel pipeline cascaded design: The input, comparison and decision logic levels are triggered continuously in the same clock domain, eliminating the synchronization delay problem of traditional software or multiple modules and ensuring the integrity of the timing chain;

[0148] Dual-port ring buffer structure: Supports simultaneous read and write operations through dual-port BRAM, binds phase data with decision flags for output, and ensures uninterrupted data flow, realizing true real-time streaming buffer;

[0149] Pointer distance self-monitoring mechanism: Add read / write distance detection and write protection logic to the hardware logic.

[0150] To prevent buffered data from being overwritten prematurely, thus ensuring the reliability of the untangling results;

[0151] Unified clock domain coordination mechanism: All pipelines and buffer modules operate under a single clock signal.

[0152] Eliminate phase drift and synchronization distortion caused by cross-clock domain transmission;

[0153] In summary, the pipeline and cache collaborative structure of the present invention not only ensures the timing continuity and storage stability of the untangling process, but also realizes high-bandwidth, low-latency phase data stream transmission through hardware-level design, which has significant speed advantages and robustness improvements compared with traditional architectures.

[0154] In this embodiment, in order to achieve real-time accuracy detection and error self-correction of the phase expansion results, the present invention introduces a quality measurement and closed-loop correction mechanism inside the FPGA.

[0155] This mechanism evaluates the quality of the untangling result in real time through hardware logic without relying on an external CPU or software control. When the detected error exceeds the threshold, it automatically triggers recalculation, thus achieving fully hardware-level adaptive closed-loop control.

[0156] Collection and calculation of quality measurement parameters

[0157] The phase expansion sequence output from the ring buffer is read sequentially according to the sampling window, and each window contains a fixed number of sampling period points;

[0158] The window length is set by the parameter register and can be dynamically adjusted according to the system sampling rate;

[0159] The statistical calculation unit performs a difference operation on the phase sequence within each window to calculate the phase change between adjacent sampling points;

[0160] These changes are used to evaluate the smoothness of phase changes within the current window. Subsequently, the computing unit generates a quality metric parameter to reflect the overall stability and continuity of phase unwrapping.

[0161] In this embodiment, the main quality metric is mean square error (MSE), which measures the average deviation of phase change within the window.

[0162] Optionally, the system can also simultaneously calculate auxiliary indicators such as phase mutation rate and amplitude consistency ratio to achieve multi-dimensional evaluation of the unwrapping results. These parameters are weighted by registers to generate a comprehensive quality index for subsequent recalculation and judgment.

[0163] Recalculation trigger logic and signal generation

[0164] The quality measurement module compares the comprehensive index of each window with the fourth threshold stored in the threshold register; when the quality index of two consecutive sampling windows is higher than the threshold, the control logic generates a single-cycle high-level pulse signal as a recalculation trigger signal.

[0165] To avoid false triggering caused by transient noise, the system will also check whether the amplitude change rate is lower than the amplitude threshold before generating the recalculation signal. Only when the amplitude changes continuously and the limit is exceeded and the amplitude changes smoothly will the recalculation signal be confirmed and sent to the buffer management unit.

[0166] Cache recalculation and data reflow control

[0167] Upon receiving the recalculation trigger signal, the cache management unit executes the recalculation control in the following order;

[0168] Clear the temporary storage partition: Clear the temporary storage partition in the cache used to store intermediate expanded results;

[0169] Preserve input data: The original phase sequence and amplitude data in the input partition are not affected, ensuring that the recalculation process is re-executed based on the original signal;

[0170] Maintain parameter register settings: keep all threshold, weight, and timing parameters unchanged to avoid reconfiguration delays;

[0171] Triggering backflow execution: The control logic sends a recalculation instruction signal through the internal bus, and at the same time activates the "stable group formation module" and the "phase progression unfolding module" to re-unfold the phase sequence under a unified clock domain;

[0172] After the new phase unrolling results are generated, they will overwrite the original temporary storage data and be rewritten to the cache output port for the quality measurement module to detect again.

[0173] Closed-loop feedback mechanism

[0174] The above process forms a complete hardware-level closed-loop path:

[0175] Forward path: Phase sequence output from phase unrolling module → buffer → quality measurement module;

[0176] Feedback path: Quality measurement module calculation result → Recalculation trigger signal → Buffer management unit → Phase expansion module;

[0177] Through this closed-loop feedback, the system can achieve adaptive correction between data acquisition, unfolding and quality assessment, so that the phase data remains continuous and stable over a long period of time.

[0178] The entire process is completed within the FPGA's internal logic units, without the need for CPU intervention or external clock coordination, which greatly improves the real-time performance and stability of the unwinding process.

[0179] The closed-loop correction mechanism of this invention has the following unique technical features:

[0180] Hardware-level real-time quality assessment: Quality parameters are calculated on the FPGA chip in a streaming manner with a response time of milliseconds;

[0181] Dual-condition triggering mechanism: Simultaneously judges continuous over-limit and amplitude change stability to ensure reliable recalculation triggering;

[0182] Partition cache reflow control: Enables partial clearing of intermediate data while preserving original data, reducing computational latency;

[0183] Unified clock domain design: All logic runs under a unified system clock, avoiding cross-clock drift and data asynchrony issues;

[0184] This design effectively avoids problems such as incorrect correction, excessive delay, or computational blockage in traditional solutions, and achieves high-precision, sustainable phase expansion closed-loop control, demonstrating outstanding technical effectiveness and innovation.

[0185] This invention also proposes a time-axis phase unwrapping system based on FPGA, which is based on the above method and includes:

[0186] Phase demodulation module: used to perform orthogonal demodulation on interference signals and output initial phase data of the time axis;

[0187] FPGA unwrapping module: includes a reliable periodic screening unit, a phase progressive development unit, an anomaly detection unit, a quality measurement and recalculation control unit, and a three-stage pipeline comparator coupled thereto;

[0188] Ring buffer module: Composed of on-chip dual-port BRAM of FPGA, including input partition, temporary storage partition and output partition, used to perform parallel reading and writing and cyclic storage of phase data and judgment results during unwrapping process;

[0189] Control and Clock Module: Used to provide system clock, threshold and window parameters, recalculation trigger signals, and to perform timing synchronization control on read / write pointers and pipeline stage registers;

[0190] Among them, the FPGA unwrapping module and the ring buffer module are bidirectionally coupled through correction signals and holding signals: the anomaly judgment result is used to guide the phase correction of the unfolding unit, and at the same time, it is output to the quality measurement and recalculation control unit to participate in the online adjustment of threshold and window parameters, forming an algorithm-hardware collaborative closed loop.

[0191] The FPGA-based time-axis phase unwrapping system consists of four main modules: a phase demodulation module, an FPGA unwrapping module, a ring buffer module, and a control and clock module. Each module is deployed within the same logical area of ​​the FPGA chip and achieves signal transmission, data interaction, and unified timing synchronization through the on-chip AXI bus and control registers. The entire system forms a continuous streaming data processing path from interference signal acquisition to phase unwrapping output.

[0192] Phase demodulation module

[0193] The phase demodulation module is used to receive the in-phase channel signal and the orthogonal channel signal output by the distributed optical fiber sensing system. The module includes a multiply-accumulate logic unit and a CORDIC algorithm core. The multiply-accumulate unit performs orthogonal demodulation operation on the two signals, and the CORDIC algorithm core is responsible for converting the signals in rectangular coordinate form into polar coordinate form and outputting the corresponding instantaneous phase value.

[0194] This module adopts a pipelined design, calculating the phase value of one sampling point in each system clock cycle. The calculation result is temporarily stored in a first-level register and then written to the input buffer to form the initial phase data sequence of the time axis, which provides input for the subsequent unwrapping module.

[0195] FPGA unwrapping module

[0196] The FPGA unwrapping module is the core computing unit of the system, responsible for performing phase filtering, progressive unfolding, and error correction on the initial phase data;

[0197] This module consists of the following sub-units:

[0198] Reliable period screening unit: Determines the stability of the initial phase sequence, removes noisy periods, and forms a reliable data set;

[0199] Phase progressive expansion unit: The phase value is continuously expanded in the time axis direction to achieve periodic phase compensation;

[0200] Anomaly detection unit: detects abrupt changes and makes corrections based on trend and amplitude change characteristics;

[0201] Quality Measurement and Recalculation Control Unit: Determines whether to trigger a recalculation instruction based on the error index calculation results returned by the buffer.

[0202] The entire unwrapping module operates in a parallel pipeline manner within the FPGA. Data is synchronously transferred between each sub-unit through registers. The phase filtering, unwrapping, and correction processes are completed continuously within the same system clock domain.

[0203] Ring cache module

[0204] The ring buffer module consists of a dual-port BRAM, internally divided into an input partition, a temporary storage partition, and an output partition. The input partition stores the initial phase data of the phase demodulation module; the temporary storage partition stores the intermediate unwrapping results; and the output partition outputs the final unwrapped phase value to the quality measurement module and external interfaces.

[0205] The buffer controls data flow through read and write pointers, which increment synchronously on the rising edge of the clock.

[0206] When the interval between the write pointer and the read pointer reaches the preset cache depth limit, the write pointer returns to the starting address, realizing cyclic writing;

[0207] When the quality metric module triggers the recalculation signal, the cache management logic only clears the temporary storage partition and retains the input partition data so that the system can quickly re-expand and ensure real-time performance.

[0208] Control and Clock Module

[0209] The control and clock module provides the system with unified clock signal and parameter management functions. This module includes a phase-locked loop (PLL), a clock distribution network, and a parameter register group.

[0210] Phase-locked loops are used to stabilize the system master clock and distribute the clock signal to each module;

[0211] The parameter register group is used to store the threshold, sampling window length, and weighting coefficients required for the unwrapping process;

[0212] The control logic writes parameter values ​​via the FPGA on-chip bus on the rising edge of the clock and dynamically adjusts the contents of the threshold register based on the feedback signal from the quality measurement module to ensure that all modules operate collaboratively under the same timing reference.

[0213] Through the above control mechanism, the system can automatically optimize the unwrapping parameters when it detects noise or signal changes, thereby achieving adaptive operation;

[0214] Module collaboration relationships and data paths

[0215] The four modules collaborate bidirectionally via data lines and a control bus, forming the following two logical paths:

[0216] Master data path:

[0217] Interference signal input → Phase demodulation module → FPGA unwrapping module → Ring buffer module → Quality measurement and closed-loop correction module;

[0218] Feedback control path:

[0219] Quality Measurement Module → Control and Clock Module → FPGA Unwrapping Module and Buffer Module;

[0220] This dual-path design enables the system to provide real-time feedback, automatically adjusting parameters and re-unfolding when the error exceeds the threshold, achieving continuous self-correction and high-precision phase recovery.

[0221] Unlike existing distributed fiber unwrapping systems that rely solely on external CPUs or independent DSPs, this invention achieves the following innovations through an integrated multi-module design within an FPGA:

[0222] The entire signal chain is hardware-based: demodulation, unwinding, buffering, and control are all performed on the same chip, avoiding external bus delays;

[0223] Closed-loop control architecture: The phase expansion results are fed back to the control module in real time to achieve dynamic error correction;

[0224] Unified clock domain architecture: All logic runs under a single PLL output clock, eliminating cross-domain phase drift;

[0225] Adaptive parameter update mechanism: The parameter register is automatically adjusted based on real-time feedback to enhance system robustness;

[0226] These features together ensure the system's high real-time performance, scalability, and long-term stability, effectively solving problems such as large latency, synchronization errors, and fixed parameters in traditional systems.

[0227] The FPGA unwrapping module is the core computing and control unit of the system. This module consists of five functional units connected in sequence: a reliable cycle screening unit, a phase progressive development unit, an anomaly detection unit, a quality measurement and recalculation control unit, and a three-stage pipeline comparison unit.

[0228] All units exchange signals and parameters with the register group through the on-chip bus and operate synchronously under the same system clock to ensure the real-time performance and data consistency of the unwrapping process;

[0229] Reliable Periodic Screening Unit

[0230] This unit is used to filter out stable periods from the input raw phase and amplitude data. Its inputs are: the phase data sequence, amplitude data sequence, sliding window length and threshold parameters output by the demodulation module;

[0231] The processing flow is as follows:

[0232] Within a set window length, calculate the phase change and amplitude change between consecutive sampling points;

[0233] The fluctuation of phase change within the window is statistically analyzed (by calculating the average value and dispersion of the change), and the stability of amplitude change is also statistically analyzed.

[0234] If the phase fluctuation is less than the first threshold and the amplitude stability is not lower than the second threshold, it indicates that the data in this interval is stable, and the system writes the "reliable flag" at the corresponding address.

[0235] When the number of consecutive reliable flag bits reaches the preset group length, the system automatically defines the consecutive data segment as a "stable group" and records the start and end positions in the group index register. This information will be used as a reference interval in the subsequent phase unfolding process.

[0236] The output includes the address index of the stable group and the corresponding reliable flag sequence. This filtering process is implemented in hardware using registers and accumulators, without involving complex mathematical models, and is suitable for the parallel pipeline structure of FPGA.

[0237] Phase progression open unit

[0238] Based on the reliable period, this unit expands the phase on the time axis point by point;

[0239] The inputs include: stable group index, raw phase data, amplitude data, and third threshold and tolerance parameters;

[0240] The processing flow is as follows:

[0241] Starting from the end point of the stable group, the phase values ​​of adjacent samples are read sequentially;

[0242] Compare whether the phase change between adjacent samples is less than a set third threshold:

[0243] If the change is less than the threshold, the phase is considered continuous, and the change is directly accumulated and added to the expansion result.

[0244] If the change is greater than or equal to the threshold, several samples of data before and after that point are read to determine whether the phase change trend is continuous, and at the same time, the amplitude change is checked to see if it is within the tolerance range.

[0245] If the trend direction reverses but the amplitude change remains stable, the system considers a cycle jump to have occurred and automatically performs a cycle angle compensation in the hardware (equivalent to adding or subtracting the phase value of a complete cycle); otherwise, the current result remains unchanged.

[0246] The final expanded phase data is written to the output partition of the cache module in chronological order for use by the subsequent quality assessment unit.

[0247] This unit implements a phase continuity correction mechanism, avoiding the phase discontinuity problem caused by foldback or drift in traditional algorithms;

[0248] Anomaly Detection Unit

[0249] This unit is used to identify abnormal jump points that occur during the unfolding process. The input signals include phase change results, amplitude change results, third threshold and tolerance parameters.

[0250] The processing steps are as follows:

[0251] The first channel is used to detect whether the phase change exceeds the third threshold. If it does, a "phase jump signal" is output.

[0252] The second channel is used to detect whether the amplitude change exceeds the tolerance range. If it does, an "amplitude abnormality signal" is output.

[0253] The control logic makes a comprehensive judgment on the results from the two channels:

[0254] If only a phase jump occurs and the amplitude is normal, the output abnormality flag is valid.

[0255] If both are abnormal, the abnormality flag will not be triggered immediately. Instead, short-term delayed monitoring will be initiated to reconfirm the status over several consecutive sampling periods.

[0256] If only the amplitude is abnormal but the phase is continuous, it is considered to be a noise disturbance and no abnormal signal is triggered.

[0257] This determination mechanism can distinguish between true phase reversals and spurious transitions caused by noise, thus ensuring the reliability of unwrapped data.

[0258] Quality Measurement and Recalculation Control Unit

[0259] This unit continuously evaluates the overall quality of the unwrapping results during system operation and automatically triggers recalculation based on the evaluation results;

[0260] The inputs include: the expanded phase data, the preset sampling window length, and the fourth threshold.

[0261] The processing flow is as follows:

[0262] The system performs quality analysis on phase data within a sampling window of a set length, including but not limited to:

[0263] The average deviation of phase fluctuation;

[0264] The phase jump ratio exceeding the threshold;

[0265] Synchronous consistency between phase change and amplitude change;

[0266] The above results are weighted and combined into a single quality index value;

[0267] If the quality index in two consecutive assessments is higher than the fourth threshold, the system outputs a recalculation trigger signal.

[0268] Upon receiving the recalculation signal, the cache management logic will clear the data in the intermediate calculation area, but retain the original input data and parameter settings, and re-execute the stable group filtering and phase expansion process;

[0269] The new unwrapping results overwrite the old results, forming an automatic closed-loop correction process;

[0270] This mechanism ensures the long-term stability of the untangling process and enables the system to have self-correcting capabilities;

[0271] Three-stage assembly line comparison unit

[0272] To ensure that data comparison and judgment between units are performed under a fixed timing, the system constructs a three-stage pipelined comparator structure inside the FPGA;

[0273] The first level is the input comparison level, which is responsible for comparing the current phase and amplitude data with each threshold parameter in parallel;

[0274] The second level is the trend comparison level, which is responsible for analyzing the direction and magnitude of changes in continuous periodic data.

[0275] The third level is the comprehensive decision-making level, which combines the results of the first two levels with the abnormal indicator signals to generate the final judgment result;

[0276] Each stage is connected sequentially through registers and triggered by the rising edge of the system clock, ensuring that data transmission and judgment are synchronized and that there is no cross-clock delay or signal jitter.

[0277] Unlike existing CPU or DSP-based untangling algorithms, this invention implements all calculation processes in hardware logic.

[0278] Reliable periodic screening, progressive development, anomaly detection, quality measurement and recalculation are all completed in parallel pipeline within the FPGA, and data is transmitted without leaving the chip.

[0279] This structure achieves true real-time phase unwrapping and has the following significant advantages:

[0280] No software iteration is required, and the response time is only in the microsecond range.

[0281] The threshold register can be dynamically configured to adapt to different sensing scenarios;

[0282] A fixed delay and continuous output are maintained through a three-stage pipelined comparator;

[0283] A complete hardware closed-loop feedback structure was formed, which effectively suppressed noise and drift.

[0284] The design of this embodiment achieves synergy in the logic layer, timing layer, and storage layer, which not only improves the untangling accuracy but also enhances the system robustness, demonstrating significant innovative features.

[0285] Among them, a bidirectional communication mechanism is set between the FPGA unwrapping module and the ring buffer module to form real-time collaborative feedback between the algorithm control logic and the hardware execution unit. This mechanism is implemented through two types of signals: one is a "correction signal" used for instruction phase adjustment; the other is a "hold signal" used to lock the buffer area during correction to prevent data overwriting. Together, they form a closed-loop control link for phase filtering, unwrapping and quality evaluation.

[0286] Two-way communication and signal interaction mechanism

[0287] Correction signal generation and transmission

[0288] When the anomaly detection unit inside the FPGA unwrapping module detects a continuity interruption, abrupt change, or reversal in the phase unfolding result, it immediately generates a correction signal. The correction signal is transmitted to the phase progressive unfolding unit via the on-chip control bus to trigger its internal phase compensation logic.

[0289] The compensation logic performs data correction in the next clock cycle, adjusting the phase value corresponding to the anomaly to a reasonable range. The adjusted result is rewritten to the output partition of the ring buffer module, overwriting the original abnormal data.

[0290] Maintain signal triggering and recovery

[0291] While the correction signal is generated, the anomaly detection unit outputs a hold signal to the ring buffer module; while the hold signal is high, the read and write pointers of the buffer area pause incrementing, locking the current buffer page to prevent data from being overwritten by new samples during the correction period;

[0292] Once phase compensation is complete, the system automatically clears the hold signal, restores the normal incrementing state of the read / write pointer, and allows the buffer to re-enter the loop for read / write.

[0293] This dual-signal mechanism ensures that the correction process and the data access process are always synchronized under high-speed data flow, and will not cause timing disorder or data loss.

[0294] Parameter dynamic update and feedback path

[0295] During the correction and hold signal operation, the ring buffer module synchronously sends trigger pulses to the quality measurement and recalculation control unit;

[0296] After receiving the pulse, the quality measurement and recalculation control unit recalculates the parameters applicable to the current state, including the phase determination threshold and the sliding window length, based on the error distribution and data stability of the current unwrapping result.

[0297] The new threshold parameters and window length are written to the threshold register and window parameter register in the FPGA in real time. These registers are connected to the phase filtering unit and the phase unrolling unit to ensure that the new parameters take effect immediately in subsequent data processing. The entire parameter update and write-back process is completed inside the FPGA with a delay of only a few clock cycles, without the need for external controllers.

[0298] When the error assessment module detects that the phase change rate is continuously higher than the preset stable range, the system automatically increases the upper limit parameter in the threshold register and appropriately increases the window length; when the data is detected to be continuously stable, the system automatically decreases the threshold and shortens the window length.

[0299] This real-time adaptive mechanism can dynamically adjust the judgment criteria according to the signal and noise environment, so that the system can maintain reliable untangling output under different interference conditions.

[0300] Hardware closed-loop execution process

[0301] The aforementioned bidirectional signals and parameter update logic together constitute the hardware feedback path inside the FPGA.

[0302] Its workflow is as follows:

[0303] The anomaly detection unit sends a correction signal after detecting an anomaly.

[0304] The phase progression unit immediately performs phase correction while keeping the signal active to freeze the buffer.

[0305] The circular cache module pauses data updates and waits for the correction to complete.

[0306] Upon receiving the synchronization trigger pulse, the quality measurement and recalculation control unit performs real-time evaluation and generates new parameter values;

[0307] The new parameter values ​​are written back to each unwrapping unit via registers;

[0308] Once the signal is released, the cache resumes operation and enters the next data processing cycle;

[0309] Through this hardware closed-loop structure, the system achieves complete synchronization of anomaly detection, data correction, parameter update and cache management, ensuring real-time continuous output under high-speed sampling conditions;

[0310] Two-way signal interaction:

[0311] This invention simultaneously designs correction signals and hold signals to achieve bidirectional synchronous control of the unwinding module and the buffer module. Traditional technologies are mostly unidirectional data output modes and lack real-time feedback capabilities.

[0312] Parameter adaptive update:

[0313] The system can automatically adjust the threshold and window length based on the real-time data quality, which is different from existing fixed threshold or static judgment methods;

[0314] The entire film achieves a closed-loop system:

[0315] The entire process from anomaly detection to parameter update is completed within the FPGA logic without the need for external CPU intervention, and the response time is controlled within microseconds, significantly improving real-time performance.

[0316] Hardware-level synchronization control:

[0317] The correction, hold, and evaluation signals are all triggered synchronously by the on-chip clock to ensure that they are executed under the same timing reference and to eliminate cross-clock domain interference.

[0318] This structure is not a simple improvement on existing algorithms, but a new FPGA hardware adaptive control system with clear technological advancements.

[0319] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0320] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An FPGA-based time series phase unwrapping method, characterized in that: The specific steps of the method are as follows: Phase data acquisition: the interference signal collected by the distributed optical fiber sensing system is quadrature demodulated, the CORDIC algorithm is used to obtain the initial phase data on the time axis, and the phase data is written into the FPGA input buffer at a fixed sampling rate, the sampling rate is synchronized with the system clock; Stable group formation: the phase stability index and the amplitude stability index of the continuous period are jointly determined in the FPGA; when the phase stability index is lower than the first threshold value and the amplitude stability index is not lower than the second threshold value, the period is marked as a reliable period point; when the number of continuous reliable period points is not less than the preset group length, a stable group is formed as the unwinding reference; Phase progressive unwinding: starting from the end period of the stable group, the periods are processed along the time axis; when the phase difference between adjacent periods is lower than the third threshold value, cumulative unwinding is performed; When the phase difference is not lower than the third threshold value, the phase change trend index and the amplitude change rate index of the adjacent periods are jointly determined: if the abnormal determination condition is met, the ±2π correction is performed, otherwise the current phase value is kept unchanged; Pipeline and buffer cooperative processing: three pipeline comparators of input stage, comparison stage and determination stage are cascaded in the FPGA; the phase data and the determination result are read and written in parallel and stored in a circular buffer composed of double-port BRAM, and the read and write pointers are cyclically managed by the control logic according to the preset update strategy; Quality metric closed-loop correction: the quality metric index of the unwound phase sequence is calculated, and when the index exceeds the fourth threshold value, the control logic sends a recalculation trigger signal, clears the intermediate result partition of the buffer and retains the input partition data, and returns to the stable group formation and phase progressive unwinding for reselection and unwinding.

2. The FPGA-based time series phase unwrapping method of claim 1, wherein: The specific steps of the phase data acquisition are as follows: The FPGA demodulation unit receives the in-phase channel and quadrature channel voltage values of the interference signal output by the distributed optical fiber sensing system, respectively generates quadrature components and in-phase components through on-chip multiplication and addition operation logic, and then converts the components into polar coordinates by using the CORDIC algorithm to obtain the instantaneous phase of each sampling point; The instantaneous phase is temporarily stored in a first-level cache register and then written into the FPGA internal input buffer area; the input buffer area is composed of a double-port storage unit, the write end is driven by the sampling clock, and the read end and the subsequent phase selection unit work synchronously in the same system clock domain; the sampling clock and the system clock are phase-locked through a clock distribution network, ensuring that the sampling interval is constant and that data writing and reading are performed under the same timing reference.

3. The FPGA-based time series phase unwrapping method of claim 2, wherein: The specific steps of the stable group formation are as follows: The determination logic circuit inside the FPGA receives the phase data and amplitude data of the input buffer area output by the phase data acquisition; The phase change amount and the corresponding amplitude change amount of adjacent periods are extracted in a preset sampling window, the phase stability index and the amplitude stability index of each period are obtained through a statistical calculation unit, and the values of the two indexes are compared with the first threshold value and the second threshold value stored in the threshold register in parallel; When the phase stability index of a certain cycle is less than the first threshold value and the amplitude stability index is not lower than the second threshold value, a reliable flag bit is written at the cycle address position by the control logic; when the number of continuous reliable flag bits reaches a preset group length, the control logic identifies the data of the continuous address segment as a stable group and records the start address and end address thereof in the group index register, and the stable group index information is used as an input reference of a subsequent phase unwrapping unit.

4. The FPGA-based time series phase unwrapping method of claim 3, wherein: The specific steps of the phase progressive unwrapping are as follows: The end cycle of the stable group is taken as the unwrapping start cycle, the phase data of adjacent cycles are read along the time axis in sequence, the phase difference between adjacent cycles is calculated and compared with a third threshold value stored in a threshold register; When the phase difference is less than the third threshold value, the phase values are accumulated in time sequence; When the phase difference is not less than the third threshold value, the phase change trend data and amplitude change rate data of several cycles before and after the current cycle are read, and a joint judgment is made according to preset trend judgment conditions and amplitude change conditions: if the judgment result satisfies the correction condition, the phase value of the current cycle is corrected by cycle jump; if the judgment result does not satisfy the correction condition, the phase value of the current cycle is kept unchanged; The unwrapped phase data are output to a cache area in time sequence for subsequent quality measurement and closed-loop correction.

5. The FPGA-based time series phase unwrapping method of claim 4, wherein: The specific steps of the pipeline and cache cooperative processing are as follows: A three-stage pipeline structure connected in sequence by an input stage, a comparison stage and a judgment stage is formed in the FPGA, The phase data are sequentially processed in the input stage, the comparison stage and the judgment stage in sequence, and the data are sequentially transmitted between stages through registers to keep the time sequence consistent; The phase data and the judgment result output by the judgment stage are written into a ring-shaped cache area composed of double-port BRAM, the cache area is provided with a read pointer and a write pointer, the read and write pointers are cyclically moved according to a preset update rule at the clock beat, and when the interval between the write pointer and the read pointer reaches a preset cache depth, the cyclic coverage mode is automatically entered, so that the parallel reading and writing and continuous storage of the phase data and the judgment result are realized; The output end of the cache area synchronously transmits the unwrapped phase data of the current cycle to the subsequent quality measurement and closed-loop correction.

6. The FPGA-based time series phase unwrapping method of claim 5, wherein: The specific steps of the quality measurement and closed-loop correction are as follows: The unwrapped phase sequence output by the cache area is read in sequence according to a preset sampling window, the phase difference data in the window are obtained by a statistical calculation unit, and the corresponding quality measurement parameters are calculated, the quality measurement parameters including an error evaluation quantity reflecting the phase unwrapping accuracy; When the calculated quality measurement parameter exceeds a fourth threshold value stored in a threshold register, a recalculation trigger signal is generated by the control logic and sent to a cache management unit; After receiving the recalculation trigger signal, the cache management unit clears the intermediate results in the temporary storage partition, retains the original phase data in the input partition and the threshold setting in the parameter register, so that the system re-executes the stable group formation and phase progressive unwrapping process in the same clock domain. After the re-computation is completed, the new phase unwrapping result replaces the original temporary data and is output to the buffer area, thereby forming a continuous feedback loop between data acquisition, unwrapping computation and error evaluation.

7. An FPGA-based time series phase unwrapping system, characterized in that: The FPGA-based time series phase unwrapping system is based on the method of any one of claims 1-6, and the system comprises: a phase demodulation module for quadrature demodulating the interference signal and outputting time series initial phase data; an FPGA unwrapping module comprising a reliable period screening unit, a phase progressive unwrapping unit, an abnormality judging unit, a quality metric and re-computation control unit, and a three-stage pipeline comparator coupled therewith; a ring buffer module composed of on-chip dual-port BRAMs, comprising an input partition, a temporary storage partition and an output partition, for parallel reading and writing and cyclic storage of phase data and judgment results during unwrapping; a control and clock module for providing system clock, threshold and window parameters, re-computation trigger signals, and timing synchronization control of reading and writing pointers and pipeline stage registers; wherein the FPGA unwrapping module and the ring buffer module are bidirectionally coupled through correction signals and holding signals: the abnormality judgment result is used to guide the phase correction of the unwrapping unit, and is output to the quality metric and re-computation control unit to participate in the online adjustment of threshold and window parameters, forming an algorithm-hardware co-synergic closed loop.

8. The FPGA-based time series phase unwrapping system of claim 7, wherein: The phase demodulation module quadrature demodulates the interference signal to obtain time series initial phase data, the FPGA unwrapping module receives the initial phase data and performs phase screening, unwrapping and correction processing, the ring buffer module accesses phase data and judgment results during unwrapping, and the control and clock module provides uniform clock signals and threshold parameters for each module and realizes overall timing synchronization.

9. The FPGA-based time series phase unwrapping system of claim 8, wherein: The FPGA unwrapping module comprises a reliable period screening unit, a phase progressive unwrapping unit, an abnormality judging unit, a quality metric and re-computation control unit, and a three-stage pipeline comparator sequentially connected with the units; wherein the reliable period screening unit is used for continuous period screening of input phase data, the phase progressive unwrapping unit performs phase unwrapping calculation according to the screening result, the abnormality judging unit judges the phase change trend and amplitude change rate, the quality metric and re-computation control unit calculates quality parameters and generates re-computation trigger signals according to the judgment result, and the three-stage pipeline comparator sequentially transmits comparison results between the units to ensure consistent data processing timing.

10. The FPGA-based time series phase unwrapping system of claim 9, wherein: The FPGA unwrapping module and the ring buffer module are bidirectionally connected through correction signals and holding signals, the correction signal output by the abnormality judging unit is used to guide the phase adjustment of the phase progressive unwrapping unit, and the holding signal and the correction signal are simultaneously input to the quality metric and re-computation control unit to update real-time parameters in the threshold register and the window parameter register, so as to form an algorithm-hardware co-synergic feedback closed loop in the phase screening, unwrapping and quality metric processes.

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