Floating voltage source circuits, units, power management chips and electronic devices

Abstract

This application relates to a floating voltage source circuit, unit, power management chip, and electronic device. The floating voltage source circuit includes: an error amplifier, the first input terminal of which is used to connect to a reference voltage; a floating power supply circuit, the first terminal of which is connected to the output terminal of the error amplifier, and the second terminal of which is connected to the second input terminal of the error amplifier; a floating ground circuit, the first terminal of which is connected to both the output terminal of the error amplifier and the first terminal of the floating power supply circuit, and the second terminal of which is connected to both the second terminal of the floating power supply circuit and the second input terminal of the error amplifier; both the second terminals of the floating power supply circuit and the floating ground circuit are used to provide a floating voltage to the load; and a reference voltage is used to clamp the floating voltage to the reference voltage value. This application features low quiescent current loss, high drive capability, and active self-adjustment capability, which can improve the current efficiency of the circuit and the flexibility of the design.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a floating voltage source circuit, unit, power management chip, and electronic device. Background Technology

[0002] With the widespread use of portable electronic products such as mobile phones, computers, and wearable devices, power management performance has gradually become a key factor in the performance of electronic products. In high-voltage power management chips, for purposes such as protecting low-voltage circuits, ensuring effective driving of power switches, or optimizing energy efficiency, a floating power supply typically generates a supply voltage with a fixed voltage drop relative to the external input power supply to power the load.

[0003] In applications where low power consumption is required, multiple floating power supplies and floating grounds are needed inside the chip to achieve the minimum voltage drop that meets circuit performance requirements and minimize current loss. Therefore, the design of floating power supply voltages needs to be more flexible.

[0004] However, traditional floating rail circuits suffer from weak voltage regulation capability, high static power consumption, and the inability to simultaneously achieve floating ground and floating power supply, resulting in a lack of flexibility in application. Summary of the Invention

[0005] Therefore, it is necessary to provide a floating voltage source circuit, unit, power management chip, and electronic device that can effectively reduce static current loss and improve flexibility in response to the above-mentioned technical problems.

[0006] In a first aspect, this application provides a floating voltage source circuit, the floating voltage source circuit comprising:

[0007] An error amplifier, the first input terminal of which is used to connect a reference voltage;

[0008] A floating power supply circuit, with its first terminal connected to the output terminal of the error amplifier and its second terminal connected to the second input terminal of the error amplifier.

[0009] A floating ground circuit is provided. The first terminal of the floating ground circuit is connected to the output terminal of the error amplifier and the first terminal of the floating power supply circuit, respectively. The second terminal of the floating ground circuit is connected to the second terminal of the floating power supply circuit and the second input terminal of the error amplifier, respectively.

[0010] The second terminal of the floating power supply circuit and the second terminal of the floating ground circuit are both used to provide a floating voltage to the load; the reference voltage is used to clamp the floating voltage to the reference voltage value.

[0011] In one embodiment, the floating voltage source circuit further includes:

[0012] The first compensation circuit has its first terminal connected to the third terminal of the floating power supply circuit, and its second terminal connected between the second terminal of the floating power supply circuit and the second input terminal of the error amplifier.

[0013] The second compensation circuit has its first terminal connected to the third terminal of the floating ground circuit, and its second terminal connected between the second terminal of the floating ground circuit and the second input terminal of the error amplifier.

[0014] In one embodiment, the floating power supply circuit includes a first PMOS transistor, a second PMOS transistor, and a first resistor;

[0015] The source of the first PMOS transistor is connected to one end of the first resistor, the gate of the first PMOS transistor is connected to the output of the error amplifier and the first end of the floating ground circuit, and the drain of the first PMOS transistor is used to ground; the other end of the first resistor is used to connect to the power supply voltage.

[0016] The source of the second PMOS transistor is connected between the other end of the first resistor and the power supply voltage. The gate of the second PMOS transistor is connected to one end of the first PMOS transistor, one end of the first resistor, and the first end of the first compensation circuit. The drain of the second PMOS transistor is connected to the second input terminal of the error amplifier, the second end of the floating ground circuit, the second end of the first compensation circuit, and the second end of the second compensation circuit.

[0017] In one embodiment, the floating ground circuit includes a first NMOS transistor, a second NMOS transistor, and a second resistor;

[0018] The source of the first NMOS transistor is connected to one end of the second resistor, the gate of the first NMOS transistor is connected to the input of the error amplifier and the first end of the floating power supply circuit, and the drain of the first NMOS transistor is used to connect to the power supply voltage; the other end of the second resistor is used to ground.

[0019] The source of the second NMOS transistor is connected to the other end of the second resistor. The gate of the second NMOS transistor is connected to the source of the first NMOS transistor, one end of the second resistor, and the first end of the second compensation circuit. The drain of the second NMOS transistor is connected to the second input terminal of the error amplifier, the second end of the floating power supply circuit, the second end of the first compensation circuit, and the second end of the second compensation circuit.

[0020] In one embodiment, a compensation capacitor is also included;

[0021] One end of the compensation capacitor is connected to the output terminal of the error amplifier, the first terminal of the floating power supply circuit, and the first terminal of the floating ground circuit, respectively. The other end of the compensation capacitor is connected to the second terminal of the floating power supply circuit, the second terminal of the floating ground circuit, the second input terminal of the error amplifier, the second terminal of the first compensation circuit, and the second terminal of the second compensation circuit, respectively.

[0022] In one embodiment, the first compensation circuit includes a third PMOS transistor, a fourth PMOS transistor, a first switch, a fifth NMOS transistor, a sixth NMOS transistor, and a first reference current source;

[0023] The source of the third PMOS transistor is connected to the power supply voltage. The gate of the third PMOS transistor is connected to the third terminal of the floating power supply circuit and one terminal of the first switch. The drain of the third PMOS transistor is connected to the control terminal of the first switch and the drain of the sixth NMOS transistor.

[0024] The source of the fourth PMOS transistor is connected between the source of the third PMOS transistor and the power supply voltage. The gate of the fourth PMOS transistor is connected to the other end of the first switch. The drain of the fourth PMOS transistor is connected to the second end of the floating power supply circuit, the second end of the floating ground circuit, the second end of the second compensation circuit, and the second input end of the error amplifier, respectively.

[0025] The drain of the fifth NMOS transistor is connected to the first reference current source, the gate of the fifth NMOS transistor is connected to the drain of the fifth NMOS transistor and the gate of the sixth NMOS transistor, and the source of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor and ground.

[0026] The drain of the sixth NMOS transistor is connected to the drain of the third PMOS transistor and the control terminal of the first switch, respectively, and the source of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor and ground.

[0027] In one embodiment, the second compensation circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a second reference current source, an inverter, a third NMOS transistor, a fourth NMOS transistor, and a second switch;

[0028] The source of the fifth PMOS transistor is connected to the power supply voltage. The gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor and the gate of the sixth PMOS transistor. The drain of the fifth PMOS transistor is also connected to the second reference current source.

[0029] The source of the sixth PMOS transistor is connected between the source of the fifth PMOS transistor and the power supply voltage, and the drain of the sixth PMOS transistor is connected to the drain of the third NMOS transistor.

[0030] The gate of the third NMOS is connected to the third terminal of the floating ground circuit and one terminal of the second switch, respectively. The source of the third NMOS is connected to the source of the fourth NMOS and ground.

[0031] The drain of the fourth NMOS transistor is connected to the second terminal of the floating power supply circuit, the second terminal of the floating ground circuit, the second terminal of the first compensation circuit, and the second input terminal of the error amplifier, respectively. The gate of the fourth NMOS transistor is connected to the other end of the second switch, and the source of the fourth NMOS transistor is connected to the source of the third NMOS transistor and ground.

[0032] One end of the inverter is connected between the drain of the sixth PMOS transistor and the drain of the third NMOS transistor, and the other end of the inverter is connected to the control terminal of the second switch.

[0033] Secondly, this application provides a floating voltage source unit, including the floating voltage source circuit as described in any embodiment of the first aspect.

[0034] Thirdly, this application provides a power management chip, including one or more floating voltage source units as described in the second aspect.

[0035] Fourthly, this application provides an electronic device including the power management chip as described in the third aspect.

[0036] The aforementioned floating voltage source circuit, unit, power management chip, and electronic device include an error amplifier, a floating power supply circuit, and a floating ground circuit. When the floating voltage output by the floating voltage source circuit serves as the floating power supply for the load, the floating ground circuit is shut off in a loop, while the floating power supply circuit continuously supplies power to the load. Conversely, when the floating voltage output by the floating voltage source circuit serves as the floating ground for the load, the floating voltage source circuit is shut off in a loop, while the floating ground circuit continuously supplies power to the load. Through this method, the floating voltage output by the floating voltage source circuit of this application can be precisely designed to any floating voltage value according to load requirements. Furthermore, the floating voltage can serve as both a floating power supply and a floating ground, enabling flexible application in various scenarios and effectively improving the circuit's flexibility. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of a conventional floating power / ground structure in one embodiment;

[0039] Figure 2 This is a block diagram of a floating voltage source circuit in one embodiment;

[0040] Figure 3This is a block diagram of a floating voltage source circuit in another embodiment;

[0041] Figure 4 This is a schematic diagram of the floating voltage generation process in one embodiment;

[0042] Figure 5 This is a schematic diagram of the circuit structure of a floating voltage source circuit in one embodiment;

[0043] Figure 6 This is a schematic diagram of the circuit structure of a floating voltage source circuit in another embodiment. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0045] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0046] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0047] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0048] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0049] It should be noted that in high-voltage power management chips, for purposes such as protecting low-voltage circuits, ensuring effective driving of power switches, or optimizing energy efficiency, a floating power supply typically generates a supply voltage with a fixed voltage drop relative to the external input power supply to power the load.

[0050] In applications where low power consumption is paramount, multiple floating power supplies and floating grounds are required within the chip to achieve the minimum voltage drop needed to meet circuit performance requirements and minimize current loss. This necessitates more flexible floating power supply voltage design. Furthermore, for chips with larger integration scales, the driving capability requirements of floating power supplies become even higher under heavy loads.

[0051] In traditional schemes, the floating rail circuit voltage is determined by the reverse breakdown voltage of the Zener diode or the gate-source voltage of the MOSFET. However, the voltage generated by the Zener diode cannot be adjusted, and the gate-source voltage of the MOSFET will exhibit a large voltage deviation, resulting in weak regulation capability. Furthermore, as... Figure 1 As shown, Figure 1 It showcases a traditional floating power / ground structure, while Figure 1 The structures in (a) to (d) do not have the ability to simultaneously implement floating ground and floating power supply in the circuit. Furthermore, under heavy loads, these circuit structures require greater static current loss, which is unacceptable for some low-power applications.

[0052] To address the aforementioned issues, this application provides a floating voltage source circuit that effectively improves circuit flexibility.

[0053] In one exemplary embodiment, such as Figure 2 As shown, a floating voltage source circuit 200 is provided, the floating voltage source circuit 200 including:

[0054] Error amplifier OP, the first input terminal of error amplifier OP is used to connect the reference voltage Vref;

[0055] The first terminal of the floating power supply circuit 204 is connected to the output terminal of the error amplifier OP, and the second terminal of the floating power supply circuit 204 is connected to the second input terminal of the error amplifier OP.

[0056] The first terminal of the floating ground circuit 206 is connected to the output terminal of the error amplifier OP and the first terminal of the floating power supply circuit 204, respectively. The second terminal of the floating ground circuit 206 is connected to the second terminal of the floating power supply circuit 204 and the second input terminal of the error amplifier OP, respectively.

[0057] The second terminal of the floating power supply circuit 204 and the second terminal of the floating ground circuit 206 are both used to provide a floating voltage to the load; the reference voltage Vref is used to clamp the floating voltage Vfloating at the voltage value Vref of the reference voltage.

[0058] For example, such as Figure 2 As shown, the first input terminal of the error amplifier OP can be the inverting input terminal of the amplifier, and the second input terminal of the error amplifier OP can be the non-inverting input terminal of the amplifier.

[0059] Specifically, the output of the floating voltage source circuit 200 includes a floating power supply circuit 204 (also known as the "UP current" module) and a floating ground circuit 206 (also known as the "DOWN current" module). When the floating voltage output by the floating voltage source circuit 200 is used as the floating power supply for the current load, the floating ground circuit 206 will be shut off in a loop, while the floating power supply circuit 204 will continue to supply power to the load. When the floating voltage output by the floating voltage source circuit 200 is used as the floating ground for the current load, the floating power supply circuit 204 will be shut off in a loop, while the floating ground circuit 206 will continue to supply power to the load.

[0060] Understandably, based on the negative feedback structure, the floating voltage at the output of the floating voltage source circuit 200 will be clamped to the reference voltage value. Therefore, when the reference voltage Vref changes, the floating voltage at the output can obtain the corresponding reference voltage value. Furthermore, in the feedback loop formed by the floating voltage source circuit 200, load changes at the output of the floating voltage source circuit 200 will change the supply current at the output, resulting in voltage change information at the output. After the negative feedback structure feeds the voltage change information back to the error amplifier OP, the signal output by the error amplifier OP will adjust the current of the floating power supply circuit 204 and the current of the floating ground circuit 206 (i.e., the UP current and the DOWN current) to compensate for load changes, thereby maintaining the floating voltage at the output of the floating voltage source circuit 200.

[0061] In one embodiment, such as Figure 3 As shown, the floating voltage source circuit 200 also includes:

[0062] The first compensation circuit 208 has its first end connected to the third end of the floating power supply circuit 204, and its second end connected between the second end of the floating power supply circuit 204 and the second input end of the error amplifier OP.

[0063] The second compensation circuit 210 has its first end connected to the third end of the floating ground circuit 206, and its second end connected between the second end of the floating ground circuit 206 and the second input end of the error amplifier OP.

[0064] For example, the first compensation circuit 208 and / or the second compensation circuit 210 may include their respective "detection & sampling" modules and compensation current modules. The "detection & sampling" module can be used to detect the load condition at the output terminal and control the operating state of the compensation current module according to the load condition; the compensation current module can be used to perform current compensation to maintain the floating voltage at the output terminal.

[0065] In some instances, the floating voltage generation process corresponding to the floating voltage source circuit 200 is as follows: Figure 4 As shown, when the "detection & sampling" module corresponding to the first compensation circuit 208 and / or the second compensation circuit 210 detects a large load at the output terminal, it automatically turns on the corresponding compensation current module to maintain the floating voltage at the output terminal; while when the "detection & sampling" module corresponding to the first compensation circuit 208 and / or the second compensation circuit 210 detects a small load at the output terminal, it turns off the corresponding compensation current module so as not to affect the operation of the system.

[0066] Furthermore, such as Figure 4 As shown, when the output of the floating voltage source circuit 200 is under a small load, no load, or the load is off, the "UP current" and "DOWN current" in the figure will be biased to a low current state. When the floating voltage at the output of the floating voltage source circuit 200 serves as the power supply for the load, the "UP current" module (i.e., the floating power supply circuit 204) continuously supplies power, while the "DOWN current" module (i.e., the floating ground circuit 206) will be turned off or in a very low current state. Similarly, when the floating voltage at the output of the floating voltage source circuit 200 serves as the floating ground of the load, the "UP current" module (i.e., the floating power supply circuit 204) will be turned off or in a very low current state, while the "DOWN current" module (i.e., the floating ground circuit 206) continuously supplies power. It can be understood that, through the above method, the floating voltage source circuit 200 of this application can self-adjust the compensation current module to improve current efficiency according to the power supply situation of the load.

[0067] In one embodiment, such as Figure 5 As shown, the floating power supply circuit 204 includes a first PMOS transistor MP1, a second PMOS transistor MP2, and a first resistor R1;

[0068] The source of the first PMOS transistor MP1 is connected to one end of the first resistor R1, the gate of the first PMOS transistor MP1 is connected to the output of the error amplifier OP and the first end of the floating ground circuit 206, and the drain of the first PMOS transistor MP1 is used to ground; the other end of the first resistor R1 is used to connect to the power supply voltage VDD.

[0069] The source of the second PMOS transistor MP2 is connected between the other end of the first resistor R1 and the power supply voltage VDD. The gate of the second PMOS transistor MP2 is connected to one end of the first PMOS transistor MP1, one end of the first resistor R1 and the first end of the first compensation circuit 208. The drain of the second PMOS transistor MP2 is connected to the second input terminal of the error amplifier OP, the second terminal of the floating ground circuit 206, the second terminal of the first compensation circuit 208 and the second terminal of the second compensation circuit 210.

[0070] It should be noted that the first PMOS transistor MP1 and the first resistor R1 can form an upper buffer stage module.

[0071] It is understandable that the gate voltage of the second PMOS transistor MP2 will be one gate-source voltage (denoted as |Vgsp|) lower than the gate voltage of the first PMOS transistor MP1. The first resistor R1 can reduce the static current of the buffer stage. In this way, the upper buffer stage circuit can bias the driving transistor of the output stage of the floating power supply circuit 204 into a weak conduction mode, thereby minimizing the static current loss.

[0072] Specifically, the floating power supply circuit 204 can provide a floating voltage through the drain of the second PMOS transistor MP2 to the load, and effectively reduce the loss of static current by using the upper buffer module composed of the first PMOS transistor MP1 and the first resistor R1.

[0073] In one embodiment, the floating ground circuit 206 includes a first NMOS transistor MN1, a second NMOS transistor MN2, and a second resistor R2;

[0074] The source of the first NMOS transistor MN1 is connected to one end of the second resistor R2. The gate of the first NMOS transistor MN1 is connected to the input of the error amplifier OP and the first end of the floating power supply circuit 204, respectively. The drain of the first NMOS transistor MN1 is used to connect to the power supply voltage VDD. The other end of the second resistor R2 is used to ground.

[0075] The source of the second NMOS transistor MN2 is connected to the other end of the second resistor R2. The gate of the second NMOS transistor MN2 is connected to the source of the first NMOS transistor MN1, one end of the second resistor R2, and the first end of the second compensation circuit 210. The drain of the second NMOS transistor MN2 is connected to the second input terminal of the error amplifier OP, the second end of the floating power supply circuit 204, the second end of the first compensation circuit 208, and the second end of the second compensation circuit 210.

[0076] For example, the first NMOS transistor MN1 and the second resistor R2 can form a lower buffer stage module.

[0077] It is understandable that, similar to the floating power supply circuit 204 described above, the second resistor R2 can also reduce the quiescent current of the buffer stage, thereby enabling the lower buffer stage circuit to bias the drive transistor of the output stage of the floating ground circuit 206 in a weak conduction mode, thus minimizing the loss of quiescent current.

[0078] Specifically, the floating ground circuit 206 can provide a floating voltage through the drain of the second NMOS transistor MN2 as the load, and effectively reduce the loss of static current by utilizing the lower buffer module composed of the first NMOS transistor MN1 and the second resistor R2.

[0079] In one embodiment, such as Figure 6 As shown, the first compensation circuit 208 includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first switch Sw1, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a first reference current source;

[0080] The source of the third PMOS transistor MP3 is connected to the power supply voltage VDD. The gate of the third PMOS transistor MP3 is connected to the third terminal of the floating power supply circuit 204 and one terminal of the first switch Sw1. The drain of the third PMOS transistor MP3 is connected to the control terminal of the first switch Sw1 and the drain of the sixth NMOS transistor MN6.

[0081] The source of the fourth PMOS transistor MP4 is connected between the source of the third PMOS transistor MP3 and the power supply voltage VDD. The gate of the fourth PMOS transistor MP4 is connected to the other end of the first switch Sw1. The drain of the fourth PMOS transistor MP4 is connected to the second end of the floating power supply circuit 204, the second end of the floating ground circuit 206, the second end of the second compensation circuit 210, and the second input end of the error amplifier OP.

[0082] The drain of the fifth NMOS transistor MN5 is connected to the first reference current source. The gate of the fifth NMOS transistor MN5 is connected to the drain of the fifth NMOS transistor MN5 and the gate of the sixth NMOS transistor MN6. The source of the fifth NMOS transistor MN5 is connected to the source of the sixth NMOS transistor MN6 and ground.

[0083] The drain of the sixth NMOS transistor MN6 is connected to the drain of the third PMOS transistor MP3 and the control terminal of the first switch Sw1, respectively. The source of the sixth NMOS transistor MN6 is connected to the source of the fifth NMOS transistor MN5 and ground.

[0084] Specifically, the gate of the third PMOS transistor MP3 is used to detect and sample the current of the floating power supply circuit 204, and when the sampled current meets the preset current conditions, it controls the first switch Sw1 to perform corresponding actions to determine whether it is necessary to provide compensation current (also called upper compensation current) to the output terminal through the fourth PMOS transistor MP4.

[0085] In one embodiment, such as Figure 6 As shown, the second compensation circuit 210 includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a second reference current source, an inverter INV, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a second switch Sw2.

[0086] The source of the fifth PMOS transistor MP5 is connected to the power supply voltage VDD. The gate of the fifth PMOS transistor MP5 is connected to the drain of the fifth PMOS transistor MP5 and the gate of the sixth PMOS transistor MP6. The drain of the fifth PMOS transistor MP5 is also connected to the second reference current source.

[0087] The source of the sixth PMOS transistor MP6 is connected between the source of the fifth PMOS transistor MP5 and the power supply voltage VDD, and the drain of the sixth PMOS transistor MP6 is connected to the drain of the third NMOS transistor.

[0088] The gate of the third NMOS is connected to the third terminal of the floating ground circuit 206 and one terminal of the second switch Sw2, respectively. The source of the third NMOS is connected to the source of the fourth NMOS transistor MN4 and ground.

[0089] The drain of the fourth NMOS transistor MN4 is connected to the second terminal of the floating power supply circuit 204, the second terminal of the floating ground circuit 206, the second terminal of the first compensation circuit 208, and the second input terminal of the error amplifier OP. The gate of the fourth NMOS transistor MN4 is connected to the other end of the second switch Sw2. The source of the fourth NMOS transistor MN4 is connected to the source of the third NMOS transistor MN3 and ground.

[0090] One end of the inverter INV is connected between the drain of the sixth PMOS transistor MP6 and the drain of the third NMOS transistor, and the other end of the inverter INV is connected to the control terminal of the second switch Sw2.

[0091] Specifically, the gate of the third NMOS transistor MN3 is used to detect and sample the current of the floating ground circuit 206, and when the sampled current meets the preset current condition, it controls the second switch Sw2 to perform the corresponding action to determine whether it is necessary to provide compensation current (also called lower compensation current) to the output terminal through the fourth NMOS transistor MN4.

[0092] In one embodiment, such as Figure 6 As shown, the floating voltage source circuit 200 also includes a compensation capacitor;

[0093] One end of the compensation capacitor is connected to the output terminal of the error amplifier OP, the first terminal of the floating power supply circuit 204, and the first terminal of the floating ground circuit 206, respectively. The other end of the compensation capacitor is connected to the second terminal of the floating power supply circuit 204, the second terminal of the floating ground circuit 206, the second input terminal of the error amplifier OP, the second terminal of the first compensation circuit 208, and the second terminal of the second compensation circuit 210, respectively.

[0094] Specifically, the compensation capacitor can be used to improve the phase margin of the corresponding loop of the floating voltage source circuit 200, thereby ensuring loop stability.

[0095] To further illustrate this application, Figure 6 Taking the specific circuit structure of the floating voltage source circuit 200 shown as an example, the process of outputting the floating voltage is further described as follows:

[0096] For example, such as Figure 6 As shown, when the output is unloaded, the third PMOS transistor MP3 mirrors the second PMOS transistor MP2, and the sampling current ratio is N:1, that is, the current Ip3 of the third PMOS transistor MP3 = N*Ip2, where Ip2 is the current of the second PMOS transistor MP2. The reference current Iref1 provided by the first reference current source is mirrored to the branch corresponding to the sixth NMOS transistor MN6 through the fifth NMOS transistor MN5, and the ratio is K:1, that is, the current In6 of the sixth NMOS transistor MN6 = K*Iref1.

[0097] Furthermore, when the current Ip2 of the second PMOS transistor MP2 is mirrored to the current N*Ip2 of the third PMOS transistor MP3, which is less than K*Iref1, the control terminal voltage Vct1 of the first switch Sw1 decreases to control the first switch Sw1 to turn off, thereby further turning off the fourth PMOS transistor MP4, and thus controlling the first compensation circuit 208 not to provide the upper compensation current at this time.

[0098] Similarly, the third NMOS transistor MN3 mirrors the second NMOS transistor MN2, and the sampling current ratio is N:1, meaning the current In3 of the third NMOS transistor MN3 = N*In2, where In2 is the current of the second NMOS transistor MN2. The reference current Iref2 provided by the second reference current source is mirrored to the branch corresponding to the sixth PMOS transistor MP6 through the fifth PMOS transistor MP5, and the ratio is K:1, meaning the current Ip6 of the sixth PMOS transistor MP6 = K*Iref2.

[0099] Furthermore, when the current In2 of the second NMOS transistor MN2 is mirrored to the current N*In2 of the third NMOS transistor MN3, which is less than K*Iref2, the voltage Vct2 at the control terminal of the second switch Sw2 will decrease, thereby controlling the second switch Sw2 to turn off, which in turn turns off the fourth NMOS transistor MN4, and thus controls the second compensation circuit 210 to not provide the lower compensation current at this time.

[0100] It should be noted that, due to the mirror ratio, the current values ​​of Iref1, Iref2, N*Ip2, and K*In2 can be designed to be in the range of uA or nA to further reduce static current loss.

[0101] It is understandable that the gate voltage of the second PMOS transistor MP2 will be lower than the gate voltage of the first PMOS transistor MP1 by one gate-source voltage (i.e., |Vgsp|), and the first resistor R1 and the second resistor R2 can reduce the quiescent current of the buffer stage. In this way, the buffer stage module in the floating power supply circuit 204 and the floating ground circuit 206 can bias the drive transistor of the output stage in a weak conduction mode, thereby minimizing the loss of quiescent current.

[0102] In some examples, taking the load of the floating voltage source circuit 200 requiring a floating power supply with a power supply capability of less than 1mA as an example, the floating voltage Vfloating at the output of the floating voltage source circuit 200 will decrease, then the control voltage Vop output by the error amplifier OP will decrease, the gate voltage of the second PMOS transistor MP2 will decrease, further turning on the second PMOS transistor MP2 and removing it from the weak conduction mode to enhance the power supply capability. Further, the above circuit operation process can be represented as follows: Vfloating↓——Vop↓——Vgsp2↓——Vfloating↑; at this time, for the lower buffer stage module, the circuit operation process is as follows: Vfloating↓——Vop↓——Vgsn2↓——Vfloating↑, where the second NMOS transistor MN2 will further turn off from the weak conduction mode, thereby further reducing unnecessary current loss. Simultaneously, the third PMOS transistor MP3 detects that the Ip2 current of the second PMOS transistor MP2 does not exceed a preset value, and will turn off the first switch Sw1 and the fourth PMOS transistor MP4, thus not providing the upper compensation current. Similarly, at this time, the circuit N*In2 of the third NMOS transistor MN3 decreases, and the voltage Vct2 at the control terminal of the second switch Sw2 decreases, which will turn off the second switch Sw2 and the fourth NMOS transistor MN4, thus not providing the lower compensation current.

[0103] In some possible implementations, taking a floating power supply requiring a load capacity of over 100mA as an example, the third PMOS transistor MP3 will detect that the rising current Ip2 of the second PMOS transistor MP2 has reached the pre-designed limit. At this time, the current N*Ip2 of the third PMOS transistor MP3 will be greater than the current K*Iref1 of the sixth PMOS transistor MP6, causing the control terminal voltage Vct1 of the first switch Sw1 to rise. This turns on the first switch Sw1, enabling the fourth PMOS transistor MP4 to provide upper compensation current to maintain the floating voltage Vfloating. Due to the feedback loop, the second NMOS transistor MN2 will be further turned off. After the third NMOS transistor MN3 detects the decrease in the current of the second NMOS transistor MN2, its current N*In2 will decrease, thus reducing the control terminal voltage Vct2 of the second switch Sw2. This causes the second switch Sw2 and the fourth NMOS transistor MN4 to turn off, thereby not providing lower compensation current and effectively reducing unnecessary current loss. It is understandable that when the load requires a floating power supply with a power supply capacity in the range of 1mA to 100mA or a floating ground, the circuit operation is similar to that described above, and will not be repeated here.

[0104] It should be noted that when the load of the floating voltage source circuit requires stronger power supply capability, that is, when the output current exceeds the pre-design value, the corresponding compensation current of the floating voltage source circuit will be activated. This realizes the active self-adjustment capability and large driving capability of the floating voltage source circuit. In addition, the circuit also has the advantage of low static current loss, which effectively improves current efficiency and increases the flexibility of output floating voltage design.

[0105] It is understood that, compared with traditional solutions, the floating voltage source circuit of this application has at least the following beneficial technical effects:

[0106] ① It features low quiescent current loss and high drive capability: First, the compensation current module of the floating voltage source circuit only turns on under heavy load conditions, such as when the load requires a power supply path of more than 100mA. At this time, the compensation current module turns on and continuously supplies power to the load. Second, the output current of the floating voltage source circuit is biased to a low current state. Then, when the "UP current" of the floating power supply circuit or the "DOWN current" of the floating ground circuit is under load, only one module will be turned on, while the other module will be turned off or in an extremely low current state, thereby reducing quiescent current loss and enabling the circuit to achieve high drive capability under low quiescent current conditions, thus improving the current efficiency of the circuit.

[0107] ② It has active self-adjustment capability: The power supply requirements of the load to the circuit will be reflected at the output terminal, and the compensation current module will automatically detect the power supply status at the output terminal to compensate or turn off. For small loads, the compensation current module is turned off, while for large loads, it will compensate current to maintain the floating voltage at the output terminal.

[0108] ③ The design of the output floating voltage is flexible: the floating voltage at the output terminal can be precisely designed to any floating voltage value according to the load requirements, and the floating voltage can be used as a floating power supply or a floating ground, so that the floating voltage source circuit of this application can be flexibly applied in a variety of scenarios.

[0109] In one exemplary embodiment, this application provides a floating voltage source unit, including the floating voltage source circuit as described in any of the foregoing embodiments.

[0110] It is understood that the solution provided by the floating voltage source unit is similar to the solution described in the above embodiments. For specific limitations in the embodiments of this application, please refer to the limitations of the floating voltage source circuit above, which will not be repeated here.

[0111] In one exemplary embodiment, this application provides a power management chip including one or more floating voltage source units as described in the above embodiments.

[0112] It is understood that the solution provided by the power management chip is similar to the solution described in the above embodiments. For specific limitations in the embodiments of this application, please refer to the limitations on the floating voltage source circuit above, which will not be repeated here.

[0113] In one exemplary embodiment, this application provides an electronic device including a power management chip as described in the above embodiments.

[0114] It is understood that the solution provided by this electronic device is similar to the solution described in the above embodiments. For specific limitations in the embodiments of this application, please refer to the limitations on the floating voltage source circuit above, which will not be repeated here.

[0115] In practical applications, the electronic device may include portable electronic products such as mobile phones, computers, and wearable devices, and this application does not make specific limitations here.

[0116] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0117] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A floating voltage source circuit, characterized by, The floating voltage source circuit includes: An error amplifier, wherein the first input terminal of the error amplifier is used to connect a reference voltage; A floating power supply circuit, wherein the first end of the floating power supply circuit is connected to the output end of the error amplifier, and the second end of the floating power supply circuit is connected to the second input end of the error amplifier; A floating ground circuit, wherein the first terminal of the floating ground circuit is connected to the output terminal of the error amplifier and the first terminal of the floating power supply circuit, and the second terminal of the floating ground circuit is connected to the second terminal of the floating power supply circuit and the second input terminal of the error amplifier. The second terminal of the floating power supply circuit and the second terminal of the floating ground circuit are both used to provide a floating voltage to the load; the reference voltage is used to clamp the floating voltage at the voltage value of the reference voltage. The floating voltage source circuit also includes: A first compensation circuit, wherein a first terminal of the first compensation circuit is connected to a third terminal of the floating power supply circuit, and a second terminal of the first compensation circuit is connected between a second terminal of the floating power supply circuit and a second input terminal of the error amplifier. The second compensation circuit has a first terminal connected to the third terminal of the floating ground circuit, and a second terminal connected between the second terminal of the floating ground circuit and the second input terminal of the error amplifier.

2. The floating voltage source circuit according to claim 1, characterized in that, The floating power supply circuit includes a first PMOS transistor, a second PMOS transistor, and a first resistor; The source of the first PMOS transistor is connected to one end of the first resistor, the gate of the first PMOS transistor is connected to the output of the error amplifier and the first end of the floating ground circuit, and the drain of the first PMOS transistor is used to ground; the other end of the first resistor is used to connect to the power supply voltage. The source of the second PMOS transistor is connected between the other end of the first resistor and the power supply voltage. The gate of the second PMOS transistor is connected to one end of the first PMOS transistor, one end of the first resistor, and the first end of the first compensation circuit. The drain of the second PMOS transistor is connected to the second input terminal of the error amplifier, the second terminal of the floating ground circuit, the second terminal of the first compensation circuit, and the second terminal of the second compensation circuit.

3. The floating voltage source circuit according to claim 1, characterized in that, The floating ground circuit includes a first NMOS transistor, a second NMOS transistor, and a second resistor; The source of the first NMOS transistor is connected to one end of the second resistor, the gate of the first NMOS transistor is connected to the input terminal of the error amplifier and the first terminal of the floating power supply circuit, and the drain of the first NMOS transistor is used to connect to the power supply voltage; the other end of the second resistor is used to ground. The source of the second NMOS transistor is connected to the other end of the second resistor. The gate of the second NMOS transistor is connected to the source of the first NMOS transistor, one end of the second resistor, and the first end of the second compensation circuit. The drain of the second NMOS transistor is connected to the second input terminal of the error amplifier, the second end of the floating power supply circuit, the second end of the first compensation circuit, and the second end of the second compensation circuit.

4. The floating voltage source circuit according to claim 1, characterized in that, The first compensation circuit includes a third PMOS transistor, a fourth PMOS transistor, a first switch, a fifth NMOS transistor, a sixth NMOS transistor, and a first reference current source; The source of the third PMOS transistor is connected to the power supply voltage, the gate of the third PMOS transistor is connected to the third terminal of the floating power supply circuit and one terminal of the first switch, and the drain of the third PMOS transistor is connected to the control terminal of the first switch and the drain of the sixth NMOS transistor. The source of the fourth PMOS transistor is connected between the source of the third PMOS transistor and the power supply voltage. The gate of the fourth PMOS transistor is connected to the other end of the first switch. The drain of the fourth PMOS transistor is connected to the second terminal of the floating power supply circuit, the second terminal of the floating ground circuit, the second terminal of the second compensation circuit, and the second input terminal of the error amplifier. The drain of the fifth NMOS transistor is connected to the first reference current source, the gate of the fifth NMOS transistor is connected to the drain of the fifth NMOS transistor and the gate of the sixth NMOS transistor, and the source of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor and ground. The drain of the sixth NMOS transistor is connected to the drain of the third PMOS transistor and the control terminal of the first switch, respectively, and the source of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor and ground.

5. The floating voltage source circuit according to claim 1, characterized in that, The second compensation circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a second reference current source, an inverter, a third NMOS transistor, a fourth NMOS transistor, and a second switch; The source of the fifth PMOS transistor is used to connect to the power supply voltage, the gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor and the gate of the sixth PMOS transistor respectively, and the drain of the fifth PMOS transistor is also connected to the second reference current source. The source of the sixth PMOS transistor is connected between the source of the fifth PMOS transistor and the power supply voltage, and the drain of the sixth PMOS transistor is connected to the drain of the third NMOS transistor. The gate of the third NMOS is connected to the third terminal of the floating ground circuit and one terminal of the second switch, respectively, and the source of the third NMOS is connected to the source of the fourth NMOS transistor and ground. The drain of the fourth NMOS transistor is connected to the second terminal of the floating power supply circuit, the second terminal of the floating ground circuit, the second terminal of the first compensation circuit, and the second input terminal of the error amplifier, respectively. The gate of the fourth NMOS transistor is connected to the other end of the second switch, and the source of the fourth NMOS transistor is connected to the source of the third NMOS transistor and ground. One end of the inverter is connected between the drain of the sixth PMOS transistor and the drain of the third NMOS transistor, and the other end of the inverter is connected to the control terminal of the second switch.

6. The floating voltage source circuit according to any one of claims 1 to 5, characterized in that, It also includes compensation capacitors; One end of the compensation capacitor is connected to the output terminal of the error amplifier, the first terminal of the floating power supply circuit, and the first terminal of the floating ground circuit, respectively. The other end of the compensation capacitor is connected to the second terminal of the floating power supply circuit, the second terminal of the floating ground circuit, the second input terminal of the error amplifier, the second terminal of the first compensation circuit, and the second terminal of the second compensation circuit, respectively.

7. A floating voltage source unit, characterized in that, Includes the floating voltage source circuit as described in any one of claims 1 to 6.

8. A power management chip, characterized in that, It includes one or more floating voltage source units as described in claim 7.

9. An electronic device, characterized in that, Includes the power management chip as described in claim 8.

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