Data synchronization systems, methods and equipment

Abstract

This application provides a data synchronization system, method, and device. The system includes a control signal line, a data signal line, and multiple functional units. The multiple functional units include a first functional unit, which is any one of the multiple functional units. The first functional unit is configured to, in response to the presence of data to be synchronized, change the level state of the control signal line from a first state to a second state; send the data to be synchronized to a second functional unit via the data signal line; and reset the level state of the control signal line back to the first state. The second functional unit is any one or more functional units other than the first functional unit. This technical solution improves the data synchronization efficiency between functional units in a multi-functional unit system.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data synchronization system, method and device. Background Technology

[0002] In a multi-chip system, multiple chips can work together to complete system tasks. For any single chip in a multi-chip system, its operation may require data from other chips; therefore, data synchronization between chips is necessary in a multi-chip system. Summary of the Invention

[0003] In view of this, embodiments of this application provide a data synchronization system, method, and apparatus to at least partially solve the above-mentioned problems.

[0004] According to a first aspect of the embodiments of this application, a data synchronization system is provided, including: a control signal line, a data signal line, and a plurality of functional units; the functional units are hardware units with preset functions; the plurality of functional units include a first functional unit, which is any one of the plurality of functional units; the first functional unit is configured to, in response to the existence of data to be synchronized, set the level state of the control signal line from a first state to a second state; send the data to be synchronized to a second functional unit through the data signal line, and set the level state of the control signal line back to the first state; the second functional unit is any one or more functional units other than the first functional unit among the plurality of functional units.

[0005] According to a second aspect of the embodiments of this application, a data synchronization method is provided, applied to the system as described in the first aspect, the method comprising: a first functional unit, in response to the existence of data to be synchronized, setting the level state of the control signal line from a first state to a second state; the first functional unit sending the data to be synchronized to a second functional unit through the data signal line, and setting the level state of the control signal line back to the first state; the second functional unit being any one or more functional units other than the first functional unit among the plurality of functional units.

[0006] According to a third aspect of the embodiments of this application, an electronic device is provided, comprising: the system as described in the first aspect.

[0007] In the above technical solution, any functional unit in the multifunctional unit system can actively synchronize the data to be synchronized to other functional units without the need for other functional units to frequently query and retrieve data, thereby improving the data synchronization efficiency between functional units. Furthermore, when synchronizing the data to be synchronized to other functional units, the occupancy status of data transmission resources can be determined by controlling the state of the signal line, and the data transmission resources can be competed for, thereby coordinating the data sending and receiving between different functional units and preventing data synchronization failure caused by multiple functional units occupying the data signal line at the same time. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0009] Figure 1 A schematic diagram of the structure of a data synchronization system provided in an embodiment of this application;

[0010] Figure 2 This is another schematic diagram of the data synchronization system provided in the embodiments of this application;

[0011] Figure 3 This is another schematic diagram of the data synchronization system provided in the embodiments of this application;

[0012] Figure 4 This is another schematic diagram of the data synchronization system provided in the embodiments of this application;

[0013] Figure 5 This is another schematic diagram of the data synchronization system provided in the embodiments of this application;

[0014] Figure 6 This is another schematic diagram of the data synchronization system provided in the embodiments of this application;

[0015] Figure 7 This is another schematic diagram of the data synchronization system provided in the embodiments of this application;

[0016] Figure 8 This is another schematic diagram of the data synchronization system provided in the embodiments of this application;

[0017] Figure 9 A flowchart illustrating a data synchronization method provided in an embodiment of this application;

[0018] Figure 10This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0020] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0021] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0022] It should also be noted that the terms "first, second, and third" used in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, and third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0023] Furthermore, in the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0024] In multi-chip systems, when data synchronization is required between chips, some technical solutions involve retrieving data from other chips via data queries. Specifically, for any chip in a multi-chip system, when it needs to obtain target data from other chips, it typically sends query requests for the target data to other chips at a set frequency. Once the query confirms that the target data has been generated in another chip, it retrieves the target data from that chip. This approach is inefficient and detrimental to improving overall system performance.

[0025] This application provides a data synchronization system that can realize data synchronization between different chips in a multi-chip system and improve the efficiency of data synchronization, thereby improving the overall performance of the system.

[0026] The data synchronization system provided in this application embodiment may include: control signal lines, data signal lines, and multiple functional units. Here, a functional unit refers to a hardware unit with a specific preset function. In this application embodiment, the functional unit may be a packaged chip, or it may be a chiplet, or multiple functional units may simultaneously include both chips and chipslets. The functional units can be connected to each other via control signal lines, and the functional units can also be connected to each other via data signal lines.

[0027] Figure 1 Taking a scenario where the functional unit is a chip as an example, a schematic diagram of the structure of a data synchronization system provided in an embodiment of this application is given. Figure 1 As shown, the data synchronization system provided in this application embodiment may include: control signal lines, data signal lines, and multiple chips. Each chip can be connected to the control signal lines and data signal lines respectively via a bus topology.

[0028] Figure 2 Taking a scenario where functional units are the core components as an example, a structural diagram of a data synchronization system provided in an embodiment of this application is given. Figure 2 As shown, the data synchronization system provided in this application embodiment may include: control signal lines, data signal lines, and multiple cores. Each core can be connected to the control signal lines and data signal lines respectively via a bus topology. Figure 2 The multiple chips shown can be, for example, multiple chips contained in the same chip, or chips contained in different chips.

[0029] In this embodiment, the control signal line can be used to control the data transmission and reception status of each functional unit, and the data signal line can be used to transmit data to be synchronized between the functional units. In this embodiment, for any one of the multiple functional units in the data synchronization system, in response to the existence of data to be synchronized, the level state of the control signal line can be set from a first state to a second state. Then, this functional unit can send the data to be synchronized to any one or more other functional units through the data signal line, and after data synchronization is completed, the level state of the control signal line is set back to the first state.

[0030] The first state can be used to indicate that there is currently no data to be synchronized being transmitted on the data signal line, and the second state can be used to indicate that there is currently data to be synchronized being transmitted on the data signal line. The first state can be, for example, a high-level state (or a low-level state), and the second state can be, for example, a low-level state (or a high-level state). That is, when the control signal line is in a high-level state, it can be assumed that there is currently no data to be synchronized being transmitted on the data signal line, i.e., the data signal line is idle; when the control signal line is in a low-level state, it can be assumed that there is currently data to be synchronized being transmitted on the data signal line, i.e., the data signal line is occupied.

[0031] For ease of description, in the subsequent embodiments of this application, any one of the functional units in the above-mentioned multifunctional unit system will be referred to as the "first functional unit", and any one or more other functional units in the multifunctional unit system will be referred to as the "second functional unit".

[0032] Through the above technical solution, any functional unit in the multifunctional unit system can actively synchronize the data to be synchronized to other functional units without the need for other functional units to frequently query and retrieve data, thereby improving the data synchronization efficiency between functional units. Furthermore, when synchronizing the data to be synchronized to other functional units, the occupancy status of data transmission resources can be determined by controlling the state of the data transmission signal line, and the data transmission resources can be competed for, thereby coordinating the data sending and receiving between different functional units and preventing data synchronization failures caused by multiple functional units simultaneously occupying the data signal line.

[0033] For ease of description and understanding, the following description uses a scenario where the functional unit is a chip as an example, and explains the functional implementation of the data synchronization system provided in this application in conjunction with relevant accompanying drawings. It should be understood that the following functional implementation also applies to scenarios where the functional unit is a chip, or where each functional unit has both a chip and a chip.

[0034] Figure 3 A schematic diagram of the data synchronization system provided in an embodiment of this application is given. For example... Figure 3 As shown, the data synchronization system provided in this application embodiment may include: a control signal line, a data signal line, and multiple chips. The control signal line includes a serial clock line (SCL), and the multiple chips are respectively connected to the clock signal line. The data signal line includes a serial data line (SDA), and the multiple chips are respectively connected to the serial data line.

[0035] based on Figure 3 The system shown allows for data synchronization among individual chips in a multi-chip system, based on a synchronous serial transmission method.

[0036] The following is about... Figure 3 The specific functional implementation method of the system shown will be explained.

[0037] In such Figure 3 In the system shown, the first chip can be used to detect the level state of the clock signal line in response to the presence of data to be synchronized. If the clock signal line is detected to be in a first state, indicating that no data to be synchronized is currently being transmitted on the serial data line, the first chip can set the clock signal line's level state from the first state to a second state. Once the clock signal line's level state is set to the second state, the first chip can send the data to be synchronized to the second chip. If the clock signal line is detected to be in a second state, indicating that data to be synchronized is currently being transmitted on the serial data line, the first chip can wait for the clock signal line's level state to return to the first state before setting the clock signal line's level state from the first state to the second state and sending the data to be synchronized to the second chip.

[0038] During the process of the first chip sending synchronization data to the second chip, the clock signal line can switch to a square wave signal. Therefore, the first chip can determine the transmission frequency of the synchronization data based on the clock period of the clock signal line, and then, according to this transmission frequency, transmit the data via... Figure 3 The single serial data line shown transmits the data to be synchronized to the second chip using a synchronous serial transmission method. Specifically, the first chip can broadcast the data to be synchronized to, for example,... Figure 3 As shown in the diagram, a single serial data line allows a second chip to monitor data on the serial data line and receive data after detecting data to be synchronized.

[0039] Through the above technical solution, the first chip can complete the synchronous serial transmission of the data to be synchronized using a single serial data line according to the clock cycle of the clock signal line, and actively synchronize the data to be synchronized to the second chip.

[0040] Before sending the data to be synchronized to the second chip, the first chip can also send transmission parameters to the second chip.

[0041] In one implementation, the transmission parameters include the identification information of the first chip. The length of the identification information can be pre-configured according to the number of chips included in the multi-chip system. The first chip can first transmit information via... Figure 3 The serial data line shown transmits the identification information of the first chip to the second chip. This identification information is used by the second chip to determine whether the data to be synchronized is the same data it needs to receive. After confirming that the data is the same, the second chip listens for and receives the data. Specifically, the first chip can broadcast its identification information to the second chip via a specific method. Figure 3The second chip, using a single serial data line, can monitor the data on the serial data line to obtain the identification information of the first chip. The second chip can parse the identification information via system interrupts and software, or it can parse it via hardware. For example, an event can trigger a corresponding processing module or processor to parse the identification information. Based on the identification information of the first chip, the second chip can determine the source of the data to be synchronized, thus determining whether the data to be synchronized is its own data to be received. After determining that the data to be synchronized is its own data to be received, the second chip can receive the data after subsequently monitoring the data to be synchronized on the serial data line. If it determines that the data to be synchronized is not its own data to be received, the second chip does not need to monitor the data to be synchronized on the serial data line, or it does not need to receive the data to be synchronized after monitoring the data to be synchronized on the serial data line. Through this implementation, the transmitting chip does not need to distinguish the receiving chip, but can broadcast the data to be synchronized to other chips. Each receiving chip can automatically determine whether the current data is its own data to be received and complete the reception. This implementation scheme enables efficient data synchronization between chips through a simple hardware connection method.

[0042] In another implementation, based on the above, the transmission parameters may further include the length information of the data to be synchronized. This length information can be used by the second chip to determine whether the data to be synchronized has been completely received. The length threshold of the data to be synchronized can be preset. The first chip may also first... Figure 3 The serial data line shown transmits the length information of the data to be synchronized to the second chip. Specifically, the first chip can broadcast the length information of the data to be synchronized to the second chip. Figure 3 As shown in the diagram, a second chip can monitor the data on the serial data line to obtain the length information of the synchronization data. Based on the length information, the second chip can determine whether the data to be synchronized has been completely received. Before determining that the data to be synchronized has been completely received, the second chip can wait for the first chip to complete the transmission of the data to be synchronized. After determining that the data to be synchronized has been completely received, each chip can change the level state of the clock signal line to re-compete for data transmission resources and transmit its own data to be synchronized to other chips. This implementation method prevents the data transmission process of a chip from being interrupted by the data transmission of other chips, improving data transmission efficiency and reliability.

[0043] Furthermore, in this embodiment, the data to be synchronized can be divided into multiple data units and transmitted sequentially. A data unit can be, for example, a data packet. After sending any one data unit to the second chip, the first chip can also be used to, through methods such as... Figure 3The single serial data line shown sends a check signal and a stop signal to the second chip. The check signal and stop signal can each occupy 1 bit, for example. The stop signal can be a 1-bit high-level signal. The stop signal can be used by the second chip to determine that the data unit has been received. The check signal can be used by the second chip to perform data verification on the data unit. Specifically, after receiving the stop signal, the second chip can determine that the current data unit has been received. Then, the second chip can use the check signal to perform data verification on the current data unit, such as parity checking. The specific method by which the first chip sends the check signal and stop signal to the second chip via the serial data line can be referred to the transmission method of the aforementioned transmission parameters, and will not be repeated here.

[0044] After the data to be synchronized has been sent, the first chip can reset the clock signal line to its first state. Then, each chip can change the clock signal line's level to compete for data transmission resources again, thereby synchronizing its own data with other chips.

[0045] The above implementation method achieves synchronous serial transmission of data to be synchronized among chips in a multi-chip system. Furthermore, in this embodiment, each chip is connected to the clock signal line and serial data line via a bus topology, simplifying the wiring, reducing hardware implementation complexity, and increasing reliability.

[0046] Figure 4 Another schematic diagram of the data synchronization system provided in this application embodiment is given. Figure 3 Different, such as Figure 4 In the system shown, the data signal lines may include multiple serial data lines, with multiple chips connected to each serial data line respectively. Based on Figure 4 The system shown demonstrates that in a multi-chip system, each chip can achieve data synchronization based on a synchronous parallel transmission method. The following section discusses... Figure 4 The specific functional implementation method of the system shown will be explained.

[0047] like Figure 4 As shown, the first chip can send transmission parameters to the second chip via any one of multiple serial data lines. The transmission parameters may include the identification information of the first chip and / or the length information of the data to be synchronized. For specific data transmission methods, please refer to [example example]. Figure 3 Explanation of how the system's functions are implemented.

[0048] Furthermore, the first chip can send the data to be synchronized to the second chip via various serial data lines in a parallel transmission manner. Specifically, the first chip can determine the transmission frequency of the data to be synchronized based on the clock period of the clock signal line, and then, according to this transmission frequency, transmit the data via a parallel transmission method such as... Figure 4The serial data lines shown transmit the data to be synchronized to the second chip using a synchronous parallel transmission method. The first chip can broadcast the data to be synchronized to the second chip. Figure 4 The second chip can be used to monitor the data on each serial data line shown, and receive the data after it detects the data to be synchronized.

[0049] Furthermore, similar to the aforementioned embodiments, the data to be synchronized can be divided into multiple data units and transmitted sequentially. These data units can be, for example, data packets. After sending any data unit to the second chip via any serial data line, the first chip can also be used to, through, as... Figure 4 Each of the serial data lines shown sends a verification signal and a stop signal to the second chip, respectively. The stop signal is used by the second chip to confirm that the data unit has been received. The verification signal is used by the second chip to verify the data in the data unit.

[0050] After the data to be synchronized has been sent, the first chip can reset the clock signal line to its first state. Then, each chip can change the clock signal line's level to compete for data transmission resources again, thereby synchronizing its own data with other chips.

[0051] The above implementation method achieves synchronous and parallel transmission of data to be synchronized among chips in a multi-chip system. Furthermore, in this embodiment, each chip is connected to the clock signal line and each serial data line via a bus topology, simplifying the wiring, reducing hardware implementation complexity, and increasing reliability.

[0052] Figure 5 Another schematic diagram of the data synchronization system provided in this application embodiment is given. For example... Figure 5 As shown in the illustration, the data synchronization system provided in this application embodiment may include: a control signal line, a data signal line, and multiple chips. The control signal line includes a chip select signal line, and the multiple chips are respectively connected to the chip select signal line. The data signal line includes a serial data line, and the multiple chips are respectively connected to the serial data line.

[0053] based on Figure 5 The system shown allows for data synchronization between individual chips in a multi-chip system based on asynchronous serial transmission. The following section discusses... Figure 5 The specific functional implementation method of the system shown will be explained.

[0054] In such Figure 5In the system shown, the first chip can be used to detect the level state of the chip select signal line in response to the presence of data to be synchronized. If the chip select signal line is detected to be in a first state, indicating that no data to be synchronized is currently being transmitted on the serial data line, the first chip can set the level state of the chip select signal line from the first state to a second state. Once the chip select signal line is set to the second state, the first chip can send the data to be synchronized to the second chip. If the chip select signal line is detected to be in a second state, indicating that data to be synchronized is currently being transmitted on the serial data line, the first chip can wait for the chip select signal line to return to the first state before setting the level state of the chip select signal line from the first state to the second state and sending the data to be synchronized to the second chip.

[0055] The first chip can be accessed via, for example... Figure 5 The single serial data line shown transmits the data to be synchronized to the second chip using an asynchronous serial transmission method. Since the transmission frequency cannot be determined by a clock signal in asynchronous transmission, the first chip can transmit the data to be synchronized to the second chip according to a preset baud rate. The first chip can also broadcast the data to be synchronized to the second chip, such as... Figure 5 The single serial data line shown allows the second chip to monitor data on the serial data line and receive data after detecting data to be synchronized. The preset baud rate can be determined in advance through negotiation between the first and second chips.

[0056] In this embodiment, since the receiving end cannot determine the timing to start receiving the data to be synchronized via a clock signal under asynchronous transmission, in this embodiment, before the first chip sends the data to be synchronized to the second chip via a serial data line based on asynchronous transmission, it can also: send a start signal to the second chip via the serial data line. The start signal can, for example, occupy 1 bit, and can be, for example, a change from a high level to a low level in the serial data line signal. The hold time of the start signal can be determined according to a preset baud rate. The start signal can be used by the second chip to determine the timing to start receiving the data to be synchronized, and then the second chip can start receiving the data to be synchronized according to the timing indicated by the start signal.

[0057] Furthermore, similar to the aforementioned embodiments, the first chip can also send transmission parameters to the second chip before sending the data to be synchronized. In this embodiment, the transmission parameters can be sent to the second chip according to a preset baud rate. The specific types and functions of the transmission parameters, as well as the specific method by which the first chip sends the transmission parameters to the second chip, can be found in the aforementioned embodiments. Figure 3 The explanation of how the system's functions are implemented is omitted.

[0058] In this embodiment, the data to be synchronized can be divided into multiple data units and transmitted sequentially. A data unit can be, for example, a data packet. After sending any one data unit to the second chip, the first chip can also be used to, via, such as... Figure 5 The single serial data line shown sends a verification signal and a stop signal to the second chip. The stop signal is used by the second chip to determine that the data unit has been received. The verification signal is used by the second chip to verify the data in the data unit. For details, please refer to the description of the foregoing embodiment; further elaboration is omitted here.

[0059] After the data to be synchronized has been sent, the first chip can reset the level of its chip select signal line to the first state. Then, each chip can change the level of its chip select signal line to compete for data transmission resources again, thereby synchronizing its own data to be synchronized with other chips.

[0060] The above implementation method achieves asynchronous serial transmission of data to be synchronized between chips in a multi-chip system. Furthermore, in this embodiment, each chip is connected to the chip select signal line and serial data line via a bus topology, simplifying the wiring, reducing hardware implementation complexity, and increasing reliability. Meanwhile, compared to... Figure 3 The synchronous serial transmission method of the system shown has a single function: the chip select signal line is used only for each chip to compete for data transmission resources, and does not need to be used to control the data transmission timing during data transmission, thereby improving data transmission efficiency.

[0061] Figure 6 Another schematic diagram of the data synchronization system provided in this application embodiment is given. Figure 5 Different, such as Figure 6 The data synchronization system shown may include multiple serial data lines, with multiple chips connected to each serial data line respectively. Based on Figure 6 The system shown demonstrates that in a multi-chip system, individual chips can achieve data synchronization based on asynchronous parallel transmission. The following section discusses... Figure 6 The specific functional implementation method of the system shown will be explained.

[0062] With Figure 5 Unlike the systems shown, the first chip can send a start signal to the second chip via any one of the multiple serial data lines. Furthermore, the first chip can send transmission parameters to the second chip via any one of the multiple serial data lines. These transmission parameters may include the identification information of the first chip and / or the length information of the data to be synchronized. For specific data transmission methods, please refer to [examples of other chips]. Figure 5 Explanation of how the system's functions are implemented.

[0063] Furthermore, the first chip can send the data to be synchronized to the second chip via various serial data lines in a parallel transmission mode. Specifically, the first chip can transmit the data according to a preset baud rate, such as... Figure 6 The serial data lines shown transmit the data to be synchronized to the second chip using an asynchronous parallel transmission method. The first chip can broadcast the data to be synchronized to the second chip. Figure 6 The second chip can be used to monitor the data on each serial data line shown, and receive the data after it detects the data to be synchronized.

[0064] Furthermore, similar to the aforementioned embodiments, the data to be synchronized can be divided into multiple data units and transmitted sequentially. These data units can be, for example, data packets. After sending any data unit to the second chip via any serial data line, the first chip can also be used to, through, as... Figure 6 Each of the serial data lines shown sends a verification signal and a stop signal to the second chip, respectively. The stop signal is used by the second chip to confirm that the data unit has been received. The verification signal is used by the second chip to verify the data in the data unit.

[0065] After the data to be synchronized has been sent, the first chip can reset the level of its chip select signal line to the first state. Then, each chip can change the level of its chip select signal line to compete for data transmission resources again, thereby synchronizing its own data to be synchronized with other chips.

[0066] The above implementation method achieves asynchronous parallel transmission of data to be synchronized between chips in a multi-chip system. Furthermore, in this embodiment, each chip is connected to the chip select signal line and each serial data line via a bus topology, simplifying the wiring, reducing hardware implementation complexity, and increasing reliability. Meanwhile, compared to... Figure 4 The synchronous parallel transmission method of the system shown has a single function: the chip select signal line is used only for each chip to compete for data transmission resources, and does not need to be used to control the data transmission timing during data transmission, thereby improving data transmission efficiency.

[0067] In another embodiment of this application, such as Figure 7 As shown, the control signal lines may also include clock signal lines and chip select signal lines. Each chip can be connected to the clock signal lines and chip select signal lines respectively based on a bus topology. The chip select signal lines are used for chips to compete for data transmission resources, while the clock signal lines are used to control the data transmission timing during data transmission.

[0068] Specifically, the first chip can be used to set the level state of the chip select signal line from a first state to a second state in response to the presence of data to be synchronized. Furthermore, the first chip can determine the transmission frequency of the data to be synchronized based on the clock period of the clock signal line, and then, according to the transmission frequency, transmit the data to be synchronized to the second chip through one or more data signal lines based on synchronous serial or synchronous parallel transmission mode, and set the level state of the chip select signal line back to the first state.

[0069] In this implementation, a chip select signal line is set up for each chip to compete for data transmission resources, and a clock signal line is set up to control the data transmission timing during data transmission. Compared to... Figure 3 The clock signal line in the system shown is used simultaneously by various chips to compete for data transmission resources and to control the timing of data transmission, which can improve data transmission efficiency.

[0070] In another embodiment of this application, for example... Figure 5 or Figure 6 The system shown is as follows: Figure 8 As shown, the connection between each chip and the chip select signal line can also be such that any one chip is connected to all other chips via the chip select signal line. In response to the presence of data to be synchronized, the first chip can identify the receiving chip for the data to be synchronized, and then set the level of the chip select signal line between itself and the receiving chip from a first state to a second state. The receiving chip can then determine that it is the receiver of the data to be synchronized. The first chip can then send the data to be synchronized to the data signal line, and the receiving chip can receive the data from the data signal line. Other chips, determining that they are not the receivers of the data to be synchronized, will no longer listen for or receive the data. Furthermore, after data synchronization is complete, the first chip can reset the level of the chip select signal line between itself and the receiving chip to the first state.

[0071] Through such Figure 8 In the connection method shown, the first chip can actively select the receiving chip for the data to be synchronized. In this way, the first chip does not need to send its own identification information to other chips before transmitting the data to be synchronized, thus improving data transmission efficiency. However, due to... Figure 8 The connection method shown increases hardware complexity; therefore, it can be applied when the number of chips in a multi-chip system is relatively small. Figure 8 The connection method shown is used when the number of chips in a multi-chip system is large, and the aforementioned bus topology connection method is applied.

[0072] Figure 9 A flowchart of a data synchronization method provided in an embodiment of this application is given. The data synchronization method provided in this application can be applied to the systems described in the above embodiments, such as… Figure 9 As shown, the data synchronization method provided in this application embodiment may include:

[0073] Step 101: In response to the presence of data to be synchronized, the first functional unit sets the level state of the control signal line from the first state to the second state.

[0074] Step 102: The first functional unit sends the data to be synchronized to the second functional unit through the data signal line, and resets the level state of the control signal line to the first state.

[0075] In one specific implementation, the control signal line includes a clock signal line; multiple functional units are respectively connected to the clock signal line; the method further includes: determining the transmission frequency of the data to be synchronized according to the clock period of the clock signal line; and transmitting the data to be synchronized to the second functional unit through the data signal line according to the transmission frequency and based on the synchronous transmission method.

[0076] In one specific implementation, the control signal line includes a chip select signal line; multiple functional units are respectively connected to the chip select signal line; the first functional unit sends the data to be synchronized to the second functional unit through the data signal line, including: the first functional unit sends the data to be synchronized to the second functional unit through the data signal line at a preset baud rate, based on an asynchronous transmission method.

[0077] In one specific implementation, the method further includes: the first functional unit sending a start signal to the second functional unit via a data signal line, the start signal being used by the second functional unit to determine when to begin receiving data to be synchronized.

[0078] In one specific implementation, the control signal line includes a clock signal line and a chip select signal line; multiple functional units are respectively connected to the clock signal line and the chip select signal line; the method further includes: in response to the existence of data to be synchronized, the first functional unit sets the level state of the chip select signal line from a first state to a second state; the transmission frequency of the data to be synchronized is determined according to the clock period of the clock signal line; and the data to be synchronized is transmitted to the second functional unit through the data signal line according to the transmission frequency and based on the synchronous transmission method.

[0079] In one specific implementation, the number of data signal lines is one or more; the first functional unit sends the data to be synchronized to the second functional unit through the data signal lines, including: the first functional unit sends the data to be synchronized to the second functional unit through a single data signal line in a serial transmission manner; or, the first functional unit sends the data to be synchronized to the second functional unit through multiple data signal lines in a parallel transmission manner.

[0080] In one specific implementation, multiple functional units are connected to data signal lines respectively; the first functional unit sends the data to be synchronized to the second functional unit through the data signal lines, including: the first functional unit uploads the data to be synchronized to the data signal lines so that the second functional unit can listen to and receive the data to be synchronized from the data signal lines.

[0081] In one specific implementation, the method further includes: a first functional unit sending transmission parameters to a second functional unit via a data signal line; the transmission parameters include the identification information of the first functional unit and the length information of the data to be synchronized; the identification information of the first functional unit is used by the second functional unit to determine whether the data to be synchronized is its own data to be received, and after determining that the data to be synchronized is its own data to be received, it listens for and receives the data to be synchronized; the length information of the data to be synchronized is used by the second functional unit to determine whether the data to be synchronized has been completely received.

[0082] In one specific implementation, the data to be synchronized includes multiple data units; after the first functional unit sends any one of the data units to the second functional unit via a data signal line, the method further includes: the first functional unit sending a verification signal and a stop signal to the second functional unit via the data signal line; the verification signal is used by the second functional unit to perform data verification on the data unit; the stop signal is used by the second functional unit to determine that the data unit has been received.

[0083] The specific implementation method has been described in detail in the foregoing system embodiments. For details, please refer to the foregoing embodiments, and will not be repeated here.

[0084] In another embodiment of this application, an electronic device may be provided, which may be configured with the system provided in the embodiments of this application. The embodiments of this application do not limit the specific form of the electronic device; for example, it may be a mobile phone, computer, intelligent robot, wearable device, etc.

[0085] Figure 10 A schematic diagram of the structure of an electronic device according to an embodiment of the present application is shown. The electronic device may be configured with a system provided in the embodiment of the present application. The system can be used to execute the data synchronization method provided in the embodiment of the present application. The specific embodiments of the present application do not limit the specific implementation of the electronic device.

[0086] like Figure 10 As shown, the electronic device may include: a processor 602, a communications interface 604, a memory 606, and a communications bus 608.

[0087] The processor 602, communication interface 604, and memory 606 communicate with each other via communication bus 608. Communication interface 604 is used to communicate with other electronic devices or servers. The processor 602 is used to execute program 610, specifically performing the relevant steps in the above method embodiments.

[0088] Specifically, program 610 may include program code that includes computer operation instructions.

[0089] Processor 602 may be a CPU, an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. The smart device includes one or more processors, which may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0090] Memory 606 is used to store program 610. Memory 606 may include high-speed RAM or non-volatile memory. volatile memory), such as at least one disk storage device.

[0091] Specifically, program 610 can be used to cause processor 602 to perform the following operations: In an optional embodiment, program 610 is further used to cause processor 602 to perform the following operations. The specific implementation of each step in program 610 can be found in the corresponding steps in the above method embodiments and the corresponding descriptions in the system, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.

[0092] This application also provides a computer program product, including computer instructions that instruct a computing device to perform an operation corresponding to any of the methods in the above-described plurality of method embodiments. It should be noted that, depending on implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0093] This application also provides a computer-readable storage medium in which the methods described in this application embodiment can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as CDROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code downloaded over a network that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0094] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0095] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0096] Furthermore, it should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Moreover, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0097] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0098] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0099] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0100] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0101] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A data synchronization system, characterized in that, include: The system includes control signal lines, data signal lines, and multiple functional units; each functional unit is a hardware unit with a preset function. The plurality of functional units are connected to each other via the control signal lines, and are also connected to each other via the data signal lines; the control signal lines include clock signal lines and / or chip select signal lines; the data signal lines include one or more serial data lines, and when the data signal lines include multiple serial data lines, each of the functional units is connected to the other functional units via the multiple serial data lines; the plurality of functional units includes a first functional unit, which is any one of the plurality of functional units; When the control signal line includes the clock signal line, the first functional unit is configured to, in response to the presence of data to be synchronized, change the level state of the clock signal line from a first state to a second state. The data to be synchronized is sent to the second functional unit in a synchronous transmission manner through the data signal line, based on the clock period of the clock signal line. The level state of the clock signal line is reset to the first state; the second functional unit is any one or more functional units other than the first functional unit among the plurality of functional units; When the control signal line includes the clock signal line and the chip select signal line, the first functional unit is configured to, in response to the presence of data to be synchronized, change the level state of the chip select signal line from a first state to a second state. The data to be synchronized is sent to the second functional unit in a synchronous transmission manner through the data signal line, based on the clock period of the clock signal line. Set the level of the chip select signal line back to the first state; When the control signal line includes the chip select signal line, the first functional unit is configured to, in response to the presence of data to be synchronized, set the level state of the chip select signal line from a first state to a second state; and send the data to be synchronized to the second functional unit via the data signal line in an asynchronous transmission manner. Set the level of the chip select signal line back to the first state.

2. The system according to claim 1, characterized in that, The control signal line includes a clock signal line; the plurality of functional units are respectively connected to the clock signal line; The first functional unit is specifically used for: The transmission frequency of the data to be synchronized is determined based on the clock period of the clock signal line. According to the transmission frequency, the data to be synchronized is sent to the second functional unit through the data signal line in a synchronous transmission manner.

3. The system according to claim 1, characterized in that, The control signal line includes a chip select signal line; the plurality of functional units are respectively connected to the chip select signal line; The first functional unit is specifically used for: According to the preset baud rate, the data to be synchronized is sent to the second functional unit through the data signal line in an asynchronous transmission mode.

4. The system according to claim 3, characterized in that, Before the first functional unit sends the data to be synchronized to the second functional unit via the data signal line in an asynchronous transmission mode, the first functional unit is further configured to: A start signal is sent to the second functional unit via the data signal line. The start signal is used by the second functional unit to determine when to start receiving the data to be synchronized.

5. The system according to claim 1, characterized in that, The control signal line includes a clock signal line and a chip select signal line; the plurality of functional units are respectively connected to the clock signal line and the chip select signal line; the first functional unit is specifically used for: In response to the presence of data to be synchronized, the level state of the chip select signal line is changed from the first state to the second state; The transmission frequency of the data to be synchronized is determined based on the clock period of the clock signal line. According to the transmission frequency, the data to be synchronized is sent to the second functional unit through the data signal line in a synchronous transmission manner.

6. The system according to claim 1, characterized in that, The number of data signal lines is one or more; the first functional unit is specifically used to: send the data to be synchronized to the second functional unit in a serial transmission manner through a single data signal line; or, send the data to be synchronized to the second functional unit in a parallel transmission manner through multiple data signal lines.

7. The system according to claim 1, characterized in that, The plurality of functional units are respectively connected to the data signal line; the first functional unit is specifically used to: upload the data to be synchronized to the data signal line, so that the second functional unit can listen to and receive the data to be synchronized from the data signal line.

8. The system according to claim 1, characterized in that, Before sending the data to be synchronized to the second functional unit via the data signal line, the first functional unit is further configured to: The transmission parameters are sent to the second functional unit via the data signal line; the transmission parameters include the identification information of the first functional unit and the length information of the data to be synchronized. The identification information of the first functional unit is used by the second functional unit to determine whether the data to be synchronized is its own data to be received, and to listen to and receive the data to be synchronized after determining that the data to be synchronized is its own data to be received; The length information of the data to be synchronized is used by the second functional unit to determine whether the data to be synchronized has been completely received.

9. The system according to claim 8, characterized in that, The data to be synchronized includes multiple data units; after sending any one data unit to the second functional unit via the data signal line, the first functional unit is further configured to: A verification signal and a stop signal are sent to the second functional unit via the data signal line; the verification signal is used by the second functional unit to verify the data of the data unit; the stop signal is used by the second functional unit to determine that the data of the data unit has been received.

10. A data synchronization method, characterized in that, An application is made in a data synchronization system, the data synchronization system comprising: control signal lines, data signal lines, and multiple functional units; each functional unit is a hardware unit with a preset function; the multiple functional units are connected to each other via the control signal lines, and are also connected to each other via the data signal lines; the control signal lines include clock signal lines and / or chip select signal lines; the data signal lines include one or more serial data lines, and when the data signal lines include multiple serial data lines, each functional unit is connected to other functional units via the multiple serial data lines; the multiple functional units include a first functional unit, which is any one of the multiple functional units; the method includes: When the control signal line includes the clock signal line, the first functional unit, in response to the presence of data to be synchronized, sets the level state of the clock signal line from a first state to a second state; the first functional unit then transmits the data to be synchronized to the second functional unit via the data signal line, based on the clock period of the clock signal line, in a synchronous transmission manner; the level state of the clock signal line is then set back to the first state; the second functional unit is any one or more functional units other than the first functional unit among the plurality of functional units; When the control signal line includes the clock signal line and the chip select signal line, the first functional unit, in response to the presence of data to be synchronized, sets the level state of the chip select signal line from a first state to a second state; the data to be synchronized is transmitted to the second functional unit via the data signal line in a synchronous transmission manner based on the clock period of the clock signal line; and the level state of the chip select signal line is then set back to the first state. When the control signal line includes the chip select signal line, the first functional unit, in response to the presence of data to be synchronized, sets the level state of the chip select signal line from a first state to a second state; transmits the data to be synchronized to the second functional unit asynchronously via the data signal line; and sets the level state of the chip select signal line back to the first state.

11. An electronic device, characterized in that, include: The system as described in any one of claims 1-9.

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