A redundant residue number system (RRNS) channel encoder, a RRNS channel decoder, a RRNS channel encoding method, a RRNS channel decoding method, an electronic device, and a storage medium

Abstract

The present disclosure relates to a redundant residue number system (RRNS) channel encoder, a RRNS channel decoder, a RRNS channel encoding method, a RRNS channel decoding method, an electronic device, and a storage medium. The RRNS channel encoder corresponds to a modulus set including k information moduli and n-k redundancy moduli. The RRNS channel encoder includes an input module configured to receive a first k-residue vector including k information residue components; a first to (k-1)-th modulus operation module configured to determine k weights based on the k information residue components and the k information moduli; a k-th modulus operation module configured to determine n-k check residue components based on the k information moduli, the k weights, and the n-k redundancy moduli; and an output module configured to determine a first n-residue vector based on the k information residue components and the n-k check residue components, and send the first n-residue vector to a target channel. The embodiments of the present disclosure can reduce the complexity of digital circuit implementation of the RRNS channel encoder.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a Redundancy Remainder System (RRNS) channel encoder, RRNS channel decoder, RRNS channel coding method, RRNS channel decoding method, electronic device, and storage medium. Background Technology

[0002] With the ever-increasing data rates required for processing high-performance workloads (such as deep learning and video streaming) in hyperscale data centers, there is a growing need to build highly reliable, high-bandwidth, and low-latency information transmission network architectures, exemplified by IEEE 802.3 200 / 400GBASE-R Ethernet. Forward Error Correction (FEC) coding, as a technique to improve the reliability of information transmission, can detect and automatically correct errors occurring during channel transmission at the data receiver without requiring data retransmission. Retransmission is costly, leading to low communication efficiency and information transmission delays. Existing multi-level FEC codes suitable for correcting burst errors, such as the RS(544, 514) and RS(528, 514) codes widely used in Ethernet, while possessing strong error correction capabilities, suffer from complex decoding processes requiring multiple iterations. Implementing this algorithm in digital circuits typically consumes over 100 clock cycles, making it unsuitable for latency-sensitive High Performance Computing (HPC) communication scenarios. Summary of the Invention

[0003] This disclosure proposes a technical solution for a Redundancy Remainder System (RRNS) channel encoder, RRNS channel decoder, RRNS channel coding method, RRNS channel decoding method, electronic device, and storage medium.

[0004] According to one aspect of this disclosure, a Redundancy Remainder System (RRNS) channel encoder is provided, comprising: the RRNS channel encoder corresponding to a modulus set consisting of n pairwise coprime numbers, the modulus set including k information modulo numbers and nk redundant modulo numbers, wherein k is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 4; the RRNS channel encoder includes: an input module, a first to k-th level modulus operation module, and an output module; the input module is used to receive a first k-ary remainder vector, wherein the first k-ary remainder vector includes k information remainders. The system comprises: a number of data components; a first to k-1 level modulo operation module for determining k weights based on the k information remainder components and the k information moduloes; a k-level modulo operation module for determining nk check remainder components based on the k information moduloes, the k weights, and the nk redundancy moduloes; and an output module for determining and sending a first n-ary remainder vector to a target channel based on the k information remainder components and the nk check remainder components, wherein the target channel is used to transmit the first n-ary remainder vector from the data sending end to the data receiving end.

[0005] In one possible implementation, the k information modules are m1 to m k The k information remainder components include x1 to x k The k weights include a1 to a k Where a1 = x1; the i-th level modular arithmetic module includes ki first modular arithmetic modules, each of which is used to perform operations. Where i is a positive integer greater than or equal to 1 and less than or equal to k-1; for the j-th first modular arithmetic module included in the i=1-th level modular arithmetic module, the input x corresponding to the first modular arithmetic module is x j+1 Input 'a' as a1, input m -1 for Input m is m j+1 Where j is a positive integer greater than or equal to 1 and less than or equal to ki; for the j-th first modular arithmetic module included in the i>1 level modular arithmetic module, the input x corresponding to the first modular arithmetic module is the output of the (j+1)-th first modular arithmetic module included in the (i-1)-th level modular arithmetic module, and the input a is a i Enter m -1 for Input m is m j+1 .

[0006] In one possible implementation, the nk redundant modules include m k+1 to m n The k-th level modular arithmetic module includes k-1 second modular arithmetic modules; the i-th second modular arithmetic module included in the k-th level modular arithmetic module is used to perform the operation. When i=1, When i>1, For any redundant module m z The redundant module m z When used as input m to each of the second modular arithmetic modules included in the k-th level modular arithmetic module, the redundant modular arithmetic m is obtained based on the k-th level modular arithmetic module. z The corresponding check remainder component, where z is a positive integer greater than or equal to k+1 and less than or equal to n.

[0007] In one possible implementation, for the operation OR operation ,exist or It is a 16-bit binary number. In the case of an 8-bit binary number, Where P[15:12] is the 12th to 15th bits of P, P[11:8] is the 8th to 11th bits of P, and P[7:0] is the 0th to 7th bits of P; for any first or second modular arithmetic module, based on the first preset modular arithmetic table, the following is obtained: The modulo operation result is obtained based on the second preset modulo operation table. The modulo operation result, wherein the first preset modulo operation table includes For the modulo operation result of any information modulus or redundant modulus, the second preset modulo operation table includes The result of the modulo operation on any information modulus or redundancy modulus, where A represents 16 4-bit binary numbers from 0000 to 1111.

[0008] In one possible implementation, the RRNS channel encoder further includes k dff latches; wherein one dff latch is inserted after each stage of modulo operation module.

[0009] In one possible implementation, after determining the nk check remainder components based on the first to k level modulo operation modules, a delay of k clock cycles is introduced.

[0010] According to one aspect of this disclosure, an RRNS channel decoder is provided, comprising: an input module and a plurality of RRNS channel encoders, wherein the RRNS channel encoders are the aforementioned RRNS channel encoders; the input module is configured to obtain a second n-ary remainder vector from a target channel at a data receiving end; the plurality of RRNS channel encoders are configured to decode the second n-ary remainder vector to obtain a third n-ary remainder vector, wherein the third n-ary remainder vector is the same as the first n-ary remainder vector received by the target channel from a data transmitting end.

[0011] In one possible implementation, the RRNS channel decoder includes: an output module, an exclusion module and a comparison module corresponding to each RRNS channel encoder; the plurality of exclusion modules are used to perform multiple exclusion operations in parallel on the second n-ary remainder vector to obtain multiple second k-ary remainder vectors, wherein each exclusion operation selects nk remainder components from the second n-ary remainder vector for exclusion, and the multiple exclusion operations can support any remainder component in the second n-ary remainder vector. Each remainder component has undergone an exclusion operation once; the multiple RRNS encoders are used to encode the multiple second k-ary remainder vectors in parallel to obtain multiple fourth n-ary remainder vectors; the multiple comparison modules are used to compare the number of differences between the remainder components of the multiple fourth n-ary remainder vectors and the second n-ary remainder vectors; the output module is used to determine the fourth n-ary remainder vectors whose number of differences between the remainder components of the second n-ary remainder vectors and the remainder vectors is less than nk as the third n-ary remainder vectors and output them.

[0012] In one possible implementation, n=26, k=24, and the number of each of the plurality of RRNS channel encoders, the plurality of exclusion modules, and the plurality of comparison modules is 2; two exclusion modules are used to utilize at least In each time segment, multiple elimination operations are performed in parallel on the second n-ary remainder vector to obtain... The system comprises 13 second k-ary remainder vectors, wherein each exclusion module performs an exclusion operation once within each time segment, and each exclusion operation selects 2 remainder components from the second n-ary remainder vector for exclusion; two RRNS channel encoders are used to encode the 13 second k-ary remainder vectors in parallel using at least 7 time segments to obtain 13 fourth n-ary remainder vectors, wherein each RRNS channel encoder encodes one second k-ary remainder vector within each time segment; and two comparison modules are used to compare the number of differences in remainder components between the 13 fourth n-ary remainder vectors obtained by each RRNS channel encoder and the second n-ary remainder vector.

[0013] According to one aspect of this disclosure, an RRNS channel coding method is provided, the method being applied to an RRNS channel encoder, wherein the RRNS channel encoder corresponds to a modulus set consisting of n pairwise coprime numbers, the modulus set including k information moduloes and nk redundant moduloes, where k is a positive integer greater than or equal to 2 and n is a positive integer greater than or equal to 4; the RRNS channel encoder includes: an input module, a modulus operation module for levels 1 to k, and an output module; the method includes: receiving a first k-ary remainder vector using the input module, wherein the first k-ary remainder vector contains... It includes k information remainder components; based on the k information remainder components and the k information modulo, k weights are determined using the first to (k-1)th level modulo operation modules; based on the k information modulo, the k weights, and the nk redundant modulo, nk check remainder components are determined using the k-th level modulo operation module; according to the k information remainder components and the nk check remainder components, a first n-ary remainder vector is determined and sent to the target channel using the output module, wherein the target channel is used to transmit the first n-ary remainder vector from the data sending end to the data receiving end.

[0014] According to one aspect of this disclosure, an RRNS channel decoding method is provided. The method is applied to an RRNS channel decoder, which includes: an input module and a plurality of RRNS channel encoders, wherein the RRNS channel encoders are the aforementioned RRNS channel encoders. The method includes: at a data receiving end, using the input module to obtain a second n-ary remainder vector from a target channel; and using the plurality of RRNS channel encoders to decode the second n-ary remainder vector to obtain a third n-ary remainder vector, wherein the third n-ary remainder vector is the same as the first n-ary remainder vector received by the target channel from the data transmitting end.

[0015] According to one aspect of this disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to perform the method described above.

[0016] According to one aspect of this disclosure, a computer-readable storage medium is provided that stores computer program instructions thereon, which, when executed by a processor, implement the above-described method.

[0017] According to one aspect of this disclosure, a computer program product is provided, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program implements the above-described method when executed by a processor.

[0018] In this embodiment, the RRNS channel encoder corresponds to a modulus set consisting of n pairwise coprime numbers, including k information moduloes and nk redundant moduloes. The RRNS channel encoder includes: an input module, a first to k-th level modulus operation module, and an output module. The input module receives a first k-ary remainder vector, which includes k information remainder components. The first to k-1 level modulus operation modules determine k weights based on the k information remainder components and the k information moduloes. The k-th level modulus operation module determines nk check remainder components based on the k information moduloes, the k weights, and the nk redundant moduloes. The output module determines and sends a first n-ary remainder vector to the target channel based on the k information remainder components and the nk check remainder components. The target channel is used to transmit the first n-ary remainder vector from the data transmitter to the data receiver. By utilizing the k-level modulus operation module, the RRNS channel encoder can progressively determine the nk check remainder components based on the properties of modulus operation, without the need for large number multiplication and large number modulo operations, thereby effectively reducing the complexity of the digital circuit implementation of the RRNS channel encoder.

[0019] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0021] Figure 1 A block diagram of an RRNS channel encoder according to an embodiment of the present disclosure is shown.

[0022] Figure 2 A schematic diagram of a first modulo operation module according to an embodiment of the present disclosure is shown;

[0023] Figure 3 A schematic diagram of an RRNS channel encoder according to an embodiment of the present disclosure is shown.

[0024] Figure 4 A schematic diagram of a second modulo operation module according to an embodiment of the present disclosure is shown.

[0025] Figure 5 A block diagram of an RRNS channel decoder according to an embodiment of the present disclosure is shown.

[0026] Figure 6 A schematic diagram of an RRNS channel decoder according to an embodiment of the present disclosure is shown.

[0027] Figure 7 A schematic diagram of an RRNS channel decoder according to an embodiment of the present disclosure is shown.

[0028] Figure 8 A flowchart of an RRNS channel coding method according to an embodiment of the present disclosure is shown;

[0029] Figure 9 A flowchart of an RRNS channel decoding method according to an embodiment of the present disclosure is shown;

[0030] Figure 10 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0031] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0032] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0033] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0034] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0035] To address the high reliability and low latency requirements of physical layer encoding and decoding in high-performance computing chip interconnect scenarios, this disclosure provides an RRNS channel encoder / decoder. At the data transmitting end, FEC encoding is performed based on the RRNS channel encoder, and at the data receiving end, the RRNS channel decoder detects and automatically corrects bit errors occurring during channel transmission. Here, the data transmitting end and data receiving end can be two interconnected chips, with data transmission between the interconnected chips based on the channel. The channel encoder / decoder provided in this disclosure is described in detail below.

[0036] The Residue Number System (RNS) can be viewed as both a representation of numbers and an encoding. An RNS consists of a set of pairwise coprime moduli: m1 <m2<m3<…<m k Definition: If an integer 0 ≤ X <M, Then the integer X can be represented by the remainder vector (x1, x2, ..., xn) determined based on RNS. k ) represents X with respect to modulus m. i The remainder can be expressed as: , i = 1, 2, ..., k.

[0037] Correspondingly, the Chinese Remainder Theory (CRT) formula shown in formula (1) can also be used, based on the remainder vector (x1, x2, ..., x...). k Reconstruct the integer X:

[0038] (1).

[0039] in, , For M i Regarding module m i The reverse of the model.

[0040] Based on the RNS system, add r=nk redundant modules m k+1 , ..., m n A Redundant Remainder System (RRNS) is constructed, where an integer X is increased by the corresponding remainder x. k+1 , ..., x n That is, an integer X can be determined by the remainder vector (x1, x2, ..., x) of RRNS. k x k+1 , ..., x n This means that, at this point, the n-ary remainder vector obtained by encoding the k-ary remainder vector through RRNS becomes a type of FEC encoding, which has the ability to correct... The ability of the remainder component to produce errors. Therefore, RRNS-FEC is also a systematic code, with the information remainder component first and the added check remainder component second.

[0041] In related technologies, RRNS corresponds to the set of modulo (m1, m2, ..., m) k m k+1 , ..., m n ), where (m1, m2, ..., m k ) is the information module, (m) k+1 , ..., m n When the modulus is redundant, the process of obtaining an n-ary remainder vector by performing RRNS encoding on the k-ary remainder vector is as follows: Based on the input k-ary remainder vector (x1, x2, ..., x...), ... k ) and information modules (m1, m2, ..., m k X is reconstructed using the above formula (1), and then X is used to compare the redundant modulus (m). k+1 , ..., m n The remainder component (x) is obtained by taking the remainder. k+1 , ..., x n Finally, we obtain an n-ary remainder vector (x1, x2, ..., x...). k x k+1 , ..., x n This completes the RRNS encoding. However, when the selected modulus m... i When the value of X is large and the number of X is large, reconstructing X using the above formula (1) will involve multiplying large numbers and taking the remainder of large numbers, which is very inconvenient for the implementation of digital circuits.

[0042] Formula (1) above can be expressed using the base-extension (BEX) method shown in Formula (2) below:

[0043] (2).

[0044] in,

[0045] (3).

[0046] According to the above formulas (2) and (3), it can be seen that for an integer X, the remainder x is the basis for... i and based on weight a i The two expressions can be derived from each other. To simplify the expression, the above formula (3) can be derived from the remainder x. i Obtain weight a i The process is called r2a, which is the weight a shown in the above formula (2). i Obtain the remainder x i The process is called a2r.

[0047] In this embodiment of the disclosure, an RRNS channel encoder that is easy to implement with digital circuits is designed using the r2a and a2r processes.

[0048] Figure 1 A block diagram of an RRNS channel encoder according to an embodiment of the present disclosure is shown. The RRNS channel encoder corresponds to a modulus set consisting of n pairwise coprime numbers, the modulus set including k information modulus and nk redundant modulus, where k is a positive integer greater than or equal to 2 and n is a positive integer greater than or equal to 4.

[0049] like Figure 1 As shown, the RRNS channel encoder includes: an input module, a first to k-th level modulus operation module, and an output module; the input module is used to receive a first k-ary remainder vector, wherein the first k-ary remainder vector includes k information remainder components; the first to k-1 level modulus operation modules are used to determine k weights based on the k information remainder components and the k information modulo; the k-th level modulus operation module is used to determine nk check remainder components based on the k information modulo, the k weights, and nk redundancy modulo; the output module is used to determine and send a first n-ary remainder vector to the target channel according to the k information remainder components and the nk check remainder components, wherein the target channel is used to transmit the first n-ary remainder vector from the data transmitter to the data receiver.

[0050] The input module receives the first k-ary remainder vector (x1, x2, ..., x...). k ).

[0051] The modular arithmetic modules at levels 1 to k-1 are based on k information remainder components (x1, x2, ..., xk). k ), and the k information modules (m1, m2, ..., m) corresponding to the RRNS channel encoder. k By performing the above r2a operation, k weights (a1, a2, ..., a) are determined. k ).

[0052] The k-th level modular arithmetic module is based on k information modules (m1, m2, ..., m...). k k weights (a1, a2, ..., a) k ), and nk redundant modules (m k+1 , ..., m n By performing the above a2r operation, nk check remainder components (x) are determined. k+1 , ..., x n ).

[0053] The output module, based on the remainder components (x1, x2, ..., xk) of the k pieces of information... k ) and nk check remainder components (xk+1 , ..., x n ), determine and send the first n-ary remainder vector (x1, x2, ..., x) to the target channel k x k+1 , ..., x n ( ), so as to transmit the first n-ary remainder vector from the data sender to the data receiver through the target channel.

[0054] In this embodiment of the disclosure, the RRNS channel encoder utilizes a k-level modulo operation module, which can gradually determine nk check remainder components based on the properties of modulo operation, without the need for large number multiplication and large number remainder operations, thereby effectively reducing the complexity of the digital circuit implementation of the RRNS channel encoder.

[0055] The RRNS channel encoder determines nk check remainder components (x k+1 , ..., x n In the above process, it is not necessary to actually calculate X as shown in the above formula (2), but to repeatedly use the modular operation property shown in the following formula (4), so as to effectively avoid the problem of multiplying large numbers and taking the remainder of large numbers.

[0056] (4).

[0057] In one possible implementation, the k information modules are m1 to m... k The k information remainder components include x1 to x k The k weights include a1 to a k Where a1 = x1; the i-th level modular arithmetic module includes ki first modular arithmetic modules, each of which is used to perform operations. Where i is a positive integer greater than or equal to 1 and less than or equal to k-1; for the j-th first modular arithmetic module included in the i=1-th level modular arithmetic module, the input x corresponding to the first modular arithmetic module is x j+1 Input 'a' as a1, input m -1 for Input m is m j+1 Where j is a positive integer greater than or equal to 1 and less than or equal to ki; for the j-th first modular arithmetic module included in the i>1 level modular arithmetic module, the input x corresponding to the first modular arithmetic module is the output of the (j+1)-th first modular arithmetic module included in the (i-1)-th level modular arithmetic module, and the input a is a i Enter m -1 for Input m is m j+1 .

[0058] Figure 2 A schematic diagram of a first modulo operation module according to an embodiment of the present disclosure is shown. Figure 2 As shown, the first modular arithmetic module performs the operation. By cascading multiple first-level modular arithmetic modules, a k-1 level modular arithmetic module can be obtained. This k-1 level modular arithmetic module, based on the cascaded first-level modular arithmetic modules, can effectively perform the aforementioned r2a operation and determine k weights.

[0059] Figure 3 A schematic diagram of an RRNS channel encoder according to an embodiment of the present disclosure is shown. Figure 3 A schematic diagram of the RRNS channel encoder is shown when k=4. (For example...) Figure 3 As shown, the RRNS channel encoder includes multiple first-mode operation modules connected in series at levels k-1=3. The i=1 level modulus operation module includes ki=3 first-mode operation modules, the i=2 level modulus operation module includes ki=2 first-mode operation modules, and the i=3 level modulus operation module includes ki=1 first-mode operation module.

[0060] For the j=1th first modular arithmetic module included in the i=1th level modular arithmetic module, the input x corresponding to the first first modular arithmetic module of the first level is x. j+1 =x2, input a as a1, input m -1 for = Input m is m j+1 =m2; For the j=2nd first modular arithmetic module included in the i=1st level modular arithmetic module, the input x corresponding to the second first modular arithmetic module of the first level is x. j+1 =x3, input a as a1, input m -1 for Input m is m j+1 =m3; For the j=3rd first modular arithmetic module included in the i=1st level modular arithmetic module, the input x corresponding to the 3rd first modular arithmetic module of the 1st level is x. j+1 =x4, input a as a1, input m -1 for Input m is m j+1 =m4.

[0061] For the j=1th first modular arithmetic module included in the i=2nd level modular arithmetic module, the input x corresponding to the first first modular arithmetic module of the second level is the output of the j+1=2nd first modular arithmetic module of the (i-1)th level, and the input a is a i =a2, input m -1 for Input m is m j+1=m3; For the j=2nd first modular arithmetic module included in the i=2nd level modular arithmetic module, the input x corresponding to the 2nd first modular arithmetic module of the 2nd level is the output of the j+1=3rd first modular arithmetic module of the i-1=1st level, and the input a is a i =a2, input m -1 for Input m is m j+1 =m4.

[0062] For the j=1th first modular arithmetic module included in the i=3rd level modular arithmetic module, the input x corresponding to the 1st first modular arithmetic module of the 3rd level is the output of the j+1=2nd first modular arithmetic module of the (i-1)th level, and the input a is a i =a3, input m -1 for Input m is m j+1 =m4.

[0063] like Figure 3 As shown, the k-1=3 level modulus operation module, which is connected in series with multiple first modulus operation modules, can effectively perform the above r2a operation based on k=4 information remainder components (x1, x2, x3, x4) and k=4 information moduli (m1, m2, m3, m4) corresponding to the RRNS channel encoder, and determine k=4 weights (a1, a2, a3, a4).

[0064] Figure 3 This diagram only shows the RRNS channel encoder when k=4. The structure of the RRNS channel encoder changes as the value of k changes, and is not affected by external factors. Figure 3 limited.

[0065] In one possible implementation, the nk redundant modules include m k+1 to m n The k-th level modular arithmetic module includes k-1 second modular arithmetic modules; the i-th second modular arithmetic module included in the k-th level modular arithmetic module is used to perform the operation. When i=1, When i>1, For any redundant module m z The redundant module m z When used as input m to each of the second modular arithmetic modules included in the k-th level modular arithmetic module, the redundant modulus m is obtained based on the k-th level modular arithmetic module. z The corresponding check remainder component, where z is a positive integer greater than or equal to k+1 and less than or equal to n.

[0066] Figure 4 A schematic diagram of a second modulo operation module according to an embodiment of the present disclosure is shown. Figure 4As shown, the i-th second modular arithmetic module included in the k-th level modular arithmetic module performs the operation. Based on the k-1 second modular arithmetic modules included in the k-th level modular arithmetic module, the above a2r operation can be effectively performed to determine nk check remainder components.

[0067] Based on the above Figure 3 For example, when k=4, the RRNS channel encoder includes a k=4th level modulus operation module, and the k=4th level modulus operation module includes k-1=3 second modulus operation modules.

[0068] Figure 3 This illustrates the determination of redundancy mode m based on the RRNS channel encoder. z A schematic diagram of the check remainder component x5 corresponding to =m5. (See diagram below.) Figure 3 As shown, the i=1th second modular arithmetic module included in the k=4th level modular arithmetic module performs the operation. ,in, The second modular arithmetic module, which is included in the k=4th level modular arithmetic module, performs the operation. ,in, The i=3rd second modular arithmetic module, which is included in the k=4th level modular arithmetic module, performs the operation. ,in, .

[0069] like Figure 3 As shown, after passing through the k-1=3 second-modulus operation modules included in the k=4th level modulus operation module, the above r2a operation can be effectively performed based on the k=4 information moduloes (m1, m2, m3, m4), k=4 weights (a1, a2, a3, a4), and the redundancy modulo m5 corresponding to the RRNS channel encoder, to determine the check remainder component x5 corresponding to the redundancy modulo m5. The process of determining the check remainder components corresponding to other redundancy moduloes is similar to the above process. For example, when the input m in each second-modulus operation module is the redundancy modulo m6, the check remainder component x6 corresponding to the redundancy modulo m6 can be determined, and so on, without further details.

[0070] In one possible implementation, the RRNS channel encoder also includes k dff latches; wherein, a dff latch is inserted after each stage of modulo operation module.

[0071] Considering timing convergence issues, to avoid timing problems caused by excessively long logic paths in the k-level modular arithmetic modules, a DFF latch is inserted after each level of modular arithmetic module to latch the calculation results of that level of modular arithmetic module and output the calculation results in the next clock cycle, so as to ensure stable data transmission under clock synchronization.

[0072] Based on the above Figure 3 For example, in the RRNS channel encoder, there are k=4 levels of modulus operation modules. A dff latch needs to be inserted after each level of modulus operation module, for a total of k=4 dff latches.

[0073] In one possible implementation, after determining the nk check remainder components based on the first to kth level modulo operation modules, a delay of k clock cycles is introduced.

[0074] Since a DFF latch is inserted after each modular arithmetic module, and this DFF latch latches the calculation result of that module and outputs it in the next clock cycle, each DFF latch introduces a one-clock-cycle delay. After determining nk check remainder components based on k-level modular arithmetic modules, a k-clock-cycle delay is introduced.

[0075] With n=26 and k=24, the RRNS(26,24) channel encoder includes k=24 levels of modulo operation modules and k=24 dff latches. Based on the k=24 level modulo operation modules, nk=2 check remainder components (m... 25 m 26 After that, a delay of k=24 clock cycles is introduced.

[0076] In one possible implementation, for the operation OR operation ,exist or It is a 16-bit binary number. In the case of an 8-bit binary number, Where P[15:12] is the 12th to 15th bits of P, P[11:8] is the 8th to 11th bits of P, and P[7:0] is the 0th to 7th bits of P; for any first or second modular arithmetic module, the first preset modular arithmetic table is used to obtain... The modulo operation result is obtained based on the second preset modulo operation table. The modulo operation result, wherein the first preset modulo operation table includes For any information module or redundant module, the result of the module operation is included in the second preset module operation table. The result of the modulo operation on any information modulus or redundancy modulus, where A represents 16 4-bit binary numbers from 0000 to 1111.

[0077] Perform calculations on the first modular arithmetic module mentioned above. And / or the second modular arithmetic module performs the operation. In order to simplify the calculation complexity, a first preset modular operation table and a second preset modular operation table can be set in advance, and the modular operation result can be directly determined by looking up the table.

[0078] Assumption or It is a 16-bit binary number. In the case of an 8-bit binary number, according to the modulo operation property shown in formula (4) above, Therefore, a first preset modular operation table and a second preset modular operation table can be pre-set. The first preset modular operation table includes... For any information module or redundant module, the result of the module operation is included in the second preset module operation table. The result of the modulo operation on any information modulus or redundancy modulus, where A represents 16 4-bit binary numbers from 0000 to 1111.

[0079] With n=26 and k=24, this embodiment selects 26 pairwise coprime numbers between 137 and 255 as the modulus set corresponding to the RRNS (26, 24) channel encoder. Table 1 shows the modulus set corresponding to the RRNS channel (26, 24) encoder.

[0080]

[0081] As shown in Table 1, the first 24 numbers, from smallest to largest, represent 24 information modules m1 to m... 24 The remaining two numbers are two redundant modulo m. 25 and m 26 .

[0082] Based on the modulus set corresponding to the RRNS (26, 24) channel encoder shown in Table 1 above, the first preset modulus operation table shown in Table 2 and the second preset modulus operation table shown in Table 3 can be predetermined.

[0083]

[0084] Table 2

[0085] As shown in Table 2, when P[15:12]=0011, The result of the modulo operation is 95 when looking up Table 2; when P[15:12]=0111, The result of the modulo operation is 128, as obtained from Table 2; and so on, without further explanation.

[0086]

[0087] Table 3

[0088] As shown in Table 3, when P[11:8]=1010, The result of the modulo operation is 54 when looking up Table 3; when P[11:8]=1100, The result of the modulo operation is 36, as obtained from Table 3; and so on, without further explanation.

[0089] In this embodiment, the RRNS channel encoder corresponds to a modulus set consisting of n pairwise coprime numbers, including k information moduloes and nk redundant moduloes. The RRNS channel encoder includes: an input module, a first to k-th level modulus operation module, and an output module. The input module receives a first k-ary remainder vector, which includes k information remainder components. The first to k-1 level modulus operation modules determine k weights based on the k information remainder components and the k information moduloes. The k-th level modulus operation module determines nk check remainder components based on the k information moduloes, the k weights, and the nk redundant moduloes. The output module determines and sends a first n-ary remainder vector to the target channel based on the k information remainder components and the nk check remainder components. The target channel is used to transmit the first n-ary remainder vector from the data transmitter to the data receiver. By utilizing the k-level modulus operation module, the RRNS channel encoder can progressively determine the nk check remainder components based on the properties of modulus operation, without the need for large number multiplication and large number modulo operations, thereby effectively reducing the complexity of the digital circuit implementation of the RRNS channel encoder.

[0090] After receiving the second n-ary remainder vector from the target channel, the data receiver decodes the second n-ary remainder vector to detect and correct any errors that may occur in the second n-ary remainder vector during transmission to the target channel, thus obtaining a third n-ary remainder vector that is identical to the first n-ary remainder vector before transmission.

[0091] In related technologies, it is assumed that the received second n-ary remainder vector (y1, y2, ..., y...) k y k+1 , ..., y n ) and the actual first n-ary remainder vector (x1, x2, ..., x k x k+1 , ..., x n The relationship is (y1, y2, ..., y). k y k+1 , ..., y n ) = (x1, x2, ..., x k x k+1 , ..., x n ) + (e1, e2, ..., e k e k+1 , ..., e n When (e1, e2, ..., e k e k+1 , ..., en When only one element in () is non - zero, it can be determined that only one remainder component in the second n - ary remainder vector needs error correction; when (e1, e2, ……, e k , e k+1 , ……, e n ) has two non - zero elements, it can be determined that two remainder components in the second n - ary remainder vector need error correction; and so on.

[0092] The error - correcting ability of RRNS(n, k) is . For example, when n - k = 2, the maximum number of errors that can be corrected for one remainder component is 1; when n - k = 3, the maximum number of errors that can be corrected for one remainder component is 1; when n - k = 4, the maximum number of errors that can be corrected for two remainder components is 2; and so on.

[0093] In the scenario where n - k = 2, = 1, the error - correcting process in the related technology: According to the received second n - ary remainder vector (y1, y2, ……, y k , y<8000128>, ……, y n ), use the following formula (5) to reconstruct the integer Y:

[0094] (5).

[0095] Among them, . <<>

[0096] Assume that C is the set of moduli corresponding to the correct remainder components in the second n - ary remainder vector. In the case where there is only one incorrect remainder component in the second n - ary remainder vector, there are n possible cases for the set C. Perform the operation on each set C: , where Z C is the product of the elements in the set C. Among the n sets C, only the operation result of one set C satisfies X < M. The remainder component corresponding to the modulus in this set C is the correct remainder component, and the modulus corresponding to the remainder component y i is the incorrect remainder component, which can be corrected through .

[0097] 8]However, when the value of the selected modulus m i is relatively large and the number is relatively large, reconstructing Y through the above formula (5) will involve large - number multiplication and large - number modulo operation, which is very inconvenient for the implementation of digital circuits. In addition, when the number of incorrect remainder components in the second n - ary remainder components is relatively large, there are more possible ways for the set C, and the above error - correcting process takes a long time.

[0098] In this embodiment, an RRNS channel decoder that is easy to implement with digital circuits is designed. It can reuse the BEX algorithm shown in formulas (2) and (3) above. Figure 1 The RRNS channel encoder shown is used for decoding.

[0099] Figure 5 A block diagram of an RRNS channel decoder according to an embodiment of the present disclosure is shown. Figure 5 As shown, the RRNS channel decoder includes: an input module and multiple RRNS channel encoders, wherein the RRNS channel encoders are as described above. Figure 1 The diagram shows an RRNS channel encoder; an input module for obtaining a second n-ary remainder vector from the target channel at the data receiver; and multiple RRNS channel encoders for decoding the second n-ary remainder vector to obtain a third n-ary remainder vector, wherein the third n-ary remainder vector is the same as the first n-ary remainder vector received by the target channel from the data transmitter.

[0100] The input module obtains the second n-ary remainder vector (y1, y2, ..., y) from the target channel. n ).

[0101] Multiple RRNS channel encoders, for the second n-ary remainder vector (y1, y2, ..., y n Decode the vector to obtain the third n-ary remainder vector.

[0102] In this embodiment, the RRNS channel decoder reuses multiple RRNS channel encoders for decoding and error correction, increasing the reusability and scalability of the hardware circuit.

[0103] In one possible implementation, the RRNS channel decoder includes: an output module, an exclusion module corresponding to each RRNS channel encoder, and a comparison module; multiple exclusion modules are used to perform multiple exclusion operations in parallel on the second n-ary remainder vector to obtain multiple second k-ary remainder vectors, wherein each exclusion operation selects nk remainder components from the second n-ary remainder vector for exclusion, and the multiple exclusion operations can support any remainder component in the second n-ary remainder vector. Each remainder component has undergone an exclusion operation; multiple RRNS encoders are used to encode multiple second k-ary remainder vectors in parallel to obtain multiple fourth n-ary remainder vectors; multiple comparison modules are used to compare the number of differences between the remainder components of multiple fourth n-ary remainder vectors and second n-ary remainder vectors; an output module is used to identify and output the fourth n-ary remainder vectors whose number of differences between the remainder components of the second n-ary remainder vector and nk.

[0104] Since the error correction capability of RRNS(n,k) is Therefore, in the second n-ary remainder vector received by the RRNS(n,k) channel decoder from the target channel, there exists a remainder less than or equal to... In the case of a remainder component with a transmission error, the RRNS(n,k) channel decoder can correct the error by decoding the second n-ary remainder vector.

[0105] The elimination method is employed to remove erroneous remainder components from the second n-ary remainder vector. Since the second n-ary remainder vector contains nk redundant remainder components, the RRNS(n,k) channel decoder incorporates multiple elimination modules that perform multiple elimination operations in parallel on the second n-ary remainder vector. Each elimination module can select nk remainder components from the second n-ary remainder vector for elimination, and multiple elimination operations can support any nk remainder components in the second n-ary remainder vector. Each remainder component has undergone an exclusion operation once.

[0106] When nk=2, When nk = 1, multiple elimination operations are performed in parallel on the second n-ary remainder vector. Each elimination operation selects two remainder components from the second n-ary remainder vector for elimination, and multiple elimination operations ensure that any one remainder component in the second n-ary remainder vector has undergone an elimination operation at least once; when nk = 4, When the remainder is 2, multiple exclusion operations are performed in parallel on the second n-ary remainder vector. Each exclusion operation can select 4 remainder components in the second n-ary remainder vector for exclusion, and multiple exclusion operations can support the exclusion operation being performed once on any 2 remainder components in the second n-ary remainder vector; and so on.

[0107] Compared to decoding and error correction by excluding a single remainder component each time, the present invention excludes nk remainder components each time for decoding and error correction, which can effectively improve decoding and error correction efficiency.

[0108] The RRNS(n,k) channel decoder uses multiple RRNS(n,k) channel encoders. Multiple second k-ary remainder vectors are obtained by performing multiple exclusion operations in parallel by multiple exclusion modules. Each RRNS(n,k) channel encoder performs RRNS encoding on a second k-ary remainder vector to obtain the corresponding fourth n-ary remainder vector. Multiple comparison modules compare the number of differences in remainder components between the fourth n-ary remainder vector obtained from each RRNS(n,k) channel encoder and the second n-ary remainder vector. The output module identifies and outputs fourth n-ary remainder vectors whose remainder component differences are less than nk.

[0109] If there is no fourth n-ary remainder component whose number of differences with the remainder components of the second n-ary remainder vector is less than nk, then it can be determined that the number of erroneous remainder components in the second n-ary remainder vector exceeds [a certain threshold]. If the error is not within the error correction capability of RRNS(n,k), the output module will directly output the second n-ary remainder vector received from the target channel as the third n-ary remainder vector.

[0110] With n=26 and k=24, the second n-ary remainder vector is (y1, y2, ..., y 26 The error correction capability of RRNS(n,k) is Taking 1 as an example. Each exclusion operation excludes nk=2 remainder components from the second n-ary remainder vector. A total of 13 exclusion operations are required to ensure that every remainder component in the second n-ary remainder vector has undergone an exclusion operation. Therefore, the RRNS channel decoder includes: 13 exclusion modules, 13 RRNS channel encoders, and 13 comparison modules.

[0111] Figure 6 A schematic diagram of an RRNS channel decoder according to an embodiment of the present disclosure is shown. Figure 6 As shown, the RRNS channel decoder includes: an input module, 13 exclusion modules, 13 RRNS(n,k) channel encoders, 13 comparison modules, and an output module. Figure 6 As shown, the input module receives the second n-ary remainder vector (y1, y2, ..., y) from the target channel. 25 y 26 ).

[0112] like Figure 6 As shown, based on 13 exclusion modules, the second k-ary remainder vector (y3, y4, ..., y) is processed. 25 y 26 ) Perform 13 exclusion operations in parallel. For example Figure 6 As shown, after excluding the remainder components (y1, y2) by the exclusion module 1, the second k-ary remainder vector (y3, y4, ..., y2) is obtained. 25 y 26 After excluding the remainder components (y3, y4) by module 2, the second k-ary remainder vector (y1, y2, y5, y6, ..., y4) is obtained. 25 y 26 And so on, until module 12 excludes the remainder component (y). 23 y 24 After that, we obtain the second k-element remainder vector (y1, y2, ..., y). 21 y 22 y 25 y 26 ), Exclusion module 13 excludes the remainder component (y)25 y 26 After that, we obtain the second k-element remainder vector (y1, y2, ..., y). 23 y 24 ).

[0113] like Figure 6 As shown, based on 13 RRNS(n,k) channel encoders, the second k-ary remainder vector obtained after the exclusion operation of each exclusion module is RRNS encoded to obtain the corresponding 13 fourth n-ary remainder vectors. Figure 6 As shown, the RRNS(n,k) channel encoder 1 pairs the second k-ary remainder vector (y3, y4, ..., y... 25 y 26 ) Perform RRNS encoding to obtain the fourth n-ary remainder vector ;RRNS(n,k) channel encoder 2 for the second k-ary remainder vector (y1, y2, y5, y6, ..., y 25 y 26 ) Perform RRNS encoding to obtain the fourth n-ary remainder vector ; and so on, until the RRNS(n,k) channel encoder 12 pairs the second k-ary remainder vector (y1, y2, ..., y 21 y 22 y 25 y 26 ) Perform RRNS encoding to obtain the fourth n-ary remainder vector ;RRNS(n,k) channel encoder 13 pairs of the second k-ary remainder vector (y1, y2, ..., y 23 y 24 ) Perform RRNS encoding to obtain the fourth n-ary remainder vector .

[0114] like Figure 6 As shown, based on 13 comparison modules, the number of differences between the fourth n-ary remainder vector and the second n-ary remainder vector obtained by each RRNS(n,k) channel encoder is compared; the output module determines the fourth n-ary remainder vector with a remainder component difference of less than 2 as the third n-ary remainder vector and outputs it.

[0115] Alternatively, if there is no fourth n-ary remainder vector whose remainder components differ from the second n-ary remainder vector by less than 2, the output module determines the second n-ary remainder vector as the third n-ary remainder vector and outputs it.

[0116] Since the more RRNS(n,k) channel encoders are set, the larger the hardware circuit area will be, in order to balance decoding efficiency and hardware circuit area, a small number of RRNS(n,k) channel encoders can be set and multiplexed in different time segments to achieve decoding error correction.

[0117] In one possible implementation, n=26, k=24, and the number of multiple RRNS channel encoders, multiple exclusion modules, and multiple comparison modules are all 2; two exclusion modules are used to utilize at least In each time segment, multiple elimination operations are performed in parallel on the second n-ary remainder vector to obtain... There are 13 second k-ary remainder vectors, wherein each exclusion module performs an exclusion operation once within each time segment, and each exclusion operation selects 2 remainder components from the second n-ary remainder vector for exclusion; two RRNS channel encoders are used to encode the 13 second k-ary remainder vectors in parallel using at least 7 time segments to obtain 13 fourth n-ary remainder vectors, wherein each RRNS channel encoder encodes one second k-ary remainder vector within each time segment; and two comparison modules are used to compare the number of differences in remainder components between the 13 fourth n-ary remainder vectors obtained by each RRNS channel encoder and the second n-ary remainder vectors.

[0118] In practical applications, setting up two RRNS channel encoders can achieve balanced improvement in decoding and error correction efficiency, as well as reduce the hardware circuit area occupied.

[0119] Figure 7 A schematic diagram of an RRNS channel decoder according to an embodiment of the present disclosure is shown. Figure 7 As shown, the RRNS (n=26, k=24) channel decoder includes: an input module, two exclusion modules, two RRNS (n=26, k=24) channel encoders, two comparison modules, and an output module. The input module receives the second n-ary remainder vector (y1, y2, ..., y) from the target channel. 25 y 26 ).

[0120] like Figure 7 As shown, the two exclusion modules utilize seven time slices to perform 13 parallel exclusion operations on the second n-ary remainder vector, resulting in 13 second k-ary remainder vectors. Within each time slice, each exclusion module performs one exclusion operation, selecting two remainder components from the second n-ary remainder vector for exclusion in each operation. In the first time slice: Exclusion module 1 excludes remainder components (y1, y2) to obtain the second k-ary remainder vector (y3, y4, ..., y...). 25 y 26After excluding the remainder components (y3, y4) by module 2, the second k-ary remainder vector (y1, y2, y5, y6, ..., y4) is obtained. 25 y 26 In the second time segment: after module 1 excludes the remainder components (y5, y6), the second k-ary remainder vector (y1, ..., y4, y7, y8, ..., y6) is obtained. 25 y 26 After excluding the remainder components (y7, y8) by module 2, the second k-ary remainder vector (y1, ..., y6, y9, y1) is obtained. 10 , ..., y 25 y 26 ); and so on, until the 6th time segment, when module 1 excludes the remainder component (y). 21 y 22 After that, the second k-element remainder vector (y1, ..., y) is obtained. 20 y 23 y 24 y 25 y 26 ), Exclusion Module 2 excludes the remainder component (y) 23 y 24 After that, we obtain the second k-element remainder vector (y1, y2, ..., y). 21 y 22 y 25 y 26 ); In the 7th time segment, module 1 excludes the remainder component (y). 25 y 26 After that, we obtain the second k-element remainder vector (y1, y2, ..., y). 23 y 24 ), Exclusion module 2 does not perform exclusion operations.

[0121] like Figure 7 As shown, two RRNS(n,k) channel encoders utilize seven time slices to perform RRNS encoding on 13 second k-ary remainder vectors in parallel, resulting in 13 fourth n-ary remainder vectors. Within each time slice, each RRNS channel encoder encodes one second k-ary remainder vector. In the eighth time slice: RRNS(n,k) channel encoder 1 encodes the second k-ary remainder vectors (y3, y4, ..., y...). 25 y 26 ) Perform RRNS encoding to obtain the fourth n-ary remainder vector RRNS(n,k) channel encoder 2 for the second k-ary remainder vector (y1, y2, y5, y6, ..., y 25 y 26 ) Perform RRNS encoding to obtain the fourth n-ary remainder vector In the 9th time segment, the RRNS(n,k) channel encoder 1 pairs the second k-ary remainder vector (y1, ..., y4, y7, y8, ..., y...). 25 y 26 ) Perform RRNS encoding to obtain the fourth n-ary remainder vector RRNS(n,k) channel encoder 2 pairs of the second k-ary remainder vector (y1, ..., y6, y9, y 10 , ..., y 25 y 26 ) Perform RRNS encoding to obtain the fourth n-ary remainder vector ; and so on, until the 13th time segment, the RRNS(n,k) channel encoder 1 pairs the second k-ary remainder vector (y1, ..., y 20 y 23 y 24 y 25 y 26 ) Perform RRNS encoding to obtain the fourth n-ary remainder vector RRNS(n,k) channel encoder 2 for the second k-ary remainder vector (y1, y2, ..., y 21 y 22 y 25 y 26 ) Perform RRNS encoding to obtain the fourth n-ary remainder vector During the 14th time segment, the RRNS(n,k) channel encoder 1 pairs the second k-ary remainder vector (y1, y2, ..., y...). 23 y 24 ) Perform RRNS encoding to obtain the fourth n-ary remainder vector RRNS(n,k) channel encoder 2 does not perform RRNS coding.

[0122] like Figure 7 As shown, the two comparison modules compare the number of differences in the remainder components between the 13 fourth n-ary remainder vectors obtained from each RRNS channel encoder and the second n-ary remainder vector. Comparison module 1 compares the number of differences in the remainder components between the 7 fourth n-ary remainder vectors obtained from RRNS channel encoder 1 and the second n-ary remainder vector; comparison module 2 compares the number of differences in the remainder components between the 6 fourth n-ary remainder vectors obtained from RRNS channel encoder 2 and the second n-ary remainder vector. Figure 7 As shown, the output module determines the fourth n-ary remainder vector with a remainder component difference of less than 2 as the third n-ary remainder vector and outputs it.

[0123] Alternatively, if there is no fourth n-ary remainder vector whose remainder components differ from the second n-ary remainder vector by less than 2, the output module determines the second n-ary remainder vector as the third n-ary remainder vector and outputs it.

[0124] In one example, assume that receiving a data packet (the second n-ary remainder vector) takes 8 clock cycles, meaning that a complete set of valid data is generated and enters the RRNS channel decoder only every 8 clock cycles. Utilizing Figure 7 The RRNS(26,24) channel decoder shown uses two parallel logic paths for decoding and error correction, introducing a 32-clock-cycle delay. Therefore, the RRNS(26,24) channel decoder introduces a total of 40 clock-cycle delays.

[0125] As can be seen from the 24 clock cycle delay introduced by the RRNS(26,24) channel encoder described above, the RRNS(26,24) channel encoding and decoding scheme of this disclosure embodiment only requires a delay of 60 clock cycles. Compared with the multi-level FEC encoding in the prior art that consumes more than 100 clock cycles, the embodiment of this disclosure can reduce the delay and is effectively applicable to some high performance computing (HPC) communication scenarios that are sensitive to delay.

[0126] Figure 8 A flowchart illustrating an RRNS channel coding method according to an embodiment of this disclosure is shown. The method is applied to... Figure 1 The RRNS channel encoder shown corresponds to a modulus set consisting of n pairwise coprime numbers. This modulus set includes k information modulo numbers and nk redundant modulo numbers, where k is a positive integer greater than or equal to 2 and n is a positive integer greater than or equal to 4. The RRNS channel encoder includes: an input module, modulus operation modules for levels 1 to k, and an output module. Figure 8 As shown, the method includes:

[0127] In step S81, the first k-ary remainder vector is received using the input module, wherein the first k-ary remainder vector includes k information remainder components;

[0128] In step S82, based on the k information remainder components and the k information modulo, the k weights are determined using the first to k-1 level modulo operation modules;

[0129] In step S83, based on k information moduloes, k weights, and nk redundant moduloes, the k-th level modulo operation module is used to determine nk check remainder components;

[0130] In step S84, based on the k information remainder components and the nk check remainder components, the output module determines and sends the first n-ary remainder vector to the target channel, wherein the target channel is used to transmit the first n-ary remainder vector from the data sender to the data receiver.

[0131] In one possible implementation, Figure 8 The RRNS channel coding method shown can be executed by electronic devices such as terminal devices or servers. These electronic devices include... Figure 1 The RRNS channel encoder is shown. The terminal device can be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. The method can be implemented by a processor calling computer-readable instructions stored in memory. Alternatively, the method can be executed by a server.

[0132] Figure 8 For the specific implementation process of each method step in the RRNS channel coding method shown above, please refer to the aforementioned... Figure 1 The specific implementation process of each module in the RRNS channel encoder shown is not specifically limited in this disclosure.

[0133] Figure 9 A flowchart illustrating an RRNS channel decoding method according to an embodiment of this disclosure is shown. The method is applied to... Figure 5 The RRNS channel decoder shown includes: an input module and multiple RRNS channel encoders, wherein the RRNS channel encoders are... Figure 1 The RRNS channel encoder shown is an example. Figure 9 As shown, the method includes:

[0134] In step S91, at the data receiving end, the second n-ary remainder vector is obtained from the target channel using the input module;

[0135] In step S92, the second n-ary remainder vector is decoded using multiple RRNS channel encoders to obtain the third n-ary remainder vector, wherein the third n-ary remainder vector is the same as the first n-ary remainder vector received by the target channel from the data transmitter.

[0136] In one possible implementation, Figure 9 The RRNS channel decoding method shown can be executed by electronic devices such as terminal devices or servers. These electronic devices include... Figure 5The RRNS channel decoder is shown. The terminal device can be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. The method can be implemented by a processor calling computer-readable instructions stored in memory. Alternatively, the method can be executed by a server.

[0137] Figure 9 For the specific implementation process of each method step in the RRNS channel decoding method shown above, please refer to the aforementioned... Figure 5 The specific implementation process of each module in the RRNS channel decoder shown is not specifically limited in this disclosure.

[0138] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0139] In addition, this disclosure also provides electronic devices, computer-readable storage media, and programs, all of which can be used to implement any of the RRNS channel coding / decoding methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the corresponding section of the method and will not be repeated here.

[0140] This method is specifically technically related to the internal structure of computer systems and can solve technical problems of how to improve hardware computing efficiency or execution performance (including reducing data storage, reducing data transmission, and increasing hardware processing speed), thereby achieving technical effects that improve the internal performance of computer systems in accordance with natural laws.

[0141] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0142] This disclosure also proposes a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method. The computer-readable storage medium can be volatile or non-volatile.

[0143] This disclosure also proposes an electronic device, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to execute the above-described method.

[0144] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0145] Electronic devices can be provided as terminals, servers, or other forms of devices.

[0146] Figure 10 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. (Refer to...) Figure 10 The electronic device 1900 can be provided as a server or a terminal device. (See reference...) Figure 10 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0147] Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input / output interface 1958. Electronic device 1900 can operate on an operating system stored in memory 1932, such as a Microsoft Server operating system (Windows Server). TM Apple's graphical user interface-based operating system (Mac OS X) TM ), a multi-user, multi-process computer operating system (Unix) TM Linux is a free and open-source Unix-like operating system. TM ), an open-source Unix-like operating system (FreeBSD) TM (or similar.)

[0148] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of an electronic device 1900 to perform the above-described method.

[0149] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0150] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, (but not limited to) electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0151] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0152] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0153] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0154] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0155] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0156] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0157] The computer program product can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0158] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0159] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0160] If the technical solution of this application involves personal information, the product using this technical solution has clearly informed the user of the personal information processing rules and obtained the user's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using this technical solution has obtained the user's separate consent before processing the sensitive personal information, and also meets the requirement of "express consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set up to inform users that they have entered the scope of personal information collection and that personal information will be collected. If an individual voluntarily enters the collection scope, it is deemed that they have agreed to the collection of their personal information; or on the personal information processing device, with clear signs / information informing users of the personal information processing rules, authorization is obtained from the individual through pop-up information or by asking the individual to upload their personal information; wherein, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the types of personal information processed.

[0161] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A Redundancy Remainder System (RRNS) channel encoder, characterized in that, The RRNS channel encoder corresponds to a modulus set consisting of n pairwise coprime numbers. The modulus set includes k information moduloes and nk redundant moduloes, where k is a positive integer greater than or equal to 2 and n is a positive integer greater than or equal to 4. The RRNS channel encoder includes: an input module, modulus operation modules for levels 1 to k, and an output module. The input module is used to receive a first k-ary remainder vector, wherein the first k-ary remainder vector includes k information remainder components; The first to k-1 level modulo operation modules are used to determine k weights based on the k information remainder components and the k information modulo. The k-th level modular arithmetic module is used to determine nk check remainder components based on the k information modules, the k weights, and the nk redundant modules. The output module is used to determine and send a first n-ary remainder vector to a target channel based on the k information remainder components and the nk check remainder components, wherein the target channel is used to transmit the first n-ary remainder vector from the data sending end to the data receiving end.

2. The RRNS channel encoder according to claim 1, characterized in that, The k information modules are m1 to m k The k information remainder components include x1 to x k The k weights include a1 to a k Where a1 = x1; The i-th level modular arithmetic module includes ki first modular arithmetic modules, each of which is used to perform operations. , where i is a positive integer greater than or equal to 1 and less than or equal to k-1; For the j-th first modular arithmetic module included in the i=1-th level modular arithmetic module, the input x corresponding to this first modular arithmetic module is x. j+1 Input 'a' as a1, input m -1 for Input m is m j+1 , where j is a positive integer greater than or equal to 1 and less than or equal to ki; For the j-th first modular arithmetic module included in the i>1 level modular arithmetic module, the input x corresponding to this first modular arithmetic module is the output of the (j+1)-th first modular arithmetic module included in the (i-1)-th level modular arithmetic module, and the input a is a i Enter m -1 for Input m is m j+1 .

3. The RRNS channel encoder according to claim 2, characterized in that, The nk redundant modules include m k+1 to m n The k-th level modular arithmetic module includes k-1 second modular arithmetic modules. The i-th second modular arithmetic module included in the k-th level modular arithmetic module is used to perform calculations. ; When i=1, ; When i>1, ; For any redundant module m z The redundant module m z When used as input m to each of the second modular arithmetic modules included in the k-th level modular arithmetic module, the redundant modular arithmetic m is obtained based on the k-th level modular arithmetic module. z The corresponding check remainder component, where z is a positive integer greater than or equal to k+1 and less than or equal to n.

4. The RRNS channel encoder according to claim 2 or 3, characterized in that, For the operation OR operation ,exist or It is a 16-bit binary number. In the case of an 8-bit binary number, Where P[15:12] is the 12th to 15th bits of P, P[11:8] is the 8th to 11th bits of P, and P[7:0] is the 0th to 7th bits of P; For any first or second modular arithmetic module, obtain based on the first preset modular arithmetic table. The modulo operation result is obtained based on the second preset modulo operation table. The modulo operation result, wherein the first preset modulo operation table includes For the modulo operation result of any information modulus or redundant modulus, the second preset modulo operation table includes The result of the modulo operation on any information modulus or redundancy modulus, where A represents 16 4-bit binary numbers from 0000 to 1111.

5. The RRNS channel encoder according to claim 1, characterized in that, The RRNS channel encoder also includes k dff latches; wherein, one dff latch is inserted after each stage of the modulus operation module.

6. The RRNS channel encoder according to claim 5, characterized in that, Based on the first to kth level modular arithmetic modules, after determining the nk check remainder components, a delay of k clock cycles is introduced.

7. An RRNS channel decoder, characterized in that, The RRNS channel decoder includes: an input module and a plurality of RRNS channel encoders, wherein the RRNS channel encoder is the RRNS channel encoder according to any one of claims 1 to 4; The input module is used to obtain the second n-ary remainder vector from the target channel at the data receiving end; The plurality of RRNS channel encoders are used to decode the second n-ary remainder vector to obtain a third n-ary remainder vector, wherein the third n-ary remainder vector is the same as the first n-ary remainder vector received by the target channel from the data transmitter.

8. The RRNS channel decoder according to claim 7, characterized in that, The RRNS channel decoder includes: an output module, an exclusion module and a comparison module corresponding to each RRNS channel encoder; The multiple exclusion modules are used to perform multiple exclusion operations in parallel on the second n-ary remainder vector to obtain multiple second k-ary remainder vectors. Each exclusion operation selects nk remainder components from the second n-ary remainder vector for exclusion, and the multiple exclusion operations can support any... Each of the remainder components has undergone an exclusion operation once; The plurality of RRNS encoders are used to encode the plurality of second k-ary remainder vectors in parallel to obtain a plurality of fourth n-ary remainder vectors. The plurality of comparison modules are used to compare the number of differences in the remainder components between the plurality of fourth n-ary remainder vectors and the second n-ary remainder vector; The output module is used to determine the fourth n-ary remainder vector, which has a difference of less than nk between its remainder components and the second n-ary remainder vector, as the third n-ary remainder vector and output it.

9. The RRNS channel decoder according to claim 8, characterized in that, n=26, k=24, and the number of each of the plurality of RRNS channel encoders, the plurality of exclusion modules, and the plurality of comparison modules is 2; Two exclusion modules, used to utilize at least In each time segment, multiple elimination operations are performed in parallel on the second n-ary remainder vector to obtain... There are two second k-ary remainder vectors, where each exclusion module performs an exclusion operation once within each time segment, and each exclusion operation selects two remainder components from the second n-ary remainder vector for exclusion. Two RRNS channel encoders are used to encode the 13 second k-ary remainder vectors in parallel using at least 7 time segments to obtain 13 fourth n-ary remainder vectors, wherein each RRNS channel encoder encodes one second k-ary remainder vector within each time segment; Two comparison modules are used to compare the number of differences between the remainder components of the 13 fourth n-ary remainder vectors obtained by each RRNS channel encoder and the second n-ary remainder vector.

10. An RRNS channel coding method, characterized in that, The method is applied to an RRNS channel encoder, which corresponds to a modulus set consisting of n pairwise coprime numbers. The modulus set includes k information modulo numbers and nk redundant modulo numbers, where k is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 4. The RRNS channel encoder includes: an input module, modulus operation modules for levels 1 to k, and an output module. The method includes: The input module is used to receive a first k-ary remainder vector, wherein the first k-ary remainder vector includes k information remainder components; Based on the k information remainder components and the k information modulo, k weights are determined using the first to k-1 level modulo operation modules; Based on the k information modules, the k weights, and the nk redundant modules, the k-th level module is used to determine the nk check remainder components. Based on the k information remainder components and the nk check remainder components, the output module determines and sends a first n-ary remainder vector to the target channel, wherein the target channel is used to transmit the first n-ary remainder vector from the data sender to the data receiver.

11. A method for decoding an RRNS channel, characterized in that, The method is applied to an RRNS channel decoder, the RRNS channel decoder comprising: an input module and a plurality of RRNS channel encoders, wherein the RRNS channel encoder is the RRNS channel encoder according to any one of claims 1 to 4; the method comprises: At the data receiving end, the input module is used to obtain the second n-ary remainder vector from the target channel; The second n-ary remainder vector is decoded using the multiple RRNS channel encoders to obtain a third n-ary remainder vector, wherein the third n-ary remainder vector is the same as the first n-ary remainder vector received by the target channel from the data transmitter.

12. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the method of claim 10 or 11.

13. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method of claim 10 or 11.

14. A computer program product comprising a computer program, or a non-volatile computer-readable storage medium carrying a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of claim 10 or 11.

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