An eye diagram limit offset amount determination method and system

Abstract

The application relates to the technical field of communication signals, and relates to a method and system for determining an eye diagram limit offset, which comprises the following steps: performing data pull sampling in an analog circuit according to a current pull data code value to obtain current pull data; comparing the current normal data and the current pull data by using a serial-parallel conversion module to obtain waveform comparison data; performing ratio calculation on the total bit number and the error bit number according to the waveform comparison data to obtain a current error code rate; judging whether the current error code rate is greater than an error code rate threshold; if the current error code rate is not greater than the error code rate threshold, returning to perform pull data code value regulation; and if the current error code rate is greater than the error code rate threshold, obtaining a previous pull data code value of the current pull data code value and determining an eye diagram limit offset according to the previous pull data code value. The application can improve the identification efficiency of the eye diagram limit offset.

Description

Technical Field

[0001] This invention relates to the field of communication signal technology, and in particular to a method and system for determining the eye diagram limit offset. Background Technology

[0002] Eye diagrams are the most intuitive tool for evaluating digital signal quality. An "open" eye diagram implies greater noise margin and timing margin. The goal of signal eye diagram calibration is to precisely adjust the phase of its internal sampling clock and the voltage threshold of the decision circuit to the center of the open region of the eye diagram. Therefore, it is particularly important to quickly and accurately determine the boundaries of the eye diagram (i.e., the extreme offsets in the horizontal and vertical directions).

[0003] Modern high-speed transceivers (such as SerDes) generally integrate online eye diagram monitoring technology based on bit error rate scanning (BER Scan) within the chip. The basic principle is to introduce a "pairing" test path parallel to the main data path in the receive path. Through digital control codes, the sampling phase (horizontal pull) and decision threshold (vertical pull) of this path are actively and controllably changed. By statistically analyzing the bit error rate at different offset positions, a performance profile can be plotted under the current channel conditions, thereby locating the eye diagram boundary. However, existing eye diagram scanning methods only provide static "snapshot" information and fail to form an efficient closed loop with adaptive modules such as clock data recovery (CDR) loops, continuous-time linear equalizers (CTLE), or decision feedback equalizers (DFE). The calibration results cannot directly and optimally guide the coefficient updates of these modules. Therefore, current methods suffer from low recognition efficiency for eye diagram limit offsets. Summary of the Invention

[0004] This invention provides a method and system for determining the eye diagram limit offset, the main purpose of which is to improve the recognition efficiency of the eye diagram limit offset.

[0005] To achieve the above objectives, the present invention provides a method for determining the eye diagram limit offset, comprising:

[0006] The biased data code value is adjusted using a pre-built eye diagram scanning module to obtain the current biased data code value;

[0007] Based on the current biased data code value, data biasing sampling is performed in a pre-constructed analog circuit to obtain the current biased data;

[0008] Obtain the current normal data, and use a pre-built serial-to-parallel conversion module to compare the current normal data and the current bias data to obtain waveform comparison data;

[0009] The eye scan module is used to count the total number of bits of the current normal data and the number of error bits of the current pull-off data according to the waveform comparison data, and the total number of bits and the number of error bits are calculated by ratio to obtain the current bit error rate;

[0010] It is judged whether the current bit error rate is greater than a preset bit error rate threshold value;

[0011] If the current bit error rate is not greater than the bit error rate threshold value, the step of controlling the pull-off data code value by using the pre-constructed eye scan module is returned to.

[0012] If the current bit error rate is greater than the bit error rate threshold value, the previous pull-off data code value of the current pull-off data code value is obtained, and the eye limit offset is determined according to the previous pull-off data code value.

[0013] Optionally, the step of controlling the pull-off data code value by using the pre-constructed eye scan module to obtain the current pull-off data code value comprises:

[0014] The eye scan module is used to receive a pull-off control code value of the pull-off data input by a user, wherein the pull-off control code value is a horizontal control code value or a vertical control code value of the pull-off data.

[0015] When the pull-off control code value is a horizontal control code value, the current pull-off data code value is set according to the pull-off control code value and a preset standard vertical sampling code value, wherein the horizontal control code value is CDR Code.

[0016] When the pull-off control code value is a vertical control code value, the current pull-off data code value is set according to the pull-off control code value and a preset standard horizontal sampling code value, wherein the vertical control code value is DAC Code.

[0017] Optionally, before the current pull-off data code value is used to perform data pull-off sampling in the pre-constructed analog circuit, the method further comprises:

[0018] The high-frequency component of the preset received signal is linearly amplified by using an active amplification circuit in a pre-constructed continuous-time linear equalizer to obtain a time-domain waveform complete signal, wherein the continuous-time linear equalizer is CTLE.

[0019] The symbol linear distortion of the time-domain waveform complete signal is compensated by using a feedforward filter in a pre-constructed decision feedback equalizer, the symbol crosstalk amount is calculated by using a feedback filter in the decision feedback equalizer, and the time-domain waveform complete signal is crosstalk-eliminated according to the symbol crosstalk amount, wherein the decision feedback equalizer is DFE, the feedforward filter is FFF, and the feedback filter is FBF.

[0020] Optionally, the acquiring the current normal data comprises:

[0021] setting a preset Error_Det_EN signal to high level 1, and collecting the current normal data by using the standard vertical sampling code value and the standard horizontal sampling code value.

[0022] Optionally, the comparing the current normal data and the current pull-off data by using the pre-constructed serial-parallel conversion module to obtain waveform comparison data comprises:

[0023] setting a preset control signal EN to high level 1, and performing XOR comparison on the current normal data and the current pull-off data by using an XOR logic structure in the serial-parallel conversion module to obtain a detection output value, wherein the XOR logic structure is XOR.

[0024] constructing waveform comparison data according to the detection output value.

[0025] Optionally, the performing XOR comparison on the current normal data and the current pull-off data by using the XOR logic structure in the serial-parallel conversion module to obtain a detection output value comprises:

[0026] judging whether the current normal data and the current pull-off data are the same by using the XOR logic structure.

[0027] if the current normal data and the current pull-off data are the same, setting the detection output value to 0.

[0028] if the current normal data and the current pull-off data are not the same, setting the detection output value to 1.

[0029] Optionally, the using the eye diagram scanning module to count a total bit number of the current normal data and an error bit number of the current pull-off data according to the waveform comparison data comprises:

[0030] counting the total bit number of the current normal data and the error bit number of the current pull-off data by using a counter function in the eye diagram scanning module, wherein the total bit number is ALL_BIT_COUNT, the error bit number is ERROR_BIT_COUNT, and the eye diagram scanning module is built in a pre-constructed eye diagram calibration algorithm module.

[0031] Optionally, the determining an eye diagram limit offset according to a last pull-off data code value comprises:

[0032] when the last pull-off data code value is a horizontal control code value, determining an eye diagram horizontal limit offset according to the last pull-off data code value.

[0033] determining an eye diagram vertical limit offset according to the last pull data code value when the last pull data code value is a vertical control code value;

[0034] determining the eye diagram limit offset according to the eye diagram horizontal limit offset and the eye diagram vertical limit offset.

[0035] Optionally, the eye diagram calibration algorithm module, the pre-constructed CDR module and the DAC calibration module belong to preset digital circuits, and the continuous-time linear equalizer, the decision feedback equalizer, the pre-constructed DAC module, the clock generation module, the data recovery module and the serial-to-parallel conversion module belong to preset analog circuits.

[0036] The clock generation module performs data pull sampling according to a horizontal control code value, and the DAC module performs data pull sampling according to a vertical control code value.

[0037] To achieve the above-mentioned purpose, the present application further provides an eye diagram limit offset determination system, comprising:

[0038] A pull sampling module is configured to perform pull data code value control by using a pre-constructed eye diagram scanning module to obtain a current pull data code value, and perform data pull sampling in a pre-constructed analog circuit according to the current pull data code value to obtain current pull data.

[0039] A waveform data comparison module is configured to obtain current normal data, compare the current normal data and the current pull data by using a pre-constructed serial-to-parallel conversion module to obtain waveform comparison data.

[0040] A pull data code value cyclic control module is configured to use the eye diagram scanning module to count the total number of bits of the current normal data and the number of error bits of the current pull data according to the waveform comparison data, and perform ratio calculation on the total number of bits and the number of error bits to obtain a current bit error rate, and determine whether the current bit error rate is greater than a preset bit error rate threshold, and if the current bit error rate is not greater than the bit error rate threshold, return to the step of performing pull data code value control by using the pre-constructed eye diagram scanning module.

[0041] An eye diagram limit offset determination module is configured to obtain a last pull data code value of the current pull data code value if the current bit error rate is greater than the bit error rate threshold, and determine an eye diagram limit offset according to the last pull data code value.

[0042] To solve the above-mentioned problems, the present application further provides an electronic device, comprising:

[0043] A memory is configured to store at least one instruction, and a processor is configured to execute the instruction stored in the memory to implement the above-mentioned eye diagram limit offset determination method.

[0044] To solve the above problems, the application further provides a computer readable storage medium, wherein at least one instruction is stored in the computer readable storage medium, and the at least one instruction is executed by a processor in an electronic device to implement the eye diagram limit offset determination method.

[0045] To solve the problems in the background art, firstly, the waveform comparison data obtained by comparing the waveforms of the current normal data and the current pull-off data contains the total number of bits of the current normal data and the number of error bits of the current pull-off data, and the total number of bits of the current normal data and the number of error bits of the current pull-off data can be used to calculate the current bit error rate. Therefore, whether to continue the cycle judgment of the eye diagram limit offset can be determined by the waveform comparison data obtained by comparing the waveforms of the current normal data and the current pull-off data. Firstly, the pull-off data code value is obtained by using the eye diagram scanning module to control the pull-off data code value. At this time, the current pull-off data is obtained by sampling the data in the pre-constructed analog circuit according to the current pull-off data code value. When the current pull-off data is obtained, the current normal data can be directly obtained. Then, the current normal data and the current pull-off data are compared by using the pre-constructed serial-parallel conversion module to obtain the waveform comparison data. At this time, the total number of bits of the current normal data and the number of error bits of the current pull-off data are counted according to the waveform comparison data by using the eye diagram scanning module, and the total number of bits and the number of error bits are calculated by using the ratio to obtain the current bit error rate. When the current bit error rate is greater than the bit error rate threshold, it indicates that the current pull-off data code value has exceeded the pull-off data code value corresponding to the eye diagram limit offset. Therefore, it is necessary to determine whether the current bit error rate is greater than the preset bit error rate threshold. If the current bit error rate is not greater than the bit error rate threshold, the step of using the eye diagram scanning module to control the pull-off data code value is returned. If the current bit error rate is greater than the bit error rate threshold, the previous pull-off data code value of the current pull-off data code value is obtained, and the eye diagram limit offset is determined according to the previous pull-off data code value. Therefore, the recognition efficiency of the eye diagram limit offset can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 The flowchart of the eye diagram limit offset determination method provided by an embodiment of the application is shown in the figure.

[0047] Figure 2 The overall structure diagram of the analog circuit and the digital circuit provided by an embodiment of the application is shown in the figure.

[0048] Figure 3 The data detection circuit structure diagram of the serial-parallel conversion module provided by an embodiment of the application is shown in the figure.

[0049] Figure 4 The detection result diagram of the waveform comparison data provided by an embodiment of the application is shown in the figure.

[0050] Figure 5 A functional module diagram of an eye diagram limit offset determination system provided by an embodiment of the present application is shown in FIG. 1.

[0051] Figure 6 A structural schematic diagram of an electronic device implementing the eye diagram limit offset determination method provided by an embodiment of the present application is shown in FIG. 2.

[0052] Legend of reference signs:

[0053] 1. Electronic device; 10, processor; 11, memory; 12, bus.

[0054] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0055] It should be understood that the specific embodiments described herein are merely intended to explain the present application and not to limit the present application.

[0056] An eye diagram limit offset determination method is provided by an embodiment of the present application. The execution subject of the eye diagram limit offset determination method includes, but is not limited to, at least one of the electronic devices that can be configured to execute the method provided by the present application, such as a server and a terminal. In other words, the eye diagram limit offset determination method can be executed by software or hardware installed in a terminal device or a server device, and the software can be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0057] Referring to FIG. 1, a flowchart of an eye diagram limit offset determination method provided by an embodiment of the present application is shown. In the embodiment, the eye diagram limit offset determination method includes: Figure 1 S1, performing pull data code value control by using a pre-constructed eye diagram scanning module to obtain a current pull data code value.

[0058] As can be explained, refer to

[0059] Figure 2 ​As shown, the function of the Eye Diagram_scan module is to receive offset data output by an analog circuit (ANA), to determine the horizontal limit offset position and the vertical limit offset position of the eye diagram by calculating the error rate of the offset data, and to finally obtain the offset information of the eye diagram. After obtaining the offset information, the Eye Diagram_scan module outputs the offset information to a calibration module in the Eye Calibration Module for processing. The pull offset data code value control points to the control of the horizontal Code value (DAC_Code) and the vertical Code value (CDR_Code) of the pull offset data (i.e., O-channel data) by the Eye Diagram_scan module when sampling the pull offset data on the analog circuit side. Finally, the pull offset data output by the serial-parallel conversion module (SIPO) is the offset data, which is compared with normal data (D-channel data) in the serial-parallel conversion module. The current pull offset data code value refers to the horizontal Code value (DAC_Code) and the vertical Code value (CDR_Code) of the pull offset data (i.e., O-channel data) obtained after the current pull offset data code value control.

[0060] Further, the offset data refers to the data recovered by the data recovery module (Slicer) in the receiving end using a sampling clock or a decision voltage deviating from the optimal sampling point (eye diagram center point) to sample the input signal. Figure 2 The eye diagram refers to a core test graph in the communication field for intuitively and quantitatively evaluating signal transmission quality. Its formation mechanism is to perform time domain superposition on a plurality of cycles of digital signals collected by the receiving end (these signals exist random distortion due to factors such as additive noise, inter-symbol interference, clock offset, channel attenuation, etc. in the transmission process). Since the amplitude distribution of digital signals of different cycles at the same symbol time has statistical regularity, the final graph will present a profile similar to a human eye. This graph contains the opening degree of the "eye" (the greater the opening, the better the signal quality), the eye crossing point (the symmetry of the crossing point reflects the clock synchronization accuracy), the thickness of the eyelid (directly related to the noise amplitude), and the slope of the upper and lower edges of the eye diagram, and other key features. By observing and analyzing these key features, problems such as inter-symbol interference, noise pollution, and clock synchronization deviation in the transmission system can be quickly located, thereby guiding equalizer parameter adjustment, channel optimization, clock circuit calibration, and other work, and ultimately ensuring reliable transmission of digital signals.

[0061] As can be understood, the horizontal limit offset position refers to the position at which the receiver can correctly recover data (i.e., the error rate is lower than a certain standard, for example, the error rate ) can deviate from the optimal sampling point in the corresponding position of the eye diagram. The vertical limit offset position refers to the position that the receiver can correctly recover data (the bit error rate is lower than a certain standard, for example: the bit error rate ) can deviate from the optimal decision voltage in the corresponding position of the eye diagram. The offset information refers to a series of key parameter sets obtained in the process of eye diagram scanning in two dimensions of sampling time and decision voltage, which mainly includes boundary information of the eye diagram, for example: the horizontal maximum offset of the eye diagram, the vertical maximum offset of the eye diagram.

[0062] In detail, the bit error rate (BER) refers to the ratio of the number of error bits of the receiving end to the total number of transmission bits within a certain time. The higher the bit error rate, the higher the accuracy of transmission.

[0063] Further, referring to Figure 2 As shown in the figure, the eye calibration algorithm module, the pre-constructed CDR module, and the DAC calibration module belong to the preset digital circuit (DIG), and the continuous-time linear equalizer (CTLE), the decision feedback equalizer (DFE), the pre-constructed DAC module, the clock generation module (CLKGEN), the data recovery module (Slicer), and the serial-to-parallel conversion module (SIPO) belong to the preset analog circuit (ANA).

[0064] The clock generation module performs data pull sampling according to the horizontal control code value, and the DAC module performs data pull sampling according to the vertical control code value.

[0065] In detail, the horizontal control code value refers to the horizontal Code value of the pull data (O data) manually controlled by the eye diagram scan (Eye Diagram_scan) module, and the vertical control code value refers to the vertical Code value of the pull data (O data) manually controlled by the eye diagram scan (Eye Diagram_scan) module.

[0066] Further, referring to Figure 2As shown, the eye diagram limit offset determination method needs the cooperation of multiple functional modules in analog circuits and digital circuits. First, the received signal is scanned and analyzed by the Eye Diagram_scan module in the eye diagram calibration algorithm module, so as to obtain and generate corresponding eye diagram offset information. The offset information mainly includes the boundary information of the eye diagram, i.e. the maximum horizontal and vertical offset. This module can scan the received data under different sampling phases and threshold voltages, extract key parameters reflecting signal quality, and provide basis for subsequent equalization and threshold calibration.

[0067] In detail, CDR (Clock Data Recovery) is a core synchronization technology in high-speed serial communication systems. Its core principle is to extract a local clock from a serial data stream carrying clock information in a scene without an independent clock signal line, which is the same as the sending end clock in terms of origin and frequency, and the phase is accurately aligned. The clock is used to complete data sampling and recovery at the best sampling time of the data signal (such as the center area of the signal eye diagram to avoid inter-symbol interference and noise influence), so as to realize reliable data reception. DAC (Digital-to-Analog Converter) is a module that converts discrete digital signals into continuously changing analog signals (such as voltage or current). Its core principle is based on weighted synthesis: the input digital signal is composed of several binary numbers, each corresponding to a specific weight, which realizes the conversion of Code value to corresponding voltage value. CLKGEN (Clock Generator) is mainly used to generate accurate multi-phase clocks to sample the input signal; the core principle is to receive the Code output by CDR, and to realize the phase adjustment of the sampling clock through the continuously changing CDR Code, so as to realize center sampling. SIPO (Serial-In Parallel-Out) is a timing circuit that realizes the conversion of serial data to parallel data, which is composed of multiple flip-flops in series. The serial data is shifted into the register bit by bit under the control of the clock signal, and after a clock period equal to the number of data bits, all data bits are output from the parallel output terminal at the same time. The core is to complete the data format conversion through clock-synchronous shift operation.

[0068] Further, the equalization circuit includes a continuous-time linear equalizer (CTLE) and a decision feedback equalizer (DFE), which are core modules in the analog data path. In a high-speed serial data transmission system, the integrity of the signal is usually damaged after long-distance transmission or multiple signal reflections, attenuation, etc., especially the influence of inter-symbol interference (ISI) and other non-ideal factors. The DAC module is a core control module for controlling the vertical offset in the eye diagram calibration algorithm. It adjusts the sampling threshold of the signal accurately by receiving the DAC_Code generated by the digital circuit. This adjustment enables the DAC module to change the sampling position of the signal in the vertical direction in real time, thereby effectively calibrating the position of the eye diagram center. The clock generation module (CLKGEN) is a core control module for controlling the horizontal offset in the eye diagram calibration algorithm. It receives the CDR_Code generated by the digital circuit and adjusts the center sampling position of the clock in real time to calibrate the center position of the eye diagram. The data recovery module (Slicer) is one of the most critical modules in the eye diagram calibration algorithm. This module receives the threshold voltage and sampling clock signal generated by the DAC module and the clock generation module (CLKGEN), as well as the data signal processed by the equalization circuit. In this process, the Slicer uses the threshold voltage and sampling clock to determine the sampling time of the signal and the position of the eye diagram center. The serial-to-parallel conversion module (SIPO) is a custom circuit module that outputs parallel data after serial-to-parallel conversion. This module is an important module in the feedback system, and the parallel data is input to the eye diagram scan (Eye Diagram_scan) module for calculating the bit error rate and offset information.

[0069] Further, the eye diagram calibration algorithm module (Eye Calibration Module) includes a calibration module and an eye diagram scan module. The eye diagram scan module receives the offset data output by the analog circuit, calculates the horizontal and vertical limit offset positions based on the bit error rate of the offset data, obtains the offset information of the eye diagram, and outputs the information to the calibration module for processing. The calibration module converts the offset information into Trim Code (trim code) based on the mapping relationship between the offset information and the Code. The DAC calibration module (DAC Calibration Module) is mainly used to receive and process the Trim Code of the vertical offset. Through accurate processing of the Trim Code, the DAC calibration module can output real-time updated Trim Code, which will be transmitted to the DAC module of the analog circuit for dynamic adjustment of the sampling threshold. The CDR module is a horizontal offset control module in the eye diagram calibration algorithm, which is mainly used to receive the Trim Code generated by the horizontal offset. By changing the Code value of the control clock through the CDR module, the center position of the sampling clock is changed, and the eye diagram center calibration is realized.

[0070] In the embodiment of the present application, the pre-built eye scan module is used to perform pull-off data code value regulation to obtain the current pull-off data code value, which comprises:

[0071] The eye scan module is used to receive a user input pull-off data pull-off regulation code value, wherein the pull-off regulation code value is a horizontal regulation code value or a vertical regulation code value of the pull-off data;

[0072] When the pull-off regulation code value is the horizontal regulation code value, the current pull-off data code value is set according to the pull-off regulation code value and a preset standard vertical sampling code value, wherein the horizontal regulation code value is CDR_Code.

[0073] When the pull-off regulation code value is the vertical regulation code value, the current pull-off data code value is set according to the pull-off regulation code value and a preset standard horizontal sampling code value, wherein the vertical regulation code value is DAC_Code.

[0074] It can be understood that the pull-off regulation code value refers to the horizontal or vertical Code value of the pull-off data manually controlled by the user, the standard vertical sampling code value refers to the Code value corresponding to the best sampling time, and the standard horizontal sampling code value refers to the Code value corresponding to the best decision voltage. When the pull-off regulation code value is the horizontal regulation code value, the current pull-off data code value is composed of the pull-off regulation code value and the standard vertical sampling code value; when the pull-off regulation code value is the vertical regulation code value, the current pull-off data code value is composed of the pull-off regulation code value and the standard horizontal sampling code value.

[0075] S2, data pull-off sampling is performed in the pre-built analog circuit according to the current pull-off data code value to obtain the current pull-off data.

[0076] It can be understood that the current pull-off data refers to the offset data output by the serial-parallel conversion module after the signal data is sampled in the analog circuit according to the current pull-off data code value.

[0077] In the embodiment of the present application, before the data pull-off sampling is performed in the pre-built analog circuit according to the current pull-off data code value, the method further comprises:

[0078] A high-frequency component linear amplifier in a pre-built continuous-time linear equalizer is used to perform linear amplification on a preset received signal to obtain a time-domain waveform complete signal, wherein the continuous-time linear equalizer is CTLE.

[0079] The symbol linear distortion compensation is performed on the time-domain waveform integrity signal by using a feed-forward filter in a pre-constructed decision feedback equalizer, and the symbol crosstalk quantity is calculated by using a feedback filter in the decision feedback equalizer, and the crosstalk cancellation is performed on the time-domain waveform integrity signal according to the symbol crosstalk quantity, wherein the decision feedback equalizer is a DFE, the feed-forward filter is a FFF, and the feedback filter is a FBF.

[0080] It can be understood that the time-domain waveform integrity signal refers to a signal recovered in time-domain waveform integrity. The symbol crosstalk quantity refers to a crosstalk quantity caused by a previously correctly judged symbol to a current symbol.

[0081] Further, the continuous-time linear equalizer (CTLE) is a key circuit used for compensating signal transmission distortion at a high-speed serial communication receiving end, and the core principle thereof is to construct a linear filter characteristic complementary to a transmission channel frequency response, to perform targeted enhancement on high-frequency components attenuated in a received signal due to channel bandwidth limitation, so as to offset inter-symbol interference (ISI). Specifically, when a signal is transmitted in a high-frequency channel, high-frequency components are more significantly attenuated due to greater channel loss, resulting in waveform superposition of adjacent symbols. The CTLE realizes an amplitude-frequency characteristic of gain increment with frequency increase by means of an active amplification circuit, linearly amplifies high-frequency components of the received signal, while keeping low-frequency components relatively stable, so that the attenuation of each frequency component of the compensated signal tends to be balanced, thereby recovering the time-domain waveform integrity of the signal. The decision feedback equalizer (DFE) is an adaptive equalization technology used for eliminating inter-symbol interference (ISI) in a communication system, and the core principle thereof is to use previously judged pre-sequence symbol information to compensate for interference on a current symbol. The structure is usually composed of a feed-forward filter (FFF) and a feedback filter (FBF). The feed-forward filter performs preliminary processing on a received signal, to compensate for linear distortion of a channel on a current symbol, and the feedback filter calculates a crosstalk quantity caused by previously correctly judged symbols on a current symbol by using preset coefficients, and subtracts the crosstalk quantity from a signal after the feed-forward filtering, thereby eliminating interference of pre-sequence symbols on the current symbol.

[0082] S3, acquiring current normal data, comparing the current normal data and current pull data by using a pre-constructed serial-parallel conversion module, to obtain waveform comparison data.

[0083] The current normal data is normal data outputted by the serial-parallel conversion module after sampling the signal data in the analog circuit without code value regulation of the current unbalanced data. Figure 4 As shown in the figure, wherein D data represents normal data, O data represents unbalanced data, and Module Out represents waveform comparison data.

[0084] In the embodiment of the present application, the current normal data is obtained by:

[0085] The preset Error_Det_EN signal is set to high level 1, and the current normal data is collected by using the standard vertical sampling code value and the standard horizontal sampling code value.

[0086] As shown in the figure, Error_Det_EN is a control enable signal, which is effective at high level, and is used to start or stop the error code comparison logic in the receiver. Figure 3

[0087] In the embodiment of the present application, the waveform comparison data is obtained by comparing the current normal data and the current unbalanced data by using the pre-constructed serial-parallel conversion module, and the waveform comparison data is obtained by:

[0088] The preset control signal EN is set to high level 1, and the current normal data and the current unbalanced data are compared by using the XOR logic structure in the serial-parallel conversion module, and a detection output value is obtained, wherein the XOR logic structure is XOR.

[0089] The waveform comparison data is constructed according to the detection output value.

[0090] As shown in the figure, EN is a digital control signal, which is effective at high level, and is used to control whether the unbalanced data is injected into the main signal processing link. Figure 3

[0091] In the embodiment of the present application, the detection output value is obtained by comparing the current normal data and the current unbalanced data by using the XOR logic structure in the serial-parallel conversion module, and the detection output value is obtained by:

[0092] Whether the current normal data and the current unbalanced data are the same is judged by using the XOR logic structure.

[0093] If the current normal data and the current unbalanced data are the same, the detection output value is set to 0.

[0094] If the current normal data and the current unbalanced data are not the same, the detection output value is set to 1. ​​

[0095] Explainable, see [link / reference] Figure 3 The diagram shows the data detection circuit structure of the serial-to-parallel conversion module. The serial-to-parallel conversion module (SIPO) implements the data detection function through an internal XOR logic structure. The data stream after sampling and parallelization is sent to this module for error detection. When the control signal EN is set to high level 1, the detection function is activated. At this time, the serial-to-parallel conversion module performs an XOR comparison between the current biased data (O-channel data) and the current normal data (D-channel data). When the two data channels are the same, the detection result output is 0; when the two data channels are different, the detection result output is 1, thereby realizing the data consistency and bit error detection functions.

[0096] S4. Using the eye diagram scanning module, the total number of bits of the current normal data and the number of error bits of the current biased data are counted based on the waveform comparison data, and the ratio of the total number of bits and the number of error bits is calculated to obtain the current bit error rate.

[0097] Explained, the current bit error rate refers to the bit error rate of the currently biased data.

[0098] In this embodiment of the invention, the step of using the eye diagram scanning module to count the total number of bits of the current normal data and the number of error bits of the current biased data based on the waveform comparison data includes:

[0099] The counter function in the eye diagram scanning module is used to count the total number of bits in the current normal data and the number of error bits in the current biased data. The total number of bits is ALL_BIT_COUNT, and the number of error bits is ERROR_BIT_COUNT. The eye diagram scanning module is built into a pre-built eye diagram calibration algorithm module.

[0100] For details, please refer to Figure 4 As shown, Figure 4The detection result of the waveform contrast data is shown in the figure, wherein the detection result of the serial-parallel conversion module generates waveform data (O data) containing error information, which is fed back to the eye diagram calibration algorithm module for subsequent analysis, and meanwhile, the current normal data (D data) is also transmitted to the eye diagram calibration algorithm module, and the eye diagram scanning module (Eye Diagram_scan) in the eye diagram calibration algorithm module integrates the counter function, which is used for counting the total number of bits of the current normal data (D data) (i.e. ALL_BIT_COUNT) and the number of error bits "1" of the current pull-off data (O data) (i.e. ERROR_BIT_COUNT). Then, the eye diagram scanning module (Eye Diagram_scan) obtains the bit error rate (BER) under the current pull-off condition by calculating the ratio of ERROR_BIT_COUNT to ALL_BIT_COUNT, thereby providing a basis for accurate eye diagram calibration.

[0101] S5, determining whether the current bit error rate is greater than a preset bit error rate threshold.

[0102] It can be understood that the bit error rate threshold refers to a bit error rate preset to identify the performance boundary of the system, and the bit error rate threshold is the highest acceptable bit error rate. If the current bit error rate is greater than the bit error rate threshold, it is determined that the system performance does not meet the requirements.

[0103] If the current bit error rate is not greater than the bit error rate threshold, return to the step of controlling the code value of the pull-off data by using the pre-constructed eye diagram scanning module.

[0104] If the current bit error rate is greater than the bit error rate threshold, perform S6, obtain the previous pull-off data code value of the current pull-off data code value, and determine the eye diagram limit offset according to the previous pull-off data code value.

[0105] It can be understood that by gradually pulling off the current pull-off data (O data) and monitoring the bit error rate (BER) under each offset condition in real time, when the bit error rate of the O data under a certain pull-off condition exceeds the set threshold and no longer meets the system requirements, the previous pull-off code is the eye diagram boundary point, and the offset corresponding to the condition is determined as the limit offset.

[0106] In the embodiment of the application, the determination of the eye diagram limit offset according to the previous pull-off data code value comprises:

[0107] When the previous pull-off data code value is a horizontal control code value, the eye diagram horizontal limit offset is determined according to the previous pull-off data code value.

[0108] determining an eye diagram vertical limit offset according to the last pull data code value when the last pull data code value is a vertical control code value;

[0109] determining the eye diagram limit offset according to the eye diagram horizontal limit offset and the eye diagram vertical limit offset.

[0110] It can be understood that the eye diagram horizontal limit offset refers to the maximum time offset of the sampling clock phase relative to the optimal sampling point when the system bit error rate reaches the bit error rate threshold under the condition of maintaining the optimal decision level in the vertical direction. The eye diagram vertical limit offset refers to the maximum voltage offset of the decision voltage threshold relative to the optimal decision level when the system bit error rate reaches the bit error rate threshold under the condition of maintaining the optimal sampling time in the horizontal direction.

[0111] To solve the problems in the background art, first, the waveform comparison data obtained by comparing the waveforms of the current normal data and the current pull data contains the total number of bits of the current normal data and the number of error bits of the current pull data, and the total number of bits of the current normal data and the number of error bits of the current pull data can be used to calculate the current bit error rate. Therefore, whether to continue the cycle judgment of the eye diagram limit offset can be determined by the waveform comparison data obtained by comparing the waveforms of the current normal data and the current pull data. First, the pull data code value is obtained by using the eye diagram scanning module to control the pull data code value. At this time, the current pull data is obtained by performing data pull sampling in the pre-constructed analog circuit according to the current pull data code value. After obtaining the current pull data, the current normal data can be directly obtained. Then, the waveform comparison data is obtained by comparing the current normal data and the current pull data using the pre-constructed serial-parallel conversion module. At this time, the total number of bits of the current normal data and the number of error bits of the current pull data can be counted according to the waveform comparison data using the eye diagram scanning module. The total number of bits and the number of error bits are calculated by ratio to obtain the current bit error rate. When the current bit error rate is greater than the bit error rate threshold, it indicates that the current pull data code value has exceeded the pull data code value corresponding to the eye diagram limit offset. Therefore, it is necessary to determine whether the current bit error rate is greater than the preset bit error rate threshold. If the current bit error rate is not greater than the bit error rate threshold, the step of using the eye diagram scanning module to control the pull data code value is returned. If the current bit error rate is greater than the bit error rate threshold, the last pull data code value of the current pull data code value is obtained, and the eye diagram limit offset is determined according to the last pull data code value. Therefore, the recognition efficiency of the eye diagram limit offset can be improved.

[0112] As shown in FIG. 1, it is a functional module diagram of an eye diagram limit offset determination system provided by an embodiment of the present application. Figure 5

[0113] ​The eye diagram limit offset amount determination system 100 can be installed in an electronic device. According to the implemented function, the eye diagram limit offset amount determination system 100 can include a pull-off sampling module 101, a waveform data comparison module 102, a pull-off data code value cycle control module 103, and an eye diagram limit offset amount determination module 104. The modules in the present application can also be referred to as units, which refer to a series of computer program segments that can be executed by an electronic device processor and can complete a fixed function, which are stored in the memory of the electronic device.

[0114] The pull-off sampling module 101 is configured to perform pull-off data code value control using a pre-constructed eye diagram scanning module to obtain a current pull-off data code value; perform data pull-off sampling on the current pull-off data code value in a pre-constructed analog circuit to obtain current pull-off data.

[0115] The waveform data comparison module 102 is configured to obtain current normal data, compare the current normal data and the current pull-off data using a pre-constructed serial-parallel conversion module to obtain waveform comparison data.

[0116] The pull-off data code value cycle control module 103 is configured to use the eye diagram scanning module to count the total number of bits of the current normal data and the number of error bits of the current pull-off data according to the waveform comparison data, and perform ratio calculation on the total number of bits and the number of error bits to obtain a current bit error rate; determine whether the current bit error rate is greater than a preset bit error rate threshold; if the current bit error rate is not greater than the bit error rate threshold, return to the step of using the pre-constructed eye diagram scanning module to perform pull-off data code value control.

[0117] The eye diagram limit offset amount determination module 104 is configured to obtain a previous pull-off data code value of the current pull-off data code value if the current bit error rate is greater than the bit error rate threshold, and determine an eye diagram limit offset amount according to the previous pull-off data code value.

[0118] In detail, the modules in the eye diagram limit offset amount determination system 100 in the embodiment of the present application use the same technical means as the eye diagram limit offset amount determination method described in the above Figure 1 , and can produce the same technical effects, which will not be described here.

[0119] As Figure 6 shown is a structural schematic diagram of an electronic device for implementing an eye diagram limit offset amount determination method according to an embodiment of the present application.

[0120] The electronic device 1 can include a processor 10, a memory 11, and a bus 12, and can also include a computer program stored in the memory 11 and executable on the processor 10, such as an eye diagram limit offset amount determination method program.

[0121] The memory 11 includes at least one type of readable storage medium, such as flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as a portable hard drive. In other embodiments, the memory 11 can be an external storage device of the electronic device 1, such as a plug-in portable hard drive, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the electronic device 1. Furthermore, the memory 11 includes both internal storage units and external storage devices of the electronic device 1. The memory 11 can be used not only to store application software and various types of data installed on the electronic device 1, such as the code of the eye diagram limit offset determination method program, but also to temporarily store data that has been output or will be output.

[0122] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the memory 11 (e.g., eye diagram limit offset determination method program) and calls data stored in the memory 11 to perform various functions of the electronic device 1 and process data.

[0123] The bus 12 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize the connection and communication between the memory 11 and at least one processor 10, etc.

[0124] Figure 6 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 6The illustrated structure does not constitute a limitation on the electronic device 1, and can include fewer or more components than illustrated, or combine certain components, or different component arrangements.

[0125] For example, although not shown, the electronic device 1 can also include a power supply (such as a battery) to power the various components, and preferably the power supply can be logically connected to the at least one processor 10 through a power management device, so that the power management device can implement functions such as charge management, discharge management, and power consumption management. The power supply can also include one or more DC or AC power sources, recharging devices, power failure detection circuits, power converters or inverters, power status indicators, and any other components. The electronic device 1 can also include various sensors, Bluetooth modules, Wi-Fi modules, and the like, which are not described here.

[0126] Further, the electronic device 1 can also include a network interface, which can optionally include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), and is typically used to establish a communication connection between the electronic device 1 and other electronic devices.

[0127] Optionally, the electronic device 1 can also include a user interface, which can be a display (Display), an input unit (such as a keyboard (Keyboard)), and optionally a standard wired interface, a wireless interface. Optionally, in some embodiments, the display can be an LED display, a liquid crystal display, a touch liquid crystal display, and an OLED (Organic Light-Emitting Diode) touch, etc. The display can also be appropriately referred to as a display screen or a display unit, and is used to display information processed in the electronic device 1 and to display a visualized user interface.

[0128] The eyediagram limit offset determination method program stored in the memory 11 in the electronic device 1 is a combination of multiple instructions, which, when executed in the processor 10, can implement:

[0129] Perform pull bias data code value regulation using a pre-built eyediagram scanning module to obtain a current pull bias data code value;

[0130] Perform data pull sampling in a pre-built analog circuit according to the current pull bias data code value to obtain current pull bias data;

[0131] Obtain current normal data, and compare the current normal data and the current pull bias data using a pre-built serial-to-parallel conversion module to obtain waveform comparison data;

[0132] The eye pattern scanning module is used to count total bits of current normal data and error bits of current pull-off data according to the waveform comparison data, and a ratio calculation is performed on the total bits and the error bits to obtain a current bit error rate.

[0133] It is judged whether the current bit error rate is greater than a preset bit error rate threshold value.

[0134] If the current bit error rate is not greater than the bit error rate threshold value, the step of performing pull-off data code value control by using the pre-constructed eye pattern scanning module is returned to.

[0135] If the current bit error rate is greater than the bit error rate threshold value, a previous pull-off data code value of the current pull-off data code value is obtained, and an eye pattern limit offset is determined according to the previous pull-off data code value.

[0136] Specifically, the specific implementation method of the processor 10 to the above instructions can refer to Figures 1 to 6 The description of related steps in the corresponding embodiments is not repeated here.

[0137] Further, the modules / units integrated in the electronic device 1 are implemented in the form of software function units and sold or used as independent products, which can be stored in a computer readable storage medium. The computer readable storage medium can be volatile or non-volatile. For example, the computer readable medium can include any entity or device capable of carrying the computer program code, a recording medium, a U disk, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM, Read-Only Memory).

[0138] The application also provides a computer readable storage medium, which stores a computer program. When the computer program is executed by a processor of an electronic device, the following steps can be implemented:

[0139] Performing pull-off data code value control by using a pre-constructed eye pattern scanning module to obtain a current pull-off data code value;

[0140] Performing data pull-off sampling on the current pull-off data code value in a pre-constructed analog circuit to obtain current pull-off data;

[0141] Obtaining current normal data, and performing comparison on the current normal data and the current pull-off data by using a pre-constructed serial-parallel conversion module to obtain waveform comparison data;

[0142] The eye pattern scanning module is used to count total bits of current normal data and error bits of current pull-off data according to the waveform comparison data, and a ratio calculation is performed on the total bits and the error bits to obtain a current bit error rate;

[0143] determining whether the current bit error rate is greater than a preset bit error rate threshold value;

[0144] If the current bit error rate is not greater than the bit error rate threshold value, returning to the step of regulating the pull data code value by using the pre-constructed eye scan module.

[0145] If the current bit error rate is greater than the bit error rate threshold value, obtaining a previous pull data code value of the current pull data code value, and determining an eye limit offset value according to the previous pull data code value.

[0146] In several embodiments provided by the present application, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and the actual implementation can have other division manners.

[0147] The modules illustrated as separate components can or can not be physically separate, and the components illustrated as modules can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment according to actual needs.

[0148] In addition, each functional module in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically independently, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware, or in the form of hardware plus software function module.

[0149] It is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application but not limit the present application, and although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present application.

Claims

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to high level 1, and utilize the exclusive OR logic structure in the serial-parallel conversion module to compare the current normal data and the current pull-off data by exclusive OR, to obtain a detection output value, wherein the exclusive OR logic structure is XOR; Construct waveform comparison data according to the detection output value.

6. The eye diagram margin offset amount determination method of claim 5, wherein The utilization of the exclusive OR logic structure in the serial-parallel conversion module to compare the current normal data and the current pull-off data by exclusive OR to obtain a detection output value comprises: Utilize the exclusive OR logic structure to determine whether the current normal data and the current pull-off data are the same; If the current normal data and the current pull-off data are the same, set the detection output value to 0; If the current normal data and the current pull-off data are not the same, set the detection output value to 1.

7. The eye diagram margin offset amount determination method of claim 6, wherein The utilization of the eye scan module to statistically determine the total bit number of the current normal data and the error bit number of the current pull-off data according to the waveform comparison data comprises: Utilize the counter function in the eye scan module to statistically determine the total bit number of the current normal data and the error bit number of the current pull-off data, wherein the total bit number is ALL_BIT_COUNT, the error bit number is ERROR_BIT_COUNT, and the eye scan module is built in a pre-constructed eye calibration algorithm module.

8. The eye diagram margin offset amount determination method of claim 7, wherein The determination of the eye limit offset according to the last pull-off data code value comprises: When the last pull-off data code value is a horizontal control code value, determine an eye horizontal limit offset according to the last pull-off data code value; When the last pull-off data code value is a vertical control code value, determine an eye vertical limit offset according to the last pull-off data code value; Determine the eye limit offset according to the eye horizontal limit offset and the eye vertical limit offset.

9. The eye diagram margin offset amount determination method of claim 8, wherein The eye calibration algorithm module, the pre-constructed CDR module, and the DAC calibration module belong to preset digital circuits, and the continuous-time linear equalizer, the decision feedback equalizer, the pre-constructed DAC module, the clock generation module, the data recovery module, and the serial-parallel conversion module belong to preset analog circuits. The clock generation module performs data pull-off sampling according to a horizontal control code value, and the DAC module performs data pull-off sampling according to a vertical control code value.

10. An eye diagram limit offset amount determination system characterized by comprising: The system comprises: A pull-off sampling module, configured to utilize a pre-constructed eye scan module to control a pull-off data code value, to obtain a current pull-off data code value; and perform data pull-off sampling in a pre-constructed analog circuit according to the current pull-off data code value, to obtain current pull-off data; A waveform data comparison module, configured to obtain current normal data, utilize a pre-constructed serial-parallel conversion module to compare the current normal data and the current pull-off data, and obtain waveform comparison data; and The pull bias data code value cyclic control module is configured to utilize the eye diagram scanning module to count a total bit number of current normal data and an error bit number of current pull bias data according to the waveform comparison data, and perform ratio calculation on the total bit number and the error bit number to obtain a current error rate; determine whether the current error rate is greater than a preset error rate threshold; if the current error rate is not greater than the error rate threshold, return to the step of utilizing the pre-constructed eye diagram scanning module to control the pull bias data code value; The eye diagram limit offset amount determination module is configured to, if the current error rate is greater than the error rate threshold, obtain a previous pull bias data code value of the current pull bias data code value, and determine an eye diagram limit offset amount according to the previous pull bias data code value.

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