Photoelectric virtual loop multi-view linkage method and system based on quadratic logic model

Abstract

The application provides a kind of photoelectric virtual loop multi-viewport linkage method and system based on secondary logic model, it is related to communication technical field, method includes: obtaining optical circuit diagram, electric circuit diagram and virtual circuit diagram;The optical circuit diagram, electric circuit diagram and virtual circuit diagram are standardized, and element connection point database is obtained;Based on element connection point database, secondary logic model is constructed;Based on secondary logic model, the association between each road map is determined by graph matching algorithm;The support degree between association is calculated;According to support degree, threshold value determination is carried out to association, and target association is obtained;According to target association, the mapping dictionary between test data input point and target association is determined;Real-time monitoring test data input point, and combined with monitoring result and mapping dictionary, associated view switching instruction is generated;View switching instruction is executed, and specified loop path following switching and highlight display are realized in multiple viewports.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method and system for multi-viewport linkage of optoelectronic virtual loops based on a quadratic logic model. Background Technology

[0002] The optoelectronic virtual loop multi-viewport linkage method based on quadratic logic model is a technical method that uses a quadratic logic model to uniformly abstract and model optical loops, electrical loops, and virtual loops. It represents the components, boards, and connection points in the loop as nodes, and the signal or energy flow as directed edges. The loop topology is characterized by the logical relationship between nodes and edges, and the multi-viewport interface is used to realize the synchronous display and interactive linkage of different loop diagrams. This allows users to intuitively track the signal flow and node status in the loop in multiple viewports, thereby supporting the real-time analysis, monitoring, and operation of complex loops.

[0003] As power and communication systems become increasingly complex, the number and interconnection of optical, electrical, and virtual loops are constantly increasing. Loop structures are complex and signal paths are numerous. At the same time, there are complex logic and signal relationships between multiple loops. Single-viewport visualization is insufficient to intuitively present the signal flow across loops. Therefore, a loop linkage method is needed that can achieve unified modeling of loop information, automatic identification of cross-loop relationships, and dynamic highlighting display across multiple viewports.

[0004] However, different loop types (optical loops, electrical loops, virtual loops) usually exist in the form of independent drawings, lacking a unified data structure and logical connection. The correspondence between signals across loops is difficult to identify, requiring a lot of manual comparison and analysis. At the same time, the loop status visualization and path tracking functions are limited, and dynamic highlighting and automatic view switching cannot be achieved, resulting in low operation efficiency, untimely fault location, and inaccurate analysis results. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a multi-viewport linkage method for optoelectronic virtual circuits based on a secondary logic model. This method can solve the technical problems in the prior art where different circuit types (optical circuits, electrical circuits, and virtual circuits) usually exist in the form of independent drawings, lack a unified data structure and logical association, and the cross-circuit signal correspondence is difficult to identify, requiring a lot of manual comparison and analysis. It also cannot achieve dynamic highlighting and automatic view switching, resulting in low operation efficiency, untimely fault location, and inaccurate analysis results.

[0006] A first aspect of this invention proposes a multi-viewport linkage method for optoelectronic virtual loops based on a quadratic logic model, comprising:

[0007] S1: Obtain the optical loop diagram, electrical loop diagram, and virtual loop diagram;

[0008] S2: Standardize the optical circuit diagram, the electrical circuit diagram, and the virtual circuit diagram to obtain a component connection point database;

[0009] S3: Construct a secondary logic model based on the aforementioned component connection point database;

[0010] S4: Based on the aforementioned secondary logic model, the association between the optical loop diagram, the electrical loop diagram, and the virtual loop diagram is determined using a graph matching algorithm;

[0011] S5: Calculate the support level between the associations; when the support level is greater than or equal to a preset support level, determine the association as a target association; when the support level is less than the preset support level, modify the association to obtain the target association.

[0012] S6: Determine the mapping dictionary between the experimental data input points and the target association relationship based on the target association relationship;

[0013] S7: Monitor the test data input points in real time, and generate associated view switching instructions by combining the monitoring results and the mapping dictionary;

[0014] S8: Execute the view switching command to achieve the following switching and highlighting of the specified loop path in multiple viewports.

[0015] A second aspect of this invention proposes a photoelectric virtual loop multi-viewport linkage system based on a quadratic logic model, comprising: a processor and a memory;

[0016] The memory stores programs or instructions that can run on the processor, and when the program or instructions are executed by the processor, they implement the steps of the optoelectronic virtual loop multi-viewport linkage method based on the quadratic logic model as described in the first aspect.

[0017] A third aspect of the present invention provides a readable storage medium storing a program or instructions, which, when executed by a processor, implements the steps of the optoelectronic virtual loop multi-viewport linkage method based on a quadratic logic model as described in the first aspect.

[0018] The beneficial effects of the technical solutions provided by the embodiments of the present invention include at least the following:

[0019] In this embodiment of the invention, by acquiring optical loop diagrams, electrical loop diagrams, and virtual loop diagrams and performing standardized processing, information on different types of loops is uniformly converted into a structured component connection point database, achieving data standardization and unified management. A secondary logic model is constructed based on the database, accurately representing the internal hierarchy of components and signal flow. A graph matching algorithm is used to determine the correlation between loops and calculate the support degree, automatically identifying reliable logical correspondences between optical, electrical, and virtual loops. Simultaneously, the accuracy of correlations is improved by correcting low-support correlations. A mapping dictionary is used to establish the correspondence between experimental data input points and target signal flow paths. Combined with monitoring input point-triggered view switching commands and multi-viewport highlighting, dynamic tracking of loop paths, real-time visualization of signal flow, and cross-loop synchronous monitoring are achieved. Attached Figure Description

[0020] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0021] Figure 1 This is a flowchart illustrating a multi-viewport linkage method for optoelectronic virtual loops based on a secondary logic model, provided in an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of the structure of a photoelectric virtual loop multi-viewport linkage system based on a secondary logic model provided in an embodiment of the present invention. Detailed Implementation

[0023] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0024] The following description, in conjunction with the accompanying drawings, details the optoelectronic virtual loop multi-viewport linkage method based on a secondary logic model provided by the present invention through specific embodiments and application scenarios.

[0025] Reference manual attached Figure 1 The diagram shows a flowchart of a photoelectric virtual loop multi-viewport linkage method based on a quadratic logic model provided by an embodiment of the present invention.

[0026] This invention provides a method for multi-viewport linkage of optoelectronic virtual loops based on a quadratic logic model, which may include the following steps:

[0027] S1: Obtain the optical loop diagram, electrical loop diagram, and virtual loop diagram.

[0028] Optical loop diagrams are drawings that depict the transmission path of optical signals between optical devices such as optical fibers, optical modules, and optical relays. They primarily show the input and output ports of optical signals and the connections between optical fibers, used to analyze the flow of optical signals and the optical path topology between devices. Electrical loop diagrams depict the transmission path of electrical signals between electrical devices, relays, terminals, and boards, showing circuit connections and switching logic, used to understand the flow of electrical signals and the electrical topology. Virtual loop diagrams are abstract descriptions of the transmission of system logic or functional signals, not directly corresponding to physical circuits. They are used to represent the signal dependencies and flows between logical nodes, helping to analyze functional relationships across loops.

[0029] S2: Standardize the optical circuit diagram, electrical circuit diagram, and virtual circuit diagram to obtain a component connection point database.

[0030] The component connection point database is a structured database that stores information about all components and their connection points in the circuit diagram. It includes unique identifiers of components, coordinates of physical or logical connection points, and connection relationships between components, which are used for subsequent logic modeling and correlation analysis.

[0031] It should be noted that by standardizing optical circuit diagrams, electrical circuit diagrams, and virtual circuit diagrams and generating a component connection point database, the component information and connection relationships of different types of circuits can be managed in a unified manner, realizing data structuring and standardization, which facilitates subsequent logical modeling, cross-circuit correlation analysis, and automated processing, thereby improving the efficiency and accuracy of system analysis.

[0032] In one possible implementation, S2 specifically includes:

[0033] S201: Using a graph analysis engine, identify graphic elements and their corresponding connection lines in optical loop diagrams, electrical loop diagrams, and virtual loop diagrams. Specifically, graphic elements include relays, ports, fiber optic interfaces, and terminals.

[0034] A graph analysis engine is a software tool capable of reading and parsing vector graphics (such as SVG and DXF) or other electronic drawing formats. It identifies graphic elements and connections within the drawing, providing foundational data for automated analysis. Graphical elements refer to symbols or graphics in a circuit diagram that represent actual devices or interfaces, such as relays, ports, fiber optic interfaces, and terminals. Each element corresponds to a specific function or signal interface in the diagram.

[0035] Specifically, by using a graph analysis engine to identify graphic elements and their connecting lines in a loop diagram, it is possible to automatically parse drawings of different formats and complexities, quickly digitize the physical or logical structure, and provide an accurate and structured data foundation for subsequent standardization, topology generation, and logical modeling, thereby significantly reducing manual drawing interpretation and error rates.

[0036] S202: Extract the unique identifier and logical coordinates of the physical connection point of the graphic element according to its type.

[0037] The unique identifier refers to a unique name or number generated for each component, such as "Board A-Port 3" or "Relay K1-Normally Open Contact," used to distinguish different components and facilitate subsequent reference. The physical connection point logical coordinates refer to the spatial or logical location of the component on the drawing, used to identify the specific location of the connection point, supporting subsequent topology determination and signal flow analysis.

[0038] Specifically, by extracting the unique identifiers of graphic elements and the logical coordinates of physical connection points, the complex equipment and port information in the drawings can be digitized and uniquely identified, facilitating unified management of elements and accurate establishment of topological relationships.

[0039] S203: Generate the loop topology based on the logical coordinates of the physical connection points and the connection lines.

[0040] The loop topology is a graph structure that represents the components and their connections in the loop in the form of nodes and edges. Nodes correspond to the connection points of components, and edges correspond to the connecting lines. It is used to describe the structure of the entire loop and the direction of signal flow.

[0041] Specifically, by generating loop topology based on the logical coordinates of physical connection points and connection lines, complex loop diagrams can be converted into computable graph models, realizing a structured representation of signal flow and component connection relationships. This provides an accurate foundation for logic modeling, cross-loop correlation analysis, and automated simulation, while reducing the complexity of manually interpreting drawings.

[0042] S204: Store the unique identifier, the logical coordinates of the physical connection point, and the loop topology into a unified database to obtain the component connection point database.

[0043] In this embodiment of the invention, a graph parsing engine (such as one based on an SVG / DXF parsing library) is used to parse the input optical loop diagram, electrical loop diagram, and virtual loop diagram files. This process identifies the graphic elements contained in the drawings and their corresponding connection information. During parsing, the geometric features, text annotations, and line type information of each graphic element are extracted to obtain the spatial distribution of elements and the layout of connection lines in the drawings. Based on the identified graphic element type and its drawing annotation information, a unique identifier is generated for each element (e.g., "Board A - Port 3", "Relay K1 - Normally Open Contact"), and the logical coordinate information of all its physical connection points is extracted. This identifier enables unified naming of the same device or module in different drawings, and the actual position of the port in the drawing is recorded using logical coordinates for subsequent connection relationship determination. Then, combining the logical coordinates of the physical connection points with the geometric relationship of the connection lines, the interconnected port pairs are determined, and directed connections between nodes and edges are established based on the direction of the connection lines, arrow markings, or signal directions. The topology uses "element connection points" as nodes and "connection lines" as edges, fully describing the connection relationships between elements in the three types of loops. Finally, the standardized component identifiers, connection point logical coordinates, and corresponding loop topologies generated above are uniformly stored in the database to form a structured component connection point database.

[0044] S3: Construct a secondary logic model based on the component connection point database.

[0045] The secondary logic model refers to a logic graph model built on the basis of the component connection point database. Nodes represent component connection points, and edges represent the direction of signal or energy flow. Loop type and attribute information can also be added to analyze the internal function of the loop and the logical relationship between loops.

[0046] It should be noted that constructing a secondary logic model can transform the physical connection relationship of the original loop diagram into a structured logic diagram, clearly expressing the internal hierarchy of components and the direction of signal flow, which facilitates cross-loop analysis, automated simulation and fault location, while providing a unified data structure for subsequent graph matching and correlation calculation.

[0047] In one possible implementation, S3 specifically includes:

[0048] S301: Extract components, boards, and connection points from the component connection point database and form a triplet.

[0049] In this context, a board refers to a circuit board or functional module installed in a device to implement specific control, signal processing, or communication functions. A triplet is a unique identifier formed by combining a component, board, and connection point to precisely describe a specific node, such as "Protection Device PRP1 – CPU Board – Optical Port TX".

[0050] Specifically, by extracting components, boards, and connection points to form triplet groups, the functional level and interface position of each node in the device and loop can be accurately represented, realizing the unique identification of nodes, providing an accurate basis for logic modeling and cross-loop signal analysis, and avoiding information duplication or confusion.

[0051] S302: Define a triple as a set of nodes.

[0052] S303: Map the connection lines in the component connection point database to the edges between each node in the node set.

[0053] In this embodiment of the invention, the direction of the edge represents the direction of signal or energy flow, such as from "optical port TX" to "optical port RX of the peer device".

[0054] S304: Add attributes to each edge according to the circuit type to which each edge belongs, and obtain a set of directed edges.

[0055] S305: Construct a quadratic logic model based on the set of nodes and the set of directed edges.

[0056] In this embodiment of the invention, basic information related to logic modeling is extracted from the component connection point database, including components, boards, and the physical connection points corresponding to each board. The component name, board name, and connection point name are combined to form a unique triplet identifier, such as "Protection Device PRP1 – CPU Board – Optical Port TX". The triplet is used to accurately describe the functional hierarchy and signal interface relationships within the device. All triplets are used as elements of a node set, defined as nodes in the quadratic logic model, with each node corresponding to a specific device board port. For example, when the CPU board of the protection device has optical ports TX and RX, nodes "PRP1 – CPU Board – TX" and "PRP1 – CPU Board – RX" can be defined respectively. Then, based on the existing connection line information in the component connection point database, the connection relationships between each node are mapped as directed edges. The direction of the edge is determined according to the direction of signal or energy flow; for example, when a signal is transmitted from "Optical Port TX" to "Optical Port RX of the peer device", a directed edge from "TX" to "RX" is established in the logic model. Based on the loop type (optical loop, electrical loop, or virtual loop) of each connecting edge, attribute information is added to each directed edge, including parameters such as loop type, line type, color, and view layer, thereby achieving loop hierarchy differentiation and visual mapping. Finally, based on the above set of nodes and the set of directed edges with attributes, a secondary logic model is constructed. ,in Represents a set of nodes. Represents the set of directed edges. Represents the set of edge attributes.

[0057] S4: Based on the quadratic logic model, the relationship between the optical loop diagram, electrical loop diagram and virtual loop diagram is determined by the graph matching algorithm.

[0058] Among them, the association relationship refers to the logical or signal correspondence between nodes across loops. Graph matching is used to determine which nodes have potential mappings in different loops.

[0059] It should be noted that, based on the quadratic logic model, the graph matching algorithm determines the correlation between loops, which can automatically identify the potential logical correspondences and signal mappings between optical loops, electrical loops and virtual loops, and realize cross-loop information fusion.

[0060] In one possible implementation, the secondary logic model includes an optical circuit logic diagram, an electrical circuit logic diagram, and a virtual circuit logic diagram.

[0061] In one possible implementation, S4 specifically includes:

[0062] S401: Extract the node features and edge features of the quadratic logic model to obtain the node embedding set and edge embedding set.

[0063] S402: Based on the node embedding set and the edge embedding set, perform intra-graph message propagation on the optical loop logic graph, electrical loop logic graph and virtual loop logic graph respectively to obtain intra-graph propagation embedding.

[0064] Intra-graph message passing refers to a method within a single logical graph where nodes exchange information through their connecting edges to update their node embeddings, used to capture local topology and neighbor relationships. Intra-graph propagation embedding refers to the updated embedding vector obtained by each node after message propagation iterations, which integrates information from its neighboring nodes and edge features, and is used for subsequent cross-graph matching.

[0065] Specifically, by propagating intra-circuit messages in each loop logic diagram, node embedding can comprehensively consider neighboring nodes and edge features, thereby encoding local topology and signal flow information. This provides accurate and rich node representations for subsequent cross-loop matching and correlation analysis, improving matching accuracy and system robustness.

[0066] The specific calculation method for message propagation within the graph is as follows:

[0067]

[0068] in, p Indicates the circuit type. p = o Indicates the optical loop. p = e Indicates an electrical circuit. p =v Represents a virtual circuit. Representation of loop logic diagram p Nodes in j To the node i The message vector being transmitted Representation of loop logic diagram p Inner propagation embedding, i.e. At the +1st iteration, the node Loop Logic Diagram p The updated results in ( ) represents a message generation function. Representation of loop logic diagram p Nodes in In the Embedding representation at the next iteration Representation of loop logic diagram p nodes In the Embedding representation at the next iteration Representation of loop logic diagram p nodes i and nodes j Edge features between them This represents the node update function.

[0069] S403: Based on the intra-graph propagation embedding, perform cross-graph fusion update on the optical loop logic diagram, electrical loop logic diagram and virtual loop logic diagram after intra-graph message propagation to obtain the optical loop fusion node embedding, electrical loop fusion node embedding and virtual loop fusion node embedding.

[0070] Cross-graph fusion update refers to embedding nodes between different loop logic graphs to exchange and merge information, adjusting the node representation according to the matching weight, so that the node embedding retains the information within the graph and integrates cross-graph relevance.

[0071] Specifically, through cross-graph fusion updates, node embedding not only encodes the topological information of its own loop, but also integrates the association features of other loops, enabling optical, electrical, and virtual loop nodes to perceive each other, improving the accuracy of cross-loop matching and the ability to identify association relationships, and enhancing the comprehensiveness and reliability of system analysis.

[0072] In one possible implementation, S403 specifically includes:

[0073] S403A: Calculate multiple cross-graph matching weights between optical loop logic diagrams, electrical loop logic diagrams, and virtual loop logic diagrams, respectively.

[0074] The specific method for calculating cross-graph matching weights is as follows:

[0075]

[0076] in, Representation of loop logic diagram q Nodes in j Loop Logic Diagram p Nodes in i Matching weights q Indicates the circuit type. q = o Indicates the optical loop. q = e Indicates an electrical circuit. q = v Let denot be a virtual circuit, and let exp denote an exponential function. Representation of loop logic diagram q nodes In the Embedding representation at the next iteration Representation of loop logic diagram q nodes In the Embedding representation at the next iteration Representation of loop logic diagram p The set of all nodes in the set, where s() represents the similarity kernel function.

[0077] In this embodiment of the invention, when performing pairwise cross-matching on the optical loop logic diagram, electrical loop logic diagram, and virtual loop logic diagram to obtain multiple cross-graph matching weights, the loops are divided into 6 groups (electric → optical, virtual → optical, optical → electrical, virtual → electrical, optical → virtual, electrical → virtual), resulting in 6 cross-graph matching weights.

[0078] S403B: Based on the matching weights of each cross-graph, calculate multiple matching difference vectors between the optical loop logic graph, the electrical loop logic graph, and the virtual loop logic graph.

[0079] S403C: Based on the matching difference vectors, cross-graph fusion updates are performed on the optical loop logic graph, electrical loop logic graph, and virtual loop logic graph after message propagation within the graph, resulting in the optical loop fusion node embedding, electrical loop fusion node embedding, and virtual loop fusion node embedding.

[0080]

[0081] in, Representation of loop logic diagram p nodes In the t The final embedding at +1 iteration, i.e., the fused node embedding. ( ) represents the node update function. Representation of loop logic diagram p Nodes in i And loop logic diagramq Nodes in j The difference vector between them.

[0082] In this embodiment of the invention, the matching difference vectors of electric → optical and virtual → optical are aggregated to obtain the optical loop fusion node embedding; the matching difference vectors of optical → electric and virtual → electric are aggregated to obtain the electrical loop fusion node embedding; and the matching difference vectors of optical → virtual and electric → virtual are aggregated to obtain the virtual loop fusion node embedding.

[0083] S404: Repeat steps S402 to S403 until the maximum number of iterations is reached to obtain multiple cross-graph node embeddings, including: optical loop cross-graph node embedding, electrical loop cross-graph node embedding and virtual loop cross-graph node embedding.

[0084] S405: Calculate the similarity between each cross-graph node embedding to obtain multiple global similarities.

[0085] Specifically, by calculating the similarity between cross-graph node embeddings and obtaining the global similarity, the overall matching degree between optical loops, electrical loops and virtual loops can be quantified, providing an objective basis for the identification of cross-loop associations, accurately locating logically corresponding nodes and reducing erroneous matching.

[0086] The global similarity is calculated as follows:

[0087]

[0088] in, ( ) represents a feature transformation network. ( ) represents a gated multilayer sensor. Representation of loop logic diagram q nodes i In the T Cross-graph node embedding after the next iteration This represents element-wise multiplication of vectors, and s() represents the similarity kernel function. Representation of loop logic diagram p , Representation of loop logic diagram q , f s ( ) represents the similarity function. Representation of loop logic diagram p The global embedding vector, Representation of loop logic diagram q The global embedding vector, Representation of loop logic diagram p And loop logic diagram q The global similarity matrix between them Represents the fusion coefficient. ( ) represents the normalization function. Representation of loop logic diagram p And loop logic diagram q The node-level similarity matrix between them Representation of loop logic diagram p The node weight vector, Representation of loop logic diagram q The node weight vector, where || represents the vector norm. T This indicates transpose.

[0089] The similarity matrices for the three pairs of loops (optical-electric, optical-virtual, and electrical-virtual) are calculated using the above method: .

[0090] S406: Map all elements in each global similarity matrix to obtain the association between the optical loop diagram, the electrical loop diagram, and the virtual loop diagram.

[0091] Specifically, by mapping all elements in the global similarity matrix, it is possible to accurately associate potential corresponding nodes in optical loops, electrical loops, and virtual loops, forming a unified cross-loop association network, and realizing an intuitive expression of signal flow or logical relationship.

[0092] In this embodiment of the invention, the global similarity matrices corresponding to each pair of optical loops, electrical loops, and virtual loops are traversed. For each element in the matrix The system detects that when the similarity value exceeds a preset threshold, the corresponding node pairs (i.e., connection points such as optical ports, electrical terminals, or virtual terminals) have a logical or signal association across loops. These node pairs that meet the criteria are then categorized according to their loop type, forming three association sets: optical-electrical, optical-virtual, and electrical-virtual. Each set represents a pair of ports with a potential mapping relationship and their association strength. Finally, the three association sets are combined to construct a unified association network that includes signal flow or logical mappings between optical loop diagrams, electrical loop diagrams, and virtual loop diagrams.

[0093] S5: Calculate the support level between associations. When the support level is greater than or equal to the preset support level, the association is determined as the target association. When the support level is less than the preset support level, the association is modified to obtain the target association.

[0094]

[0095] in, Representation of loop logic diagram AND loop logic diagram The level of support V p Representation of loop logic diagramp The set of all nodes in the set. V q Representation of loop logic diagram q The set of all nodes in the set. E p Representation of loop logic diagram p The set of all edges in the set. E q Representation of loop logic diagram p The set of all edges in the set. Representation of loop logic diagram The adjacency matrix in the th u Okay, number v Column entries, Representation of loop logic diagram nodes AND loop logic diagram nodes x The strength of the association, Representation of loop logic diagram The adjacency matrix in the th x Okay, number y Column entries, Representation of loop logic diagram nodes u AND loop logic diagram nodes y The strength of the association, Representing a circuit p and loop q The degree of support for the relationship between them and represents the weighting coefficient, and min means minimization.

[0096] It should be noted that those skilled in the art can set the preset support level according to actual needs, and this invention does not limit this.

[0097] Among them, the support level is an indicator that measures the reliability of a certain association. It combines node matching, edge adjacency matrix and global similarity calculation to reflect the credibility of cross-loop association.

[0098] It should be noted that by calculating the support level of the association and comparing it with a preset threshold, reliable cross-loop mapping relationships can be automatically filtered out, while low-support associations can be corrected to ensure the accuracy and credibility of the target association relationship.

[0099] In one possible implementation, node pairs with support levels below a threshold are identified. Then, by combining information about their neighboring nodes, the topological features of the edges, and the global similarity of the loops, unreliable matching weights are adjusted or recalculated. At the same time, possible erroneous mappings are eliminated, and missing potential associations are supplemented. Finally, an optimized target association relationship is generated, thereby ensuring the accuracy and consistency of cross-loop mapping.

[0100] S6: Determine the mapping dictionary between the experimental data input points and the target association based on the target association.

[0101] In this context, the test data input point refers to the selected starting node or specific monitoring node in the secondary logic model, such as "Intelligent Terminal ST1 - Switch Input Point 1," used to input signals or monitor data. The mapping dictionary is a data structure used to store the mapping relationship between test data input points and their corresponding target signal flow paths, enabling fast retrieval and recall.

[0102] Specifically, by establishing a mapping dictionary between experimental data input points and target correlations, input signals can be quickly located to the corresponding loop path, enabling automatic tracking and path analysis of signal flow, improving system response speed and data management efficiency, and providing data support for visualization and dynamic monitoring.

[0103] In one possible implementation, S6 specifically includes:

[0104] S601: Define the test data input points.

[0105] In this embodiment of the invention, the test data input point is specifically the starting node of a certain loop in the secondary logic model or a specific monitoring point (such as "intelligent terminal ST1 - switch input point 1").

[0106] S602: In the quadratic logic model, traverse all signal flow paths originating from the test data input point.

[0107] S603: Select all signal flow paths that pass through the target association as the target signal flow path.

[0108] S604: Establish the mapping relationship between the test data input points and the target signal flow path corresponding to the test data input points, and obtain the mapping dictionary.

[0109] In this embodiment of the invention, a specific test data input point is first selected in the secondary logic model, such as "intelligent terminal ST1 - switch input point 1". Then, all signal flow paths originating from the input point are traversed, and the paths that pass through the target association are selected as the target signal flow paths. A mapping relationship is established between each test data input point and its corresponding target signal flow path to form a mapping dictionary. This enables one-to-one correspondence management between input points and cross-loop signal paths, providing a reliable data foundation for subsequent signal tracking and view switching.

[0110] S7: Real-time monitoring of test data input points, and combined with monitoring results and mapping dictionary to generate associated view switching instructions.

[0111] Among them, the diagram switching command refers to the command to switch the control loop diagram visualization interface. According to the mapping dictionary, the system highlights the corresponding path in the optical loop diagram, electrical loop diagram and virtual loop diagram.

[0112] It should be noted that by monitoring the test data input points and combining them with the mapping dictionary to trigger view switching commands, user operations or signal changes can be mapped to the loop diagram path in real time, highlighting relevant nodes and signal flow directions, thereby improving the visualization of loop status, ease of operation, and efficiency of fault location.

[0113] In one possible embodiment, S7 specifically includes:

[0114] S701: Monitor the test data input point when the user selects it.

[0115] S702: Combining the detection results and the mapping dictionary, retrieve the association relationships related to the experimental data input points to obtain the target association relationships.

[0116] S703: Based on the target association relationship, generate view identifiers and view switching instructions that include the optical loop diagram, electrical loop diagram, and virtual loop diagram containing the target association relationship.

[0117] In this embodiment of the invention, nodes and paths in optical loops, electrical loops, and virtual loops related to the selected test data input point are identified based on a mapping dictionary or target association. Then, a corresponding view identifier is generated for each loop diagram to mark the loop areas that need to be displayed or highlighted. Next, a view switching command is generated to automatically switch the relevant paths in the optical loop diagram, electrical loop diagram, and virtual loop diagram to the foreground display or highlight state, thereby achieving dynamic following and visual display of the loop paths corresponding to the test data input point in multiple viewports. For example, a test data input point is defined as "Intelligent Terminal ST1 - Switch Input Point 1". The optical loop corresponding to the input point is "Optical Port TX → Optical Port RX Path", the electrical loop is "Relay K1 Normally Open Contact → Terminal T3", and the virtual loop is "Logic Node L1 → Logic Node L2". The system monitors the switching status of the input point in real time. When the input point detects a "closed" signal, the system looks up the path information corresponding to the input point in the mapping dictionary and automatically generates a view switching instruction: the "TX→RX" path in the optical loop diagram, the "K1 normally open contact→T3" path in the electrical loop diagram, and the "L1→L2" path in the virtual loop diagram are switched to the foreground display and highlighted. At the same time, irrelevant nodes and edges are weakened to realize the synchronous dynamic display of loops in multiple viewports, so that users can intuitively track the cross-loop signal flow and node status caused by the input point.

[0118] S8: Executes a view switching command to achieve the following switching and highlighting of a specified loop path in multiple viewports.

[0119] It should be noted that executing view switching commands and implementing loop path following and highlighting in multiple viewports allows users to intuitively observe the signal flow corresponding to the test data input point, track the dynamic changes of optical loops, electrical loops and virtual loops in real time, improve the efficiency of loop status monitoring, fault location and operation decision-making, and reduce the complexity of manually searching and switching drawings.

[0120] In this embodiment of the invention, after receiving a view switching command generated by a mapping dictionary or target association, the display state is automatically switched in multiple loop viewports. The paths of the optical loop diagram, electrical loop diagram, and virtual loop diagram related to the test data input point are highlighted, while irrelevant paths are hidden or weakened. This ensures that the user can synchronously follow the changes in signal flow in different viewports, achieve dynamic tracking and real-time visualization of the specified loop path, and provide intuitive interface feedback for operation, monitoring, and fault diagnosis.

[0121] Reference manual attached Figure 2 The diagram shows a schematic of the structure of a photoelectric virtual loop multi-viewport linkage system based on a quadratic logic model provided in an embodiment of the present invention.

[0122] This invention provides a photoelectric virtual loop multi-viewport linkage system 20 based on a quadratic logic model, including: a processor 201 and a memory 202;

[0123] The memory 202 stores programs or instructions that can run on the processor 201. When the program or instructions are executed by the processor 201, they implement the steps of the above-mentioned photoelectric virtual loop multi-viewport linkage method based on the secondary logic model and achieve the same technical effect. To avoid repetition, the present invention will not elaborate further.

[0124] It should be understood that the processor 201 in this embodiment of the invention may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0125] It should also be understood that the memory 202 in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DR RAM).

[0126] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0127] It should be understood that, in various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0128] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0129] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0130] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0131] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0132] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0133] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0134] This invention provides a readable storage medium comprising: storing a program or instructions on the readable storage medium, wherein when the program or instructions are executed by a processor, the program or instructions implement the steps of the above-described photoelectric virtual circuit multi-viewport linkage method based on a quadratic logic model, and can achieve the same technical effect. To avoid repetition, this invention will not elaborate further.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the protection scope of the present invention.

Claims

1. A method for multi-viewport linkage of optoelectronic virtual loops based on a quadratic logic model, characterized in that, include: S1: Obtain the optical loop diagram, electrical loop diagram, and virtual loop diagram; S2: Standardize the optical circuit diagram, the electrical circuit diagram, and the virtual circuit diagram to obtain a component connection point database; S3: Construct a secondary logic model based on the aforementioned component connection point database; The secondary logic model includes an optical circuit logic diagram, an electrical circuit logic diagram, and a virtual circuit logic diagram. S4: Based on the aforementioned secondary logic model, the association between the optical loop diagram, the electrical loop diagram, and the virtual loop diagram is determined using a graph matching algorithm; Specifically, S4 includes: S401: Extract the node features and edge features of the quadratic logic model to obtain the node embedding set and the edge embedding set; S402: Based on the node embedding set and the edge embedding set, perform in-graph message propagation on the optical loop logic diagram, the electrical loop logic diagram and the virtual loop logic diagram respectively to obtain in-graph propagation embedding; S403: Based on the intra-graph propagation embedding, cross-graph fusion update is performed on the optical loop logic diagram, electrical loop logic diagram and virtual loop logic diagram after intra-graph message propagation to obtain optical loop fusion node embedding, electrical loop fusion node embedding and virtual loop fusion node embedding. S404: Repeat steps S402 to S403 until the maximum number of iterations is reached to obtain multiple cross-graph node embeddings, wherein the cross-graph node embeddings include: optical loop cross-graph node embeddings, electrical loop cross-graph node embeddings, and virtual loop cross-graph node embeddings. S405: Calculate the similarity between each of the cross-graph node embeddings to obtain multiple global similarity matrices; S406: Map all elements in each of the global similarity matrices to obtain the association relationship between the optical loop diagram, the electrical loop diagram, and the virtual loop diagram; S5: Calculate the support level between the associations; when the support level is greater than or equal to a preset support level, determine the association as a target association; when the support level is less than the preset support level, modify the association to obtain the target association. S6: Determine the mapping dictionary between the experimental data input points and the target association relationship based on the target association relationship; S7: Monitor the test data input points in real time, and generate associated view switching instructions by combining the monitoring results and the mapping dictionary; S8: Execute the view switching command to achieve the following switching and highlighting of the specified loop path in multiple viewports.

2. The photoelectric virtual loop multi-viewport linkage method based on a quadratic logic model according to claim 1, characterized in that, S2 specifically includes: S201: Using a graph analysis engine, identify the graphic elements and corresponding connection lines in the optical loop diagram, the electrical loop diagram, and the virtual loop diagram, wherein the graphic elements specifically include relays, ports, fiber optic interfaces, and terminals. S202: Extract the unique identifier and logical coordinates of the physical connection point of the graphic element according to its type; S203: Generate a loop topology based on the logical coordinates of the physical connection points and the connection lines; S204: Store the unique identifier, the logical coordinates of the physical connection point, and the loop topology into a unified database to obtain the component connection point database.

3. The photoelectric virtual loop multi-viewport linkage method based on a quadratic logic model according to claim 1, characterized in that, S3 specifically includes: S301: Extract the components, boards, and connection points from the component connection point database and form a triplet; S302: Define the triplet as a set of nodes; S303: Map the connection lines in the component connection point database to the edges between each node in the node set; S304: Based on the circuit type to which each edge belongs, add attributes to each edge to obtain a set of directed edges; S305: Construct the quadratic logic model based on the set of nodes and the set of directed edges.

4. The photoelectric virtual loop multi-viewport linkage method based on a quadratic logic model according to claim 1, characterized in that, Specifically, S403 includes: S403A: Calculate multiple cross-graph matching weights between the optical circuit logic diagram, the electrical circuit logic diagram, and the virtual circuit logic diagram, respectively; S403B: Based on the cross-graph matching weights, calculate multiple matching difference vectors between the optical loop logic diagram, the electrical loop logic diagram, and the virtual loop logic diagram; S403C: Based on each of the matching difference vectors, perform cross-graph fusion update on the optical loop logic diagram, electrical loop logic diagram, and virtual loop logic diagram after the message propagation within the graph, to obtain the optical loop fusion node embedding, the electrical loop fusion node embedding, and the virtual loop fusion node embedding.

5. The photoelectric virtual loop multi-viewport linkage method based on a quadratic logic model according to claim 1, characterized in that, S6 specifically includes: S601: Define the test data input points; S602: In the secondary logic model, traverse all signal flow paths originating from the test data input point; S603: Select all signal flow paths that pass through the target association as the target signal flow paths; S604: Establish the mapping relationship between the test data input point and the target signal flow path corresponding to the test data input point, and obtain the mapping dictionary.

6. The photoelectric virtual loop multi-viewport linkage method based on a quadratic logic model according to claim 1, characterized in that, Specifically, S7 includes: S701: When the user selects the test data input point, the test data input point is monitored; S702: Based on the mapping dictionary, retrieve the association relationships related to the experimental data input points to obtain the target association relationships; S703: Based on the target association relationship, generate a view identifier and a view switching instruction that include the optical loop diagram, the electrical loop diagram, and the virtual loop diagram containing the association relationship.

7. A photoelectric virtual loop multi-viewport linkage system based on a quadratic logic model, characterized in that, include: Processor and memory; The memory stores programs or instructions that can run on the processor, and when the program or instructions are executed by the processor, they implement the steps of the optoelectronic virtual loop multi-viewport linkage method based on a quadratic logic model as described in any one of claims 1 to 6.

8. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions, which, when executed by a processor, implement the steps of the optoelectronic virtual loop multi-viewport linkage method based on a quadratic logic model as described in any one of claims 1 to 6.

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