Wafer edge cutting method

Abstract

The invention discloses a wafer edge cutting method, which comprises the steps of performing edge cutting treatment through a first tool bit, cutting into a preset depth of a bearing wafer in an edge cutting area, and forming a groove cutting mark in the bearing wafer; edge cutting treatment is carried out through a second tool bit, the device wafer and the bearing wafer in an edge cutting area are removed, and the width of the second tool bit is larger than that of the first tool bit; wherein the device wafer and the bearing wafer are bonded, the circle center of the device wafer and the circle center of the bearing wafer are overlapped when the device wafer and the bearing wafer are observed from an overlook angle, the edge cutting area is an annular area which is a preset distance inwards from the edge of the bearing wafer along the radius of the bearing wafer, and a gap exists between the contact surfaces of the device wafer and the bearing wafer in the edge cutting area. According to the invention, the edge with the gap is cut off through the pre-trimming of the first tool bit, so that the device wafer is not stressed in the process of trimming by using the second tool bit, the probability of damage caused by uneven stress is reduced, and the yield and production efficiency of products are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a wafer trimming method. BACKGROUND

[0002] An image sensor is an electronic device that converts optical signals into electrical signals, and is widely used in photography, security systems, smart mobile phones, medical electronics and other fields. In the image sensor, a complementary metal oxide semiconductor contact image sensor (CIS) is made by using a traditional CMOS circuit process, and the image sensor and its required peripheral circuit can be integrated, so that the CIS has a wide application prospect.

[0003] According to the different positions of the received light, the CIS can be divided into front-side illumination (FSI) and back-side illumination (BSI) structures. Compared with the FSI CIS, the BSI CIS changes the internal structure of the element, turns the incident light path of the light-sensitive layer element in the direction, and makes the light directly enter from the back of the element, avoiding the influence of the structure and thickness between the microlens and the photodiode (PD) on the light in the FSI CIS, and improving the efficiency of light reception.

[0004] In the manufacturing process of the BSI CIS, trimming is an important process, which is to cut off a certain width of the edge of the wafer with a cutter. Usually, in the manufacturing process of the BSI CIS, trimming is completed by three processes, and the main purpose of the second trimming is to correct the gap between the carrier wafer and the device wafer (the wafer formed with semiconductor devices) at the edge after the wet etching in the previous process.

[0005] However, due to the gap defects in the edge area, the bonding force between the carrier wafer and the device wafer in this area is insufficient, so when trimming, the edge of the device wafer is easily damaged due to uneven stress, thereby affecting the yield and manufacturing efficiency of the product. SUMMARY

[0006] The present application provides a wafer trimming method, which can solve the problem that the wafer trimming method provided in the related art is prone to damage. The method comprises:

[0007] The edge cutting treatment is performed by the first cutter head, the edge cutting treatment cuts into the predetermined depth of the edge cutting area of the wafer carrier, and a groove cut mark is formed in the wafer carrier;

[0008] The edge cutting treatment is performed by the second cutter head, the device wafer in the edge cutting area is removed, and the width of the second cutter head is greater than the width of the first cutter head;

[0009] The device wafer is bonded to the wafer carrier, and the device wafer and the wafer carrier overlap in the center from the top view, the edge cutting area is an annular area from the edge of the wafer carrier along the radius inward by a predetermined distance, and there is a gap between the surfaces of the device wafer and the wafer carrier in the edge cutting area.

[0010] In some embodiments, the width of the first cutter head is 0.1mm to 2mm.

[0011] In some embodiments, the thickness of the device wafer is 550μm to 800μm.

[0012] In some embodiments, the groove cut mark is annular from the top view, and the inner diameter of the groove cut mark coincides with the inner diameter of the edge cutting area.

[0013] In some embodiments, the radius of the wafer carrier is greater than the radius of the device wafer.

[0014] In some embodiments, the device wafer has undergone wet etching in the previous process.

[0015] The technical scheme of the present application at least has the following advantages:

[0016] In the edge cutting process of the wafer, the edge of the device wafer in the edge cutting area is first cut off by the first cutter head, and a groove cut mark is formed in the wafer carrier, and then the edge of the device wafer is removed by the second cutter head, because the edge with the gap is cut off by the first cutter head, the device wafer will not be stressed in the process of cutting the edge by the second cutter head, the probability of damage caused by uneven stress is reduced, and the yield and production efficiency of the product are improved to a certain extent. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0018] Figure 1is a flow chart of a cutting edge method of a wafer provided by an exemplary embodiment of the present application;

[0019] Figure 2 is a schematic cross-sectional view before cutting edge;

[0020] Figure 3 is a schematic top view before cutting edge;

[0021] Figure 4 is a schematic partial cross-sectional view of cutting edge by a first cutting head;

[0022] Figure 5 is a schematic partial cross-sectional view after cutting edge by the first cutting head;

[0023] Figure 6 is a schematic top view after cutting edge by the first cutting head;

[0024] Figure 7 is a schematic partial cross-sectional view of cutting edge by a second cutting head;

[0025] Figure 8 is a schematic partial cross-sectional view after cutting edge by the second cutting head;

[0026] Figure 9 is a schematic top view after cutting edge by the second cutting head. DETAILED DESCRIPTION

[0027] The technical solutions in the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0028] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0029] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0030] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0031] refer to Figure 1 It illustrates a flowchart of a wafer trimming method provided in an exemplary embodiment of this application, such as... Figure 1 As shown, the method includes:

[0032] Step S1: The first cutting head is used to cut the edge to a predetermined depth in the edge area of ​​the wafer, forming a groove in the wafer.

[0033] like Figure 2 and Figure 3 As shown, device wafer 100 is bonded to carrier wafer 200. Viewed from above, the centers of device wafer 100 and carrier wafer 200 overlap. The radius R2 of carrier wafer 200 is larger than the radius R1 of device wafer 100. The dicing region 201 is an annular region extending inwards from the edge of carrier wafer 200 along its radius by a predetermined distance r1. Within the dicing region 201, a gap exists between the contacting surfaces of device wafer 100 and carrier wafer 200. Device wafer 100 has undergone wet etching in the front-end process (gap is created due to surface unevenness, and wet etching exacerbates the gap, easily causing breakage during dicing). Device wafer 100 can be a wafer used to form BSICIS, and its thickness is between 550 micrometers (μm) and 800 micrometers.

[0034] like Figure 4 , Figure 5 and Figure 6As shown, after edge trimming by the first cutting head 301, the cutting head cuts into the edge trimming area 201 to a predetermined depth into the carrier wafer 200, forming a groove cut 401 in the carrier wafer 200. Since the groove cut 401 extends into the carrier wafer 200, the edge of the device wafer 200 is cut off. Optionally, the depth h1 of the cut 401 is the target depth of the carrier wafer 200 in this edge trimming process; optionally, the width w1 of the first cutting head 301 is 0.1 mm to 2 mm. Viewed from a top angle, the groove cut 401 is annular, and its inner diameter coincides with the inner diameter of the edge trimming area 201, that is, the groove cut 401 is an annular ring with an inner diameter of (R2-r1) and an outer diameter of R2.

[0035] Step S2: The device wafer in the edge-cutting area is removed by the second cutting head. The width of the second cutting head is greater than the width of the first cutting head.

[0036] like Figure 7 , Figure 8 and Figure 9 As shown, after the edge cutting is performed by the second cutting head 302, the device wafer 100 in the edge cutting area 201 is removed and the carrier wafer 200 in the edge cutting area 201 is cut to the target depth h1. The width w2 of the second cutting head 302 is greater than the width w1 of the first cutting head 301.

[0037] In summary, in the embodiments of this application, during the edge trimming process of the wafer, the edge of the device wafer in the trimming area is first cut off by a narrower first cutting head, forming a groove in the carrier wafer. Then, the edge of the device wafer is removed by a wider second cutting head. Since the edge with gaps is cut off by the first cutting head, the device wafer will not be subjected to force during the edge trimming process using the second cutting head, reducing the probability of damage caused by uneven force, and improving the product yield and production efficiency to a certain extent.

[0038] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method of trimming a wafer, characterized by, The method comprises: performing a dicing process by a first blade to cut into a predetermined depth of a dicing area of a carrier wafer to form a groove cut in the carrier wafer; performing a dicing process by a second blade to remove a device wafer of the dicing area, the second blade having a width greater than the first blade; wherein the device wafer is a wafer formed with semiconductor devices, the device wafer is bonded to the carrier wafer and the center of the device wafer and the carrier wafer overlap when viewed from a top view, the dicing area is an annular area from an edge of the carrier wafer along a radius of the carrier wafer by a predetermined distance inwardly, and a gap exists between surfaces of the device wafer and the carrier wafer in contact within the dicing area.

2. The method of claim 1, wherein, The width of the first blade is 0.1mm to 2mm.

3. The method of claim 2, wherein, The thickness of the device wafer is 550μm to 800μm.

4. The method of claim 3, wherein, The groove cut is annular when viewed from a top view, and the inner diameter of the groove cut coincides with the inner diameter of the dicing area.

5. The method according to any one of claims 1 to 4, characterized in that, The radius of the carrier wafer is greater than the radius of the device wafer.

6. The method of claim 5, wherein, The device wafer has undergone a wet etching process in a previous process.

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