Fused instruction processor

Abstract

This invention provides a fusion instruction processor, belonging to the field of processor technology, comprising: a decoding module, multiple conflict detection modules, a first arithmetic module, and an instruction execution module. The decoding module decodes the fusion instruction to be sent to obtain the expected occupancy times. The multiple conflict detection modules, based on the received expected occupancy times and the locally stored sequence of occupied times, obtain conflict judgment results regarding whether resource conflicts exist in the target hardware unit, and send control signals. The first arithmetic module, based on the control signals received from the conflict detection modules, determines whether to send the decoded fusion instruction to be sent. The fusion instruction processor provided by this invention effectively avoids resource conflicts during processor operation at the fine-grained level, from each micro-operation of the fusion instruction to each hardware unit of the execution module, significantly improving computational efficiency, reducing power consumption, maximizing hardware performance, and substantially increasing the number of instructions executed per clock cycle.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and more particularly to a fused instruction processor. Background Technology

[0002] Resource conflict, also known as structural conflict or structural hazard, refers to a situation where two processor instructions simultaneously use the same hardware.

[0003] The main methods to resolve resource conflicts include: (1) increasing the number of hardware units; (2) long pipeline blocking method, where after each instruction is sent, instructions using the same hardware are not allowed to be sent until the sent instruction has been executed and the execution result has been written back; (3) fully pipelined method, which is to use an arithmetic logic unit (ALU) design with equal-length pipelines.

[0004] However, increasing the number of hardware components can lead to excessively high hardware costs; long pipeline blocking limits processor performance, preventing the processor from fully utilizing its hardware capabilities; and while full pipelined architecture avoids resource conflicts, it cannot leverage the performance of fused instructions.

[0005] Therefore, it is necessary to provide a fusion instruction processor that can fully utilize hardware performance without increasing hardware costs. Summary of the Invention

[0006] This invention provides a fused instruction processor to address the shortcomings of existing technologies in resolving resource conflicts due to increased hardware quantity, long pipeline blocking methods, and fully pipelined methods, thereby achieving a fused instruction processor that can fully utilize hardware performance without increasing hardware costs.

[0007] This invention provides a fused instruction processor, comprising:

[0008] The system comprises a decoding module, multiple conflict detection modules, a first arithmetic module, and an instruction execution module; the instruction execution module includes multiple hardware units for executing micro-operations of fused instructions; each conflict detection module stores a sequence of times when a hardware unit is occupied;

[0009] The decoding module is used to decode the fusion command to be sent, obtain the expected occupancy times, and send the expected occupancy times to the conflict detection modules; the expected occupancy times are the times when each hardware unit is occupied when the fusion command to be sent is executed.

[0010] The conflict detection module is used to obtain a conflict judgment result on whether there is a resource conflict in the target hardware unit based on the received expected occupancy time and the occupancy time sequence stored locally, and to send a control signal based on the conflict judgment result; the received expected occupancy time is the expected time when the target hardware unit is occupied when the fusion instruction to be sent is executed; the occupancy time sequence stored locally is the time sequence when the target hardware unit is occupied when the fusion instruction has been sent is executed.

[0011] The first arithmetic module is used to determine whether to send the decoded fusion command to be sent based on the control signals sent by each conflict detection module.

[0012] The instruction execution module is used to execute the decoded fusion instruction to be sent.

[0013] According to a fusion instruction processor provided by the present invention, the control signal is a transmit enable signal or a transmit disable signal; the conflict detection module further includes: a second arithmetic module;

[0014] The second calculation module is used to obtain the conflict judgment result based on the AND operation result of the received expected occupancy time and the occupancy time sequence stored locally;

[0015] The conflict detection module is further configured to send a prohibition signal when the conflict determination result indicates that the target hardware unit has a resource conflict, and to send a permission signal when the conflict determination result indicates that the target hardware unit does not have a resource conflict.

[0016] According to a fusion instruction processor provided by the present invention, the step of determining whether to send the decoded fusion instruction to be sent based on the control signals sent by each conflict detection module includes:

[0017] If all control signals received from the conflict detection modules are permission signals, determine to send the decoded fusion command to be sent;

[0018] If the control signals received from the various collision detection modules include a prohibition signal, it is determined not to send the decoded fusion command to be sent.

[0019] According to a fusion instruction processor provided by the present invention, the conflict detection module includes a resource occupancy register, which is used to store the time sequence of the occupancy of the hardware unit.

[0020] According to a fusion instruction processor provided by the present invention, the bit positions of the resource occupancy register are used to indicate the occupancy time, and the values ​​of the bit positions are used to indicate the occupancy status; the values ​​of each bit position of the resource occupancy register constitute the occupancy time sequence stored locally.

[0021] When the value at the bit position is 1, the target hardware unit is in an occupied state during the occupied time.

[0022] When the value at the bit position is 0, the target hardware unit is in an idle state during the occupancy time.

[0023] According to a fusion instruction processor provided by the present invention, the first arithmetic module is further configured to send a time sequence update signal based on the control signals sent by each conflict detection module; the time sequence update signal is used to instruct each conflict detection module to update the occupied time sequence stored locally.

[0024] According to a fusion instruction processor provided by the present invention, the conflict detection module is further configured to perform a first update operation based on the received expected occupied time and the occupied time sequence stored locally when the received time sequence update signal is a first update signal; and to perform a second update operation based on the occupied time sequence stored locally when the received time sequence update signal is a second update signal.

[0025] The first update signal is sent when all control signals sent by the conflict detection modules received by the first arithmetic module are allow signals; the second update signal is sent when the control signals sent by the conflict detection modules received by the first arithmetic module include prohibit signals.

[0026] According to a fusion instruction processor provided by the present invention, the execution of the first update operation includes: using the received expected occupied time, performing an OR operation on the occupied time sequence stored locally to obtain an intermediate sequence; shifting the intermediate sequence one bit to the right to update the occupied time sequence stored locally.

[0027] The second update operation includes: shifting the locally stored occupied time sequence one position to the right to update the locally stored occupied time sequence.

[0028] According to a fusion instruction processor provided by the present invention, the type of hardware unit includes an arithmetic unit and a write-back unit;

[0029] The type of arithmetic unit includes at least one of a multiplier, an adder, a logic unit, and a post-processing unit.

[0030] According to a fusion instruction processor provided by the present invention, the conflict detection module and the first arithmetic module are integrated on the decoding module.

[0031] The fusion instruction processor provided by this invention translates the expected time occupancy of the micro-operations of each hardware unit in the instruction execution module during the decoding stage, and instantiates conflict detection modules corresponding to each hardware unit to store the time sequence of occupied time when the corresponding hardware unit executes the sent fusion instruction. Furthermore, it determines whether a single hardware unit has resource conflicts based on the expected time occupancy and the time sequence of occupied time. Thus, during the instruction issuance period, it centrally determines whether to send and execute the fusion instruction to be sent based on the resource conflict status of all hardware units. This effectively avoids resource conflict problems during processor operation at the fine-grained level of each micro-operation of the fusion instruction and each hardware unit of the execution module, finely controlling each stage of the pipeline of the instruction execution unit, maximizing the utilization of multi-step pipeline and multi-step data channels, and supporting a single... Resource conflict resolution when modules occupy multiple clock cycles ensures the correct execution of multiple sequentially fused instructions, significantly improving processor efficiency and reducing power consumption. This fully leverages the processor's hardware performance, substantially increasing the number of instructions executed per clock cycle. Resolving resource conflicts eliminates the need for multiple complete hardware instruction execution modules, resulting in low hardware cost and low silicon overhead. Furthermore, by setting up multiple conflict detection modules and a centralized first arithmetic module at the fine-grained level of a single micro-operation or hardware unit, the structure is simple and highly scalable, allowing implementation on sequentially issued processors such as DSPs, ASIPs, and GPUs. Because resource conflict is resolved at the hardware level, processor programming is simplified, enabling programmers to perform programming without requiring in-depth knowledge of the processor's pipeline design. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 This is a data flow example diagram of the vcuml fusion instruction execution.

[0034] Figure 2 This is a data flow example diagram of the vadd fusion command execution.

[0035] Figure 3 This is an example diagram illustrating resource conflicts during the execution of the vcuml and vadd fusion commands.

[0036] Figure 4 This is an example diagram of a fully pipelined instruction fusion pipeline architecture.

[0037] Figure 5 This is one of the structural schematic diagrams of the fusion instruction processor provided by the present invention.

[0038] Figure 6 This is the second schematic diagram of the fusion instruction processor provided by the present invention.

[0039] Figure 7 This is a microarchitecture diagram of the hardware unit used when executing the vcuml fusion instruction and the vadd fusion instruction provided by the present invention.

[0040] Figure 8 This is a clock overhead diagram for 5G applications based on four pipeline design patterns provided by this invention.

[0041] Figure 9 This is a 5G application code overhead diagram of the three pipeline design patterns provided by this invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0043] It should be noted that, in the description of this invention, the term "comprising" or any other variations thereof is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Those skilled in the art will understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0044] The terms "first," "second," etc., used in this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more.

[0045] The following is combined Figures 1-9 This invention describes the fusion instruction processor provided by the present invention.

[0046] In the field of processor technology, a dedicated processor is a specially designed processing unit. While maximizing hardware efficiency, it also introduces challenges related to hardware reliability. Hardware programming for dedicated processors is often highly coupled with the hardware architecture, resulting in high programming complexity and difficulty in fully utilizing the hardware's performance. Instruction fusion units are one type of dedicated processor.

[0047] For user programming and compiler design, most Single Instruction Multiple Data (SIMD) architectures for Digital Signal Processing (DSP) algorithms employ Reduced Instruction Set Computer (RISC) vector instruction architecture. Each instruction specifies relatively few functions and is simple to compile, but this limits the functionality of the DSP.

[0048] Based on application requirements and the instruction fusion approach of Application-Specific Instruction-Set Processors (ASIPs), two or more instructions that meet the fusion criteria or are frequently combined are merged into a single instruction, also known as a fused instruction. Executing a fused instruction is equivalent to sending and executing multiple fused instructions simultaneously, allowing the processor to complete the same task in less time.

[0049] After instruction fusion, the RISC data path is synthesized into a multi-pipeline, multi-step data path. The instruction fusion pipeline also has different execution entry and exit points. The pipeline depth occupied by each fused instruction is different, and the resources occupied are different. This leads to a significant increase in the complexity of resource management and data path control within the Arithmetic Logic Unit (ALU), and resource conflicts occur more and more frequently.

[0050] Figure 1 This is an example diagram of the data flow during the execution of the vcuml fusion instruction, as shown below. Figure 1 As shown, the dashed line represents the path used by the internal hardware units (also known as hardware resources) of the ALU when the vcuml fusion instruction is executed, and the solid line represents the unused path of the internal hardware units of the ALU when the vcuml fusion instruction is executed. When the vcuml fusion instruction is executed, the instruction fetch (IF), decode (ID), and fetch (DF) are performed in sequence and distributed to the ALU. The multiplier (Mul), adder 1 (Add1), and post-processing unit (Post) in the ALU are used in sequence to perform operations, and finally the data is written back (WB).

[0051] Figure 2 This is an example diagram of the data flow during the execution of the vadd fusion command, such as... Figure 2 As shown, the dashed line represents the path used by the internal hardware unit of the ALU when the vadd fusion instruction is executed, and the solid line represents the unused path of the internal hardware unit of the ALU when the vadd fusion instruction is executed. When the vadd fusion instruction is executed, the instruction fetch (IF), decode (ID), and fetch (DF) are performed in sequence and then distributed to the ALU. The adder 1 (Add1) and the post-processing unit (Post) in the ALU are used in sequence for operation, and finally the data is written back (WB).

[0052] Figure 3 This is an example diagram illustrating resource conflicts during the execution of the vcuml and vadd fusion instructions, as shown below. Figure 3 As shown, the vcuml fusion command in Instruction fetching begins at any moment, and the vadd fusion instruction is performed at... Instruction fetching begins at each step, and as the fetching and decoding processes progress, vcuml fuses instructions within... Adder 1 needs to be occupied at all times, while the vadd fusion instruction is in Adder 1 (Add1) also needs to be used at all times, that is, in At that moment, resource conflicts occurred.

[0053] Without proper control over resource conflicts, processor performance cannot be improved; in fact, it can lead to errors. Therefore, processors must have mechanisms to manage hardware resources to ensure correct operation and maximize the performance of their hardware units.

[0054] The fused instruction ALU data path has different ALU entries, and resource conflicts may occur at each stage of the execution pipeline. Distributed structural conflict judgment at each stage of the pipeline would make processor control very complex, requiring backpressure step by step forward from the conflict point. It is crucial to find a simpler mechanism to resolve resource conflicts.

[0055] The simplest way for a processor to resolve resource conflicts is through long pipeline blocking. This means that after each fusion instruction that occupies the target ALU is sent, no other fusion instructions occupying that target ALU are allowed to be sent until the result of the fusion instruction is written back, thus ensuring no resource conflicts occur. For example, if the `vcuml` and `vadd` fusion instructions occupy the same ALU unit, once the `vcuml` fusion instruction starts occupying the ALU unit, the `vadd` fusion instruction will not be sent to the ALU unit until its result is written back. However, long pipeline blocking limits processor performance, preventing the processor from fully utilizing its hardware capabilities.

[0056] Another way to resolve resource conflicts is through a fully streamlined approach. Figure 4 This is an example diagram of a fully pipelined instruction fusion pipeline architecture, such as... Figure 4 As shown, solid lines are data lines and dashed lines are control lines. The fully pipelined approach uses an ALU design with equal-length pipelines, which is simple to compile and avoids structural hazards, but cannot fully utilize the performance of fused instructions.

[0057] In response to the resource management challenges brought about by instruction fusion pipelined ALU units, advanced compilers in the industry also employ software instruction orchestration and hardware conflict control to resolve resource conflicts.

[0058] Software instruction orchestration involves statically analyzing the potential for resource conflicts using the compiler and preventing structural hazards by rearranging instruction order and inserting NOP instructions. However, this increases instruction usage and lacks runtime dynamic analysis capabilities.

[0059] Hardware conflict control primarily involves increasing the number of hardware units. Advanced processors employ an out-of-order (OoO) architecture using the Tomasulo dynamic scheduling algorithm. These processors typically have multiple identical ALU units to handle concurrency and use a coarse-grained, overall ALU unit control approach for resource conflict control. In other words, by increasing the number of hardware units, renaming and reordering buffers are used to address data dependencies such as "read-after-write" (RAW) and "write-after-write" (WAW), and coarse-grained, unified scheduling of multiple ALU units resolves resource conflicts. However, increasing the number of hardware units significantly increases hardware costs, and the added hardware is often not fully utilized.

[0060] Therefore, it is necessary to provide a fusion instruction processor that can fully utilize hardware performance without increasing hardware costs to solve the resource conflict problem.

[0061] Figure 5 This is one of the structural schematic diagrams of the fused instruction processor provided by the present invention, such as... Figure 5 As shown, the fusion instruction processor includes, but is not limited to, a decoding module 510, multiple conflict detection modules 520, a first arithmetic module 530, and an instruction execution module 540.

[0062] The instruction execution module 540 includes multiple hardware units 541. The hardware units 541 are units used to execute micro-operations of fused instructions, including but not limited to at least one of arithmetic units such as multipliers, adders, logic operators (such as AND, OR, XOR and NOT), and post-processing units.

[0063] Each conflict detection module 520 stores a sequence of times when a hardware unit 541 is occupied.

[0064] The decoding module 510 is used to perform decoding operations on the fusion command to be sent, obtain each expected occupancy time, and send each expected occupancy time to each conflict detection module 520; the expected occupancy time is the time when each hardware unit 541 is occupied when the fusion command to be sent is executed.

[0065] The conflict detection module 520 is used to obtain a conflict judgment result on whether there is a resource conflict in the target hardware unit based on the received expected occupancy time and the occupancy time sequence stored locally, and to send a control signal based on the conflict judgment result; the received expected occupancy time is the expected time when the target hardware unit is occupied when the fusion instruction to be sent is executed; the occupancy time sequence stored locally is the time sequence when the target hardware unit is occupied when the fusion instruction has been sent is executed.

[0066] The first arithmetic module 530 is used to determine whether to send the decoded fusion command to be sent based on the control signals sent by each conflict detection module 520.

[0067] The instruction execution module 540 is used to execute the decoded fusion instruction to be sent.

[0068] Specifically, structurally, the fused instruction processor includes a decoding module 510, multiple conflict detection modules 520, a first arithmetic module 530, and an instruction execution module 540. The instruction execution module 540 includes multiple hardware units 541 for executing micro-operations of fused instructions. The multiple conflict detection modules 520 operate in parallel, while the multiple hardware units 541 within the instruction execution module 540 operate serially.

[0069] A fusion instruction typically consists of multiple micro-operations (such as addition, multiplication, AND, OR, etc.), each of which is executed by a hardware unit 541 in the instruction execution module 540. Each conflict detection module 520 stores a sequence of times when a hardware unit 541 is occupied, that is, a sequence of times when the hardware unit 541 is occupied while executing one or more sent fusion instructions.

[0070] For example, if the instruction execution module 540 of the fused instruction processor includes n hardware units 541, namely hardware unit 1 to hardware unit n, n distributed conflict detection modules 520, namely conflict detection module 1 to conflict detection module n, are obtained through instantiation or other means. Each hardware unit 541 has its corresponding conflict detection module 520, and the conflict detection module 520 stores the time sequence of the corresponding hardware unit 541 being occupied when executing one or more fused instructions that have been sent. That is, conflict detection module 1 stores the time sequence of the occupied hardware unit 1, conflict detection module n stores the time sequence of the occupied hardware unit n, and hardware unit 1 is also the target hardware unit of conflict detection module 1, and hardware unit n is also the target hardware unit of conflict detection module n.

[0071] When the fusion instruction processor is working, the decoding module 510 fetches the fusion instruction to be sent. In addition to performing the regular decoding operation on the fusion instruction to be sent, it also generates the expected time when each hardware unit 541 in the instruction execution module 540 is expected to be occupied when the fusion instruction to be sent is executed. That is, it generates the expected occupancy time for each hardware unit 541 and sends each expected occupancy time to each conflict detection module 520.

[0072] Understandably, after each expected occupancy time is sent to each conflict detection module 520, the hardware unit 541 corresponding to the expected occupancy time received by each conflict detection module 520 is consistent with the hardware unit 541 corresponding to the occupancy time sequence stored locally in the conflict detection module 520.

[0073] Since the timing of the occupancy of the fused instruction relative to all hardware units 541 in the instruction execution module 540 needs to be determined during the decoding stage, the resource occupancy of each fused instruction will be clearly defined after the hardware design is finalized. During the operation of the fused instruction processor, the hardware resource occupancy of each fused instruction is predictable, and the timing and which hardware unit will be occupied by the fused instruction can be determined through decoding.

[0074] For each conflict detection module 520, each module determines whether a resource conflict exists in the corresponding target hardware unit based on the received expected occupancy time and the locally stored sequence of occupied times, obtains a conflict determination result, and sends different control signals to the first arithmetic module according to the different conflict determination results. Therefore, each conflict detection module 520 is only responsible for verifying the resource conflict status of the target hardware unit.

[0075] For example, if the expected occupancy time received by the conflict detection module A is "4", it indicates that when the fusion instruction to be sent is executed, the corresponding target hardware unit a will be occupied at time "4". At the same time, the occupancy time sequence stored locally by the conflict detection module A indicates that when the instruction execution module executes the sent fusion instruction, the target hardware unit a will be occupied at time "1" and time "4". Thus, the conflict judgment result that the target hardware unit a has a resource conflict is obtained.

[0076] For example, if the expected occupancy time received by the conflict detection module B is "3", the occupancy time sequence stored locally by the conflict detection module B indicates that when the instruction execution module executes the sent fusion instruction, the target hardware unit b will be occupied at time "2" and time "4", then the conflict judgment result that the target hardware unit b does not have a resource conflict is obtained.

[0077] For example, if the expected occupancy time received by the conflict detection module C is "0", it means that the corresponding target hardware unit c will not be occupied when the fusion command to be sent is executed, and the conflict judgment result that there is no resource conflict in the target hardware unit c can be obtained.

[0078] The first arithmetic module 530, based on the control signals received from the conflict detection modules 520, centrally determines whether there are resource conflicts among the hardware units of the instruction execution module when executing the fusion instruction to be sent. If there are no resource conflicts among all hardware units, the first arithmetic module is allowed to send the decoded fusion instruction to be sent; if any hardware unit has a resource conflict, the first arithmetic module is not allowed to send the decoded fusion instruction to be sent.

[0079] After receiving the decoded fusion instruction to be sent, the instruction execution module 540 retrieves operands from storage such as cache or resource occupancy register, so that the various hardware units 541 within the instruction execution module 540 can execute the fusion instruction to be sent and obtain the instruction execution result.

[0080] Optionally, the instruction execution module 540 is an arithmetic logic unit (ALU).

[0081] While existing resource conflict resolution methods include coarse-grained hardware resource scheduling techniques—such as long pipeline blocking methods that schedule hardware resources at the coarse-grained level of the entire fused instruction, and methods that resolve resource conflicts by increasing the number of hardware units at the coarse-grained level of the overall ALU—there is no solution that resolves resource conflicts at a finer grained level than that of the entire fused instruction or the overall ALU. Furthermore, coarse-grained resource conflict resolution methods do not translate the expected resource occupancy time of the fused instruction during the decoding stage.

[0082] The fusion instruction processor provided by this invention translates the expected time occupancy of the micro-operations of each hardware unit in the instruction execution module during the decoding stage, and instantiates conflict detection modules corresponding to each hardware unit to store the time sequence of occupied time when the corresponding hardware unit executes the sent fusion instruction. Furthermore, it determines whether a single hardware unit has resource conflicts based on the expected time occupancy and the time sequence of occupied time. Thus, during the instruction issuance period, it centrally determines whether to send and execute the fusion instruction to be sent based on the resource conflict status of all hardware units. This effectively avoids resource conflict problems during processor operation at the fine-grained level of each micro-operation of the fusion instruction and each hardware unit of the execution module, finely controlling each stage of the pipeline of the instruction execution unit, maximizing the utilization of multi-step pipeline and multi-step data channels, and supporting a single... Resource conflict resolution when modules occupy multiple clock cycles ensures the correct execution of multiple sequentially fused instructions, significantly improving processor efficiency and reducing power consumption. This fully leverages the processor's hardware performance, substantially increasing the number of instructions executed per clock cycle. Resolving resource conflicts eliminates the need for multiple complete hardware instruction execution modules, resulting in low hardware cost and low silicon overhead. Furthermore, by setting up multiple conflict detection modules and a centralized first arithmetic module at the fine-grained level of a single micro-operation or hardware unit, the structure is simple and highly scalable, allowing implementation on sequentially issued processors such as DSPs, ASIPs, and GPUs. Because resource conflict is resolved at the hardware level, processor programming is simplified, enabling programmers to perform programming without requiring in-depth knowledge of the processor's pipeline design.

[0083] As an optional embodiment, the type of the hardware unit includes an arithmetic unit and a write-back unit; the type of the arithmetic unit includes at least one of a multiplier, an adder, a logic unit, and a post-processing unit.

[0084] The read / write ports of fused instructions for different registers are also a type of hardware resource. If the execution results of different fused instructions are written back simultaneously, causing a write port conflict, this also constitutes a resource conflict.

[0085] The fused instruction processor provided by this invention effectively avoids resource conflicts during processor operation at the fine-grained level of each micro-operation of the fused instruction and each hardware unit of the execution module. Furthermore, by including the write-back unit as a hardware unit, it can simultaneously resolve the structural conflict between the arithmetic unit and the write-back unit, thereby further ensuring the correct execution of the fused instructions and fully utilizing the processor's hardware performance.

[0086] Figure 6 This is the second schematic diagram of the fused instruction processor provided by the present invention, as shown below. Figure 6 As shown, the control signal is a signal to allow transmission or a signal to prohibit transmission; the collision detection module 520 also includes: a second calculation module 610;

[0087] The second calculation module 610 is used to obtain the conflict judgment result based on the AND operation result of the received expected occupancy time and the occupancy time sequence stored locally;

[0088] The conflict detection module 520 is further configured to send a prohibition signal when the conflict determination result indicates that the target hardware unit has a resource conflict, and to send a permission signal when the conflict determination result indicates that the target hardware unit does not have a resource conflict.

[0089] The second operation module 610 is implemented based on AND operation.

[0090] Specifically, for each conflict detection module 520, a second calculation module 610 needs to be set up to perform an AND operation on the received expected occupancy time and the occupancy time sequence stored locally to obtain the AND operation result, and then obtain the conflict judgment result based on the AND operation result.

[0091] Generally speaking, if the result of the AND operation is 0, it indicates that the target hardware unit does not have a hardware conflict; if the result of the AND operation is non-zero, it indicates that the target hardware unit has a hardware conflict.

[0092] For example, if the expected occupancy time received by conflict detection module A indicates that the target hardware unit a will be occupied at time 3 when executing the fusion command to be sent, and the value of the expected occupancy time is "3", and the occupancy time sequence stored locally by conflict detection module A also indicates that the target hardware unit a will also be occupied at time 3 when executing the sent fusion command, and the value of time "3" in the occupancy time sequence is non-zero, then the second operation module of conflict detection module A performs a bitwise AND operation on the received expected occupancy time value "3" and the non-zero value of time "3" in the occupancy time sequence. The result is non-zero, and the conflict judgment result is that there is a hardware conflict in the target hardware unit a.

[0093] For example, if the expected occupancy time received by the conflict detection module B indicates that the target hardware unit b will be occupied at time 3 when executing the fusion command to be sent, and the value of the expected occupancy time is "3", and the occupancy time sequence stored locally by the conflict detection module B also indicates that the target hardware unit b will not be occupied at time 3 when executing the sent fusion command, and the value of time "3" in the occupancy time sequence is "0", then the second calculation module of the conflict detection module B performs a bitwise AND operation on the received expected occupancy time value "3" and the value of time 3 "0" in the occupancy time sequence, and the result is 0, thus the conflict judgment result is that there is no hardware conflict in the target hardware unit b.

[0094] For example, if the expected occupancy time received by the conflict detection module C indicates that the target hardware unit c will not be occupied when executing the fusion command to be sent, the value of the expected occupancy time is "0". Then, the second calculation module of the conflict detection module C performs a bitwise AND operation between the received expected occupancy time value "0" and the occupied time sequence. The result is 0, and the conflict judgment result is that there is no hardware conflict in the target hardware unit c.

[0095] After the second operation module performs an AND operation to obtain a conflict judgment result, the conflict detection module sends a prohibition signal to the first operation module if the conflict judgment result indicates that there is a resource conflict in the target hardware unit; and sends a permission signal to the first operation module if the conflict judgment result indicates that there is no resource conflict in the target hardware unit.

[0096] For example, the signal to prohibit sending is "0", and the signal to allow sending is "1".

[0097] Understandably, the input to each collision detection module 520 is the time value at which the execution of the fusion instruction S to be sent will occupy the corresponding target hardware unit. If the execution of the fusion instruction S to be sent does not use the target hardware unit, then the time value input to the collision detection module 520 is "0". Simultaneously, the output of each collision detection module 520 is a control signal, specifically a signal to disable transmission or a signal to enable transmission.

[0098] The fusion instruction processor provided by this invention, by setting a second arithmetic module in each conflict detection module to perform a bitwise AND operation between the expected occupancy time and the locally stored sequence of occupied times, and by determining a conflict based on the calculation result to output a prohibition signal or a permission signal, achieves distributed determination of whether there is a resource conflict in each hardware unit within each conflict detection module. This fine-grained control of each stage of instruction execution ensures the correct execution of multiple sequential fusion instructions, significantly improves the processor's computational efficiency, reduces the processor's power consumption, and fully utilizes the processor's hardware performance.

[0099] Based on the above embodiments, as an optional embodiment, determining whether to send the decoded fusion command to be sent based on the control signals received from each conflict detection module includes:

[0100] If all control signals received from the conflict detection modules are permission signals, determine to send the decoded fusion command to be sent;

[0101] If the control signals received from the various collision detection modules include a prohibition signal, it is determined not to send the decoded fusion command to be sent.

[0102] The first calculation module needs to coordinate the judgment results of all conflict detection modules. Only when there are no resource conflicts in the hardware units corresponding to each conflict detection module can the correct execution of the fusion instruction to be sent be ensured, and the decoded fusion instruction to be sent be determined.

[0103] Specifically, after receiving control signals from each conflict detection module, the first arithmetic module determines whether to send the decoded fusion instruction to be sent. If all control signals received by the first arithmetic module from each conflict detection module are allow signals, it means that there will be no hardware conflict in executing the fusion instruction to be sent, and it is determined that the decoded fusion instruction to be sent can be sent. If the control signals received by the first arithmetic module from each conflict detection module include prohibit signals, it means that at least one hardware unit in the instruction execution module will experience a hardware conflict when executing the fusion instruction to be sent, and it is determined that the decoded fusion instruction to be sent cannot be sent.

[0104] Optionally, the first calculation module is implemented based on AND operations.

[0105] Combination Figure 6 As shown, taking the prohibition signal as "0" and the allow signal as "1" as an example, the first arithmetic module 530 performs an AND operation on the control signals sent by each conflict detection module. If all the control signals sent by each conflict detection module are the allow signal "1", the AND operation result is 1, which means that there is no resource conflict among all hardware units, and the decoded fusion command to be sent is confirmed. If the control signals sent by each conflict detection module include the prohibition signal "0", it means that at least one hardware unit has a resource conflict, and the decoded fusion command to be sent is not sent.

[0106] Optionally, if it is determined that the decoded fusion instruction to be sent will be sent, the first arithmetic module sends a confirmation signal to the decoding module, and the decoding module responds to the confirmation signal and sends the decoded fusion instruction to the instruction execution module; if it is determined that the decoded fusion instruction to be sent will not be sent, the first arithmetic module sends a confirmation signal not to be sent to the decoding module, and the decoding module responds to the confirmation signal not to be sent, thus preventing the sending of the decoded fusion instruction.

[0107] As an optional embodiment, the collision detection module and the first arithmetic module are integrated on the decoding module.

[0108] Optionally, if it is determined that the decoded fusion instruction to be sent will be sent, the decoding module directly passes the decoded fusion instruction to the instruction execution module; if it is determined that the decoded fusion instruction to be sent will not be sent, the first arithmetic module sends a backpressure instruction to the decoding module to prevent the sending of the decoded fusion instruction.

[0109] The fusion instruction processor provided by this invention centrally determines whether there is a resource conflict in a hardware unit based on the control signals sent by each conflict detection module through the first arithmetic module, and confirms the transmission of the fusion instruction to be sent if no resource conflict occurs in any hardware unit. It controls each stage of the instruction execution pipeline with fine granularity, which can ensure the correct execution of multiple sequential fusion instructions, fully improve the processor's computing efficiency and reduce the processor's operating power consumption, and give full play to the processor's hardware performance.

[0110] Based on the above embodiments, as an optional embodiment, the conflict detection module includes a resource occupancy register, which is used to store the time sequence of when the hardware unit is occupied.

[0111] Specifically, in combination Figure 6 As shown, each conflict detection module 520 includes a resource occupancy register 620, which stores a sequence of times when a hardware unit is occupied, in order to determine the resource conflict of the target hardware unit by combining the expected occupancy time of the input conflict detection model.

[0112] Based on the above embodiments, as an optional embodiment, the bit positions of the resource occupancy register are used to indicate the occupancy time, and the values ​​of the bit positions are used to indicate the occupancy status; the values ​​of each bit position of the resource occupancy register constitute the occupancy time sequence stored locally.

[0113] When the value at the bit position is 1, the target hardware unit is in an occupied state during the occupied time.

[0114] When the value at the bit position is 0, the target hardware unit is in an idle state during the occupancy time.

[0115] Specifically, the resource occupancy register uses a bitmap to record the occupancy time sequence of hardware units. Each bit position in the resource occupancy register represents the occupancy time when the target hardware unit executes the sent fusion command. When the bit position value is 1, the target hardware unit is occupied during the corresponding occupancy time. When the bit position value is 0, the target hardware unit is idle during the corresponding occupancy time, i.e., not occupied. Thus, the values ​​of each bit position in the resource occupancy register constitute the occupancy time sequence stored locally in the conflict detection module, representing the occupancy status of the target hardware unit.

[0116] Correspondingly, each time a new fusion command is to be sent, the decoding module decodes the command and generates a bitmap value representing the expected time slot occupied by the hardware unit during execution. After each expected time slot is sent to the corresponding conflict detection module, the first arithmetic module within each conflict detection module performs a bitwise AND operation based on the received bitmap-form expected time slot and the locally stored sequence of occupied time slots to determine whether there is a resource conflict in the target hardware unit.

[0117] For example, the local occupancy time sequence stored in the resource occupancy register of the conflict detection module A is "0000101100", which means that the target hardware unit a will be occupied at times 3, 4, and 6 when executing the sent fusion instruction. When a new fusion instruction S to be sent is to be sent, the decoding module decodes the fusion instruction S to be sent and generates the expected occupancy time of each hardware unit.

[0118] If the expected time of occupation sent to the conflict detection module A is "0", it means that the execution of the fusion instruction to be sent does not require the target hardware unit a. The expected time of occupation "0" is ANDed with the value of any bit position in the occupied time sequence "0000101100". The result of the AND operation is 0, which determines that there is no resource conflict in the target hardware unit a.

[0119] If the expected occupancy time sent to the conflict detection module A is "2", the expected occupancy time "2" is ANDed with the second-to-last "0" in the occupied time sequence "0000101100". If the result of the AND operation is 0, it is determined that there is no resource conflict in the target hardware unit a.

[0120] If the expected time of occupation sent to the conflict detection module A is "4", the expected time of occupation "4" is ANDed with the "1" in the fourth-to-last position of the occupied time sequence "0000101100". The result of the AND operation is 1, which determines that there is a resource conflict in the target hardware unit a when the fusion instruction to be sent is executed.

[0121] The fusion instruction processor provided by this invention uses registers within each conflict detection module to store the occupancy time sequence of hardware units. The register bit position represents the occupancy time of the hardware unit, and the bit position value represents the occupancy status of the hardware unit. This achieves local storage of the occupancy time sequence, enabling distributed determination of resource conflicts for each hardware unit within each conflict detection module. It provides fine-grained control over each stage of the instruction execution pipeline and maximizes the efficiency of the second arithmetic module within the conflict detection module in performing a bitwise AND operation between the expected occupancy time and the locally stored occupancy time sequence. This ensures the correct execution of multiple sequential fusion instructions, significantly improving processor efficiency and reducing power consumption, thus fully utilizing the processor's hardware performance.

[0122] Based on the above embodiments, as an optional embodiment, the first calculation module is further configured to send a time sequence update signal according to the control signals sent by each conflict detection module; the time sequence update signal is used to instruct each conflict detection module to update the occupied time sequence stored locally.

[0123] Specifically, in combination Figure 6 As shown, the first calculation module 530, based on the control signals received from each conflict detection module 520, not only determines whether to send the fusion instruction to be sent, but also sends the same time sequence update signal to each conflict detection module 520 to instruct each conflict detection module 520 to update the occupied time sequence stored locally.

[0124] Based on the above embodiments, as an optional embodiment, the conflict detection module is further configured to perform a first update operation based on the received expected occupied time and the occupied time sequence stored locally when the received time sequence update signal is a first update signal; and to perform a second update operation based on the occupied time sequence stored locally when the received time sequence update signal is a second update signal.

[0125] The first update signal is sent when all control signals sent by the conflict detection modules received by the first arithmetic module are allow signals; the second update signal is sent when the control signals sent by the conflict detection modules received by the first arithmetic module include prohibit signals.

[0126] The first update operation is different from the second update operation; the first update signal is different from the second update signal.

[0127] Specifically, in combination Figure 6 As shown, if the control signals received by the first calculation module 530 from each collision detection module 520 are all allow signals, it determines to send the fusion command to be sent and returns a first update signal to each collision detection module 520. After receiving the first update signal, each collision detection module 520 simultaneously performs a first update operation on the occupied time sequence based on the received expected occupied time and the occupied time sequence stored locally, so that the updated occupied time sequence conforms to the execution status of the fusion command to be sent and the fusion command already sent.

[0128] If the control signals received by the first calculation module 530 from each conflict detection module 520 include a prohibition signal, it determines that the fusion instruction to be sent will not be sent, and returns a second update signal to each conflict detection module 520. After receiving the second update signal, each conflict detection module 520 performs a second update operation on the occupied time sequence according to the occupied time sequence stored locally, so that the updated occupied time sequence conforms to the execution status of the sent fusion instruction, and is suitable for continuing to determine whether there is a resource conflict and whether to send the decoded fusion instruction in the next time moment.

[0129] The fusion instruction processor provided by this invention, through a first arithmetic module, returns different update signals to each conflict detection module based on whether there is a resource conflict during the execution of the fusion instruction to be sent. This updates the occupied time sequence stored in each conflict detection module according to the actual sending status of the fusion instruction to be sent. The updated occupied time sequence can be used to continue judging whether there is a resource conflict and whether to send the decoded fusion instruction in the next moment, so as to achieve the correct execution of multiple sequential fusion instructions, significantly improve the processor's computing efficiency and reduce the processor's operating power consumption, and give full play to the processor's hardware performance.

[0130] Based on the above embodiments, as an optional embodiment, the first update operation includes: using the received expected occupied time, performing an OR operation on the occupied time sequence stored locally to obtain an intermediate sequence; shifting the intermediate sequence one bit to the right to update the occupied time sequence stored locally.

[0131] The second update operation includes: shifting the locally stored occupied time sequence one position to the right to update the locally stored occupied time sequence.

[0132] Specifically, in combination Figure 6As shown, after the conflict detection module 520 receives the first update signal, it performs the first update operation. Using the received expected occupancy time, it performs an OR operation on the occupancy time sequence stored locally to obtain an intermediate sequence. Then, it shifts each time in the intermediate sequence one bit to the right to obtain the updated occupancy time sequence, which represents the occupancy status of the target hardware unit when the fusion command has been sent and the fusion command to be sent is executed.

[0133] For example, the expected occupied time received by collision detection module A is "1", the occupied time sequence stored locally in collision detection module A is "0000101100", and the received time sequence update signal is the first update signal. When updating the occupied time sequence, the expected occupied time "1" and the last and first "0" in the occupied time sequence "0000101100" are ORed to obtain the intermediate sequence "0000101101", and then a right shift operation is performed to obtain the updated occupied time sequence "0000010110".

[0134] After receiving the second update signal, the conflict detection module 520 performs the second update operation, shifting each time point in the locally stored occupied time sequence by one bit to obtain the updated occupied time sequence, which represents the occupied status of the target hardware unit when the fusion command has been sent for execution.

[0135] For example, if the expected occupied time received by the conflict detection module B is "3", and the occupied time sequence stored locally in the conflict detection module B is "0000101100", the time sequence update signal received by the conflict detection module B must be the second update signal. When updating the occupied time sequence, each time in the occupied time sequence "0000101100" is directly shifted one position to the right to obtain the updated occupied time sequence "0000010110".

[0136] The fusion instruction processor provided by this invention sets a resource occupancy register in the conflict detection module. The bit position of the resource occupancy register represents the occupancy time, and the value of the bit position represents the occupancy status. When updating the occupancy time sequence, only a simple OR operation and a right shift by one bit are required to update the occupancy time sequence according to the actual sending status of the fusion instructions. This allows the processor to continuously analyze the occupancy status of each hardware unit, fully improve the processor's computing efficiency, reduce the processor's operating power consumption, give full play to the processor's hardware performance, and significantly increase the number of instructions executed per clock cycle.

[0137] The fusion instruction processor provided by this invention is equivalent to designing a Hardware Resource Table (HRT) to solve resource and structural conflicts of hardware units, including arithmetic units and write-back units.

[0138] A fused instruction processor This includes a set of multiple fusion instructions. And a vector representing all hardware units in the hardware execution module. ,in Indicates the first One hardware unit.

[0139] Each fusion instruction There is a resource requirement for each hardware unit and the timing of the requirement for each hardware unit, and each fusion instruction. The occupied hardware units can be modeled as a one-dimensional resource table. One-dimensional resource table The width is the number of hardware units for data path resources in the processor. Indicates fusion command After sending When will each hardware unit be occupied in a relative time period?

[0140] That is, in the case of a fusion command to be sent In resource conflict resolution, the inputs of each conflict detection module together constitute... The output of each collision detection module indicates whether that module grants permission to send the fusion command. send.

[0141] For fused instruction processors A two-dimensional resource table can be constructed based on the resource usage of all hardware units. Among them, two-dimensional resource table The width is the number of hardware units for data path resources in the processor, and the length is the fused instruction set. The length of time occupied by all hardware units, Indicates the future fusion instruction set During execution The collection of time occupied by each hardware unit .

[0142] Correspondingly, each resource occupancy register in the fused instruction processor provided by this invention collectively records the occupancy time sequence of each hardware unit, including the arithmetic unit and the write-back unit. The occupancy time sequences in all resource occupancy registers together constitute... .

[0143] Therefore, when a fusion instruction When execution is required, the conditional expression for its ability to be emitted is: Fusion command After transmission, the time it occupies each hardware unit is recorded in the time sequence of each hardware unit's occupation, thereby dynamically establishing the hardware resource table for each hardware unit. Table 1 is the hardware overhead table of the hardware resource table provided by this invention. As shown in Table 1, building a hardware resource table in the fusion processor instead of multiple instruction execution modules has the advantages of low hardware cost and low silicon overhead.

[0144] Table 1 Hardware Overhead Table of Hardware Resources

[0145]

[0146] Figure 7 This is a microarchitecture diagram of the hardware unit executing the vcuml fusion instruction and the vadd fusion instruction provided by the present invention, combined with... Figure 3 and Figure 7 As shown, the vcuml fusion instruction and the vadd fusion instruction are two consecutively sent fusion instructions. The one-dimensional resource table shows the hardware units occupied and the time taken by the vcuml fusion instruction. For {multiplier: 1, adder 1: 2, adder 2: 0, adder 3: 0, post-processing: 3, write-back: 4}, the one-dimensional resource table consists of the hardware units and time occupied by the vadd fusion instruction. The expression is {multiplier: 0, adder 1: 1, adder 2: 0, adder 3: 0, post-processing: 2, write-back: 3}.

[0147] The vcuml fusion command and the vadd fusion command are sent sequentially. The vcuml fusion command is then... Instruction fetching begins at any moment, and the vadd fusion instruction is performed at... The finger is taken out at a certain time, usually at Resource conflicts occur constantly.

[0148] Table 2 shows the hardware resource changes during the execution of the vcuml and vadd fusion instructions by the fusion instruction processor provided by this invention. As shown in Table 2, when the vcuml and vadd fusion instructions are executed using the fusion instruction processor provided by this invention, in... At that moment, the vcuml fusion command was issued. The occupancy time information of each hardware unit is updated to the resource occupancy register of each conflict detection module, and the two-dimensional hardware resource table of the fusion instruction processor is used. Correspondingly including Information on the time of occupation.

[0149] Table 2. Hardware resource changes during the execution of vcuml and vadd fusion instructions by the fusion instruction processor.

[0150]

[0151] exist At that moment, the vadd fusion instruction is sent as a fusion instruction. The fusion instruction processor detects resource conflicts in adder 1, the post-processing unit, and the write-back unit. and If a conflict exists, the vadd fusion instruction cannot be sent, and the occupied time sequence stored in the resource occupancy register of each conflict detection unit is updated.

[0152] exist At that moment, the vadd fusion instruction was still pending fusion instruction. The fusion instruction processor detected no resource conflict and sent the vadd fusion instruction. The occupancy time information of each hardware unit is updated to the resource occupancy register of each conflict detection module, and the two-dimensional hardware resource table of the fusion instruction processor is used. Correspondingly including Information on the time of occupation.

[0153] The fusion instruction processor continues to execute the vcuml fusion instruction and the vadd fusion instruction, in At that moment, the vcuml fusion instruction finished executing. At that moment, the vadd fusion command was completed.

[0154] As can be seen, the fusion instruction processor provided by this invention can effectively avoid resource conflicts.

[0155] To better demonstrate the performance and power consumption advantages of the fusion instruction processor provided by this invention when processing a large number of fusion instructions, the pipeline of the execution module was designed using four modes: Baseline (BL) mode, Fully Pipelined (FP) mode, Full Blocking (FS) mode, and Auto Detection (AD) mode based on the fusion instruction processor provided by this invention. Performance and power consumption analyses were then performed on the four modes.

[0156] The execution modules for each different pipeline architecture are implemented using Verilog programming. Verilator is used to compile different pipeline architectures, and then the executable files compiled by different test programs are used as test stimuli. The running results are obtained by counting the number of clock cycles of the program.

[0157] In the performance analysis, real 5G applications were used for simulation evaluation. Performance analysis was conducted from two perspectives: runtime and post-compiled code overhead. The benchmark test cases included the symbol processing program of a 5G mobile communication base station, encompassing the Physical Downlink Shared Channel (PDSCH), Physical Uplink Shared Channel (PUSCH), Physical Random Access Channel (PRACH), Physical Uplink Control Channel (PUCCH), Demodulation Reference Signal (DMRS), Precode, and Sounding Reference Signal (SRS). The benchmark test cases were programmed using inline functions, and core operations were accelerated using vector instructions, allowing for a better analysis of the overall performance improvement achieved by using the fused instruction processor provided by this invention.

[0158] Figure 8 This is a clock overhead diagram for 5G applications based on four pipeline design patterns provided by this invention, such as... Figure 8 As shown, the runtime results of 5G applications under different pipeline modes, normalized to BL mode, reveal that AD mode significantly improves the performance of 5G applications, reducing runtime by an average of 8.70% compared to BL mode, 30.2% compared to FS mode, and 16.1% compared to FP mode. In 5G applications, FS and FP modes show a performance decrease compared to BL mode, while the instruction fusion pipeline AD mode, which uses a conflict detection module and a first arithmetic module, demonstrates a performance improvement.

[0159] Figure 9 This is a 5G application code overhead diagram of the three pipeline design patterns provided by this invention, such as... Figure 9 As shown, the code overhead of 5G applications differs in BL mode, FP mode and AD mode. When the fused instruction processor uses multiple conflict detection modules for automated dependency analysis, AD no longer requires software insertion of NOPs, thus reducing code overhead by 28.8% compared to FP mode; and AD does not need to decompose the fused instructions into multiple instructions, thus reducing code overhead by 27.1% compared to BL mode.

[0160] In power consumption analysis, the dynamic energy consumed by each algorithm can be calculated by using the clock count obtained from the post-synthesis simulation results and the power consumption obtained from the simulation using the PrimeTime tool.

[0161] FS mode and AD mode use the same ALU and register resources, so their energy consumption is the same when running the same program. In BL mode, each fused instruction operation requires the use of an additional WB pipeline register after decomposition. In FP mode, additional pipeline registers are needed to handle unused ALU resources, and the dynamic reversal of pipeline registers will increase dynamic power consumption.

[0162] Table 3 shows the power consumption of different operator ALUs in the three pipelined design modes provided by this invention. As shown in Table 3, the power consumption of the execution modules for Finite Impulse Response (FIR), 4×4 Determinant (DET), 12×12×12 Matrix-Matrix Multiplication (MMM), 64-point FFT, 4×4 QR decomposition based on Gram-Schmidt Orthogonalization (SMT), 4×4 LU decomposition, 2×2 QR decomposition based on Householder (HH) transformation, and 4×4 QR decomposition based on Givens (GS) rotation is decomposed under the three pipelined modes of FP, BL, and AD. Specifically, it includes the power consumption of registers, multipliers, adders, and logic operations. Although the power consumption of logic operations is relatively low and not obvious in the table, the average power consumption of AD mode is reduced by 24.4% compared to FP mode and by 17.2% compared to BL mode.

[0163] Table 3. Power consumption of different operator execution modules in three pipeline design patterns.

[0164]

[0165] Table 4 shows the power consumption of different application execution modules under the three pipeline design modes provided by this invention. As shown in Table 4, under the three pipeline modes of FP mode, BL mode and AD mode, simple instruction fusion (FP mode and FS mode) does not improve the energy efficiency of the processor. The instruction fusion pipeline needs to be optimized in design. The average energy consumption of AD mode, which uses a conflict detection module, is reduced by 40.0% compared with FP mode and by 18.3% compared with BL mode.

[0166] Table 4. ALU power consumption in different applications using three pipeline design patterns.

[0167]

[0168] In summary, the fused instruction processor provided by this invention is optimized for long pipelined processors. It effectively avoids resource conflicts during processor operation at a fine-grained level, from each micro-operation of the fused instruction to each hardware unit of the execution module. It controls each stage of the pipeline of the instruction execution unit in a fine-grained manner, and has the characteristics of extremely low cost and significant performance improvement. It can not only ensure the correct operation of the processor, but also improve the performance of the processor and reduce power consumption. It can be widely used in sequential issue processors such as DSP / ASIP / GPU.

[0169] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0170] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fused instruction processor, characterized in that, include: The system comprises a decoding module, multiple conflict detection modules, a first arithmetic module, and an instruction execution module; the instruction execution module includes multiple hardware units for executing micro-operations of fused instructions; each conflict detection module stores a sequence of times when a hardware unit is occupied; The decoding module is used to decode the fusion command to be sent, obtain the expected occupancy times, and send the expected occupancy times to the conflict detection modules; the expected occupancy times are the times when each hardware unit is occupied when the fusion command to be sent is executed. The conflict detection module is used to obtain a conflict judgment result on whether there is a resource conflict in the target hardware unit based on the received expected occupancy time and the occupancy time sequence stored locally, and to send a control signal based on the conflict judgment result; the received expected occupancy time is the expected time when the target hardware unit is occupied when the fusion instruction to be sent is executed; the occupancy time sequence stored locally is the time sequence when the target hardware unit is occupied when the fusion instruction has been sent is executed. The first arithmetic module is used to determine whether to send the decoded fusion command to be sent based on the control signals sent by each conflict detection module. The instruction execution module is used to execute the decoded fusion instruction to be sent; The conflict detection module is further configured to perform a first update operation based on the received expected occupied time and the occupied time sequence stored locally when the received time sequence update signal is a first update signal; If the received time sequence update signal is a second update signal, a second update operation is performed based on the occupied time sequence stored locally; The first update signal is sent when all control signals sent by the conflict detection modules received by the first arithmetic module are allow signals; the second update signal is sent when the control signals sent by the conflict detection modules received by the first arithmetic module include prohibit signals. The first update operation includes: using the received expected occupied time, performing an OR operation on the locally stored occupied time sequence to obtain an intermediate sequence; shifting the intermediate sequence one bit to the right to update the locally stored occupied time sequence. The second update operation includes: shifting the locally stored occupied time sequence one position to the right to update the locally stored occupied time sequence.

2. The fused instruction processor according to claim 1, characterized in that, The control signal is a signal to allow transmission or a signal to prohibit transmission; the collision detection module further includes: a second calculation module; The second calculation module is used to obtain the conflict judgment result based on the AND operation result of the received expected occupancy time and the occupancy time sequence stored locally; The conflict detection module is further configured to send a prohibition signal when the conflict determination result indicates that the target hardware unit has a resource conflict, and to send a permission signal when the conflict determination result indicates that the target hardware unit does not have a resource conflict.

3. The fused instruction processor according to claim 2, characterized in that, The step of determining whether to send the decoded fusion command to be sent based on the control signals received from each conflict detection module includes: If all control signals received from the conflict detection modules are permission signals, determine to send the decoded fusion command to be sent; If the control signals received from the various collision detection modules include a prohibition signal, it is determined not to send the decoded fusion command to be sent.

4. The fused instruction processor according to claim 2, characterized in that, The conflict detection module includes a resource occupancy register, which is used to store the time sequence of when the hardware unit is occupied.

5. The fused instruction processor according to claim 4, characterized in that, The bit positions of the resource occupancy register are used to indicate the occupancy time, and the values ​​of the bit positions are used to indicate the occupancy status; the values ​​of each bit position of the resource occupancy register constitute the occupancy time sequence stored locally. When the value at the bit position is 1, the target hardware unit is in an occupied state during the occupied time. When the value at the bit position is 0, the target hardware unit is in an idle state during the occupancy time.

6. The fused instruction processor according to claim 5, characterized in that, The first calculation module is further configured to send a time sequence update signal according to the control signals sent by each conflict detection module; the time sequence update signal is used to instruct each conflict detection module to update the occupied time sequence stored locally.

7. The fused instruction processor according to claim 1, characterized in that, The types of hardware units include arithmetic units and write-back units; The type of arithmetic unit includes at least one of a multiplier, an adder, a logic unit, and a post-processing unit.

8. The fused instruction processor according to claim 1, characterized in that, The conflict detection module and the first arithmetic module are integrated into the decoding module.

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