Vector data processor, instruction processing method, system on chip

Abstract

The embodiment of the present application provides a vector data processor, an instruction processing method and a system on chip, after a vector instruction needing vector operation is acquired, a vector mode configuration information is used to determine an instruction calculation mode of the vector instruction, the vector configuration information includes configuration information of a data path of current vector execution adjusted by a data block size, according to the instruction calculation mode, one execution pipeline or multiple execution pipelines in the N execution pipelines are determined for the vector instruction, and the execution pipelines in the vector floating point execution unit respectively execute vector operations corresponding to the vector instruction. The scheme provided by the present application supports a mixed width calculation mode, so that the vector data processor has the ability to adjust the data path mode of current vector execution by the data block size, improves the throughput of processing small block data, and improves the performance of a large bit width vector register architecture processor when processing a software load with a mixed size data block characteristic.

Description

Technical Field

[0001] This invention relates to the field of electronic information technology, and in particular to a vector data processor, instruction processing method, and system-on-a-chip. Background Technology

[0002] With the development of semiconductor technology and processor architecture technology, vector data processors, due to their high performance and low power consumption, have been widely used in various fields such as high-performance computing, artificial intelligence, and edge computing. Vector data processors are also known as vector accelerators.

[0003] In the application scenarios of vector data processors, data centers are a typical example. The core tasks of data centers include AI inference and training, media processing and transcoding, encryption and decryption operations, etc. The related software workloads exhibit high data parallelism, meaning they require performing the same or highly similar operations on large amounts of different data. The characteristics of data center software workloads dictate that server-level high-performance processors not only need to possess efficient scalar computation capabilities but also efficient vector computation capabilities.

[0004] To meet the demands of software workloads for parallel computing capabilities, the rapid development of artificial intelligence and large language models has led to an increasing demand for parallel computing capabilities in server-grade high-performance processors. This also presents a greater challenge for processor design manufacturers to design high-performance vector computing architectures. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide an instruction processing method to solve some or all of the above-mentioned problems.

[0006] According to a first aspect of the present invention, an instruction processing method is provided applied to a vector data processor, the vector data processor including a vector register, a vector floating-point unit, and an issue unit. The vector register has a first bit width, the vector floating-point unit stores N execution pipelines, each execution pipeline supports a maximum data bit width of a second bit width, the first bit width is greater than the second bit width, and the sum of the N second bit widths is greater than the first bit width, where N is a multiple of 2. The method includes:

[0007] Obtain the vector commands that need to be performed on the vector operations;

[0008] Based on the vector mode configuration information, the instruction calculation mode of the vector instruction is determined, and the vector configuration information includes configuration information for adjusting the data path of the current vector execution by adjusting the data block size;

[0009] Based on the instruction calculation mode, determine one or more execution pipelines from the N execution pipelines for the vector instruction;

[0010] The execution pipelines in the vector floating-point execution unit perform vector operations corresponding to the vector instructions.

[0011] According to a second aspect of the present invention, a vector data processor is provided, the vector data processor including a vector register, a vector floating-point unit, and a transmit unit, the vector register having a first bit width, the vector floating-point unit storing N execution pipelines, each execution pipeline supporting a maximum data bit width of a second bit width, the first bit width being greater than the second bit width, and the sum of the N second bit widths being greater than the first bit width, where N is a multiple of 2, the method comprising:

[0012] The instruction fetch unit is used to fetch vector instructions that need to be performed on vector operations;

[0013] A mode configuration unit is used to determine the instruction calculation mode of the vector instruction based on vector mode configuration information, wherein the vector mode configuration information includes configuration information for adjusting the data path of the current vector execution by adjusting the data block size;

[0014] An instruction dispatch unit is configured to determine one or more execution pipelines from the N execution pipelines for the vector instruction based on the instruction calculation mode.

[0015] The vector floating-point unit is used to control the execution pipeline to perform vector operations corresponding to the vector instructions.

[0016] According to a third aspect of the present invention, a system-on-a-chip is provided, the system-on-a-chip comprising:

[0017] The control unit and multiple on-chip components, the multiple on-chip components including a vector data processor;

[0018] The control unit is used to control and manage the plurality of on-chip components, and the vector data processor is used to execute computer programs / instructions that, when executed by the vector data processor, implement the method described in the first aspect of the present invention.

[0019] The vector data processor and instruction processing method provided in this embodiment of the invention, after obtaining the vector instruction that needs to be performed on the vector operation, determine the instruction calculation mode of the vector instruction according to the vector mode configuration information, and adjust the configuration information of the data path for the current vector execution by adjusting the data block size;

[0020] According to the instruction calculation mode, one or more execution pipelines from the N execution pipelines are determined for the vector instruction; the execution pipelines in the vector floating-point execution unit respectively execute vector operations corresponding to the vector instruction. The solution provided by this invention supports a mixed-width calculation mode, enabling the vector data processor to adjust the data path mode of the current vector execution by the data block size, improving the throughput of processing small data blocks, and improving the performance of large-width vector register architecture processors when handling software loads with mixed-size data block characteristics. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0022] Figure 1 This is a schematic diagram of the architecture of a vector data processor provided in an embodiment of the present invention;

[0023] Figure 2 This is a flowchart illustrating one embodiment of the instruction processing method provided in this invention.

[0024] Figure 3 This is a flowchart illustrating one embodiment of the instruction processing method provided in this embodiment;

[0025] Figure 4 This is a data processing diagram of the instruction processing method provided in this embodiment;

[0026] Figure 5 This is another data processing diagram of the instruction processing method provided in this embodiment;

[0027] Figure 6 This is another data processing diagram of the instruction processing method provided in this embodiment;

[0028] Figure 7 This is a schematic diagram of the structure of a system-on-a-chip provided in one embodiment of this specification. Detailed Implementation

[0029] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art should fall within the protection scope of the present invention.

[0030] The following explains some of the technologies described in this application.

[0031] Vector data processor: A vector data processor is a dedicated piece of hardware that can perform the same operation on multiple data elements simultaneously. It efficiently processes large-scale data by driving multiple parallel computing units with a single instruction.

[0032] Vector operations: Vector operations in a processor refer to using a single instruction to perform the same operation on a group of data (called vectors) simultaneously, thereby greatly improving data processing throughput, and are especially suitable for handling intensive tasks such as scientific computing and graphics.

[0033] Floating-point numbers: Floating-point numbers are a method of approximating real numbers in a computer using scientific notation. They encode a value by combining a sign bit, an exponent bit, and a mantissa bit, thus balancing the range and precision of representation within a fixed length of storage space.

[0034] PPA: PPA is a core trade-off metric in chip design, referring to performance, power consumption, and area. Improving one metric (such as performance) often leads to a deterioration in other metrics (such as power consumption and area). Therefore, the design goal of vector data processors is to achieve the optimal balance among these three.

[0035] In related technologies, vector register width represents the maximum data bit width that a vector register can store, and also reflects the data width that a vector processor can process in a single instruction, which means higher throughput and energy efficiency. For example, a processor with a 256-bit wide vector register architecture executes a single instruction twice as efficiently as a 128-bit wide architecture, meaning that a 128-bit wide architecture processor would need two instructions to complete the same computation as a 256-bit wide architecture processor. At the same time, large-bit-width vectors can utilize memory bandwidth more efficiently and make fuller use of the data bus width between the processor and memory, reducing the number of memory accesses compared to scalar processors and lowering the pressure on the memory subsystem.

[0036] The adoption of large-width vector registers has become a mainstream trend in server-grade high-performance processors. However, the width of vector registers cannot be increased indefinitely. Excessively large vector register widths pose significant challenges to processor timing constraints, control area, and power consumption. Products using this technology have encountered situations where uncontrollable power consumption and excessively high processor temperatures necessitate frequency throttling, ultimately impacting performance. Therefore, current mainstream vector data processors are almost all 256-bit or 128-bit wide.

[0037] However, in compiler-vectorized programs, not all data blocks in the vector being processed are multiples of 256 bits in size. Many software workloads inevitably process both large and small data blocks simultaneously. Due to PPA limitations, the vector instruction throughput of a 256-bit wide vector register architecture processor is typically lower than that of a 128-bit wide vector register architecture processor. Therefore, a 256-bit wide vector register architecture processor will perform worse than a 128-bit wide vector register architecture processor when processing small data blocks—vectors with a width less than 256 bits.

[0038] like Figure 1 As shown, this embodiment of the invention provides a vector data processor, also known as a vector accelerator. Figure 1 This is a logical architecture diagram of a vector data processor provided in an embodiment of the present invention. Figure 1 As can be seen, the vector data processor 100 provided in this application embodiment may include a vector floating-point unit 105, a vector register 106, a vector floating-point execution unit 107, and also includes an instruction fetch unit 101, a mode configuration unit 102, an instruction dispatch unit 103, an instruction dispatch queue unit 104, and a miscellaneous register 108 that needs to be configured.

[0039] Typically, the instruction dispatch unit can distribute decoded instructions to different execution pipelines to ensure that the instructions can be correctly processed and executed by hardware resources.

[0040] The Vector & Floating-Point Execution Unit (VFPU) can be used to perform vector and floating-point operations, including vector addition, vector multiplication, floating-point addition, and floating-point multiplication. The VFPU supports efficient parallel computing and is particularly suitable for applications such as scientific computing, image processing, and machine learning.

[0041] Vector processing registers (VPRs) can store vector data and intermediate results, supporting vector operations. Vector registers typically have a large capacity, accommodating multiple data elements to support efficient parallel processing.

[0042] In an embodiment of this application, the vector register 106 has a first bit width VLEN. The vector floating-point unit stores N execution pipelines. The maximum data bit width supported by each execution pipeline is a second bit width DPLEN. The first bit width VLEN is greater than the second bit width DPLEN. The sum of N second bit widths is greater than the first bit width. That is, DPLEN*N is greater than VLEN, where N is a multiple of 2.

[0043] according to Figure 1 The vector data processor architecture shown has an instruction fetching unit 101 that first fetches the vector instructions that need to be used for vector operations; then, the mode configuration unit 102 determines the instruction calculation mode of the vector instructions according to the vector mode configuration information, which includes configuration information for adjusting the data path of the current vector execution by adjusting the data block size.

[0044] The instruction dispatch unit 103 can determine one or more execution pipelines from the N execution pipelines for the vector instruction according to the instruction calculation mode;

[0045] The execution pipeline in the vector floating-point unit 107 of the vector floating-point unit 105 performs vector operations corresponding to the vector instructions. Finally, the vector operation results are written back to the vector register 106.

[0046] In the above embodiments, the mode configuration unit 102 can read pre-stored vector mode configuration information from the miscellaneous register 108. For example, the vector mode configuration information may be vector element width, vector length, predicate processing method, etc., as well as rules for configuring instruction processing methods based on this information.

[0047] The vector data processor in this embodiment, operating in a hybrid width computation mode, can process large blocks of data with a width of VLEN with low throughput; this computation mode is called the long bit-width computation mode. It can also process small blocks of data with a bit width of DPLEN with high throughput. The vector data processor can adjust the data path mode of the current vector execution by adjusting the data block size, thereby improving the throughput for processing small blocks of data and enhancing the performance of the large bit-width vector register architecture processor when handling software workloads with mixed-size data block characteristics.

[0048] It should be noted that the names of the different units in the above architecture are only for logical distinction and do not represent strict distinctions between each unit.

[0049] Figure 2 This is a flowchart of an instruction processing method based on the aforementioned vector data processor architecture, consisting of... Figure 2 As can be seen, the instruction processing method provided in this embodiment may include:

[0050] S201: Obtain the vector command that needs to be performed on the vector;

[0051] For example, the instruction fetching unit or other data access unit with similar functions may be responsible for reading the vector instructions that need to be performed on the vector from the cache.

[0052] In different embodiments, decoding is required after obtaining the vector instructions, which will not be elaborated here.

[0053] S202: Determine the instruction calculation mode of the vector instruction based on the vector mode configuration information, wherein the vector mode configuration information includes configuration information for adjusting the data path of the current vector execution by adjusting the data block size.

[0054] For example, vector mode configuration information can be written into the setting register of the vector data processor. The logical mode configuration unit can read the vector mode configuration information from the register and then determine the instruction calculation mode for the vector instructions that require vector operations.

[0055] The instruction calculation mode of the vector instruction is determined based on at least one of the vector length configuration information and predicate processing method in the vector mode configuration information.

[0056] For example, the vector mode configuration information indicates that the current processor is processing a vector of length A, and the A mode is configured.

[0057] The current processor is processing a vector of length B; configure mode B.

[0058] The current processor predicate processing mode is C, the vector length is D, and the configuration is D mode.

[0059] Different modes can correspond to different launch queues, and different launch queues correspond to different execution pipelines.

[0060] For example, vector configuration mode information in a variable-length vector architecture processor may include information such as vector length, element bit width, and predicate processing method. For example, in a RISC-V architecture processor, this includes information such as Selected Element Width (SEW) and Vector Register Group Multiplication (LMUL).

[0061] Based on the vector mode configuration information, the vector instructions that need to be performed vector operations are tagged, and the tags represent the calculation mode of the instructions.

[0062] For example, determining the instruction calculation mode of the vector instruction based on the vector mode configuration information may involve tagging the vector instructions that need to perform vector operations based on the vector mode configuration information, and using the tags to characterize the instruction calculation mode.

[0063] This scheme allows instructions to be tagged based on this information. The tags represent the instruction's computation mode, and these tags are recognized by the vector processor to determine the instruction's issuance and execution methods. In this scheme, setting the instruction's computation mode and tagging it can be done in the following ways:

[0064] The calculation mode can be explicitly configured via software hints or automatically assigned by hardware recording configuration information;

[0065] Depending on the stage of instruction execution in the vector processor, instruction tagging can occur before instruction issuance, such as during instruction decoding; that is, tagging is done when decoding the vector instruction that requires vector operations. Alternatively, it can occur after instruction issuance, where the instruction dispatch unit tags the vector instruction requiring vector operations based on vector mode configuration information after the vector instruction enters the issuance queue; the vector floating-point unit then selects the corresponding execution pipeline for execution based on the tag.

[0066] The specific timing of the tagging instruction can be determined based on the specific vector data processor microarchitecture design.

[0067] S203: Based on the instruction calculation mode, determine one or more execution pipelines among the N execution pipelines for the vector instruction;

[0068] Based on the preceding example, this step may include allocating a launch queue for the vector instruction according to the instruction calculation mode; then, according to the instruction calculation mode corresponding to each launch queue, launching the vector instruction in the launch queue to one or more of the N execution pipelines in the vector floating-point unit. Corresponding to the preceding description, in this method, the tagging of the vector instruction occurs before instruction launch; that is, first, a tag is allocated to the vector instruction according to the instruction calculation mode; then, the launch queue unit identifies the tag; the launch queue unit determines the launch mode and execution mode of the vector instruction based on the tag indication. Finally, the launch queue unit launches the vector instruction in the launch queue to one or more of the N execution pipelines in the vector floating-point unit according to the tag indication.

[0069] In another implementation, the tagging action occurs after the instruction is issued. In this implementation, after the vector instruction enters the issuance queue, the instruction distribution unit tags the vector instruction that needs to perform vector operations according to the vector mode configuration information; the vector floating-point unit selects the corresponding execution pipeline to execute according to the tag.

[0070] S204: The execution pipeline in the vector floating-point execution unit performs vector operations corresponding to the vector instructions respectively.

[0071] For example, the execution pipeline of the vector floating-point arithmetic unit in the vector floating-point unit performs vector operations corresponding to the vector instructions respectively.

[0072] More specifically, this step may further include the vector floating-point arithmetic unit executing vector operation instructions, sending the vector instructions to the corresponding operator engine, the operator engine performing the corresponding vector operation on the vector instructions, and the operator engine writing the vector operation result of the vector instructions back to the vector register.

[0073] Through the instruction processing method provided in the above embodiments, the vector data processor in this embodiment with a mixed-width computation mode can process large blocks of data with a data width of VLEN with low throughput; this computation mode is called the long-bit-width computation mode. It can also process small blocks of data with a data bit width of DPLEN with high throughput. The vector data processor can adjust the data path mode of the current vector execution by adjusting the data block size, thereby improving the throughput of processing small blocks of data and improving the performance of the large-bit-width vector register architecture processor when handling software workloads with mixed-size data block characteristics.

[0074] Figure 3 This is a schematic diagram of the data flow pattern for metering data processing according to the instruction processing method provided in the embodiments of this application. Assume that, according to steps S201-S204, the vector data processor has already issued vector instructions to the issuance queue according to the instruction calculation mode label. From issuance to execution in the execution pipeline, depending on the calculation mode, the vector instructions can be issued to 1 to X execution pipelines for execution. For example... Figure 3 The diagram illustrates three possible transmission methods:

[0075] Instructions in issue queue 0 are issued to execution pipeline 0 for execution;

[0076] Instructions in launch queue 1 are launched to execution pipelines 0 and M for execution;

[0077] Instructions in the issue queue N are issued to execution pipeline 0, execution pipeline M, and execution pipeline M+L for execution;

[0078] The computational resources occupied by instructions follow these principles:

[0079] Instructions in smaller computation bit-width modes use fewer execution pipelines to complete the operation;

[0080] Instructions with larger computation bit widths use more execution pipelines to complete the operation;

[0081] Assuming that the maximum data bit width that each execution pipeline can process is DPLEN, it is easy to know Figure 3 In the execution methods shown, the instruction computation mode in issue queue 0 supports a maximum computation width of DPLEN, so only one execution pipeline is needed to complete the corresponding operation; the instructions in issue queue 1 are issued to execution pipeline 0 and execution pipeline M for execution, and the instruction computation mode in issue queue 1 supports a maximum computation width of 2*DPLEN, so two execution pipelines are needed to complete the operation; the instructions in issue queue 2 are issued to execution pipeline 0, execution pipeline M and execution pipeline M+L for execution, and the instruction computation mode in issue queue 1 supports a maximum computation width of 3*DPLEN, so three execution pipelines are needed to complete the operation.

[0082] In another embodiment, due to area and timing limitations, the distance between the launch queue and the corresponding execution pipeline is limited. It is usually not possible to have instructions in multiple computation modes in a single launch queue at the same time. Therefore, the computation mode label of the instruction not only determines the execution method of the execution pipeline, but also determines the way the instruction is enqueued in the launch queue.

[0083] Taking a vector processor architecture with 4 launch queues, 4 execution pipelines, and support for both long-width and short-width instruction computation modes as an example, a possible microarchitectural implementation of the hybrid width computation mode is as follows: Figures 3-5 As shown. The maximum computational bit width supported by the long bit width computation mode is the vector processor bit width VLEN, and the maximum computational bit width supported by the short bit width computation mode is DPLEN, where VLEN=2*DPLEN.

[0084] According to the vector configuration mode, if the current configured vector length is DPLEN, it is a short bit width calculation mode; if the current configured vector length is VLEN, it is a long bit width calculation mode. The vector length in the configuration mode determines the width of vector data that the processor can process at one time. By distinguishing between the two calculation modes, different execution pipeline resources can be allocated to execute the corresponding instructions according to the calculation data width requirements, thereby improving the utilization efficiency of the execution pipeline.

[0085] Launch queues 301, 302, 303, and 304 all support launching vector commands to the corresponding pipeline for execution.

[0086] like Figure 4As shown in data stream mode 380, in short bit-width computation mode, instructions can enter any of the four issue queues. The instructions in the corresponding issue queue will be issued to the corresponding pipeline for execution. The correspondence between the two is as follows:

[0087] The instructions in the launch queue 301 are launched to the execution pipeline 300 for execution;

[0088] The instructions in the launch queue 302 are launched to the execution pipeline 310 for execution;

[0089] The instructions in the launch queue 303 are launched to the execution pipeline 320 for execution;

[0090] The instructions in the launch queue 304 are launched to the execution pipeline 330 for execution;

[0091] like Figure 5 and Figure 6 As shown in data flow modes 360 and 370, in long-bit-width computation mode, vector instructions can enter any two of the transmit queues 301 and 302. Instructions in the corresponding transmit queues will be emitted to the corresponding pipelines for execution. In long-bit-width computation mode, the correspondence between the two is as follows:

[0092] The instructions in the launch queue 301 are launched to the execution pipeline 300 for execution, or launched to the execution pipeline group 340 for execution;

[0093] The instructions in the launch queue 302 are launched to the execution pipeline 310 for execution, or launched to the execution pipeline group 350 for execution;

[0094] From the correspondence between the above-mentioned launch queue and the various execution pipelines in the vector floating-point unit, it is easy to see that under this architecture, the short-bit-width computing mode can support the parallel execution of up to 4 vector instructions, and the long-bit-width computing mode can support the parallel execution of up to 2 vector instructions, thereby better leveraging the performance of the vector processor in the short-bit-width vector configuration mode.

[0095] To support both long-bit-width and short-bit-width computation modes, the execution pipeline is designed so that most operator engines can process DPLEN-width data per clock cycle. This design meets the computation bit-width requirements of the short-bit-width computation mode. A small number of operator engines are implemented to process VLEN-width data per clock cycle.

[0096] In the embodiments of this application, the operators in the execution pipeline are divided into symmetric operators and asymmetric operators. Symmetric operators perform symmetric operations, and asymmetric operators perform asymmetric operations.

[0097] When the first bit width VLEN = 2 * DPLEN (second bit width), the symmetric operator performs vector operations with a data bit width of the first bit width VLEN. The high-order bits (high DPLEN bits) and low-order bits (low DPLEN bits) of the first bit width VLEN complete the exact same operation process, and the two operation processes are independent of each other. For example, floating-point or integer vector addition and floating-point or integer vector multiplication are symmetric operations. The high-order bits refer to the high-order bits of the second bit width DPLEN data in the data used to calculate the width of the first bit width VLEN, and the low-order bits refer to the low-order bits of the second bit width DPLEN data in the data used to calculate the width of the first bit width VLEN.

[0098] When asymmetric operators process vector operations with a VLEN bit width, the operations on the high-DPLEN and low-DPLEN bits within the VLEN bit are different and interdependent; the result of the operation on the low-DPLEN bit source data may depend on the operation on the high-DPLEN bit data. For example, vector permutation instructions that reorder vector data are examples of asymmetric operations.

[0099] The second bit width DPLEN is the computation width supported by the execution pipeline, and the first bit width VLEN is the width of the vector register. The high-order data refers to the high-order second bit width DPLEN data in the data used to calculate the width of the first bit width VLEN, and the low-order data refers to the low-order second bit width DPLEN data in the data used to calculate the width of the first bit width VLEN.

[0100] In long-bit-width computation mode, vector instructions performing symmetric operations are split into high and low parts during transmission and sent to two execution pipelines respectively. For example, as shown in data stream mode 370, vector instructions for symmetric operations in transmission queue 301 are simultaneously transmitted to execution pipelines 310 and 320, i.e., execution pipeline group 340 is executed. If the vector instructions perform asymmetric operations, to accelerate such operations, execution pipelines 300 and 310 are designed with dedicated asymmetric operation operator engines for performing asymmetric operations. As shown in data stream mode 360, such instructions are directly sent to execution pipeline 300 or execution pipeline 310 for execution.

[0101] The vector data processor in this embodiment, operating in a hybrid width computation mode, can process large blocks of data with a width of VLEN with low throughput; this computation mode is called the long bit-width computation mode. It can also process small blocks of data with a bit width of DPLEN with high throughput. The vector data processor can adjust the data path mode of the current vector execution by adjusting the data block size, thereby improving the throughput for processing small blocks of data and enhancing the performance of the large bit-width vector register architecture processor when handling software workloads with mixed-size data block characteristics.

[0102] In this embodiment of the invention, different computing modes can be distinguished to allocate different execution pipeline resources to execute corresponding instructions according to the computing data width requirements, thereby improving the utilization efficiency of the execution pipeline.

[0103] For symmetric operations, the long-bit-width computation mode requires two execution pipelines to complete the operation, while the short-bit-width computation mode only requires one execution pipeline. For asymmetric operations, considering the area overhead, only two VLEN-width computational resources are implemented in two execution pipelines.

[0104] Corresponding to the embodiments of the instruction processing method described above, this specification also provides embodiments of on-chip systems. Figure 7 The present specification shows a schematic diagram of a system-on-a-chip (SoC) 700 according to an embodiment of the present specification. The SoC 700 includes, but is not limited to, a control unit 710 and a plurality of on-chip components 720, including a vector data processor 100.

[0105] The control unit 710 is used to control and manage multiple on-chip components 720.

[0106] The vector data processor 100 is used to execute computer programs / instructions, which, when executed by the vector data processor 100, implement the steps of the above-described instruction processing method.

[0107] The System-on-Chip (SoC) 700 is a system-on-a-chip hardware device that integrates a control unit 710 and multiple on-chip components 720. It typically integrates a control unit 710, as well as multiple on-chip components 720 such as a central processing unit, a digital signal processor, a vector data processor, and input / output interfaces (I / O). The SoC 700 can improve performance, reduce power consumption, and reduce physical size, making it suitable for various scenarios such as mobile devices, IoT devices, and embedded systems. The specific embodiments in this application do not limit the specific implementation of the SoC.

[0108] The control unit 710 is a core component of the system-on-a-chip 700, responsible for instruction decoding, execution flow control, and coordination with multiple on-chip components 720. The control unit 710 controls and manages the workflow of multiple on-chip components 720 by sending control signals, ensuring that each on-chip component can correctly complete its tasks in a predetermined order and logic.

[0109] Multiple on-chip components 720 are various functional hardware components in the system-on-a-chip 700, which work together to complete specific tasks or functions. The multiple on-chip components 720 may include, but are not limited to, a central processor, a digital signal processor, a vector data processor, and input / output interfaces.

[0110] The above is an illustrative scheme of a system-on-a-chip (SoC) according to this embodiment. It should be noted that the technical solution of this SoC and the technical solution of the instruction processing method described above belong to the same concept. Details not described in detail in the SoC technical solution can be found in the description of the instruction processing method described above.

[0111] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of the present invention can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present invention.

[0112] The methods described above according to embodiments of the present invention can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored on a remote recording medium or a non-transitory machine-readable medium and subsequently stored on a local recording medium, downloaded over a network. Thus, the methods described herein can be stored as software processing on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the business object switching method described herein. Furthermore, when a general-purpose computer accesses code used to implement the business object switching method shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the business object switching method shown herein.

[0113] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the embodiments of the present invention.

[0114] The above embodiments are only used to illustrate the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present invention, and the patent protection scope of the embodiments of the present invention should be defined by the claims.

Claims

1. An instruction processing method applied to a vector data processor, characterized in that, The vector data processor includes a vector register, a vector floating-point unit, an instruction dispatch unit, and an instruction issue queue unit. The vector register has a first bit width. The vector floating-point unit stores N execution pipelines. The maximum data bit width supported by each execution pipeline is a second bit width. The first bit width is greater than the second bit width, and the sum of N second bit widths is greater than the first bit width, where N is a multiple of 2. The method includes: Obtain the vector commands that need to be performed on the vector operations; Based on the vector mode configuration information, the instruction calculation mode of the vector instruction is determined. The vector mode configuration information includes configuration information for adjusting the data path of the current vector execution by adjusting the data block size. The vector mode configuration information includes vector element width, vector length, predicate processing method, and rules for configuring the instruction processing method based on information including vector element width, vector length, and predicate processing method. Based on the instruction calculation mode, determine one or more execution pipelines from N execution pipelines for the vector instruction; The execution pipeline in the vector floating-point unit performs vector operations corresponding to the vector instructions.

2. The method as described in claim 1, characterized in that, Before determining the instruction calculation mode of the vector instruction based on the vector mode configuration information, the process includes: The vector mode configuration information is read from the configuration information register.

3. The method as described in claim 1 or 2, characterized in that, The step of determining the instruction calculation mode of the vector instruction based on the vector mode configuration information includes: Based on the vector mode configuration information, the vector instructions that need to be performed vector operations are tagged, and the tags represent the calculation mode of the instructions.

4. The method as described in claim 3, characterized in that, The step of determining one or more execution pipelines from the N execution pipelines according to the instruction calculation mode includes: According to the instruction calculation mode, a launch queue is allocated for the vector instruction; According to the instruction calculation mode corresponding to each of the launch queues, the vector instructions in the launch queue are launched to one or more of the N execution pipelines in the vector floating-point unit.

5. The method as described in claim 4, characterized in that, The step of allocating a launch queue for the vector command according to the command calculation mode includes: According to the instruction calculation pattern, assign labels to the vector instructions; The launch queue unit identifies the tag; Based on the label indication, the transmission and execution methods of the vector commands are determined.

6. The method as described in claim 5, characterized in that, The vector instructions in each of the launch queues are launched to one or more of the N execution pipelines in the vector floating-point unit, according to the instruction calculation mode corresponding to each launch queue. include: According to the label indication, the vector commands in the launch queue are launched to one or more of the N execution pipelines in the vector floating-point unit.

7. The method as described in claim 1, characterized in that, The process of obtaining the vector instructions that need to be used for vector operations is further described; then, the process of decoding the vector instructions that need to be used for vector operations is also included. The step of tagging the vector instructions that require vector operations based on the vector mode configuration information includes: When decoding the vector instructions that require vector operations, the vector instructions that require vector operations are tagged.

8. The method as described in claim 3, characterized in that, The step of determining one or more execution pipelines from the N execution pipelines according to the instruction calculation mode includes: After the vector command enters the transmission queue, the vector command that needs to be performed on the vector operation is tagged according to the vector mode configuration information; The corresponding execution pipeline is selected based on the label.

9. The method as described in claim 1, characterized in that, The execution pipeline in the vector floating-point unit performs vector operations corresponding to the vector instructions; further including: The vector floating-point execution unit executes vector operation instructions and sends the vector instructions to the corresponding operator engine, which then performs the corresponding vector operation on the vector instructions. The operator engine writes the vector operation result of the vector instruction back to the vector register.

10. The method as described in claim 9, characterized in that, The operators in the execution pipeline include symmetric operators and asymmetric operators. The symmetric operators perform symmetric operations, and the asymmetric operators perform asymmetric operations.

11. The method as described in claim 10, characterized in that, When the symmetric operator performs vector operations with a data bit width of the first bit, the high-order data and low-order data in the first bit undergo the exact same operation process, and the two operation processes are independent of each other; the high-order data refers to the high-order second-order data in the data used to calculate the width of the first bit, and the low-order data refers to the low-order second-order data in the data used to calculate the width of the first bit. When the asymmetric operator processes the vector operation of the first bit width, the operation processes of the high-bit and low-bit data in the first bit width are different, and the two operations are interdependent. The result of the low-bit source data operation depends on the high-bit data operation.

12. The method as described in claim 1, characterized in that, The step of determining the instruction calculation mode of the vector instruction based on the vector mode configuration information, wherein the vector mode configuration information includes configuration information for adjusting the data path of the current vector execution by adjusting the data block size, further includes: The instruction calculation mode of the vector instruction is determined based on at least one of the vector length configuration information and predicate processing method in the vector mode configuration information.

13. A vector data processor, characterized in that, The vector data processor includes a vector register, a vector floating-point unit, an instruction dispatch unit, and an instruction issue queue unit. The vector register has a first bit width. The vector floating-point unit stores N execution pipelines. Each execution pipeline supports a maximum data bit width of a second bit width. The first bit width is greater than the second bit width, and the sum of the N second bit widths is greater than the first bit width, where N is a multiple of 2. The vector data processor also includes: The instruction fetch unit is used to fetch vector instructions that need to be performed on vector operations; The mode configuration unit is used to determine the instruction calculation mode of the vector instruction based on the vector mode configuration information. The vector mode configuration information includes configuration information for adjusting the data path of the current vector execution by adjusting the data block size. The vector mode configuration information includes vector element width, vector length, predicate processing method, and rules for configuring the instruction processing method based on the information including vector element width, vector length, and predicate processing method. The instruction dispatch unit is used to determine one or more execution pipelines from N execution pipelines for the vector instruction according to the instruction calculation mode. The vector floating-point unit is used to control the execution pipeline to perform vector operations corresponding to the vector instructions.

14. A system-on-a-chip, characterized in that, include: The control unit and multiple on-chip components, the multiple on-chip components including a vector data processor; The control unit is used to control and manage the plurality of on-chip components, and the vector data processor is used to execute a computer program / instruction, which, when executed by the vector data processor, implements the method according to any one of claims 1-12.

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