Parallelized fault tree minimal cut set solving method based on bit set minimal cut set representation

Abstract

The application relates to a parallelized fault tree minimal cut set solving method based on bit set minimal cut set representation, and relates to the field of fault tree analysis. In order to solve the problems of redundant cut set data representation, insufficient parallelization degree, low calculation and storage efficiency and difficulty in supporting efficient solving of large-scale complex systems in the prior art, the method generates a standardized equivalent logical structure concise form fault tree by structurally simplifying and modularly decomposing a fault tree model; an intermediate event and a module solving queue are established according to a topological relationship; a multi-core parallel computing environment is established, a bit set is used to represent a cut set and a two-dimensional data array is formed; a bit-by-bit or broadcast operation is performed for an and gate, and row splicing and merging are performed for an or gate, so that parallel calculation of logical gate outputs is realized; and then non-minimal cut sets are screened out through parallel simplification, and a top event minimal cut set result is output. The application is suitable for fault tree analysis and fast solving of minimal cut sets of complex systems such as nuclear power, aerospace, chemical industry and rail transit.

Description

Technical Field

[0001] This involves the field of fault tree analysis, and in particular, high-efficiency parallelized fault tree cut set solutions. Background Technology

[0002] Fault Tree Analysis (FTA) is one of the most classic and core deductive analysis methods in system reliability and safety engineering. It systematically identifies and analyzes various combinations of potential causes leading to the top-level failure event (the top event) of a system by constructing a top-down logic graph structure. This method can quantitatively assess the failure modes and risk factors of complex systems, and is therefore widely used in high-risk fields such as nuclear power, aerospace, rail transportation, and chemical plants.

[0003] In fault tree analysis, finding the minimum cut set is one of the core tasks. A minimum cut set is the fewest, non-reducible combination of basic events that can lead to the top event. As the system size increases, the number of minimum cut sets grows exponentially, posing a significant computational complexity challenge to fault tree solving, and is considered a typical NP-hard problem. To address this issue, academia and industry have proposed various algorithm and data structure optimization schemes.

[0004] Currently, the mainstream methods for finding the minimum cut set of fault trees mainly include the following categories:

[0005] (1) Logical expansion method based on Boolean algebra.

[0006] These methods recursively deduce the logical relationship between the top event and basic events through Boolean algebraic simplification of logic gates, such as the ascending method and the descending method. This approach was widely used in early fault tree analysis software. Its advantages lie in its simplicity and clear logic, but its disadvantages are also quite obvious: in large-scale systems, the algorithm needs to explicitly store all cutset combinations, leading to severe data redundancy; furthermore, the Boolean simplification operation significantly increases computational complexity and memory consumption when dealing with higher-order event combinations, making it difficult to support cutset generation for complex systems.

[0007] (2) Graph structure method based on binary decision diagram (BDD).

[0008] Cut set optimization (BDD) and its improved forms (such as ZBDD, Zero-suppressed BDD) can efficiently share common substructures between cut sets, and have become one of the main methods for quantitative fault tree analysis in recent years. Typical tools such as OpenFTA all adopt this approach. BDD has significant advantages in compressed storage, enabling the representation of logical functions in a compact graphical structure, thereby reducing storage overhead. However, BDD construction and traversal rely on a large number of recursive and pointer lookup operations, resulting in a highly serialized algorithm structure that is difficult to parallelize effectively. When the size of the fault tree increases further, its memory consumption still grows exponentially, becoming a performance bottleneck.

[0009] (3) Heuristic algorithms based on search and pruning.

[0010] Some studies have attempted to introduce intelligent optimization strategies such as heuristic search, genetic algorithms, or branch and bound methods to reduce the search space. For example, for models in specific fields (such as nuclear power or chemical engineering), constraint pruning and dynamic programming are used to improve the solution speed. However, these algorithms are often customized for specific scenarios and are difficult to generalize; moreover, they are limited by complex recursive call structures and still fail to fully utilize the potential of modern parallel computing hardware (such as GPUs and FPGAs).

[0011] Overall, existing research mainly focuses on Boolean logic optimization, BDD compression, and heuristic search, but there are still significant shortcomings in the following aspects:

[0012] Cut set representation has a loose structure and low storage density, which limits computational and access efficiency;

[0013] The algorithm relies heavily on recursion or depth-first traversal, exhibiting strong serial dependency and making it difficult to achieve effective parallelization.

[0014] It lacks data organization and computation mechanisms that are highly compatible with parallel hardware architectures such as GPUs;

[0015] In large-scale models, the "combinatorial explosion" and memory overflow problems still exist in the cut set generation and simplification stages.

[0016] In summary, existing technologies suffer from redundancy in cutset data representation, insufficient parallelization, and low computational and storage efficiency, making it difficult to support efficient minimum cutset solutions for fault trees in large-scale complex systems. Summary of the Invention

[0017] To address the shortcomings of existing technologies, such as redundant cutset data representation, insufficient parallelization, and low computational and storage efficiency, which make it difficult to support efficient minimum cutset solutions for fault trees in large-scale complex systems, the technical solution provided by this invention is as follows:

[0018] A parallelized fault tree minimum cut set solution method based on bit set minimum cut set representation includes:

[0019] Module.

[0020] Furthermore, a preferred implementation is provided, which uses a GPU thread block structure to divide the logic gate operation tasks and uses a unified memory space to achieve parallel reading and writing of the data array.

[0021] Furthermore, a preferred implementation is provided, which automatically identifies consecutive logic gates of the same type and merges them into a single logic node by traversing the topology of the fault tree, while performing decomposition operations on subtree modules with independent functional boundaries.

[0022] Furthermore, a preferred implementation is provided, in which a globally unique number is assigned to each basic event according to the order of event occurrence, and the numbering results are stored in a mapping table for unified invocation of subsequent bit set mapping and logical operations.

[0023] Furthermore, a preferred implementation is provided: if the number of basic events exceeds the bit width of a bit set unit, multiple bit set units can be concatenated to form a cut set vector, and multiple cut set bit set vectors can be stacked row by row to form a two-dimensional data array structure to represent a cut set set.

[0024] Furthermore, a preferred implementation is provided, in which dimensional expansion and broadcasting mechanisms are used to generate all possible cut set combinations for AND gates, and row concatenation is used to directly output the results for OR gates.

[0025] Based on the same inventive concept, this invention also provides a parallelized fault tree minimum cut set solver based on bit set minimum cut set representation, comprising:

[0026] Establish a parallel computing environment, configure multi-core processing units and thread block structures, complete task partitioning and memory initialization to form a module that can support highly parallel solution of fault trees.

[0027] The input fault tree model is structurally simplified and modularly decomposed. Continuous logic gates are identified and merged. Redundant logic branches are removed according to the Boolean absorption law. Independent subtree modules are divided and the top gate of the module is replaced by a proxy event to obtain standardized fault tree structure data modules.

[0028] Based on the preprocessed fault tree structure, a unique number is assigned to each basic event, a basic event index table is established, and a bottom-up topological sorting is used to determine the solution order of logic gates, generating a solution queue and a module for mapping event data.

[0029] Based on the basic event index table, the basic events and cut set relationships in the fault tree are converted into bit set representations. Multiple bit set units are concatenated to form a complete cut set vector, and stacked row by row into a two-dimensional data array structure. The module outputs a cut set matrix that can be directly computed in a parallel environment.

[0030] The module reads the logic gate nodes to be solved from the solution queue, calls the cut set matrix of the corresponding input event, performs a bitwise OR broadcast operation on the AND gate to generate all cut set combinations, performs row concatenation and merging on the OR gate, and outputs the initial cut set of the logic gate.

[0031] The module performs parallel simplification on the initial cut set, calculates the order of each cut set and groups them in ascending order, compares the inclusion relationship between higher and lower order cut sets through a broadcast mechanism, uses bitwise negation and bitwise AND to determine whether it is a non-minimum cut set, removes redundant cut sets and outputs the minimum cut set.

[0032] The simplified set of minimal cut sets is stored in the result container, and the solution queue is used to pass it to the upper logic gate. After the intermediate events are solved, the memory of the dependent data is reclaimed, until the minimal cut sets of the top event are all generated and the final result is output.

[0033] Based on the same inventive concept, the present invention also provides a computer storage medium for storing a computer program, wherein when the computer program is read by a computer, the computer executes the method described thereon.

[0034] Based on the same inventive concept, the present invention also provides a computer, including a processor and a storage medium, wherein when the processor reads a computer program stored in the storage medium, the computer executes the method described thereon.

[0035] Based on the same inventive concept, the present invention also provides a computer program product, which, when executed, implements the method described.

[0036] Compared with the prior art, the advantages of the technical solution provided by the present invention are as follows:

[0037] This invention achieves high-density compressed storage of cutset sets by employing bit sets as the basic representation of minimal cutsets. Traditional algorithms typically use lists, matrices, or string structures to store cutset information, which not only consumes a large amount of memory but also incurs high data access overhead. This invention maps the state of each basic event to bits, recording whether an event is included in a cutset with the smallest storage unit, ensuring that the data structure perfectly matches the hardware word length. This design significantly reduces memory usage, improves cache hit rate and data loading speed under the same hardware conditions, and maintains high computational stability in ultra-large-scale system modeling. Compared with cutset storage methods based on string or integer encoding, this invention achieves an order-of-magnitude improvement in memory utilization.

[0038] This invention constructs a regular data array structure on parallel computing platforms such as GPUs, enabling cutset operations to be executed in a matrix-like manner. Traditional fault tree algorithms, due to their irregular data structures (such as linked list storage), are difficult to effectively expand on parallel computing architectures. This solution organizes all cutsets into a unified two-dimensional array and employs a broadcast mechanism during logical operations, allowing logical combination operations such as AND gates and OR gates to be executed synchronously on thousands of threads, thereby significantly improving computational throughput. Practice has proven that batch bitwise operations based on the matrix structure achieve a significantly higher parallelization speedup than traditional recursive expansion algorithms under the same hardware environment.

[0039] This invention replaces complex Boolean operations or recursive function calls with basic hardware instructions such as bitwise OR and bitwise AND during the logic gate solving stage. Because these bit operations are deeply optimized at the instruction set level of CPU and GPU architectures, their execution speed is extremely high, achieving nanosecond-level computation. This invention transforms the logical combination and simplification process of fault trees into a set of bit operations, significantly improving computational efficiency without introducing additional algorithmic complexity. Compared with Boolean algebra methods that rely on recursive solving and dynamic memory allocation, this approach effectively avoids problems such as excessively deep function call stacks and memory fragmentation, thus improving both computational stability and execution speed.

[0040] This invention achieves rapid filtering and redundancy removal of large-scale cutset sets through a parallelized cutset simplification strategy. In traditional serial simplification algorithms, determining whether one cutset is a superset of another often requires individual comparisons, resulting in high time complexity. This invention utilizes the bitset representation characteristics of cutsets, enabling inclusion relationship determination at the hardware level through bitwise NOT and bitwise AND operations, and performs this determination in batches on a GPU. Combined with order-based parallel sorting and a step-by-step grouping simplification mechanism, the computational complexity of the simplification stage is significantly reduced, resulting in overall performance superior to simplification processes based on BDD or heuristic pruning.

[0041] This invention significantly reduces peak memory usage during computation by introducing a modular structure and dynamic memory reclamation mechanism into the solution sequence planning. Traditional fault tree solving typically saves all intermediate results throughout the computation, leading to a surge in memory pressure for large-scale models. This invention generates an ordered solution queue based on the fault tree topology and, combined with dependency analysis of intermediate results, immediately releases unused data caches after computation. This mechanism maintains computational integrity while achieving dynamic optimization of memory utilization, enabling the system to solve larger-scale complex models under limited resource conditions.

[0042] The overall algorithm of this invention achieves multi-module parallelism at the macroscopic level and parallelism of logic gate operations at the microscopic level, thus forming a multi-layered computational architecture. Compared with existing parallel strategies based on CPU multithreading, this invention can fully utilize the thread-level parallelism of GPUs, achieving synchronous computation at multiple logic gate, module, and cutset combination levels, making the solution time linearly reduced with the number of computing cores. This characteristic enables this method to demonstrate superior scalability and high-performance computing potential in fault tree solving of complex systems.

[0043] It is applicable to fault tree analysis and minimum cut set solution for complex engineering systems with extremely high requirements for system reliability and safety, such as nuclear power, aerospace, chemical industry, and rail transportation. Attached Figure Description

[0044] Figure 1 A schematic diagram of the overall process of the representation method;

[0045] Figure 2 A schematic diagram illustrating the transformation from a cut set to a bit set;

[0046] Figure 3 Example fault tree diagram. Detailed Implementation

[0047] To make the advantages and benefits of the technical solution provided by the present invention clearer, the technical solution provided by the present invention will now be described in further detail with reference to the accompanying drawings, specifically:

[0048] Implementation Method 1: This implementation method provides a parallelized fault tree minimum cut set solution method based on bit set minimum cut set representation, including:

[0049] Module.

[0050] The logic gate operation tasks are divided using a GPU thread block structure, and parallel reading and writing of the data array is achieved through a unified memory space.

[0051] By traversing the topology of the fault tree, it automatically identifies consecutive logic gates of the same type and merges them into a single logic node, while performing decomposition operations on subtree modules with independent functional boundaries.

[0052] Each basic event is assigned a globally unique number according to the order in which it occurs, and the numbering results are stored in a mapping table for unified use in subsequent bit set mapping and logical operations.

[0053] If the number of basic events exceeds the bit width of the bit set unit (e.g., 64 bits), multiple bit set units can be concatenated to form a cut set vector. Multiple cut set bit set vectors can be stacked row by row to form a two-dimensional data array structure to represent a cut set.

[0054] For AND gates, a dimension expansion and broadcasting mechanism is used to generate all possible cut set combinations, while for OR gates, a row concatenation method is used to directly output the result.

[0055] Implementation Method Two: This implementation method is a further detailed description of the technical solution provided in Implementation Method One, specifically:

[0056] First, a parallel computing environment is established. Before the system runs, the parallel computing framework is initialized to provide the hardware foundation for subsequent large-scale data processing and logical operations. This parallel computing environment may include multi-core CPUs, GPUs, or other hardware platforms capable of multi-threaded data processing. At the software level, thread block structures and memory access patterns are established using CUDA, OpenCL, or other general-purpose parallel computing libraries. Task scheduling strategies and memory allocation schemes are configured to ensure that each module and logic gate node can execute independently in different threads during the subsequent fault tree solving process, thereby achieving parallelization of the computational tasks. The output of this step is an executable computing environment that has completed task partitioning, thread scheduling, and memory space initialization, providing the execution foundation for the input and solution of the fault tree model.

[0057] Secondly, the fault tree model undergoes preprocessing. This step takes the original fault tree model as input and outputs standardized, modular fault tree structure data. Preprocessing includes two aspects: structure simplification and module decomposition. First, the system performs structure simplification on the input fault tree model, automatically identifying consecutive logic gates of the same type and merging them to reduce recursion levels. For adjacent AND and OR gate structures, logical equivalence transformations are used to merge them into a single node, thereby reducing logical depth and computational complexity. Subsequently, a logical absorption operation is performed, identifying and deleting redundant sub-branches according to the Boolean absorption law, and removing logically repeated or inclusive event combinations. The simplified fault tree structure is more flattened. Next, the system performs module decomposition, using a depth-first traversal algorithm to identify independently solvable subtree modules. Each module corresponds to a relatively independent functional unit, such as the emergency cooling module and power supply system module in a nuclear power system. The top-level logic gates of the module are replaced with unique surrogate events, serving as input nodes for the main fault tree, forming a clearly hierarchical modular structure. The output of this preprocessing step is a set of decomposable and independently solvable fault tree structure units, which provides a logical basis for subsequent event indexing and parallel scheduling.

[0058] Next, the event index and solution order are established. The input to this step is a modularized fault tree structure, and the output is a container containing a basic event index table and a sequence of logic gate solutions. The system assigns a unique numerical number to each basic event, starting from 0 and numbering consecutively to form a global index table for subsequent bit set representation construction. Then, a bottom-up topological sorting algorithm is used to determine the solution order. The algorithm first identifies logic gates whose inputs are all basic events as the first batch of solution nodes, then searches layer by layer for all upper-level logic gate nodes whose inputs have been computed, until the top event node. The sorting results are stored in a queue structure to ensure that the solution dependencies of each logic gate strictly satisfy the topological order. To manage intermediate results during the solution process, a result container is designed, which stores the identifiers of intermediate events and their corresponding minimum cut set matrix data in key-value pairs.

[0059] Next, the cutset bitset compressed representation is constructed. The input to this step is the structure information of the basic event index table and the fault tree, and the output is a cutset matrix that can be directly computed in a parallel environment. The system assigns a fixed number of bits to each basic event according to the event numbering rules. Each cutset is represented by one or more bitset units, with one bit corresponding to one basic event; 1 represents that the event occurred, and 0 represents that the event did not occur. When the number of basic events exceeds the bit width that a single bitset unit can represent, the system combines multiple bitset units to form a vector structure to ensure that any number of events can be completely covered. For example, in a scenario containing thousands of basic events, multiple 64-bit unsigned integer units can be combined to form a cutset representation vector. All cutset vector structures are stacked row-wise to construct a regular two-dimensional array data structure, where each row represents a cutset and each column corresponds to a set of bitset units. All array data is loaded into the GPU's high-speed video memory for subsequent efficient parallel logic operations. After this step, the cutset information of all events in the fault tree is stored in a high-density bitset format, with a unified and continuous data structure, facilitating parallel access and batch processing.

[0060] Next, parallel computation of logic gate events is performed. The input to this step is a solution sequence queue and a cutset matrix, and the output is a preliminary cutset set of the logic gate. The system retrieves the current logic gate node to be solved from the queue according to the solution order and obtains its input event cutset matrix. For AND gate operations, the system first expands the two input matrices into a three-dimensional structure: the first input matrix is ​​expanded in the row dimension, and the second input matrix is ​​expanded in the column dimension. A broadcast mechanism is used to simultaneously perform a bitwise OR operation between each row of the input cutset and all rows of the other input cutset, generating all possible cutset combinations. This operation is equivalent to the union operation of mathematical sets, and the GPU's thread mechanism enables the synchronous computation of thousands of cutset pairs. For OR gate operations, the system directly concatenates and merges each input cutset matrix row by row to obtain the output cutset set of the logic gate. To prevent memory overflow caused by generating high-order cutsets, the system presets an upper limit on the cutset order and quickly counts the number of "1" bits in each newly generated cutset after computation; cutsets exceeding the set order are automatically deleted. The output of this step is the unsimplified cut set matrix, which provides input for the next simplification process.

[0061] Subsequently, a parallel cutset simplification operation is performed. The input to this step is the cutset matrix to be simplified, and the output is the simplified set of minimum cutsets. The system first uses parallel bitwise operations to count the order of each cutset and sorts them in ascending order, dividing the cutset set into multiple groups. Each simplification only compares the lower-order group with the higher-order group in one direction. For the currently processed cutset group, the system uses this group as the checked set and all lower-order cutsets as the reference set. Through a broadcast mechanism, each cutset in the current group is simultaneously evaluated for inclusion with all cutsets in the reference set. Specifically, the checked cutset is bitwise inverted and then bitwise ANDed with the reference cutset. If the result is all zeros, it indicates that the checked cutset contains the reference cutset, is a non-minimum cutset, and needs to be marked and removed. All judgments are executed in parallel at the GPU hardware level, generating a Boolean label matrix, automatically removing non-minimum cutsets, and retaining only the true minimum cutsets. The simplification result is updated in the result container and used as input data for the upper-level logic gates.

[0062] Next, a loop-based solution and dynamic memory management are implemented. The input to this step is a solution queue and a container for simplified results; the output is the complete minimal cut set of the top event. Under global scheduling, the system repeatedly executes logic gate operations and parallel simplifications according to the queue order. When all inputs to a logic gate node have been calculated, the system immediately starts its computation thread and stores the results in the container in real time. After each round of computation, the system checks the dependencies of intermediate events. If the output of an event has been called by all parent nodes, its corresponding memory space is immediately released to avoid memory accumulation. Through this mechanism, the peak memory usage of the entire solution process remains at a stable level, maintaining efficient computation even in large-scale models.

[0063] Finally, module-level parallelism and global result integration are performed. The input to this step is the independent solution results of all modules, and the output is the final cut set of the top event. At the macroscopic level, the system treats each module as an independent computational unit, executing the solution task in parallel across multiple GPU cores. After each module completes its computation, it outputs its top event cut set result. The master scheduler is responsible for integrating the results of each module at the backbone fault tree level, performing final logic gate operations and simplification operations to obtain the complete minimal cut set corresponding to the system's top event.

[0064] Through the aforementioned sequential steps, this invention establishes an efficient and scalable parallel fault tree minimum cut set solution process. Data transfer between steps is explicit and logically coherent, significantly improving computational speed and memory utilization while maintaining accuracy. Compared to traditional Boolean algebra expansions or serial algorithms based on binary decision graphs, this invention utilizes bit set compression and hardware-level parallel logic operations to transform the complex process of fault tree solving into well-organized matrix operations, fully leveraging the performance advantages of modern parallel computing hardware to achieve fast and stable solutions for minimum cut sets in complex systems.

[0065] Implementation Method 3: Combination Figure 1-3 This embodiment describes the technical solution provided above in further detail through specific examples. Specifically:

[0066] A parallelized fault tree minimum cut set solution method based on bit set minimum cut set representation includes the following steps:

[0067] Step 1: Parallel computing environment configuration

[0068] Deploy parallel processing tasks on at least one parallel data processing unit to synchronously execute the generation and filtering of minimum cut sets on multiple execution units (including threads and / or thread blocks) to support efficient solution of fault tree models;

[0069] Step 2: Preprocessing

[0070] In fault tree analysis of a pressurized water reactor system in a nuclear power plant, the fault tree model to be solved is structured. This model includes basic event nodes, such as equipment failures (high-pressure safety injection pump A startup failure), instrument failures (low-level measurement failure of the refueling tank level sensor), and human error (operator mistakenly closing valve V1); intermediate event nodes, such as hierarchical system and subsystem functional failure events like "high-pressure safety injection system A-path failure," "low-pressure safety injection system B-path failure," and "emergency diesel generator set EDG-A startup failure"; top event nodes, such as reactor core meltdown; and various types of logic gate nodes. These are modularized and standardized to form divisible structural units, laying the foundation for subsequent parallel processing. The preprocessing program automatically scans the entire fault tree, identifies structurally and logically independent subtrees, and defines them as reusable structured modular units. Simultaneously, a unique numerical ID is assigned to each basic event, completing standardization and laying the foundation for subsequent bit set representation.

[0071] Step 3: Generating the solution order

[0072] Before formally solving the fault tree, based on the fault tree's topology and the logical relationships between its parts, the solution order of each modular subtree and its contained intermediate event nodes is pre-determined, and this order information is stored in a pre-defined container to provide a sequential reference and scheduling basis for subsequent parallel solutions. For example, the candidate cut set of the intermediate event "Emergency diesel generator set A failed to start" must be solved first before it can be used as the input to the logic gate of the intermediate event "A-path AC power supply failure". This solution order is stored in a pre-defined container with a queue structure as a deterministic basis for subsequent parallel task scheduling.

[0073] Step 4: Cut set bit set compressed representation

[0074] The cutset set is compressed and encoded using bitsets, where each cutset is represented by one or more bitset units. Assuming the system fault tree model contains N = 12288 basic events, each basic event is assigned a unique index from 0 to 12287. Each bit in each bitset unit corresponds to the state of a basic event node, with each bit indicating whether the corresponding basic event node is included in the cutset (0 for not included, 1 for included). When the number of basic event nodes exceeds the capacity of a single bitset unit, multiple bitset units are concatenated to completely cover all basic event nodes, forming a class vector structure capable of representing any number of basic event nodes, used to represent a complete cutset. For example, a 64-bit unsigned integer is chosen as a single bitset unit. Since the total number of basic events exceeds 64, multiple bitset units are concatenated. In this example, a complete cutset is represented by a class vector structure consisting of 12288 / 64 = 192 64-bit integers. For example, a cutset containing basic event 0 (valve V1 failure) and basic event 12287 (pump A1 failure) has a class vector structure where the 0th bit of the first 64-bit integer is 1, the 63rd bit of the last 64-bit integer is 1, and the remaining bits are 0. The class vector structures of all cutsets are stacked row-wise according to the dimensions of the cutsets, organizing them into a data array structure with scalable dimensions. All generated cutset class vector structures are organized into an M×192 two-dimensional data array, where M is the number of current cutsets. This matrix is ​​loaded into the high-speed video memory of the GPU, and its well-organized structure greatly facilitates subsequent parallel batch operations. This achieves matrix-style storage of the cutset set, facilitating subsequent batch parallel processing.

[0075] Step 5: Gate event logic operation

[0076] For the AND gate, the two-dimensional data structures corresponding to the two input cut sets are expanded into three dimensions respectively. The first cut set is dimension-incremented row by row, and the second cut set is dimension-incremented as a whole. Through this expansion, using a broadcast mechanism, each row of the first data structure can be bitwise ORed with all rows of the second data structure simultaneously, thereby generating all possible cut set combinations in batches. For the OR gate node, the cut set data structures of each input event are directly concatenated and merged to obtain the output result. For example, for the AND gate operation, the inputs of the intermediate event "High-pressure safety injection A main pipeline failure" are "Inlet electric valve MOV-01A erroneously shut off" and "Outlet pneumatic valve AOV-02A erroneously shut off". Assume that the cut set set of "MOV-01A erroneously shut off" (matrix A, size M1×192) and the cut set set of "AOV-02A erroneously shut off" (matrix B, size M2×192) have been calculated. Using a broadcast mechanism, matrix A is expanded into a 3D structure of M1×M2×192, and matrix B is also expanded into a 3D structure of M1×M2×192. M1*M2 threads are launched on the GPU, each performing a bitwise OR operation on a pair of cutset vectors from A and B in parallel, generating all M1*M2 combined cutsets at once. For the OR gate operation, the input for the intermediate event "emergency power failure" is "diesel engine failure on path A" and "diesel engine failure on path B". The cutset matrix representing "diesel engine failure on path A" (size Ma×192) and the cutset matrix representing "diesel engine failure on path B" (size Mb×192) are directly concatenated in the row dimension to form a new matrix of (Ma+Mb)×192 as the output.

[0077] Step 6: Parallel Simplification

[0078] Based on the subset relationships between cutsets and bitsets, this invention employs a parallel approach to compare and filter cutset sets, automatically identifying and removing non-minimum cutsets with inclusion relationships, thus achieving batch simplification of cutset sets. For example, when a logic gate operation generates a new higher-order cutset, such as {pump A mechanical failure, 480V bus A section power loss}, this cutset must be compared with all existing minimum cutsets in the system. Assume that a more basic cutset {pump A mechanical failure} already exists in the system. This invention utilizes GPUs to launch thousands of threads to perform parallel subset relationship judgments on massive cutset pairs. Through efficient bitwise operations, the system quickly identifies that the former is a superset (non-minimum cutset) of the latter.

[0079] Step 7: Solve the whole system

[0080] The entire process is an iterative loop: a gate event to be solved is taken from the queue, the minimum cut set matrix of its input events is obtained, the gate event logic operation in step 5 is performed according to the gate type, the parallel simplification in step 6 is performed on the generated new cut set matrix, the simplified minimum cut set result is stored and used as the input for subsequent higher-level gate events. This "operation-simplification" loop advances upward layer by layer until the minimum cut set corresponding to the final top event "ECCS function failure" is calculated.

[0081] To further understand the present invention, the parallelized fault tree minimum cut set solution method based on bit set minimum cut set representation provided by the present invention will be described in detail below with reference to the embodiments. The scope of protection of the present invention is not limited by the following embodiments.

[0082] Example 1

[0083] Taking the solution of the fault tree for "reactor core overheating" in a pressurized water reactor nuclear power plant as an example, a parallelized fault tree minimum cut set solution method based on bit set minimum cut set representation is presented. The overall process is as follows: Figure 1 As shown, it includes the following steps:

[0084] Step 1: In one specific embodiment of the present invention, a preprocessing step is first performed before efficiently solving the initial fault tree. This step aims to systematically simplify and decompose the input fault tree data structure to significantly reduce its logical complexity and data size, thereby laying the foundation for subsequent parallel cut-set solving based on bit sets.

[0085] For example, in the fault tree analysis of the top event "reactor core overheating," the initial model may contain hundreds of logic gates and basic events, and direct solution would face enormous computational challenges. Therefore, we first preprocess the fault tree model. This preprocessing step specifically includes the following sub-steps:

[0086] Step 1-1: Fault tree simplification:

[0087] This step optimizes the topology and logical relationships of the fault tree by applying a series of deterministic rules. Specific operations include:

[0088] (1) Gate merging: Traverse the fault tree and automatically identify and merge all consecutive logic gates of the same type. For example, in our nuclear power plant fault tree, a high-level intermediate event "Emergency Core Cooling System (ECCS) failure" may be the output of an AND gate (G1), one of whose inputs is another intermediate event "High-Pressure Injection System Failure". "High-Pressure Injection System Failure" itself is also the output of an AND gate (G2), whose inputs are "A-path High-Pressure Injection Pump Start-up Failure" and "B-path High-Pressure Injection Pump Start-up Failure". At this time, the system will identify that G1 and G2 are consecutive logic gates of the same type and merge them into a single AND gate with more inputs, which is directly triggered by multiple basic events at the lower level, thereby effectively reducing the logic depth of the fault tree.

[0089] (2) Logical Absorption: Apply Boolean absorption law (e.g., A∨(A∧B)=A) to identify and remove logically redundant sub-branches. For example, when analyzing the branch "plant power system failure", there may be a logical relationship like this: the failure condition is "diesel generator A fails to start" or ("diesel generator A fails to start" and "diesel generator B fails to start"). According to Boolean absorption law, this complex logical expression can be directly simplified to "diesel generator A fails to start". By performing this simplification, unnecessary calculation branches in the model can be removed, reducing the complexity of subsequent analysis.

[0090] Step 1-2: Modularization of the fault tree:

[0091] This step aims to break down a large, coupled fault tree into several independent, more manageable subproblems.

[0092] (1) Module Identification: A linear time algorithm based on depth-first traversal is used to analyze the simplified fault tree. Through algorithm traversal, the system can accurately and efficiently identify all independent subtrees that meet the module definition based on the connection relationship between nodes. In our "Reactor Core Overheating" fault tree, "Emergency Core Cooling System (ECCS) Failure" and all its subordinate causal events (including failures of various safety injection pumps, valves, power supplies, etc.) constitute a functionally relatively independent physical system. Therefore, this complete subtree can be identified as an independent computational module.

[0093] (2) Module decomposition: After identifying all modules, perform the decomposition operation. In the original fault tree, replace the top event of each identified module subtree with a unique proxy event. For example, replace the top event of the "ECCS function loss" subtree with a proxy event named "M1-ECCS failure".

[0094] Following the steps described above, the initial large-scale "reactor core overheating" fault tree was successfully transformed into a dataset containing: 1) a significantly reduced-size and simplified backbone fault tree (whose leaf nodes contain the original basic events and module proxy events such as "M1-ECCS failure"); and 2) one or more sets of modular subtrees (such as the "ECCS failure" subtree) that are computationally independent of the backbone tree and each other. This decomposition provides a solid foundation for the highly parallel processing of tasks in subsequent steps.

[0095] Step 2: Cut set bit set compressed representation:

[0096] First, the system establishes a globally unique index for all basic events in the fault tree, and encodes each independent cut set into a compact bit set, so as to... Figure 2 For example, in this vector, each bit corresponds one-to-one with a basic event, and its value (1 or 0) directly indicates whether the basic event is included in the cut set.

[0097] Taking the "reactor core overheating" fault tree as an example, the system establishes a globally unique index for all basic events (i.e., specific equipment failures or personnel misoperations) in the "reactor core overheating" fault tree. For example:

[0098] BE1: A major breach has occurred in the main pipeline.

[0099] BE2: High-pressure injection pump A failed to start.

[0100] BE3: High-pressure injection pump B failed to start.

[0101] BE4: Power supply from diesel generator on route A failed.

[0102] BE5: Power supply from diesel generator on route B failed. ...

[0103] BE64: The operator failed to perform the manual switching operation in a timely manner.

[0104] Subsequently, each independent cut set is encoded into a compact bit set. In this bit set, each bit corresponds one-to-one with a specific underlying event, and its value (1 or 0) directly indicates whether the underlying event is included in the cut set. Figure 2For example, suppose a third-order cut set is {BE1: a major breach occurs in the main pipeline, BE2: the high-pressure injection pump on route A fails to start, BE64: the operator fails to perform a manual switching operation in time}, and there are a total of 64 basic events in the system. This cut set will be encoded as a bit set: 1100…01. The first, second, and 64th bits are 1, representing that BE1, BE2, and BE64 have occurred, while the remaining bits are 0, representing that other basic events have not occurred. This representation method compresses each event state to the smallest unit of computer storage—a bit—achieving significant data compression.

[0105] To support an arbitrary number of basic events, when the total number of events exceeds the bit width of a single native data type (such as a 64-bit unsigned integer), the system logically concatenates multiple binary storage units of that type to form a scalable bit set vector, thereby ensuring complete coverage of all basic events and achieving significant compression of data representation.

[0106] Secondly, this system organizes the set of all cut sets corresponding to an event into a regular two-dimensional data array (or tensor), such as... Figure 2 As shown on the right. Each row of this array corresponds to a bit set vector of a cut set. By vertically stacking all the cut set vectors, a matrix-like storage structure is formed. This structure not only enables contiguous storage of data in memory, facilitating efficient transfer between parallel processing units (such as GPUs), but more importantly, it transforms complex logical operations on cut set collections into batched, parallel numerical computations on multidimensional arrays. This lays the data foundation for subsequent gate event logic operations and parallel simplification steps based on broadcasting mechanisms.

[0107] Step 3: After completing the preprocessing step for the fault tree, this invention then executes the solution sequence generation step. The core purpose of this step is to plan an optimal, conflict-free computational path based on the topology of the preprocessed fault tree (including the trunk tree and each independent modular subtree). This ensures that when performing cut-set solving on any intermediate event node (i.e., logic gate), the cut sets of all its input events have been pre-calculated. To analyze a reactor core overheating accident at a pressurized water reactor nuclear power plant, a simplified fault tree model is constructed here, as follows: Figure 3As shown. The occurrence of the top event is determined by AND gate G1, and its triggering condition requires the simultaneous fulfillment of the outputs of OR gates G2 and G3. OR gate G2 represents coolant loss, triggered by either basic event: BE1 (a large rupture in the main coolant pipe) or BE2 (the pressurizer safety valve being stuck in the open position). Simultaneously, AND gate G3 represents the failure of the emergency core cooling system, requiring the simultaneous occurrence of the output events of OR gates G4 and G6. OR gate G4 represents A-path injection failure, triggered by either basic event BE3 (failure to start the A-path high-pressure safety injection pump) or the triggering of AND gate G5; while AND gate G5 represents A-path power supply failure, requiring the concurrent occurrence of basic events BE4 (loss of external power grid) and BE5 (failure to start the A-path emergency diesel generator). Similarly, OR gate G6 represents B-path injection failure, triggered by either basic event BE6 (failure to start the B-path high-pressure safety injection pump) or the triggering of AND gate G7. The AND gate G7 represents a failure of power supply to circuit B, which requires the simultaneous occurrence of the underlying events BE7 (failure to start the emergency diesel generator on circuit B) and BE4.

[0108] This preprocessing step specifically includes the following sub-steps:

[0109] Step 3-1 uses a bottom-up topological sorting algorithm to generate the solution sequence:

[0110] Starting from the leaf nodes (i.e., basic events) of the fault tree, the algorithm first identifies logic gates whose inputs are all ready (i.e., all inputs are basic events) and treats these gates as the first batch of nodes to be solved. Next, the algorithm continues to identify the next batch of logic gates whose inputs have all been solved and adds them to the solution sequence. This process is iterative, progressing upwards layer by layer, until a complete and unique solution order reaching the top event is finally generated. For modular scenarios, this topological sorting is first performed independently within each module subtree, and then the proxy events of the modules are sorted as nodes with known inputs in the main tree for overall sorting.

[0111] by Figure 3 Taking the fault tree as an example, the algorithm starts from the leaf nodes of the fault tree (i.e., BE1 to BE7) and identifies logic gates where all inputs are ready.

[0112] The first batch of nodes to be solved: Scanning the entire fault tree, it was found that the inputs to logic gates G2, G5, and G7 are all basic events. Therefore, they constitute the first batch of nodes to be solved.

[0113] The second batch of solution nodes: After the cut-set computations of G5 and G7 are completed, all inputs to logic gates G4 and G6 (the outputs of BE3 and G5, and the outputs of BE6 and G7, respectively) are ready. Therefore, G4 and G6 constitute the second batch of solution nodes.

[0114] Subsequent node solutions: Following this pattern, after G4 and G6 are solved, G3 becomes the node to be solved. Finally, after G2 and G3 are solved, the logic gate G1 of the top event becomes the last node to be solved.

[0115] Ultimately, the system generates a complete and conflict-free solution sequence: [G2, G5, G7] → [G4, G6] → [G3] → [G1].

[0116] Step 3-2: Solving order and containerized storage of intermediate results:

[0117] To manage the generated solution order and data during computation, this system uses a pre-defined container. In a specific implementation, this container is designed as a structure or class object. This structure contains a queue or list to store the identifiers (IDs) or pointers of intermediate event nodes to be solved, sorted topologically, thus forming a sequence of execution instructions. Once the execution engine computes the minimum cut set (represented as a bit set data array) of a particular intermediate event according to the queue order, the result is synchronously stored in this container (e.g., using key-value pairs, with the event ID as the key and the bit set data array as the value), for subsequent computation invocation by other nodes that depend on this event.

[0118] For example, when computing the first batch of G5, its minimum cut set is {BE4, BE5}. This cut set is converted into a bit set vector 0001100 and stored as a single-row matrix in a container, associated with the identifier "G5".

[0119] When calculating the second batch of G4, the algorithm reads the result of "G5" from the container and performs a logical operation with the bit set 0010000 representing "BE3" (see step 4 for the specific operation method) to generate a new two-dimensional data array that may contain multiple rows, which is then stored back into the container and associated with the identifier "G4".

[0120] Step 3-3 Dynamic Memory Optimization and Intermediate Cache Management:

[0121] To further improve memory efficiency in solving large-scale fault tree problems, this solution order generation step integrates a dynamic cache management mechanism. While generating the solution order, the system maintains a recyclable event index container (e.g., a list). In a computation round (e.g., after processing all nodes in the current solution queue), the system checks each intermediate event computed in that round. If all parent nodes of an intermediate event have been computed, it means that the cut set result of that intermediate event has been fully utilized and will not participate in any subsequent computations. At this point, the system records the index or ID of that intermediate event in the aforementioned recyclable event index container. At the end of the computation round, the system traverses this container and proactively releases or marks the memory cache occupied by these no longer needed intermediate event cut sets. This immediate recycling strategy significantly reduces peak memory usage throughout the solution process, ensuring the robustness and efficiency of the method when handling complex models.

[0122] Continuing with the above solution sequence as an example, after the calculation of G3 is completed, the system will check whether the results of its input nodes (i.e., G4 and G6) are still needed by any other subsequent calculations.

[0123] Analysis of the fault tree diagram reveals that the outputs of G4 and G6 serve only as inputs to G3. Therefore, after G3 successfully generates its own cutset data array, the memory originally allocated for the cutset results of G4 and G6 (which could be two very large arrays, such as...) is no longer needed. Figure 2 The two-dimensional data array shown can be immediately marked as recyclable.

[0124] At the end of each computation cycle, the system will proactively release this memory. This immediate reclamation strategy ensures that memory usage remains low throughout the computation process, enabling the handling of larger and more complex fault trees.

[0125] Step 4: Gate event logic operation (intermediate event solving):

[0126] In the overall solution process, following the order established by the "solution order generation" step, the intermediate event nodes (i.e., logic gates) in the fault tree are solved generation by generation using cut sets. Gate event logic operations are the core of this process. Based on the type of logic gate (mainly AND and OR gates), it combines and transforms the already obtained cut sets of its input events to generate the output cut set of that logic gate. This invention significantly improves the efficiency and robustness of this operation stage through a series of innovative parallelization design and optimization strategies. The specific implementation of this step is as follows:

[0127] Step 4-1 Parallelized batch computation for AND gates:

[0128] (1) Dimension Expansion and Broadcasting: Suppose an AND gate has two input events A and B, whose cut sets are stored as two-dimensional data arrays (tensors) TensorA (M rows) and TensorB (N rows), respectively. During the operation, the system first expands these two two-dimensional data structures into three dimensions: TensorA is expanded to an M×1×K shape (increasing the dimension by row), while TensorB is expanded as a whole to a 1×N×K shape.

[0129] Taking gate G3 in the fault tree as an example, there are two input events A ("IE3: A-way security injection failure") and B ("IE5: B-way security injection failure"), whose cut sets are stored in the form of two-dimensional data arrays (tensors) TensorA (M=2 rows) and TensorB (N=3 rows), respectively:

[0130]

[0131] The first row of TensorA a 1 is 00000100…… (64 bits), representing cut set {BE3}, which physically means "A-line high-pressure safety injection pump failed to start".

[0132] The second row of TensorA a 2 is 00011000…… (64 bits), representing the cut set {BE4, BE5}, which physically means that "external power grid loss" and "A-line emergency diesel generator failure to start" occur simultaneously.

[0133] The first row of TensorB b 1 represents 00100000…… (64 bits), 00100000 represents the cut set {BE6}, which physically means "B-line high-pressure safety injection pump failed to start".

[0134] The second row of TensorB b 2 is 01001000…… (64 bits), representing cut set {BE4, BE7}, which physically means that "external power grid loss" and "B-line emergency diesel generator failure to start" occur simultaneously.

[0135] The third row of TensorB b 3 is 10000000…… (64 bits), representing the cut set {BE8}, which physically means "B-path pump cooling water system failure".

[0136] After dimensional expansion, TensorA and TensorB are:

[0137]

[0138] (2) Batch bitwise OR operation: By expanding the dimensionality, the broadcast mechanism of parallel computing units (such as GPUs) can be utilized. When performing a bitwise OR operation on two 3D tensors, each row of TensorA (representing a cut set) is automatically paired with all rows of TensorB. Since the cut sets are represented by bit sets, the bitwise OR operation is equivalent to the union operation of sets. This operation is executed in a single, large-scale parallel manner by the hardware at the underlying level, instantly generating an M×N×K result tensor, as shown below:

[0139]

[0140] This includes all M×N possible cut set combinations. Finally, this resulting tensor is reshaped into a (M×N)×K two-dimensional data array, which is the original output cut set of the AND gate.

[0141]

[0142] Right now:

[0143]

[0144] Step 4-2 "OR gate" operation:

[0145] The logic of an OR gate is that if any one of its input events occurs, the output event also occurs. Therefore, its output cut set is a simple union of the cut sets of all input events. This system simplifies this operation: by directly concatenating the cut set data arrays of each input event (all two-dimensional) in the row direction, the output cut set data array of the OR gate can be obtained efficiently.

[0146] We will use the solution of IE1: coolant loss accident in the fault tree as an example. The input event A is "BE1: major rupture in the main coolant pipe", and its cutset data array TensorA is: Input event B is "BE2: Voltage regulator safety valve stuck in the open position", and its cutset data array TensorB is:

[0147] Based on the principle, solving the G2 gate operation is equivalent to directly concatenating and merging TensorA and TensorB along the row direction. The final output cutset data array of G2 is as follows:

[0148]

[0149] Step 4-3: Multi-level Parallelism and Optimization Strategies

[0150] The computation is parallelized at two levels. Micro-parallelism, as described above regarding the broadcast mechanism for a single AND gate operation, achieves parallelization of cut-set combination generation. Macro-parallelism is manifested in processing multi-input AND gates or multiple gates at the same level. The system pairs input events together and simultaneously initiates AND gate operations on multiple pairs of input events across multiple execution units. After each round of computation, the newly generated intermediate results are paired again until all input events have been processed, maximizing the utilization of parallel computing resources.

[0151] Before performing operations that may generate large amounts of data, such as AND gates, the system pre-calculates the storage space required for the result (e.g., the memory required for an M×N row cut set) and pre-allocates a contiguous block of memory in the target device (such as GPU memory). This avoids the overhead of dynamic memory allocation during computation and significantly speeds up data writing and transmission efficiency.

[0152] Users can preset a cut set truncation threshold (i.e., the maximum order of the cut set). After the AND gate operation, the system uses efficient bit manipulation instructions to batch count the order of each newly generated cut set (i.e., the number of "1"s in the bit set), and quickly filters and deletes high-order cut sets that exceed the order limit based on the threshold, effectively controlling the size of intermediate results.

[0153] When the input size of an AND gate operation is enormous, generating all combinations at once might lead to memory overflow. In this case, the system will automatically initiate a chunking batch processing mode. It divides one of the larger input data arrays into multiple data blocks according to a preset block size, then performs batch parallel operations on each block with another input data, and merges the results of each batch, thereby completing ultra-large-scale computational tasks with limited memory resources.

[0154] Step 5: Parallel cut set simplification:

[0155] After the "gate event logic operation" step, the generated cut set may contain a large number of non-minimum cut sets. To ensure the correctness and conciseness of the final result, this invention designs an efficient parallel simplification process. Its core task is to identify and remove all non-minimum cut sets; that is, if a cut set is a superset of another cut set, it should be removed. This process fully utilizes the bit-set compression representation of cut sets and the characteristics of parallel computing hardware to achieve fast and efficient simplification of large-scale cut set sets. The specific implementation of this step is as follows:

[0156] Step 5-1 Parallel sorting based on cut set order:

[0157] To significantly reduce the computational cost of subsequent inclusion relationship determination, the input cutset data array is first preprocessed. The system uses efficient bit manipulation instructions (such as popcount) to calculate the order of each cutset (i.e., each row of the data array) in parallel, which is the number of bits with a value of "1" in its bitset vector. Subsequently, a high-performance parallel sorting algorithm (e.g., GPU-based radix sort or quicksort) is invoked to sort the entire data array in ascending or descending order, using the cutset order as the primary sorting key. The logical basis of this optimization step is that a cutset A can only be contained by another cutset B with an order less than or equal to itself. Through sorting, several cutset groups are formed based on their order, which limits the potential inclusion relationship check to a local region of the data array, avoiding redundant comparisons in the global scope and laying the foundation for the next step of stepwise simplification.

[0158] Take a hypothetical set of cut sets that is directly output by the top event TE and has not yet been simplified as an example. It contains: {BE1} (first order), {BE2, BE3} (second order), {BE4, BE5} (second order), {BE4, BE7} (second order).

[0159] {BE1, BE4, BE5} (third order), {BE2, BE3, BE8} (third order), {BE6, BE4, BE7} (third order)

[0160] After calculating their orders in parallel and sorting them, we obtain the cut-set matrix grouped by order:

[0161]

[0162] It can be seen that the cut sets are divided into three groups according to their order (from one to three) from smallest to largest.

[0163] Step 5-2 Determining the hierarchical parallel inclusion relationship based on grouping:

[0164] (1) Simplification process and reference set: The simplification process starts from the group with the lowest order and proceeds iteratively upwards. In a specific iterative step, assume that the current group of cut sets with order k is being processed (denoted as Group_k). At this time, the reference set used for comparison is the set of all cut sets with order less than k that have been identified as the smallest in the previous steps (denoted as Minimal_Set_Pool).

[0165] For example, when simplifying the above cut set, the group of order 2...

[0166]

[0167] The cut set in the equation only needs to be with a set of order 1. Cut set comparisons within a group containing only one cut set. That is, its Minimal_Set_Pool contains only... .

[0168] (2) Broadcast and Bitwise AND Operation: The system loads the currently processed Group_k (the set to be checked) and Minimal_Set_Pool (the reference set) into the parallel computing unit. Through the broadcast mechanism, each cut set (denoted as A) in Group_k will be subjected to parallel inclusion relationship determination with all cut sets (denoted as B) in Minimal_Set_Pool. Specifically, first, the bitwise NOT operation is performed on the checked cut set A to obtain ~A, and then a bitwise AND operation is performed on it with the reference cut set B. If the result of the operation is zero (i.e., (B&(~A))=0), it proves that all basic events in cut set B also exist in cut set A, that is, A is a superset of B, and therefore A is a non-minimum cut set. The logic of this operation is that B&(~A) calculates the set of events that belong to B but not to A. When this set is empty (the result is 0), it proves that B is a subset of A.

[0169] Taking the above case as an example. First, the system loads the currently processed order 3 group (the checked set) and the Minimal_Set_Pool (the reference set), which contains four low-order minimal cut sets, into a parallel computing unit (such as a GPU). Through a broadcast mechanism, each cut set in the order 3 group undergoes parallel inclusion relationship determination with all cut sets in the "minimal cut set pool". We focus on one key set of comparisons:

[0170] The cut set being checked is A = {BE2, BE3, BE8} (binary: 10000110...).

[0171] Referencing the cut set B = {BE2, BE3} (binary: 00000110...)

[0172] Specifically, the system performs a bitwise NOT operation on the cut set A to be checked to obtain ~A (binary: 01111001...), and then performs a bitwise AND operation with the reference cut set B.

[0173] The calculation process is as follows: (B&(~A))

[0174] Substituting the binary value: 00000110 & 01111001 = 00000000

[0175] Since the result of the operation is zero, it proves that all basic events in the reference cut set B ({BE2, BE3}) also exist in the checked cut set A ({BE2, BE3, BE8}), that is, A is a superset of B. Therefore, A is a non-minimum cut set and will be removed.

[0176] (3) Marking and updating: This series of combined bit operations is executed in batches and in parallel on the hardware. The result is a Boolean marker vector used to identify all non-minimum cut sets in Group_k. After this iterative step, all non-minimum cut sets are deleted, and the remaining cut sets in Group_k are the minimum cut sets at the current order. They will be added to Minimal_Set_Pool for reference when simplifying higher-order arrays. This process is repeated until all order groupings are processed.

[0177] The final simplified result is:

[0178]

[0179] The first line 00000001... corresponds to the cut set {BE1}, the second line 00000110... corresponds to {BE2, BE3}, the third line 00011000... corresponds to {BE4, BE5}, the fourth line 01001000... corresponds to {BE4, BE7}, the fifth line 00011001... corresponds to {BE1, BE4, BE5}, and the sixth line 01101000... corresponds to {BE4, BE6, BE7}.

[0180] Step 6: Solve the whole problem:

[0181] In each solution round, the system strictly follows the solution schedule formed in step 3, sequentially executing steps 4 to 5 for each intermediate event (i.e., logic gate or module calculated as a whole) that needs to be solved in the current round, as included in the schedule list. Specifically, this process means that the system first calls the logic operation function in step 4 to generate a preliminary cut set, and then immediately calls the parallel simplification function in step 5 to obtain the precise minimum cut set of the event, and stores the result for use in subsequent rounds.

[0182] After the above steps, the result is Figure 3 The final solution to the fault tree is as follows:

[0183]

[0184] These correspond to the following cut sets:

[0185] {E1, E3, E6} ({Main coolant pipe major rupture, A-line high-pressure safety pump fails to start, B-line high-pressure safety pump fails to start})

[0186] {E2, E3, E6} ({The pressure regulator safety valve is stuck in the open position, the A-line high-pressure safety pump fails to start, and the B-line high-pressure safety pump fails to start})

[0187] {E1, E3, E4, E7} ({Main coolant pipe rupture, A-line high-pressure safety pump fails to start, external power grid lost, B-line emergency diesel generator fails to start})

[0188] {E2, E3, E4, E7} ({The pressure regulator safety valve is stuck in the open position, the A-line high-pressure safety pump fails to start, the external power grid is lost, and the B-line emergency diesel generator fails to start})

[0189] {E1, E4, E5, E6} ({Major rupture in main coolant pipeline, loss of external power grid, failure to start emergency diesel generator on route A, failure to start high-pressure safety pump on route B})

[0190] {E2, E4, E5, E6} ({The voltage regulator safety valve is stuck in the open position, the external power grid is lost, the A-line emergency diesel generator fails to start, and the B-line high-pressure safety pump fails to start})

[0191] {E1, E4, E5, E7} ({Major rupture in main coolant pipe, loss of external power grid, failure to start emergency diesel generator A, failure to start emergency diesel generator B})

[0192] {E2, E4, E5, E7} ({The voltage regulator safety valve is stuck in the open position, the external power grid is lost, emergency diesel generator A fails to start, emergency diesel generator B fails to start})

[0193] This allows for parallelization of the solution tasks for multiple logic gates or even multiple modules within the same solution round, thereby accelerating the solution speed. Since all computing nodes within the same round are logically independent and have no dependencies according to the planning in step 2, their "logic operation-simplification" tasks can be considered independent computing units. The master scheduler can allocate these independent tasks to different processor cores for synchronous execution, thus translating the hardware advantages of parallel computing into actual solution efficiency and significantly reducing the overall analysis time.

[0194] The above description of several specific embodiments further details the technical solution provided by the present invention in order to highlight the advantages and benefits of the technical solution provided by the present invention. However, the above-described specific embodiments are not intended to limit the present invention. Any reasonable modifications and improvements to the present invention, combinations of embodiments, and equivalent substitutions based on the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A parallelized fault tree minimum cut set solution method based on bit set minimum cut set representation, characterized in that, include: The steps to establish a parallel computing environment, configure multi-core processing units and thread block structures, complete task partitioning and memory initialization, and form a runtime environment that can support highly parallel solution of fault trees. The steps involved are: structuring and modularizing the input fault tree model, identifying and merging consecutive logic gates, removing redundant logic branches according to the Boolean absorption law, dividing the model into independent subtree modules and replacing the top gate of each module with a proxy event, and obtaining standardized fault tree structure data. Based on the preprocessed fault tree structure, and based on the topology and logical relationships of each part of the fault tree, the solution order of each modular subtree and its contained intermediate event nodes is determined in advance, and the solution queue and event data mapping relationship are generated. Assign a unique number to each basic event, establish a basic event index table, and convert the basic events and cut sets in the fault tree into bit set representations based on the basic event index table. Each bit set unit corresponds to the state of a basic event node, and each bit indicates whether the corresponding basic event node is included in the cut set, where 0 indicates not included and 1 indicates included. If the number of basic events exceeds the bit width, multiple bit set units can be concatenated to form a complete cut set vector. Stack multiple cut set bit sets in rows to form a two-dimensional data array structure to represent a cut set set, and output the cut set matrix that can be directly computed in a parallel environment. The steps are as follows: read the logic gate node to be solved from the solution queue, call the cut set matrix of the corresponding input event, perform a bitwise OR broadcast operation on the AND gate to generate all cut set combinations, perform row concatenation and merging on the OR gate, and output the preliminary cut set of the logic gate. The process involves parallel simplification of the initial cut set, calculation of the order of each cut set and grouping them in ascending order, comparison of the inclusion relationship between higher and lower order cut sets through a broadcast mechanism, determination of whether a cut set is non-minimum using bitwise negation and bitwise AND, elimination of redundant cut sets, and output of the minimum cut set set. The simplified set of minimal cut sets is stored in the result container, and the solution queue is used to pass it up to the upper logic gate. After the intermediate events are solved, the memory of the dependent data is reclaimed, until the minimal cut sets of the top event are all generated and the final result is output.

2. The parallelized fault tree minimum cut set solution method based on bit set minimum cut set representation according to claim 1, characterized in that, The logic gate operation tasks are divided using a GPU thread block structure, and parallel reading and writing of the data array is achieved through a unified memory space.

3. The parallelized fault tree minimum cut set solution method based on bit set minimum cut set representation according to claim 1, characterized in that, By traversing the topology of the fault tree, it automatically identifies consecutive logic gates of the same type and merges them into a single logic node, while performing decomposition operations on subtree modules with independent functional boundaries.

4. The parallelized fault tree minimum cut set solution method based on bit set minimum cut set representation according to claim 1, characterized in that, Each basic event is assigned a globally unique number according to the order in which it occurs, and the numbering results are stored in a mapping table for unified use in subsequent bit set mapping and logical operations.

5. The parallelized fault tree minimum cut set solution method based on bit set minimum cut set representation according to claim 1, characterized in that, If the number of basic events exceeds the bit width of a bit set unit, multiple bit set units can be concatenated to form a cut set vector. Multiple cut set bit set vectors can be stacked row by row to form a two-dimensional data array structure to represent a cut set.

6. The parallelized fault tree minimum cut set solution method based on bit set minimum cut set representation according to claim 1, characterized in that, For AND gates, a dimension expansion and broadcasting mechanism is used to generate all possible cut set combinations, while for OR gates, a row concatenation method is used to directly output the result.

7. A parallelized fault tree minimum cut set solution device based on bit set minimum cut set representation, characterized in that, include: Establish a parallel computing environment, configure multi-core processing units and thread block structures, complete task partitioning and memory initialization to form a module that can support highly parallel solution of fault trees. The input fault tree model is structurally simplified and modularly decomposed. Continuous logic gates are identified and merged. Redundant logic branches are removed according to the Boolean absorption law. Independent subtree modules are divided and the top gate of the module is replaced by a proxy event to obtain standardized fault tree structure data modules. Based on the preprocessed fault tree structure, and based on the topology and logical relationships of each part of the fault tree, the solution order of each modular subtree and its contained intermediate event nodes is determined in advance, and a solution queue and event data mapping relationship module are generated. Each basic event is assigned a unique number, and a basic event index table is established. Based on the basic event index table, the basic events and cut sets in the fault tree are converted into bit set representations. Each bit of each bit set unit corresponds to the state of a basic event node. Each bit is used to indicate whether the corresponding basic event node is included in the cut set, where 0 indicates that it is not included and 1 indicates that it is included. If the number of basic events exceeds the bit width, multiple bit set units can be concatenated to form a complete cut set vector. Multiple cut set bit sets are stacked in rows to form a two-dimensional data array structure to represent a cut set set. The module outputs a cut set matrix that can be directly computed in a parallel environment. The module reads the logic gate nodes to be solved from the solution queue, calls the cut set matrix of the corresponding input event, performs a bitwise OR broadcast operation on the AND gate to generate all cut set combinations, performs row concatenation and merging on the OR gate, and outputs the initial cut set of the logic gate. The module performs parallel simplification on the initial cut set, calculates the order of each cut set and groups them in ascending order, compares the inclusion relationship between higher and lower order cut sets through a broadcast mechanism, uses bitwise negation and bitwise AND to determine whether it is a non-minimum cut set, removes redundant cut sets and outputs the minimum cut set. The simplified set of minimal cut sets is stored in the result container, and the solution queue is used to pass it to the upper logic gate. After the intermediate events are solved, the memory of the dependent data is reclaimed, until the minimal cut sets of the top event are all generated and the final result is output.

8. A computer storage medium for storing computer programs, characterized in that, When the computer program is read by the computer, the computer executes the method of claim 1.

9. A computer, comprising a processor and a storage medium, characterized in that, When the processor reads the computer program stored in the storage medium, the computer executes the method of claim 1.

10. A computer program product, characterized in that, When the computer program is executed, it implements the method of claim 1.

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