Data writing method applied to storage device and storage device

Abstract

The invention discloses a data writing method applied to a storage device and the storage device. The data writing method comprises the following steps: writing data to be written into a source physical block in a storage medium according to a single-bit programming mode; backing up the data to be written into a host memory buffer area; writing the to-be-written data into a target physical block in the storage medium according to a multi-bit programming mode to complete rough programming; re-acquiring the data to be written from the host memory buffer area; and writing the to-be-written data into the target physical block in the storage medium according to a multi-bit programming mode to complete fine programming. Compared with an existing scheme, the data writing method has the advantages that intermediate data carrying is reduced, performance is improved, writing amplification of flash memory particles is reduced, and the service life of the whole storage device is prolonged.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of memory, and in particular, to a data writing method applied to a storage device and the storage device. BACKGROUND

[0002] With the continuous evolution of NAND flash memory technology, a single QLC (Quarter Level Cell) has a significant advantage in cost and capacity because it can store 4 bits of data, and is therefore widely used in various storage devices. Currently, storage devices using QLC as the basic storage unit usually perform two-step programming, namely coarse programming and fine programming, during the writing process. That is, the same location and the same data need to be written twice to be completely and correctly written.

[0003] Under this scheme, storage devices using QLC as the basic storage unit, especially storage devices with a DRAM-less scheme, have a relatively limited size of internal cache units. During the data writing process, the data to be written cannot be kept in the cache units until the process ends, so the data to be written needs to be temporarily stored in the storage medium, and then the data is read out from the storage medium one by one. A typical data writing process includes the following steps: 1. Temporarily store the data to be written in the source physical block of the storage medium in a single-bit programming mode (SLC mode); 2. Read the data to be written from the source physical block to the cache unit of the controller; 3. Write the data to be written in the cache unit to the target physical block according to coarse programming in a multi-bit programming mode (QLC mode); 4. Read the data to be written from the source physical block to the cache unit of the controller again; 5. Write the data to be written in the cache unit to the target physical block according to fine programming in a multi-bit programming mode.

[0004] In the above steps, the data in the source physical block needs to be read twice, which occupies a lot of bandwidth during a data writing process under heavy pressure, affecting the performance of the host data writing. Moreover, since the data is first written to the source physical block and then moved to the target physical block, additional Program / Erase (P / E) operations are required, which significantly increases the write amplification factor and affects the lifespan of the flash memory. SUMMARY

[0005] To solve the above problems, the present disclosure provides a data writing method applied to a storage device and the storage device.

[0006] In a first aspect, the embodiments of the present disclosure provide a data writing method applied to a storage device, the storage device comprising a storage medium composed of a plurality of layers of storage units and a controller, the controller executing the data writing method, the data writing method comprising: writing to-be-written data into a source physical block in the storage medium according to a single-bit programming mode; backing up the to-be-written data into a host memory buffer; writing the to-be-written data into a target physical block in the storage medium according to a multi-bit programming mode to complete coarse programming; reacquiring the to-be-written data from the host memory buffer; and writing the to-be-written data into the target physical block in the storage medium according to the multi-bit programming mode to complete fine programming.

[0007] In some embodiments, the data writing method further comprises: after the to-be-written data is written into the source physical block in the storage medium according to the single-bit programming mode and the host memory buffer, updating the physical addresses in the source physical block and the host memory buffer into a mapping relationship table; and after the to-be-written data is written into the target physical block in the storage medium according to the multi-bit programming mode, updating the physical addresses in the source physical block and the host memory buffer in the mapping relationship table to the physical address of the target physical block.

[0008] In some embodiments, the to-be-written data is backed up into the host memory buffer and reacquired from the host memory buffer through PCIe.

[0009] In some embodiments, the source physical block is pre-specified by the controller.

[0010] In some embodiments, when the host memory buffer does not support backing up the to-be-written data at one time, the host memory buffer is backed up multiple times using the to-be-written data in the source physical block.

[0011] In some embodiments, the controller estimates the size of the additional storage space currently required, sends a memory allocation request to the host to obtain the host memory buffer, and sends a memory release request to the host to release the host memory buffer when no additional storage space is required.

[0012] In some embodiments, the host allocates a fixed size of memory space as the host memory buffer in an initial connection session with the storage device, and releases the host memory buffer after the connection between the host and the storage device is interrupted.

[0013] In some embodiments, the multi-layer storage unit is QLC.

[0014] In a second aspect, the embodiments of the present disclosure provide a controller of a storage device, the solid state disk comprising a storage medium composed of a plurality of multi-layer storage units and a controller, and the controller is configured to perform the data writing method described above.

[0015] In a third aspect, the embodiments of the present disclosure provide a storage device, comprising the controller described above and a storage medium composed of a plurality of multi-layer storage units.

[0016] In the background art, the data to be written issued by the host is first written to the source physical block using the single-bit programming mode, and then through the garbage collection (GC) means, the data to be written is moved from the source physical block to the target physical block twice using the multi-bit programming mode to complete the coarse programming and fine programming. The scheme of the present embodiment directly writes the data to be written issued by the host to the target physical block using the multi-bit programming mode for coarse programming, and writes the data to be written backed up in the host memory buffer (HMB) to the target physical block using the multi-bit programming mode for fine programming, thereby reducing the intermediate data transfer, improving the performance, reducing the write amplification of the flash memory particles, and improving the service life of the entire storage device. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and other objects, features and advantages of the embodiments of the present disclosure will be more apparent from the following description of the embodiments of the present disclosure taken in conjunction with the accompanying drawings, in which: Figure 1 is a schematic block diagram of a computer system based on a DRAM-less scheme storage device; Figure 2 and Figure 3 The specific flow of the data writing method proposed by the embodiments of the present disclosure is illustrated in two different forms; Figure 4 The comparison of the command sequences respectively existing in the flash memory particles in the two schemes of the background art and the present embodiment is shown. DETAILED DESCRIPTION

[0018] The embodiments of the present disclosure are described below based on the embodiments, but the embodiments of the present disclosure are not limited to only these embodiments. In the following detailed description of the embodiments of the present disclosure, some specific details are described in detail. The embodiments of the present disclosure can also be fully understood without the description of these specific details. In order to avoid confusion of the essence of the embodiments of the present disclosure, the well-known methods, processes and flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0019] The flowcharts and block diagrams in the drawings illustrate the possible architectural, functional and operational scenarios of systems, methods and apparatuses of the embodiments of the present disclosure. The blocks on the flowcharts and block diagrams can represent a module, a program segment or just a piece of code, which are executable instructions for implementing the specified logic functions. It should also be noted that the executable instructions for implementing the specified logic functions can be recombined to generate new modules and program segments. Therefore, the blocks of the drawings and the block sequence are only used to better illustrate the processes and steps of the embodiments, and should not be taken as a limitation on the invention itself.

[0020] Figure 1 is a schematic block diagram of a computer system of a storage device based on a DRAM-less scheme. The computer system 100 includes a host 110, a controller 120 and a memory 130. The controller 120 and the memory 130 constitute a certain storage device, such as a solid state disk. The following is described by taking a solid state disk as an example.

[0021] The host interface 121 of the controller 120 is connected to the host 110. The host interface 121 is, for example, an interface of SATA, M.2, mSATA or PCI-E. The processor 123 is connected to the host interface 121, the cache controller 124 and the storage medium interface 128. The cache chip in the controller 120 can store a mapping table of logical addresses to physical addresses and an FTL (Flash Translation Layer) composed of software programs. The processor 123 executes the software programs in the FTL, so that the operating system and the file system of the host 110 can access the solid state disk. The FTL also supports functions such as multi-layer storage units, bad block management, wear leveling, garbage collection, power failure recovery and write leveling technology. The FTL is also used to maintain the mapping table of logical addresses to physical addresses, and the mapping table is updated according to the read and write operations of the host 110 on the solid state disk. Specifically, when the host 110 performs a data write operation, the FTL of the controller 120 receives a host command from the host 110, maps the logical address in the command to a physical address, which represents a position in the memory 130, then organizes the data to be written into data units of physical pages, and then writes the data units one by one into the memory 130 and updates the mapping table; in the read operation, the controller 120 controls the FTL to map the logical address in the command to a physical address, and reads the data from the corresponding position in units of physical pages.

[0022] In the DRAM-less scheme, the cache chip of the controller 120 is an SRAM chip 125 arranged internally. Due to the high cost of the SRAM chip and the space limitation inside the controller 120, the use efficiency of the SRAM chip is usually improved by means of software programs.

[0023] The memory 130 is composed of flash memory grains. The storage medium interface 128 of the controller 120 connects multiple flash memory grains via multiple channels (CH0 and CH1). The flash memory grains connected by the same channel form a logical unit (LU), and each logical unit has a logical unit number (LUN). Each flash memory grain can be divided into multiple physical blocks, each physical block can be divided into multiple physical pages, and each physical page is composed of storage units such as SLC, MLC, QLC.

[0024] Multi-layer storage units such as MLC, TLC, QLC, etc. can write data in a single-bit programming mode, indicating that each multi-layer storage unit writes only one bit each time it is written, or can write data in a multi-bit programming mode, indicating that data is written to each layer of the multi-layer storage unit each time it is written, for example, MLC storage units write 2 bits, TLC storage units write 3 bits, and QLC storage units write 4 bits. The data write speed of the single-bit programming mode is faster than that of the multi-bit programming mode.

[0025] To solve the problems in the background art, the embodiments of the present disclosure provide a data write method, which is applied to a DRAM-less storage device such as Figure 1 and can be formed into a computer program in FTL and executed by the processor 123. Figure 2 A flowchart of the data write method is given.

[0026] In step S201, the to-be-written data is written to a source physical block in the storage medium in a single-bit programming mode.

[0027] In step S202, the to-be-written data is backed up to a host memory buffer.

[0028] In step S203, the to-be-written data is written to a target physical block in the storage medium in a multi-bit programming mode in a coarse programming manner.

[0029] In step S204, the to-be-written data is reacquired from the host memory buffer, and the to-be-written data is written to the target physical block in the storage medium in a multi-bit programming mode in a fine programming manner.

[0030] In this embodiment, the source physical block can be a physical block designated by the controller 120 in advance on the storage medium 130 and dedicated to temporarily storing the to-be-written data.

[0031] In this embodiment, the host memory buffer (HMB) is a memory region mapped by the host 110 for the controller 120 to use, so that the controller 120 can use the host memory buffer at the speed of, for example, peripheral component interconnect express (PCIe) (such as the PCIe 4.0 interface bandwidth of 8 GB / s and the PCIe 5.0 interface bandwidth of 16 GB / s), and the time consumed can be negligible.

[0032] In this embodiment, the allocation of the host memory buffer can be static, which means that the host determines to allocate a host memory buffer of a fixed size for the controller 120 to use in the initial connection session of starting the storage device, and releases the host memory buffer 1101 when the host 110 is disconnected from the storage device. The allocation of the host memory buffer can also be dynamic, the controller 120 estimates the size of the additional storage space currently needed, and sends a memory allocation request to the host 110 accordingly, the host 110 initializes the required memory region as the host memory buffer allocated to the controller 120 according to the request; when the controller 120 no longer needs additional storage space, the controller 120 sends a memory release request to the host 110, the host 110 gives feedback to confirm the release, the controller 120 removes data from the host memory buffer according to the feedback, and the host 110 releases the host memory buffer.

[0033] In this embodiment, when the capacity of the host memory buffer (HMB) does not support backup of all the to-be-written data at one time, part of the to-be-written data can be backed up in the host memory buffer (HMB) first, and all the to-be-written data can be backed up in the source physical block of the storage medium at the same time, and the remaining to-be-written data in the source physical block can be backed up to the host memory buffer (HMB) after the backup data in the host memory buffer (HMB) is taken away. Similarly, when the cache unit in the controller does not support rough programming of all the to-be-written data at one time, the host memory buffer (HMB) is used to complete rough programming in multiple times.

[0034] Comprehensive comparison shows that, in the background art, the to-be-written data issued by the host is first written to the source physical block in a single-bit programming mode, and then the to-be-written data is moved from the source physical block to the target physical block twice by using the garbage collection (GC) method in a multi-bit programming mode to complete rough programming and fine programming; while in the scheme of this embodiment, rough programming is to directly write the to-be-written data issued by the host to the target physical block in a multi-bit programming mode, and fine programming is to write the to-be-written data backed up in the HMB to the target physical block in a multi-bit programming mode, which reduces the intermediate data transfer, improves the performance, reduces the write amplification of the flash particles, and improves the service life of the entire storage device.

[0035] Figure 3The specific process of this embodiment is illustrated in another form. In the figure, coarse programming is completed by step S1 (writing the data to be written to the source physical block in single-bit programming mode), step S2 (backing up the data to be written to the host memory buffer (HMB) 1101), and step S3 (writing the data to be written to the target physical block in multi-bit programming mode). Step S5 completes fine programming by retrieving the data to be written from the host memory buffer (HMB) 1101 through the fine programming management module and writing it to the target physical block. Steps S4 and S6 update the relevant information in the mapping table.

[0036] and Figure 2 compared to, Figure 3 The embodiment adds a maintenance step for the mapping table. The mapping table can be stored in SRAM 125. The mapping table can adopt a two-level mapping table scheme. The first-level mapping table stores the physical address of the second-level mapping table, and the second-level mapping table stores the physical address of the actual data storage. In this embodiment, after the data to be written is written to the source physical block and HMB, the physical address of the source physical block and the HMB address are updated in the second-level mapping table. When the data to be written is written to the target physical block, the corresponding physical address of the source physical block and the HMB address in the second-level mapping table are updated to the physical address of the target physical block. The mapping table can also adopt a single-level mapping table scheme, where the first-level mapping table stores the HMB address and the physical address of the data to be written in the storage medium.

[0037] Figure 4 The diagram illustrates a comparison of the command sequences present in the flash memory chips in the background technology and this embodiment. As shown in the figure, in the background technology solution, when the host writes a unit of data, the flash memory chip contains... Figure 4 In the command sequence shown in (a), the flash memory chip in this embodiment of the present disclosure has the command sequence shown in Figure (b). As can be seen from the figure, when the host writes the same amount of data, the solution in this embodiment of the present disclosure has fewer instructions for reading data from the source physical block of the SLC. Therefore, fewer instructions are reflected on the flash memory chip, and the controller operations are correspondingly reduced, resulting in less time consumed and naturally higher performance. Furthermore, since the data to be written is directly written to the physical block of the QLC, there is no additional Program / Erase (P / E) operation, and therefore no write amplification.

[0038] Accordingly, this disclosure also provides a computer-readable storage medium that stores one or more computer instructions, which, when executed, implement the steps described in the above embodiments.

[0039] Accordingly, the embodiments of the present disclosure also provide a computing device, which comprises a processor and a memory, the memory storing one or more computer instructions capable of being executed by the processor, the one or more computer instructions, when executed, implementing the steps in the above embodiments.

[0040] Those skilled in the art can understand that the various modules or units of the data processing system according to the present application can be implemented by hardware, firmware or software. The software includes, for example, coded programs formed by various programming languages such as JAVA, C / C++ / C#, SQL, etc. Although the steps and the order of the steps of the embodiments of the present application are given in the method and the method flowchart, the executable instructions implementing the specified logical functions of the steps can be recombined to generate new steps. The order of the steps should not be limited to the order of the steps in the method and the method flowchart, and can be adjusted at any time according to the needs of the functions. For example, some of the steps can be executed in parallel or in reverse order.

[0041] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A data writing method applied to a storage device, the storage device comprising a storage medium composed of a plurality of layers of storage units and a controller, the controller performing the data writing method, the data writing method comprising: writing to-be-written data into a source physical block in the storage medium according to a single-bit programming mode; backing up the to-be-written data into a host memory buffer; writing the to-be-written data into a target physical block in the storage medium according to a multi-bit programming mode to complete coarse programming; reacquiring the to-be-written data from the host memory buffer; and writing the to-be-written data into a target physical block in the storage medium according to a multi-bit programming mode to complete fine programming. updating the physical addresses in the source physical block and the host memory buffer into a mapping table after the to-be-written data is written into the source physical block in the storage medium according to the single-bit programming mode and the host memory buffer; and 2. The data write method of claim 1, further comprising: updating the physical addresses in the source physical block and the host memory buffer in the mapping table to the physical address of the target physical block after the to-be-written data is written into the target physical block in the storage medium according to the multi-bit programming mode. backing up the to-be-written data into the host memory buffer and reacquiring the to-be-written data from the host memory buffer through PCIe.

3. The data write method of claim 1, wherein, The source physical block is designated in advance by the controller.

4. The data write method of claim 1, wherein, When the host memory buffer does not support backing up the to-be-written data at one time, the host memory buffer is backed up in multiple times by using the to-be-written data in the source physical block.

5. The data write method of claim 1, wherein, The controller estimates the size of the additional storage space currently required, sends a memory allocation request to the host to obtain the host memory buffer, and sends a memory release request to the host to release the host memory buffer when no additional storage space is required.

6. The data write method of claim 1, wherein, The host allocates a fixed-size memory space as the host memory buffer in an initial connection session with the storage device, and releases the host memory buffer after the connection with the storage device is interrupted.

7. The data write method of claim 1, wherein, The plurality of layers of storage units are QLC.

8. The data write method of claim 1, wherein, 9.A controller of a storage device, the storage device comprising a storage medium composed of a plurality of layers of storage units and a controller, the controller being configured to perform the data writing method of any one of claims 1 to 8. A storage device comprising the controller of claim 9 and the storage medium composed of a plurality of layers of storage units.

10. A storage device, wherein, ​

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