Power supply output circuit and display device

Abstract

The invention provides a power supply output circuit and a display device, the power supply output circuit is composed of a power supply circuit, a comparison circuit, a power supply output circuit, a first detection circuit, a second detection circuit and a logic control circuit, during dormancy, the comparison circuit stops outputting a first wake-up signal, and the power supply output circuit stops outputting a starting voltage; when the first detection circuit and the second detection circuit stop working, the power consumption of the display device during dormancy is reduced, and when the display device is awakened and low-voltage rebound of the power supply voltage or the power supply voltage occurs, the logic control circuit does not receive the first awakening signal, the second awakening signal and the third awakening signal at the same time, the output of the first enable signal is stopped; and the power management integrated circuit does not work, so that the problems of circuit damage and picture abnormity caused by low-voltage rebound are prevented, and the working safety and the display effect of the circuit are improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display devices, and particularly relates to a power supply output circuit and a display device. BACKGROUND

[0002] In a display device, a main board is usually used to provide a driving circuit of a display panel with a power supply voltage. The driving circuit of the display panel can include a corresponding power management integrated circuit, a panel driving circuit, etc. The power management integrated circuit provides working power for the display panel and a corresponding driving unit, and the panel driving circuit provides a corresponding row scanning signal for the display panel.

[0003] A display device such as a mobile phone, a smart watch, etc. needs to frequently enter a sleep mode. A plurality of state detection circuits are arranged in the display device, and input states of the power supply voltage and voltage states of the driving circuit of the display panel are detected respectively, and the display device is controlled to switch between the sleep state and the wake-up state. The plurality of state detection circuits are always in a working state, and power consumption is increased.

[0004] During sleep, the power supply voltage drops to a first power supply voltage, and the driving circuit of the display panel controls part of the load to switch to low power consumption or stop working. During wake-up, when the voltage of the corresponding load of the driving circuit of the display panel reaches a threshold voltage for starting during the process of the power supply voltage rising to a second power supply voltage, the load starts to work, and the load switches from a low power consumption state to a high power consumption state. The load instantaneously increases, the input voltage of the driving circuit of the display panel decreases, that is, low voltage rebound occurs, and sudden voltage jump can cause damage to the corresponding driving circuit and cause abnormal display of the display device. SUMMARY

[0005] The present application aims to provide a power supply output circuit, and aims to solve the problems of high power consumption in a conventional display device and low voltage rebound of the driving circuit of the display panel causing circuit damage and abnormal display.

[0006] A first aspect of an embodiment of the present application provides a power supply output circuit, comprising: A power supply circuit, an input end of the power supply circuit being used to input a power supply voltage, a first output end of the power supply circuit being connected with a driving circuit of a display panel, the power supply circuit being used to convert the power supply voltage into a power voltage, wherein when the display panel is switched from a sleep state to a wake-up state, the power supply voltage rises from a first power supply voltage to a second power supply voltage, the power voltage rises from a first power voltage to a second power voltage, the driving circuit of the display panel at least includes a power management integrated circuit, and the power management integrated circuit is used to start working when the second power supply voltage and a first enable signal are received. a comparison circuit connected to the input terminal of the power supply circuit, the comparison circuit configured to output a first wake-up signal when the power supply voltage reaches a first reference voltage, the first reference voltage being greater than the first power supply voltage and less than the second power supply voltage; a power supply output circuit connected to the comparison circuit, the power supply output circuit configured to output a start voltage triggered by the first wake-up signal; a first detection circuit connected to the input terminal of the power supply circuit and the power supply output circuit, the first detection circuit configured to output a second wake-up signal when the start voltage is received and the power supply voltage reaches the first reference voltage; a second detection circuit connected to the first output terminal of the power supply circuit and the power supply output circuit, the second detection circuit configured to output a third wake-up signal when the start voltage is received and the power supply voltage is greater than a second reference voltage, the second reference voltage being greater than the first power supply voltage and less than the second power supply voltage; a logic control circuit configured to output the first enable signal when the first wake-up signal, the second wake-up signal and the third wake-up signal are received simultaneously.

[0007] Optionally, the comparison circuit comprises a first comparator, a first capacitor, a first resistor and a second resistor. The non-inverting input terminal of the first comparator, the first terminal of the first capacitor, the first terminal of the first resistor and the input terminal of the power supply circuit are connected, the inverting input terminal of the first comparator is configured to input the first reference voltage, the second terminal of the first capacitor and the second terminal of the first resistor are grounded, the output terminal of the first comparator and the first terminal of the second resistor are connected to constitute the output terminal of the comparison circuit, and the power supply terminal of the first comparator and the second terminal of the second resistor are connected and configured to input a positive voltage.

[0008] Optionally, the power supply output circuit comprises a first inverter, a first electronic switch tube. The input terminal of the first inverter is connected to the output terminal of the comparison circuit, the output terminal of the first inverter is connected to the control terminal of the first electronic switch tube, the input terminal of the first electronic switch tube is configured to input a positive voltage, and the output terminal of the first electronic switch tube constitutes the output terminal of the power supply output circuit.

[0009] Optionally, the first detection circuit comprises a second comparator, a same-phase amplifier, a second inverter, a third resistor, a fourth resistor and a second capacitor. The non-inverting input terminal of the second comparator is connected with the input terminal of the power supply circuit, the inverting input terminal of the second comparator is used for inputting the first reference voltage, the power supply terminal of the second comparator is connected with the output terminal of the power supply output circuit, the output terminal of the second comparator is connected with the input terminal of the non-inverting amplifier, the output terminal of the non-inverting amplifier, the first terminal of the third resistor, the first terminal of the fourth resistor, the first terminal of the second capacitor and the input terminal of the second inverter are connected, the second terminal of the third resistor, the second terminal of the fourth resistor and the second terminal of the second capacitor are grounded, and the output terminal of the second inverter constitutes the output terminal of the first detection circuit.

[0010] Optionally, the second detection circuit comprises a third comparator, a third capacitor, a fifth resistor and a third inverter. The non-inverting input terminal of the third comparator is used for inputting the second reference voltage, the first terminal of the third capacitor, the first terminal of the fifth resistor and the first output terminal of the power supply circuit are connected, the second terminal of the third capacitor is grounded, the second terminal of the fifth resistor is connected with the inverting input terminal of the third comparator, the power supply terminal of the third comparator is connected with the output terminal of the power supply output circuit, the output terminal of the third comparator is connected with the input terminal of the third inverter, and the output terminal of the third inverter constitutes the output terminal of the second detection circuit.

[0011] Optionally, the power management integrated circuit is further configured to stop working when a third enabling signal is received. The driving circuit of the display panel further comprises a gate driving circuit. The power supply circuit further comprises a second output terminal, and the power supply circuit is further configured to convert the power supply voltage into a driving voltage and output the driving voltage through the second output terminal, wherein when the display panel is switched from a sleep state to a wake-up state, the driving voltage is increased from a first driving voltage to a second driving voltage. The power supply output circuit further comprises: A switch circuit connected with the second output terminal of the power supply circuit and the gate driving circuit, respectively, and triggered to be turned on by a second enabling signal and to be turned off by a fourth enabling signal. A third detection circuit connected with the second output terminal of the power supply circuit and the power supply output circuit, and configured to output a fourth wake-up signal when the start voltage is received and the driving voltage is greater than a third reference voltage, the third reference voltage being greater than the first driving voltage and less than the second driving voltage. The logic control circuit is configured to output the first and second enable signals when the first, second, third and fourth wake-up signals are received simultaneously, and output the third and fourth enable signals otherwise.

[0012] Optionally, the third detection circuit comprises a fourth comparator, a fourth capacitor, a sixth resistor and a fourth inverter. The non-inverting input terminal of the fourth comparator is configured to input the third reference voltage, the first terminal of the fourth capacitor, the first terminal of the sixth resistor and the second output terminal of the power supply circuit are connected, the second terminal of the fourth capacitor is grounded, the second terminal of the sixth resistor is connected with the inverting input terminal of the fourth comparator, the power supply terminal of the fourth comparator is connected with the output terminal of the power supply output circuit, the output terminal of the fourth comparator is connected with the input terminal of the fourth inverter, and the output terminal of the fourth inverter constitutes the output terminal of the third detection circuit.

[0013] Optionally, the logic control circuit comprises an SR latch, an AND gate, a seventh resistor, an eighth resistor, a ninth resistor, a second electronic switch tube, a third electronic switch tube and a fourth electronic switch tube. The reset input terminal of the SR latch is connected with the output terminal of the comparison circuit, the set input terminal of the SR latch is connected with the output terminal of the first detection circuit, the output terminal of the SR latch and the first input terminal of the AND gate are connected, the second input terminal of the AND gate is connected with the output terminal of the second detection circuit, the third input terminal of the AND gate is connected with the output terminal of the third detection circuit, the output terminal of the AND gate is connected with the control terminal of the third electronic switch tube and the control terminal of the fourth electronic switch tube respectively, the first terminal of the seventh resistor, the first terminal of the second electronic switch tube and the first terminal of the eighth resistor are connected and input a positive voltage, the second terminal of the seventh resistor, the control terminal of the second electronic switch tube and the first terminal of the third electronic switch tube are connected, the second terminal of the third electronic switch tube is grounded, the second terminal of the second electronic switch tube is connected with the control terminal of the switch circuit, the second terminal of the eighth resistor, the first terminal of the ninth resistor and the first terminal of the fourth electronic switch tube are connected, the second terminal of the ninth resistor is grounded, and the second terminal of the fourth electronic switch tube is connected with the enable terminal of the power management integrated circuit.

[0014] Optionally, the logic control circuit further comprises a tenth resistor, an eleventh resistor, a fifth capacitor and a Schmitt trigger. The first end of the tenth resistor is connected with the output end of the AND gate, the second end of the tenth resistor, the first end of the fifth capacitor, the first end of the eleventh resistor and the input end of the Schmitt trigger are connected, the second end of the fifth capacitor and the second end of the eleventh resistor are grounded, and the output end of the Schmitt trigger is connected with the control end of the third electronic switch tube and the control end of the fourth electronic switch tube respectively.

[0015] The second aspect of the embodiment of the present application provides a display device, comprising a driving circuit of a display panel and the power supply output circuit.

[0016] Compared with the prior art, the power supply output circuit has the beneficial effects that: the power supply output circuit is composed of a power supply circuit, a comparison circuit, a power output circuit, a first detection circuit, a second detection circuit and a logic control circuit, when in sleep mode, the comparison circuit stops outputting the first wake-up signal, the power output circuit stops outputting the starting voltage, the first detection circuit and the second detection circuit stop working, and the power consumption of the display device in sleep mode is reduced, and when the display device is woken up, the comparison circuit, the first detection circuit and the second detection circuit output the first wake-up signal, the second wake-up signal and the third wake-up signal respectively, the logic control circuit controlledly outputs the first enable signal to the power management integrated circuit, and the power management integrated circuit is started, when low-voltage rebound of the power supply voltage or the power voltage occurs, the logic control circuit stops outputting the first enable signal, and the power management integrated circuit does not work, thereby preventing the circuit from being damaged and the picture from being abnormal due to the low-voltage rebound, and improving the circuit working safety and the display effect. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A structural schematic diagram of the power supply output circuit provided for the embodiment one of the present application is shown in the figure; Figure 2 A circuit schematic diagram of the comparison circuit and the power output circuit provided for the embodiment one of the present application is shown in the figure; Figure 3 A circuit schematic diagram of the first detection circuit provided for the embodiment one of the present application is shown in the figure; Figure 4 A circuit schematic diagram of the second detection circuit provided for the embodiment one of the present application is shown in the figure; Figure 5 A circuit schematic diagram of the logic control circuit provided for the embodiment one of the present application is shown in the figure; Figure 6 A structural schematic diagram of the power supply output circuit provided for the embodiment two of the present application is shown in the figure; Figure 7 A circuit schematic diagram of the third detection circuit provided for the embodiment two of the present application is shown in the figure; Figure 8The first circuit schematic diagram of the logic control circuit provided for the second embodiment of the present application; Figure 9 The second circuit schematic diagram of the logic control circuit provided for the second embodiment of the present application; Figure 10 The structural schematic diagram of the display device provided for the third embodiment of the present application.

[0018] In the figure, various reference signs are as follows: 100, power supply output circuit; 200, driving circuit of display panel; 210, power management integrated circuit; 220, gate driving circuit; 10, power supply circuit; 20, comparison circuit; 30, power supply output circuit; 40, first detection circuit; 50, second detection circuit; 60, logic control circuit; 70, switching circuit; 80, third detection circuit; VCC, power supply voltage; VCC1, power supply voltage; VCC2, driving voltage; VA1, first wake-up signal; VA2, second wake-up signal; VA3, third wake-up signal; VA4, fourth wake-up signal; VDD, start-up voltage; EN, enable end; V0, positive voltage; Vref1, first reference voltage; Vref2, second reference voltage; Vref3, third reference voltage; U1, first comparator; U2, second comparator; U3, non-inverting amplifier; U4, third comparator; U5, fourth comparator; U6, SR latch; U7, AND gate; U8, Schmitt trigger; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; R11, eleventh resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor; INV1, first inverter; INV2, second inverter; INV3, third inverter; INV4, fourth inverter; Q1, first electronic switch tube; Q2, second electronic switch tube; Q3, third electronic switch tube; Q4, fourth electronic switch tube; S, set input end; R, reset input end; Q, output end of SR latch. DETAILED DESCRIPTION

[0019] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects more clearly understood, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0020] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] Example 1 A first aspect of the present invention provides a power supply output circuit 100, which is used to provide a power supply voltage VCC1 and / or a driving voltage VCC2 to a driving circuit 200 of a display panel. The driving circuit 200 of the display panel may include a corresponding power management integrated circuit 210, a panel driving circuit, etc.

[0022] During sleep mode, the power supply voltage VCC drops to the first power supply voltage, and the drive circuit 200 of the display panel controls the load to switch to low power or stop working. During wake-up, as the power supply voltage VCC rises to the second power supply voltage, the load corresponding to the drive circuit 200 of the display panel starts working when its voltage reaches the start-up threshold voltage. The load switches from a low power state to a high power state, and the load increases instantaneously. This causes a drop in the input voltage of the drive circuit 200 of the display panel, i.e., a low-voltage rebound. This sudden voltage jump can damage the corresponding drive circuit and cause abnormal display of the display device.

[0023] To reduce circuit power consumption and avoid low-voltage bounce, this embodiment proposes a power supply output circuit 100, such as... Figure 1 As shown, the power supply output circuit 100 includes: The power supply circuit 10 has an input terminal for inputting the power supply voltage VCC and a first output terminal connected to the drive circuit 200 of the display panel. The power supply circuit 10 is used to convert the power supply voltage VCC into a power supply voltage VCC1. When the display panel switches from a sleep state to a wake-up state, the power supply voltage VCC rises from a first power supply voltage to a second power supply voltage, and the power supply voltage VCC1 rises from a first power supply voltage to a second power supply voltage. The drive circuit 200 of the display panel includes at least a power management integrated circuit 210, which is used to start working when it receives the second power supply voltage and a first enable signal. The comparator circuit 20 is connected to the input terminal of the power supply circuit 10. The comparator circuit 20 is used to output a first wake-up signal VA1 when the power supply voltage VCC reaches the first reference voltage Vref1. The first reference voltage Vref1 is greater than the first power supply voltage and less than the second power supply voltage. The power output circuit 30 is connected with the comparison circuit 20, and the power output circuit 30 is triggered to output a starting voltage VDD by the first wake-up signal VA1. The first detection circuit 40 is connected with the input end of the power supply circuit 10 and the power output circuit 30, and the first detection circuit 40 is used to output a second wake-up signal VA2 when the starting voltage VDD is received and the power supply voltage VCC reaches the first reference voltage Vref1. The second detection circuit 50 is connected with the first output end of the power supply circuit 10 and the power output circuit 30, and the second detection circuit 50 is used to output a third wake-up signal VA3 when the starting voltage VDD is received and the power supply voltage VCC1 is greater than the second reference voltage Vref2, and the second reference voltage Vref2 is greater than the first power supply voltage and less than the second power supply voltage. The logic control circuit 60 is used to output a first enable signal when the first wake-up signal VA1, the second wake-up signal VA2 and the third wake-up signal VA3 are received at the same time.

[0024] In the embodiment, the driving circuit 200 of the display panel is used to provide corresponding control signals, clock signals, voltage signals and the like for the display panel, and the display panel displays corresponding image information according to the received signals. The control signals can include row scanning signals, data signals and the like. The display panel realizes line-by-line scanning when the row scanning signal is received, and displays corresponding image information when the data signal is received during row scanning.

[0025] The driving circuit 200 of the display panel at least includes a power management integrated circuit 210. The power management integrated circuit 210 includes a power input end, an enable end EN and at least one power output end. The power input end is used to connect the power supply circuit 10 and obtain the power supply voltage VCC1. The power output end of the power management integrated circuit 210 can be connected with corresponding loads, for example, the power output end of the power management integrated circuit 210 is respectively connected with a timing controller, a source driving circuit and the like in the driving circuit 200 of the display panel. The power management integrated circuit 210 enables work when the first enable signal is received, and converts the received power supply voltage VCC1 into a working voltage required by the back-end load. The source driving circuit is used to output a data signal under the control of the timing controller. The display panel displays corresponding image information under the driving of the data signal and the row scanning signal.

[0026] And stops enabling work and turns off the output when the enable end EN of the power management integrated circuit 210 does not receive the first enable signal.

[0027] The power supply circuit 10 obtains the power supply voltage VCC through the connection mainboard, and realizes the conversion work of the power supply voltage VCC to the power supply voltage VCC1, which can be boost conversion or buck conversion, and can also be voltage stabilization conversion, etc. The power supply voltage VCC and the power supply voltage VCC1 realize positive correlation change, the mainboard controls the display panel to switch to the sleep state or the wake-up state through the driving circuit 200 of the display panel, and realizes the screen-off in the sleep state and the screen lighting in the wake-up state.

[0028] In the sleep state, the mainboard reduces the size of the power supply voltage VCC, that is, the power supply voltage VCC is reduced to the first power supply voltage, at this time, the power supply voltage VCC1 is correspondingly reduced to the first power supply voltage, the comparison circuit 20 compares the power supply voltage VCC with the first reference voltage Vref1, at this time, the power supply voltage VCC is less than the first reference voltage Vref1, the comparison circuit 20 cuts off the output of the first wake-up signal VA1, when the power supply output circuit 30 does not receive the first wake-up signal VA1, the power supply output circuit 30 is cut off, and the start-up voltage VDD is cut off to the first detection circuit 40 and the second detection circuit 50, the first detection circuit 40 and the second detection circuit 50 are used to detect the change of the power supply voltage VCC and the power supply voltage VCC1 respectively, when the start-up signal is not received, the first detection circuit 40 and the second detection circuit 50 stop working, the second wake-up signal VA2 and the second wake-up signal VA2 are not output, and no additional power consumption is generated, that is, the power consumption of the display device in the sleep state is reduced.

[0029] At the same time, the logic control circuit 60 does not receive the first wake-up signal VA1, the second wake-up signal VA2 and the third wake-up signal VA3 output by the comparison circuit 20, the first detection circuit 40 and the second detection circuit 50, the logic control circuit 60 cuts off the output of the first enable signal or selects the output of the third enable signal with the opposite level of the first enable signal, the power management integrated circuit 210 stops the enable work and turns off the output when the first enable signal is not received, further reducing the circuit power consumption in the sleep state, and the load connected with the power management integrated circuit 210 does not receive the working voltage, the load does not work, and does not cause the picture flicker.

[0030] When switching from the sleep state to the wake-up state, the main board controls the power supply voltage VCC to gradually rise, and correspondingly, the power supply voltage VCC1 gradually rises. When the power supply voltage VCC gradually rises to the first reference voltage Vref1, the comparison circuit 20 compares and outputs the first wake-up signal VA1. When the power supply output circuit 30 receives the first wake-up signal VA1, it triggers the output of the starting voltage VDD to the first detection circuit 40 and the second detection circuit 50, and the first detection circuit 40 and the second detection circuit 50 start to work. When the first detection circuit 40 detects that the power supply voltage VCC reaches the first reference voltage Vref1, the first detection circuit 40 outputs the second wake-up signal VA2. Correspondingly, when the second detection circuit 50 detects that the power supply voltage VCC1 reaches the second reference voltage Vref2, the second detection circuit 50 detects and outputs the third wake-up signal VA3. At this time, the logic control circuit 60 simultaneously receives the first wake-up signal VA1, the second wake-up signal VA2, and the third wake-up signal VA3. The logic control circuit 60 switches the output of the first enable signal. When the power management integrated circuit 210 receives the power supply voltage VCC1 greater than the second reference voltage Vref2 and receives the first enable signal, it starts to work, and converts the input power supply voltage VCC1 into a working voltage and outputs it to the rear-end load. When the corresponding working voltage of the rear-end load reaches the threshold voltage, the rear-end load starts to work and controls the display panel to display the corresponding image information.

[0031] In the wake-up process, when the load is switched from the low power consumption of the sleep state to the high power consumption of the wake-up state, causing the power supply voltage VCC and / or the power supply voltage VCC1 to have voltage rebound, when the first detection circuit 40 detects that the power supply voltage VCC is less than the first reference voltage Vref1 and / or the second detection circuit 50 detects that the power supply voltage VCC1 is less than the second reference voltage Vref2, the first detection circuit 40 stops outputting the second wake-up signal VA2 and / or the second detection circuit 50 stops outputting the third wake-up signal VA3. At this time, the logic control circuit 60 does not simultaneously receive the first wake-up signal VA1, the second wake-up signal VA2, and the third wake-up signal VA3. The logic control circuit 60 stops outputting the first enable signal or outputs the third enable signal which is opposite in level to the first enable signal. When the power management integrated circuit 210 does not receive the first enable signal, it stops enabling and working and turns off the output. The load connected to the power management integrated circuit 210 does not receive the working voltage, and the load does not work, which will not cause the screen to flicker. At the same time, the corresponding load and circuit will not receive the changing working voltage, and the corresponding load and circuit maintain the stopped working state, which will not cause damage to the circuit.

[0032] The power supply circuit 10 can be selected from corresponding boost circuits, buck circuits, voltage regulator circuits, etc., according to the conversion method. The first power supply voltage, the second reference voltage Vref2, and the second power supply voltage increase sequentially. The first power supply voltage can be 0V or other low voltages. The first power supply voltage is less than the threshold operating voltage of the power management integrated circuit 210. The second reference voltage Vref2 can be set to the threshold operating voltage of the power management integrated circuit 210 or greater than the threshold operating voltage of the power management integrated circuit 210. The second power supply voltage is greater than the threshold operating voltage of the power management integrated circuit 210. For example, if the threshold operating voltage is set to 2.5V, the first power supply voltage can be 1.8V, the second reference voltage Vref2 can be 3.0V, and the second power supply voltage can be 3.3V. The magnitude of each voltage can be set according to actual needs.

[0033] The comparator circuit 20, the first detection circuit 40, and the second detection circuit 50 can be selected with corresponding comparators and auxiliary components, and the logic control circuit 60 can be selected with corresponding logic gates, signal sources, switches, etc.

[0034] like Figure 2 As shown, in an optional embodiment, the comparison circuit 20 includes a first comparator U1, a first capacitor C1, a first resistor R1, and a second resistor R2; The non-inverting input terminal of the first comparator U1, the first terminal of the first capacitor C1, the first terminal of the first resistor R1, and the input terminal of the power supply circuit 10 are connected. The inverting input terminal of the first comparator U1 is used to input the first reference voltage Vref1. The second terminal of the first capacitor C1 and the second terminal of the first resistor R1 are grounded. The output terminal of the first comparator U1 and the first terminal of the second resistor R2 are connected to form the output terminal of the comparator circuit 20. The power supply terminal of the first comparator U1 and the second terminal of the second resistor R2 are connected and used to input the positive voltage V0.

[0035] The power output circuit 30 includes a first inverter INV1 and a first electronic switch Q1; The input terminal of the first inverter INV1 is connected to the output terminal of the comparator circuit 20, and the output terminal of the first inverter INV1 is connected to the control terminal of the first electronic switch Q1. The input terminal of the first electronic switch Q1 is used to input a positive voltage V0, and the output terminal of the first electronic switch Q1 constitutes the output terminal of the power output circuit 30.

[0036] like Figure 3 As shown, the first detection circuit 40 includes a second comparator U2, a non-inverting amplifier U3, a second inverter INV2, a third resistor R3, a fourth resistor R4, and a second capacitor C2. The non-inverting input terminal of the second comparator U2 is connected with the input terminal of the power supply circuit 10, the inverting input terminal of the second comparator U2 is used for inputting the first reference voltage Vref1, the power supply terminal of the second comparator U2 is connected with the output terminal of the power supply output circuit 30, the output terminal of the second comparator U2 is connected with the input terminal of the non-inverting amplifier U3, the output terminal of the non-inverting amplifier U3, the first terminal of the third resistor R3, the first terminal of the fourth resistor R4, the first terminal of the second capacitor C2 and the input terminal of the second inverter INV2 are connected, the second terminal of the third resistor R3, the second terminal of the fourth resistor R4 and the second terminal of the second capacitor C2 are grounded, and the output terminal of the second inverter INV2 constitutes the output terminal of the first detection circuit 40.

[0037] As shown in Figure 4 , the second detection circuit 50 comprises a third comparator U4, a third capacitor C3, a fifth resistor R5 and a third inverter INV3. The non-inverting input terminal of the third comparator U4 is used for inputting the second reference voltage Vref2, the first terminal of the third capacitor C3, the first terminal of the fifth resistor R5 and the first output terminal of the power supply circuit 10 are connected, the second terminal of the third capacitor C3 is grounded, the second terminal of the fifth resistor R5 is connected with the inverting input terminal of the third comparator U4, the power supply terminal of the third comparator U4 is connected with the output terminal of the power supply output circuit 30, the output terminal of the third comparator U4 is connected with the input terminal of the third inverter INV3, and the output terminal of the third inverter INV3 constitutes the output terminal of the second detection circuit 50.

[0038] As shown in Figure 5 , the detection control circuit comprises an SR latch U6, an AND gate U7, an eighth resistor R8, a ninth resistor R9 and a fourth electronic switch tube Q4. The reset input terminal R of the SR latch U6 is connected with the output terminal of the comparison circuit 20, the set input terminal S of the SR latch U6 is connected with the output terminal of the first detection circuit 40, the output terminal Q of the SR latch U6 and the first input terminal of the AND gate U7 are connected, the second input terminal of the AND gate U7 is connected with the output terminal of the second detection circuit 50, the output terminal of the AND gate U7 is connected with the control terminal of the fourth electronic switch tube Q4, the first terminal of the eighth resistor R8 is connected and inputs a positive voltage V0, the second terminal of the eighth resistor R8, the first terminal of the ninth resistor R9 and the first terminal of the fourth electronic switch tube Q4 are connected, the second terminal of the ninth resistor R9 is grounded, and the second terminal of the fourth electronic switch tube Q4 is connected with the enable terminal EN of the power management integrated circuit 210.

[0039] In this embodiment, in the sleep state, the main board reduces the size of the supply voltage VCC, that is, the supply voltage VCC is reduced to the first supply voltage, at this time, the power supply voltage VCC1 is reduced to the first power supply voltage, the first comparator U1 compares the supply voltage VCC with the first reference voltage Vref1, at this time, the supply voltage VCC is less than the first reference voltage Vref1, the first comparator U1 outputs low level, the low level is inverted by the first inverter INV1 and outputs high level signal to the first electronic switch tube Q1, the first electronic switch tube Q1 triggers off and cuts off the output of the positive voltage V0 to the second comparator U2 and the third comparator U4, when the positive voltage V0 is not received, the second comparator U2 and the third comparator U4 do not work, the second inverter INV2 inverts the output of high level, and the second wake-up signal VA2 output has no low level, the third inverter INV3 inverts the output of low level, and the third wake-up signal VA3 output has no high level, the second comparator U2 and the third comparator U4 do not work, and the circuit power consumption in the sleep state is reduced.

[0040] At the same time, the reset input end R of the SR latch U6 of the logic control circuit 60 is low level, the setting input end S is high level, the SR trigger outputs low level, at the same time, the second detection circuit 50 outputs low level, the AND gate U7 outputs low level, the fourth electronic switch tube Q4 is turned on, the power management integrated circuit 210 receives the high level third enable signal, the power management integrated circuit 210 stops enabling work and turns off the output, further reduces the circuit power consumption in the sleep state, and the load connected with the power management integrated circuit 210 does not receive the working voltage, the load does not work, and does not cause the picture flicker.

[0041] When switching from the sleep state to the wake-up state, the main board controls the power supply voltage VCC to gradually rise, and the power supply voltage VCC1 rises correspondingly. When the power supply voltage VCC gradually rises to the first reference voltage Vref1, the first comparator U1 outputs a high-level first wake-up signal VA1, the first inverter INV1 converts and outputs a low-level signal to the first electronic switch tube Q1, the first electronic switch tube Q1 is turned on, and outputs a positive voltage V0 to the power supply end of the second comparator U2 and the power supply end of the third comparator U4. The second comparator U2 of the first detection circuit 40 and the third comparator U4 of the second detection circuit 50 start to work. The second comparator U2 detects that the power supply voltage VCC reaches the first reference voltage Vref1, the second comparator U2 outputs a high-level signal, and the second inverter INV2 inversely outputs a low-level second wake-up signal VA2. Correspondingly, the third comparator U4 of the second detection circuit 50 detects that the power supply voltage VCC1 reaches the second reference voltage Vref2, the third comparator U4 outputs a low-level signal, and the third inverter INV3 inversely outputs a high-level third wake-up signal VA3. At this time, the set input end S of the SR latch U6 is switched from high level to low level, and the reset input end R is switched from low level to high level. At this time, the output end Q of the SR latch U6 is switched from low level to high level, and the AND gate U7 of the logic control circuit 60 simultaneously receives two high-level signals. The AND gate U7 outputs a high-level signal to the fourth electronic switch tube Q4, and the fourth electronic switch tube Q4 is turned off. The logic control circuit 60 outputs a low-level first enable signal, the power management integrated circuit 210 starts to work when receiving the power supply voltage VCC1 greater than the second reference voltage Vref2 and receiving the first enable signal, and converts the input power supply voltage VCC1 into a working voltage and outputs it to the rear-end load. When the corresponding working voltage reaches the threshold voltage, the rear-end load starts to work and controls the display panel to display the corresponding image information.

[0042] In the wake-up process, when the load is switched from the low power consumption in the sleep state to the high power consumption in the wake-up state, causing the voltage rebound of the supply voltage VCC and / or the power supply voltage VCC1, the second comparator U2 of the first detection circuit 40 detects that the supply voltage VCC is less than the first reference voltage Vref1 and / or the third comparator U4 of the second detection circuit 50 detects that the power supply voltage VCC1 is less than the second reference voltage Vref2, the first detection circuit 40 stops outputting the second wake-up signal VA2 with a low level and / or the second detection circuit 50 stops outputting the third wake-up signal VA3 with a high level, at this time, the AND gate U7 of the logic control circuit 60 does not simultaneously receive the first wake-up signal VA1, the second wake-up signal VA2 and the third wake-up signal VA3, the AND gate U7 outputs a low level to control the fourth electronic switch tube Q4 to be conductive, the power management integrated circuit 210 receives the third enable signal with a high level to stop enabling the work and turn off the output, the load connected with the power management integrated circuit 210 does not receive the working voltage, the load does not work, which will not cause the picture flicker, at the same time, the corresponding load and circuit will not receive the changing working voltage, the corresponding load and circuit maintain the stop working state, which will not cause the circuit damage.

[0043] The first capacitor C1 and the first resistor R1 in the comparison circuit 20 constitute a filter circuit, which is used to filter out the noise in the supply voltage VCC, preventing the noise input from causing the first comparator U1 to control the power output circuit 30 to output the starting voltage VDD, avoiding the false output of the power output circuit 30.

[0044] The non-inverting amplifier U3 in the first detection circuit 40 is used to realize signal amplification, the third resistor R3, the fourth resistor R4 and the second capacitor C2 constitute a first delay circuit, which ensures the stable output of the signal compared and output by the second comparator U2, preventing false wake-up, the delay time is determined by the time constant, which is equal to the product of the capacitance value of the second capacitor C2 and the total resistance value of the second resistor R2 and the third resistor R3.

[0045] The third capacitor C3 and the fifth resistor R5 in the second detection circuit 50 constitute a filter circuit, which is used to filter out the noise of the power supply voltage VCC1 input to the power management integrated circuit 210, avoiding the false start of the power management integrated circuit 210.

[0046] Compared with the prior art, the power supply output circuit 100 is composed of the power supply circuit 10, the comparison circuit 20, the power supply output circuit 30, the first detection circuit 40, the second detection circuit 50 and the logic control circuit 60. When in sleep, the comparison circuit 20 stops outputting the first wake-up signal VA1, the power supply output circuit 30 stops outputting the starting voltage VDD, and the first detection circuit 40 and the second detection circuit 50 stop working, thereby reducing the power consumption of the display device in sleep. When the display device is woken up, the comparison circuit 20, the first detection circuit 40 and the second detection circuit 50 output the first wake-up signal VA1, the second wake-up signal VA2 and the third wake-up signal VA3 respectively, the logic control circuit 60 is controlled to output the first enable signal to the power management integrated circuit 210, and the power management integrated circuit 210 is started. When the low-voltage rebound of the power supply voltage VCC or the power supply voltage VCC1 occurs, the logic control circuit 60 stops outputting the first enable signal, and the power management integrated circuit 210 does not work, thereby preventing the circuit damage and the abnormal picture caused by the low-voltage rebound, and improving the working safety of the circuit and the display effect.

[0047] Embodiment two Based on the basis of embodiment one, as shown in Figure 6 The power management integrated circuit 210 is further configured to stop working when the third enable signal is received. The driving circuit 200 of the display panel further includes a gate driving circuit 220. The power supply circuit 10 further includes a second output end, and the power supply circuit 10 is configured to convert the power supply voltage VCC into a driving voltage VCC2 and output the driving voltage VCC2 through the second output end. When the display panel is switched from the sleep state to the wake-up state, the driving voltage VCC2 is increased from the first driving voltage to the second driving voltage. The power supply output circuit 100 further includes: A switch circuit 70 is connected to the second output end of the power supply circuit 10 and the gate driving circuit 220 respectively. The switch circuit 70 is triggered to be turned on by the second enable signal and is triggered to be turned off by the fourth enable signal. A third detection circuit 80 is connected to the second output end of the power supply circuit 10 and the power supply output circuit 30. The third detection circuit 80 is configured to output a fourth wake-up signal VA4 when the starting voltage VDD is received and the driving voltage VCC2 is greater than a third reference voltage Vref3. The third reference voltage Vref3 is greater than the first driving voltage and less than the second driving voltage. The logic control circuit 60 is configured to output the first enable signal and the second enable signal when the first wake-up signal VA1, the second wake-up signal VA2, the third wake-up signal VA3 and the fourth wake-up signal VA4 are received simultaneously, and output the third enable signal and the fourth enable signal otherwise.

[0048] In the embodiment, the power management integrated circuit 210 is used to provide working voltage for the timing controller and the source driving circuit, and the gate driving circuit 220 is bound to the display panel and provides the row scanning signal. When the load is switched from the low power consumption in the sleep state to the high power consumption in the wake-up state, the gate driving circuit 220 may increase the driving current due to the start of the display panel, and cause the problem of the driving voltage VCC2 drop, i.e. the voltage rebound of the driving voltage VCC2.

[0049] To solve the problem, in the embodiment, a third detection circuit 80 is further provided, the power supply end of the third detection circuit 80 is connected with the power output circuit 30, the output end of the third detection circuit 80 is connected with the logic control circuit 60, and the gate driving circuit 220 is connected to the power supply circuit 10 through the switching circuit 70, which is turned on or turned off according to the second enable signal or the fourth enable signal output by the logic control circuit 60.

[0050] The power supply circuit 10 obtains the supply voltage VCC through the connection of the mainboard, and realizes the conversion work of the supply voltage VCC to the power voltage VCC1 and the driving voltage VCC2, which can be boost conversion or buck conversion, and can also be voltage stabilization conversion, etc. The power voltage VCC1 and the supply voltage VCC realize positive correlation change, the driving voltage VCC2 and the supply voltage VCC realize positive correlation change, the power management integrated circuit 210 and the gate driving circuit 220 branch the power voltage VCC1 and the driving voltage VCC2, the mainboard controls the display panel to switch to the sleep state or the wake-up state through the power management integrated circuit 210 and the gate driving circuit 220 of the display panel, and realizes the screen off in the sleep state and the screen lighting in the wake-up state.

[0051] In the sleep state, the mainboard reduces the size of the supply voltage VCC, i.e. the supply voltage VCC is reduced to the first supply voltage, at this time, the power voltage VCC1 is correspondingly reduced to the first power voltage, and the driving voltage VCC2 is reduced to the first driving voltage. The comparison circuit 20 compares the supply voltage VCC with the first reference voltage Vref1, at this time, the supply voltage VCC is less than the first reference voltage Vref1, the comparison circuit 20 cuts off the output of the first wake-up signal VA1, the power output circuit 30 is cut off when it does not receive the first wake-up signal VA1, and the power output circuit 30 is cut off, and the start voltage VDD is cut off to the first detection circuit 40, the second detection circuit 50 and the third detection circuit 80. When the start signal is not received, the first detection circuit 40, the second detection circuit 50 and the third detection circuit 80 stop working, the second wake-up signal VA2, the second wake-up signal VA2 and the fourth wake-up signal VA4 are not output, and no additional power consumption is generated, i.e. the power consumption of the display device in the sleep state is reduced.

[0052] Meanwhile, when the logic control circuit 60 does not receive the first wake-up signal VA1, the second wake-up signal VA2, the third wake-up signal VA3 and the fourth wake-up signal VA4, the logic control circuit 60 outputs the third enable signal to the power management integrated circuit 210, and outputs the fourth enable signal to the switching circuit 70. When the power management integrated circuit 210 receives the third enable signal, the power management integrated circuit 210 stops enabling and turns off the output, further reducing the power consumption of the circuit in the sleep state, and the load connected to the power management integrated circuit 210 does not receive the working voltage, so the load does not work, which will not cause the screen to flicker. Meanwhile, the switching circuit 70 receives the fourth enable signal to trigger the turn-off, and no driving voltage VCC2 is output, so the gate drive circuit 220 stops working, that is, no row scanning signal is output to the display panel, so the display panel will not start row scanning, that is, the display panel will not display the image, and the screen will remain off.

[0053] When switching from the sleep state to the wake-up state, the main board control supply voltage VCC gradually rises, and correspondingly, the power supply voltage VCC1 and the driving voltage VCC2 gradually rise. When the supply voltage VCC gradually rises to the first reference voltage Vref1, the comparison circuit 20 compares and outputs the first wake-up signal VA1. When the power supply output circuit 30 receives the first wake-up signal VA1, it triggers the output of the start voltage VDD to the first detection circuit 40, the second detection circuit 50 and the third detection circuit 80, and the first detection circuit 40, the second detection circuit 50 and the third detection circuit 80 start working. When the first detection circuit 40 detects that the supply voltage VCC reaches the first reference voltage Vref1, the first detection circuit 40 outputs the second wake-up signal VA2. Correspondingly, when the second detection circuit 50 detects that the power supply voltage VCC1 reaches the second reference voltage Vref2, the second detection circuit 50 detects and outputs the third wake-up signal VA3. When the third detection circuit 80 detects that the driving voltage VCC2 reaches the third reference voltage Vref3, the logic control circuit 60 receives the first wake-up signal VA1, the second wake-up signal VA2, the third wake-up signal VA3 and the fourth wake-up signal VA4 at the same time. The logic control circuit 60 switches to output the first enable signal to the power management integrated circuit 210, and outputs the second enable signal to the switching circuit 70. When the power management integrated circuit 210 receives the power supply voltage VCC1 greater than the second reference voltage Vref2 and receives the first enable signal, the power management integrated circuit 210 starts working, and converts the input power supply voltage VCC1 into a working voltage and outputs it to the rear-end load. When the switching circuit 70 receives the second enable signal, it triggers the turn-on and outputs the driving voltage VCC2 greater than the third reference voltage Vref3 to the gate drive circuit 220. The gate drive circuit 220 can normally output the row scanning signal. When the rear-end load starts working when the corresponding working voltage reaches the threshold voltage, and the gate drive circuit 220 controls the display panel to display the corresponding image information.

[0054] In the wake-up process, when one or both of the power supply voltage VCC1 and the driving voltage VCC2 has voltage bounce caused by the load switching from low power consumption in the sleep state to high power consumption in the wake-up state, the second detection circuit 50 detects that the power supply voltage VCC1 is less than the second reference voltage Vref2, and the second detection circuit 50 stops outputting the third wake-up signal VA3. The third detection circuit 80 detects that the driving voltage VCC2 is less than the third reference voltage Vref3, and the third detection circuit 80 stops outputting the fourth wake-up signal VA4. At this time, the logic control circuit 60 does not simultaneously receive the first wake-up signal VA1, the second wake-up signal VA2, the third wake-up signal VA3, and the fourth wake-up signal VA4, and the logic control circuit 60 switches the output of the third enable signal and the fourth enable signal. The power management integrated circuit 210 stops enabling operation and turns off the output when receiving the third enable signal, the switching circuit 70 triggers the turn-off when receiving the fourth enable signal, the gate drive circuit 220 stops working, and the display panel does not work, which will not cause flickering of the picture. At the same time, the corresponding load and the display panel will not receive a changing working voltage, and the corresponding load and the display panel maintain the stop working state, which will not cause damage to the thin film transistor in the load or the display panel.

[0055] Among them, the first driving voltage, the second reference voltage Vref2 and the second driving voltage are sequentially increased. The first driving voltage can be 0V or other low voltage, and the first driving voltage is less than the threshold working voltage of the power management integrated circuit 210. The third reference voltage Vref3 can be set to the threshold working voltage of the gate drive circuit 220 or greater than the threshold working voltage of the gate drive circuit 220. The second driving voltage is greater than the threshold working voltage of the gate drive circuit 220. For example, the threshold working voltage of the gate drive circuit 220 is set to 1.5V, the first driving voltage can be 0V, the second reference voltage Vref2 can be 1.5V, and the second driving voltage can be 1.8V. The size of each voltage can be set according to actual needs.

[0056] The switching circuit 70 can select a switching device with controlled on-off, and the third detection circuit 80 can adopt a corresponding switching device. Correspondingly, the logic control circuit 60 can adjust the circuit structure according to the output mode of the enable signal.

[0057] In an optional embodiment, as shown in Figure 7 The third detection circuit 80 includes a fourth comparator U5, a fourth capacitor C4, a sixth resistor R6, and a fourth inverter INV4. The non-inverting input terminal of the fourth comparator U5 is used for inputting the third reference voltage Vref3, the first terminal of the fourth capacitor C4, the first terminal of the sixth resistor R6 and the second output terminal of the power supply circuit 10 are connected, the second terminal of the fourth capacitor C4 is grounded, the second terminal of the sixth resistor R6 is connected with the inverting input terminal of the fourth comparator U5, the power supply terminal of the fourth comparator U5 is connected with the output terminal of the power supply output circuit 30, the output terminal of the fourth comparator U5 is connected with the input terminal of the fourth inverter INV4, and the output terminal of the fourth inverter INV4 constitutes the output terminal of the third detection circuit 80.

[0058] As shown in Figure 8 the logic control circuit 60 comprises an SR latch U6, an AND gate U7, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a second electronic switch tube Q2, a third electronic switch tube Q3 and a fourth electronic switch tube Q4. The reset input terminal R of the SR latch U6 is connected with the output terminal of the comparison circuit 20, the set input terminal S of the SR latch U6 is connected with the output terminal of the first detection circuit 40, the output terminal Q of the SR latch U6 and the first input terminal of the AND gate U7 are connected, the second input terminal of the AND gate U7 is connected with the output terminal of the second detection circuit 50, the third input terminal of the AND gate U7 is connected with the output terminal of the third detection circuit 80, the output terminal of the AND gate U7 is connected with the control terminal of the third electronic switch tube Q3 and the control terminal of the fourth electronic switch tube Q4 respectively, the first terminal of the seventh resistor R7, the first terminal of the second electronic switch tube Q2 and the first terminal of the eighth resistor R8 are connected and input the positive voltage V0, the second terminal of the seventh resistor R7, the control terminal of the second electronic switch tube Q2 and the first terminal of the third electronic switch tube Q3 are connected, the second terminal of the third electronic switch tube Q3 is grounded, the second terminal of the second electronic switch tube Q2 is connected with the control terminal of the switch circuit 70, the second terminal of the eighth resistor R8, the first terminal of the ninth resistor R9 and the first terminal of the fourth electronic switch tube Q4 are connected, the second terminal of the ninth resistor R9 is grounded, and the second terminal of the fourth electronic switch tube Q4 is connected with the enable terminal EN of the power management integrated circuit 210.

[0059] In this embodiment, in the sleep state, the main board reduces the size of the supply voltage VCC, that is, the supply voltage VCC is reduced to the first supply voltage, at this time, the power supply voltage VCC1 corresponds to the first power supply voltage, the driving voltage VCC2 corresponds to the first driving voltage, the first comparator U1 compares the supply voltage VCC with the first reference voltage Vref1, at this time, the supply voltage VCC is less than the first reference voltage Vref1, the first comparator U1 outputs low level, cuts off the output of the first wake-up signal VA1 with high level, the low level is inverted by the first inverter INV1 to output a high level signal to the first electronic switch tube Q1, the first electronic switch tube Q1 triggers off and cuts off the output of the positive voltage V0 to the second comparator U2, the third comparator U4, when the positive voltage V0 is not received, the second comparator U2, the third comparator U4 and the fourth comparator U5 do not work, the second inverter INV2 inverts the output of the high level, the second wake-up signal VA2 with low level is not output, the third inverter INV3 inverts the output of the low level, the third wake-up signal VA3 with high level is not output, the fourth inverter INV4 inverts the output of the low level, the fourth wake-up signal VA4 with high level is not output, the second comparator U2, the third comparator U4 and the fourth comparator U5 do not work, which reduces the power consumption of the circuit in the sleep state.

[0060] At the same time, the reset input end R of the SR latch U6 of the logic control circuit 60 is low level, the set input end S is high level, the SR trigger outputs low level, the second detection circuit 50 and the third detection circuit 80 output low level, the AND gate U7 outputs low level, the third electronic switch tube Q3 is off, the control end of the second electronic switch tube Q2 is pulled up to high potential, the second electronic switch tube Q2 is off, the fourth electronic switch tube Q4 is on, the power management integrated circuit 210 receives the high level third enable signal, the power management integrated circuit 210 stops enabling and off output, further reduces the power consumption of the circuit in the sleep state, and the load connected with the power management integrated circuit 210 does not receive working voltage, the load does not work, which will not cause the picture to flicker, at the same time, the switch circuit 70 receives the low level fourth enable signal, the switch circuit 70 is off, no driving voltage VCC2 is output, the gate drive circuit 220 stops working, that is, no row scanning signal is output to the display panel, the display panel will not start row scanning, that is, the display panel will not appear picture display, and keep the screen off state.

[0061] When switching from the sleep state to the wake-up state, the main board controls the power supply voltage VCC to gradually rise, and the power supply voltage VCC1 rises correspondingly. When the power supply voltage VCC gradually rises to the first reference voltage Vref1, the first comparator U1 outputs a high-level first wake-up signal VA1, the first inverter INV1 converts and outputs a low-level signal to the first electronic switch tube Q1, the first electronic switch tube Q1 is turned on, and outputs a positive voltage V0 to the power supply end of the second comparator U2, the power supply end of the third comparator U4, and the power supply end of the fourth comparator U5. The second comparator U2 of the first detection circuit 40, the third comparator U4 of the second detection circuit 50, and the fourth comparator U5 of the third detection circuit 80 start to work.

[0062] When the power supply voltage VCC reaches the first reference voltage Vref1, the second comparator U2 detects it, outputs a high-level signal, and outputs a low-level second wake-up signal VA2 through the second inverter INV2. Correspondingly, when the power supply voltage VCC1 reaches the second reference voltage Vref2, the third comparator U4 of the second detection circuit 50 detects it, outputs a low-level signal, and outputs a high-level third wake-up signal VA3 through the third inverter INV3. When the power supply voltage VCC1 reaches the third reference voltage Vref3, the fourth comparator U5 of the third detection circuit 80 detects it, outputs a low-level signal, and outputs a high-level fourth wake-up signal VA4 through the fourth inverter INV4. At this time, the set input end S of the SR latch U6 is switched from high level to low level, the reset input end R is switched from low level to high level, the output end Q of the SR latch U6 is switched from low level to high level, and the AND gate U7 of the logic control circuit 60 simultaneously receives three high-level signals. The AND gate U7 outputs a high-level signal to the third electronic switch tube Q3 and the fourth electronic switch tube Q4, the third electronic switch tube Q3 is turned on, and the control end of the second electronic switch tube Q2 is pulled down to a low potential, the second electronic switch tube Q2 is turned on, the fourth electronic switch tube Q4 is turned off, the logic control circuit 60 outputs a low-level first enable signal to the power management integrated circuit 210, and outputs a high-level second enable signal to the switching circuit 70. The power management integrated circuit 210 starts to work when receiving the power supply voltage VCC1 greater than the second reference voltage Vref2 and receiving the first enable signal. The switching circuit 70 is triggered to be turned on and transmits the driving voltage VCC2 greater than the third reference voltage Vref3 to the gate drive circuit 220. The gate drive circuit 220 can normally output a row scan signal. The back-end load starts to work when the corresponding working voltage reaches the threshold voltage, and controls the display panel to display corresponding image information together with the gate drive circuit 220.

[0063] In the wake-up process, when the load is switched from the low power consumption in the sleep state to the high power consumption in the wake-up state, causing one or both of the power supply voltage VCC1 and the driving voltage VCC2 to have a voltage bounce, the third comparator U4 detects that the power supply voltage VCC1 is less than the second reference voltage Vref2, the second detection circuit 50 stops outputting the third wake-up signal VA3, the fourth comparator U5 detects that the driving voltage VCC2 is less than the third reference voltage Vref3, the third detection circuit 80 stops outputting the fourth wake-up signal VA4, at this time, the AND gate U7 does not simultaneously receive the first wake-up signal VA1, the second wake-up signal VA2, the third wake-up signal VA3 and the fourth wake-up signal VA4, the AND gate U7 outputs a low level, the second electronic switch Q2 is turned off, the fourth electronic switch Q4 is turned on, the third enable signal and the fourth enable signal are switched to be output, the power management integrated circuit 210 stops enabling the work and turns off the output when receiving the third enable signal, the switching circuit 70 triggers the turn-off when receiving the fourth enable signal, the gate drive circuit 220 stops working, and the display panel does not work, which will not cause the picture flicker, at the same time, the corresponding load and the display panel will not receive the changed working voltage, the corresponding load and the display panel maintain the stop working state, which will not cause the damage of the thin film transistor in the load or the display panel.

[0064] The fourth capacitor C4 and the sixth resistor R6 of the third detection circuit 80 constitute a filter circuit for filtering out the noise in the driving voltage VCC2.

[0065] Corresponding to the level of the above-mentioned signals, the first electronic switch Q1, the second electronic switch Q2, the third electronic switch Q3 and the fourth electronic switch Q4 can adopt corresponding types of switching devices, in an optional embodiment, the first electronic switch Q1, the second electronic switch Q2 and the fourth electronic switch Q4 are P-channel field effect transistors, and the third electronic switch Q3 is an N-channel field effect transistor.

[0066] In order to improve the signal stability output by the AND gate U7 and prevent the front-end detection circuit from misjudging to cause the logic control circuit 60 to output an error enable signal, in an optional embodiment, as shown in Figure 9 the logic control circuit 60 further includes a tenth resistor R10, an eleventh resistor R11, a fifth capacitor C5 and a Schmitt trigger U8; The first end of the tenth resistor R10 is connected with the output end of the AND gate U7, the second end of the tenth resistor R10, the first end of the fifth capacitor C5, the first end of the eleventh resistor R11 and the input end of the Schmitt trigger U8 are connected, the second end of the fifth capacitor C5 and the second end of the eleventh resistor R11 are grounded, and the output end of the Schmitt trigger U8 is connected with the control end of the third electronic switch Q3 and the control end of the fourth electronic switch Q4 respectively.

[0067] In this embodiment, the tenth resistor R10, the eleventh resistor R11, the fifth capacitor C5, and the Schmitt trigger U8 form the second delay circuit. The tenth resistor R10 is responsible for controlling the current flowing through the Schmitt trigger U8 to prevent damage to the Schmitt trigger U8. The eleventh resistor R11 and the fifth capacitor C5 form an RC delay circuit. During sleep mode, the eleventh resistor R11 discharges the fifth capacitor C5. When the AND gate U7 outputs a high-level signal, the second delay circuit receives the high-level signal and outputs a high-level signal after a delay for a period of time to prevent the front-end detection circuit from misjudging and outputting an abnormal wake-up signal. When the AND gate U7 continuously outputs a high-level signal for a preset period of time, the second delay circuit outputs a high-level signal and controls the corresponding fourth electronic switch Q4 to turn off and the second electronic switch Q2 to turn on, thereby enabling the power management integrated circuit 210 and powering on the gate drive circuit 220.

[0068] Example 3 A second aspect of the present invention provides a display device, such as... Figure 10 As shown, the display device includes a driving circuit 200 for the display panel and a power supply output circuit 100. The specific structure of the power supply output circuit 100 is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The power supply output circuit 100 is connected to the driving circuit 200 for the display panel.

[0069] In this embodiment, the driving circuit 200 of the display panel may include a power management integrated circuit 210 and a gate driving circuit 220. The power management integrated circuit 210 is used to provide operating voltage for the timing controller and the source driving circuit, and the gate driving circuit 220 is bonded to the display panel and provides a row scanning signal.

[0070] The power supply output circuit 100 is connected to the power supply terminal of the gate drive circuit 220. The power supply output circuit 100 is also connected to the power input terminal and the enable terminal EN of the power management integrated circuit 210. In sleep mode, the power supply output circuit 100 enables the power management integrated circuit 210 to stop working and cuts off the output drive voltage VCC2 to the gate drive circuit 220. The display panel does not work and the relevant loads switch to low power consumption.

[0071] In the wake-up state, the power supply output circuit 100 enables the power management integrated circuit 210 to work, and outputs the power supply voltage VCC1 to the power management integrated circuit 210, and outputs the driving voltage VCC2 to the gate drive circuit 220, the gate drive circuit 220 and the power management integrated circuit 210 work normally, the power management integrated circuit 210 converts the input power supply voltage VCC1 into a working voltage and outputs to the rear-end load, the gate drive circuit 220 can normally output the row scanning signal, the rear-end load starts to work when the corresponding working voltage reaches the threshold voltage, and works together with the gate drive circuit 220 to control the display panel to display the corresponding image information.

[0072] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalent ones; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A power supply output circuit, characterized by comprising: include: The power supply circuit has an input terminal for inputting a power supply voltage and a first output terminal connected to the driving circuit of the display panel. The power supply circuit is used to convert the power supply voltage into a power supply voltage. When the display panel switches from a sleep state to a wake-up state, the power supply voltage rises from a first power supply voltage to a second power supply voltage, and the power supply voltage rises from a first power supply voltage to a second power supply voltage. The driving circuit of the display panel includes at least a power management integrated circuit, which is used to start working when it receives the second power supply voltage and a first enable signal. A comparator circuit is connected to the input terminal of the power supply circuit. The comparator circuit is used to output a first wake-up signal when the power supply voltage reaches a first reference voltage. The first reference voltage is greater than the first power supply voltage and less than the second power supply voltage. A power output circuit is connected to the comparison circuit, and the power output circuit is triggered by the first wake-up signal to output a startup voltage. The first detection circuit is connected to the input terminal of the power supply circuit and the power output circuit. The first detection circuit is used to output a second wake-up signal when the start-up voltage is received and the power supply voltage reaches the first reference voltage. The second detection circuit is connected to the first output terminal of the power supply circuit and the power output circuit. The second detection circuit is used to output a third wake-up signal when the start-up voltage is received and the power supply voltage is greater than the second reference voltage. The second reference voltage is greater than the first power supply voltage and less than the second power supply voltage. A logic control circuit is used to output the first enable signal when the first wake-up signal, the second wake-up signal and the third wake-up signal are received simultaneously.

2. The power supply output circuit of claim 1, wherein, The comparison circuit includes a first comparator, a first capacitor, a first resistor, and a second resistor; The non-inverting input terminal of the first comparator, the first terminal of the first capacitor, the first terminal of the first resistor, and the input terminal of the power supply circuit are connected. The inverting input terminal of the first comparator is used to input the first reference voltage. The second terminal of the first capacitor and the second terminal of the first resistor are grounded. The output terminal of the first comparator and the first terminal of the second resistor are connected to form the output terminal of the comparator circuit. The power supply terminal of the first comparator and the second terminal of the second resistor are connected and used to input a positive voltage.

3. The power supply output circuit of claim 1, wherein, The power output circuit includes a first inverter and a first electronic switch. The input terminal of the first inverter is connected to the output terminal of the comparator circuit, the output terminal of the first inverter is connected to the control terminal of the first electronic switch, the input terminal of the first electronic switch is used to input a positive voltage, and the output terminal of the first electronic switch constitutes the output terminal of the power output circuit.

4. The power supply output circuit of claim 1, wherein, The first detection circuit includes a second comparator, a non-inverting amplifier, a second inverter, a third resistor, a fourth resistor, and a second capacitor; The positive input end of the second comparator is connected with the input end of the power supply circuit, the inverting input end of the second comparator is used for inputting the first reference voltage, the power supply end of the second comparator is connected with the output end of the power supply output circuit, the output end of the second comparator is connected with the input end of the non-inverting amplifier, the output end of the non-inverting amplifier, the first end of the third resistor, the first end of the fourth resistor, the first end of the second capacitor and the input end of the second inverter are connected, the second end of the third resistor, the second end of the fourth resistor and the second end of the second capacitor are grounded, and the output end of the second inverter constitutes the output end of the first detection circuit.

5. The power supply output circuit of claim 1, wherein, The second detection circuit comprises a third comparator, a third capacitor, a fifth resistor and a third inverter; The non-inverting input end of the third comparator is used for inputting the second reference voltage, the first end of the third capacitor, the first end of the fifth resistor and the first output end of the power supply circuit are connected, the second end of the third capacitor is grounded, the second end of the fifth resistor is connected with the inverting input end of the third comparator, the power supply end of the third comparator is connected with the output end of the power supply output circuit, the output end of the third comparator is connected with the input end of the third inverter, and the output end of the third inverter constitutes the output end of the second detection circuit.

6. The power supply output circuit according to any one of claims 1 to 5, wherein The power management integrated circuit is further used for stopping working when receiving a third enabling signal; The driving circuit of the display panel further comprises a gate driving circuit; The power supply circuit further comprises a second output end, and the power supply circuit is further used for converting the power supply voltage into a driving voltage and outputting the driving voltage through the second output end, wherein when the display panel is switched from a sleep state to a wake-up state, the driving voltage is increased from a first driving voltage to a second driving voltage; The power supply output circuit further comprises: A switch circuit connected with the second output end of the power supply circuit and the gate driving circuit respectively, the switch circuit is triggered to be turned on by a second enabling signal and is triggered to be turned off by a fourth enabling signal; A third detection circuit connected with the second output end of the power supply circuit and the power supply output circuit, the third detection circuit is used for outputting a fourth wake-up signal when receiving the starting voltage and the driving voltage is greater than a third reference voltage, the third reference voltage is greater than the first driving voltage and less than the second driving voltage; The logic control circuit is used for outputting the first enabling signal and the second enabling signal when simultaneously receiving the first wake-up signal, the second wake-up signal, the third wake-up signal and the fourth wake-up signal, and outputting the third enabling signal and the fourth enabling signal otherwise.

7. The power supply output circuit of claim 6, wherein, The third detection circuit comprises a fourth comparator, a fourth capacitor, a sixth resistor and a fourth inverter; An input terminal of the fourth comparator is used for inputting the third reference voltage, a first terminal of the fourth capacitor, a first terminal of the sixth resistor and a second output terminal of the power supply circuit are connected, a second terminal of the fourth capacitor is grounded, a second terminal of the sixth resistor is connected with an inverting input terminal of the fourth comparator, a power supply terminal of the fourth comparator is connected with an output terminal of the power supply output circuit, an output terminal of the fourth inverter constitutes an output terminal of the third detection circuit.

8. The power supply output circuit of claim 6, wherein, The logic control circuit comprises an SR latch, an AND gate, a seventh resistor, an eighth resistor, a ninth resistor, a second electronic switch tube, a third electronic switch tube and a fourth electronic switch tube. An output terminal of the SR latch and a first input terminal of the AND gate are connected, a second input terminal of the AND gate is connected with an output terminal of the second detection circuit, a third input terminal of the AND gate is connected with an output terminal of the third detection circuit, an output terminal of the AND gate is connected with a control terminal of the third electronic switch tube and a control terminal of the fourth electronic switch tube respectively, a first terminal of the seventh resistor, a first terminal of the second electronic switch tube and a first terminal of the eighth resistor are connected and input a positive voltage, a second terminal of the seventh resistor, a control terminal of the second electronic switch tube and a first terminal of the third electronic switch tube are connected, a second terminal of the third electronic switch tube is grounded, a second terminal of the second electronic switch tube is connected with a control terminal of the switch circuit, a second terminal of the eighth resistor, a first terminal of the ninth resistor and a first terminal of the fourth electronic switch tube are connected, a second terminal of the ninth resistor is grounded, and a second terminal of the fourth electronic switch tube is connected with an enable terminal of the power management integrated circuit.

9. The power supply output circuit of claim 8, wherein, The logic control circuit further comprises a tenth resistor, an eleventh resistor, a fifth capacitor and a Schmitt trigger; A first terminal of the tenth resistor and an output terminal of the AND gate are connected, a second terminal of the tenth resistor, a first terminal of the fifth capacitor, a first terminal of the eleventh resistor and an input terminal of the Schmitt trigger are connected, a second terminal of the fifth capacitor and a second terminal of the eleventh resistor are grounded, and an output terminal of the Schmitt trigger is connected with the control terminal of the third electronic switch tube and the control terminal of the fourth electronic switch tube respectively.

10. A display device, characterized by comprising: A driving circuit of a display panel and the power supply output circuit according to any one of claims 1-9 are connected.

Images