Communication method, device and system

Abstract

The invention provides a communication method, device and system, and belongs to the technical field of communication, and the method comprises the steps: obtaining a bit rearrangement book table, the bit rearrangement book table comprises output bit sequences respectively corresponding to each bit rearrangement version number under different QAMs (Quadrature Amplitude Modulation), and the different QAMs comprise 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; and determining an output bit sequence according to the bit reset list. According to the invention, the earnings of the HARQ can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, and particularly relates to a communication method, device and system. BACKGROUND

[0002] Due to the influence of fading and interference, a retransmission mechanism needs to be used to improve the reliability of transmission of a channel of a wireless communication system. The wireless communication system mainly performs fast retransmission through a media access control (MAC) layer. When the MAC layer uses a hybrid automatic repeat request (HARQ) mechanism to perform retransmission, the receiving end needs to store and superimpose the log likelihood ratio (LLR) of each bit of each transmission.

[0003] If the modulation mode used by the sending end when performing data transmission is high-order modulation, multiple bits have different reliabilities when being mapped to the same symbol. Thus, after multiple retransmissions, the receiving end superimposes the LLR of the bits of multiple transmissions, and the reliability gap of each bit mapped to the same symbol is larger, thereby resulting in poor performance benefits of HARQ retransmission. SUMMARY

[0004] The present application provides a communication method, device and system, and solves the problem of poor performance benefits of HARQ retransmission in the related art, and can effectively improve the benefits of HARQ.

[0005] In a first aspect, the present application provides a communication method, which comprises: obtaining a bit rearrangement version table, the bit rearrangement version table comprising output bit sequences respectively corresponding to bit rearrangement version (BV) numbers under different quadrature amplitude modulation (QAM), and the different QAM comprising 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; and determining the output bit sequences according to the bit rearrangement version table.

[0006] The bit rearrangement version table is used to adopt different bit rearrangement versions at each transmission, and the benefits of HARQ can be improved, and the higher the modulation mode, the greater the benefits.

[0007] In a possible implementation, the process of determining the output bit sequence according to the bit rearrangement version table comprises: determining the output bit sequence according to the input bit sequence, the bit rearrangement version number, and the bit rearrangement version table. For example, the input bit sequence is subjected to a bit rearrangement operation according to the output bit sequence corresponding to the bit rearrangement version number in the bit rearrangement version table, to obtain the output bit sequence.

[0008] The application provides a communication method, which comprises: generating scheduling type indication information, the scheduling type indication information indicating a hybrid transmission of retransmission based on a first retransmission data unit or initial transmission retransmission, determining a first redundancy version and a channel bit sequence of a first bit rearrangement version by using a first encoding mode, the first retransmission data unit being a transport block or a coded block group; and transmitting the scheduling type indication information; wherein the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number in the first QAM in a bit rearrangement version table, the first QAM being 16QAM, 64QAM, 256QAM, 1024QAM, or 4096QAM.

[0009] The application has the beneficial effect that different bit rearrangement versions are used in each transmission by means of the bit rearrangement version table, which can improve the benefits of HARQ, and the higher the modulation mode, the greater the benefits. Moreover, the bit rearrangement version is bound to the redundancy version, the redundancy version and the bit rearrangement version can be indicated simultaneously by means of the scheduling type indication information, and the bit rearrangement version does not need to occupy other bits, thereby effectively saving scheduling resources.

[0010] In a possible implementation, the input bit sequence under 16QAM is b(4i), b(4i+1), b(4i+2), and b(4i+3), b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(4i) and b(4i+2) are mapped to the real part of the constellation symbol, and b(4i+1) and b(4i+3) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table comprises:

[0011]

[0012] In a possible implementation, the input bit sequence under 64QAM is b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), and b(6i+5), b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(6i), b(6i+2), and b(6i+4) are mapped to the real part of the constellation symbol, and b(6i+1), b(6i+3), and b(6i+5) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table comprises:

[0013]

[0014] In a possible implementation, the input bit sequence under 256QAM is b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7), where b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(8i), b(8i+2), b(8i+4), and b(8i+6) are mapped to the real part of the constellation symbol, and b(8i+1), b(8i+3), b(8i+5), and b(8i+7) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0015]

[0016] In a possible implementation, the input bit sequence under 1024QAM is b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9), where b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(10i), b(10i+2), b(10i+4), b(10i+6), and b(10i+8) are mapped to the real part of the constellation symbol, and b(10i+1), b(10i+3), b(10i+5), b(10i+7), and b(10i+9) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0017]

[0018] In a possible implementation, the input bit sequence under 4096QAM is b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), b(12i+11), where b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(12i), b(12i+2), b(12i+4), b(12i+6), b(12i+8), and b(12i+10) are mapped to the real part of the constellation symbol, and b(12i+1), b(12i+3), b(12i+5), b(12i+7), b(12i+9), and b(12i+11) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0019]

[0020]

[0021] In a possible implementation, the constellation symbol is one symbol in a constellation diagram obtained by modulating and mapping the output bit sequence in the first bit rearrangement version.

[0022] In a third aspect, the present application provides a communication method, which comprises: obtaining a bit rearrangement version table, the bit rearrangement version table comprising an output bit sequence corresponding to each bit rearrangement version number in at least one QAM, the at least one QAM comprising at least one of the following: 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; and determining the output bit sequence according to the bit rearrangement version table.

[0023] In a possible implementation, the process of determining the output bit sequence according to the bit rearrangement version table comprises: determining the output bit sequence according to the input bit sequence, the bit rearrangement version number and the bit rearrangement version table. For example, performing a bit rearrangement operation on the input bit sequence according to the output bit sequence corresponding to the bit rearrangement version number in the bit rearrangement version table to obtain the output bit sequence.

[0024] In a fourth aspect, the present application provides a communication method, which comprises: generating bit rearrangement version information, the bit rearrangement version information indicating a first bit rearrangement version in a bit rearrangement version table; and transmitting the bit rearrangement version information; wherein the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number in a first QAM, and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

[0025] In a possible implementation, the bit rearrangement version information is carried in scheduling type indication information; wherein the scheduling type indication information indicates that a first redundancy version and a channel bit sequence of a first bit rearrangement version are determined by using a first encoding mode based on retransmission or initial transmission and retransmission hybrid transmission of a first retransmission data unit, and the first retransmission data unit is a transport block or a code block group.

[0026] In a possible implementation, the bit rearrangement version information is bound to target information, and the target information is used to indicate a redundancy version number or a superframe number.

[0027] In a possible implementation, the bit rearrangement version information is carried in dynamic scheduling data control information, control signaling or a superframe header.

[0028] In a possible implementation, the input bit sequence under 16QAM is i1i2q1q2, i1, i2, q1 and q2 represent a bit value respectively, i1 and i2 are mapped to the real part of a constellation symbol, and q1 and q2 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a first bit rearrangement version number, and the output bit sequence corresponding to the first bit rearrangement version number is i1i2q1q2.

[0029] In a possible implementation, the bit rearrangement version table further includes a second bit rearrangement version number, and the output bit sequence corresponding to the second bit rearrangement version number is

[0030] In a possible implementation, the bit rearrangement version table further includes a third bit rearrangement version number, and the output bit sequence corresponding to the third bit rearrangement version number is

[0031] In a possible implementation, the bit rearrangement version table further includes a fourth bit rearrangement version number, and the output bit sequence corresponding to the fourth bit rearrangement version number is i2i1q2q1.

[0032] In a possible implementation, the input bit sequence under 64QAM is i1i2i3q1q2q3, i1, i2, i3, q1, q2 and q3 represent a bit value respectively, i1, i2 and i3 are mapped to the real part of a constellation symbol, and q1, q2 and q3 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a fifth bit rearrangement version number, and the output bit sequence corresponding to the fifth bit rearrangement version number is i1i2i3q1q2q3.

[0033] In a possible implementation, the bit rearrangement version table further includes a sixth bit rearrangement version number, and the output bit sequence corresponding to the sixth bit rearrangement version number is

[0034] In a possible implementation, the bit rearrangement version table further includes a seventh bit rearrangement version number, and the output bit sequence corresponding to the seventh bit rearrangement version number is

[0035] In a possible implementation, the bit rearrangement version table further includes an eighth bit rearrangement version number, and the output bit sequence corresponding to the eighth bit rearrangement version number is

[0036] In a possible implementation, the input bit sequence under 256QAM is i1i2i3i4q1q2q3q4, i1, i2, i3, i4, q1, q2, q3, and q4 represent a bit value respectively, i1, i2, i3, i4 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a ninth bit rearrangement version number, and the output bit sequence corresponding to the ninth bit rearrangement version number is i1i2i3i4q1q2q3q4.

[0037] In a possible implementation, the bit rearrangement version table further includes a tenth bit rearrangement version number, and the output bit sequence corresponding to the tenth bit rearrangement version number is

[0038] In a possible implementation, the bit rearrangement version table further includes an eleventh bit rearrangement version number, and the output bit sequence corresponding to the eleventh bit rearrangement version number is

[0039] In a possible implementation, the bit rearrangement version table further includes a twelfth bit rearrangement version number, and the output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

[0040] In a possible implementation, the input bit sequence under 1024QAM is i1i2i3i4i5q1q2q3q4q5, i1, i2, i3, i4, i5, q1, q2, q3, q4, and q5 represent a bit value respectively, i1, i2, i3, i4, i5 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4, q5 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a thirteenth bit rearrangement version number, and the output bit sequence corresponding to the thirteenth bit rearrangement version number is i1i2i3i4i5q1q2q3q4q5.

[0041] In a possible implementation, the bit rearrangement version table further includes a fourteenth bit rearrangement version number, and the output bit sequence corresponding to the fourteenth bit rearrangement version number is i5i4i3i2i1q5q4q3q2q1.

[0042] In a possible implementation, the bit rearrangement version table further includes a fifteenth bit rearrangement version number, and the output bit sequence corresponding to the fifteenth bit rearrangement version number is

[0043] In a possible implementation, the bit rearrangement version table further includes a sixteenth bit rearrangement version number, and the output bit sequence corresponding to the sixteenth bit rearrangement version number is

[0044] In a possible implementation, the input bit sequence under 4096QAM is i1i2i3i4i5i6q1q2q3q4q5q6, i1, i2, i3, i4, i5, i6, q1, q2, q3, q4, q5, and q6 represent a bit value respectively, i1, i2, i3, i4, i5, i6 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4, q5, q6 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a seventeenth bit rearrangement version number, and the output bit sequence corresponding to the seventeenth bit rearrangement version number is i1i2i3i4i5i6q1q2q3q4q5q6.

[0045] In a possible implementation, the bit rearrangement version table further includes an eighteenth bit rearrangement version number, and the output bit sequence corresponding to the eighteenth bit rearrangement version number is i6i5i4i3i2i1q6q5q4q3q2q1.

[0046] In a possible implementation, the bit rearrangement version table further includes a nineteenth bit rearrangement version number, and the output bit sequence corresponding to the nineteenth bit rearrangement version number is

[0047] In a possible implementation, the bit rearrangement version table further includes a twentieth bit rearrangement version number, and the output bit sequence corresponding to the twentieth bit rearrangement version number is i4i2i5i3i1i6q4q2q5q3q1q6.

[0048] In a possible implementation, the method further includes: modulating and mapping the output bit sequence in the first bit rearrangement version to obtain a constellation symbol in a constellation diagram.

[0049] In a fifth aspect, the present application provides a communication method, which includes: obtaining a bit rearrangement version table, the bit rearrangement version table including output bit sequences corresponding to respective bit rearrangement version numbers under different QAMs, the different QAMs including 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM; and determining an input bit sequence according to the bit rearrangement version table.

[0050] In a possible implementation, the process of determining the input bit sequence according to the bit rearrangement version table includes: determining the input bit sequence according to the output bit sequence, the bit rearrangement version number, and the bit rearrangement version table.

[0051] In a sixth aspect, the present application provides a communication method, comprising: receiving scheduling type indication information, the scheduling type indication information indicating that a retransmission based on a first retransmission data unit or a hybrid transmission of initial transmission and retransmission, a first encoding mode is used to determine a first redundancy version and a first bit rearrangement version of a channel bit sequence, the first retransmission data unit is a transport block or a code block group; decoding and bit rearranging the channel bit sequence according to the scheduling type indication information; wherein the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number of the first QAM in a bit rearrangement version table, the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

[0052] For example, decoding and bit rearranging are performed according to the first encoding mode, the first redundancy version and the first bit rearrangement version.

[0053] In a possible implementation, the input bit sequence under 16QAM is b(4i), b(4i+1), b(4i+2), b(4i+3), b() represents a bit value, i represents the serial number of the constellation symbol corresponding to the input bit sequence in the constellation diagram, b(4i), b(4i+2) are mapped to the real part of the constellation symbol, and b(4i+1), b(4i+3) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table comprises:

[0054]

[0055] In a possible implementation, the input bit sequence under 64QAM is b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5), b() represents a bit value, i represents the serial number of the constellation symbol corresponding to the input bit sequence in the constellation diagram, b(6i), b(6i+2), b(6i+4) are mapped to the real part of the constellation symbol, and b(6i+1), b(6i+3), b(6i+5) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table comprises:

[0056]

[0057] In a possible implementation, the input bit sequence under 256QAM is b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7), b() represents a bit value, i represents the sequence number of the constellation symbol corresponding to the input bit sequence in the constellation diagram, b(8i), b(8i+2), b(8i+4), b(8i+6) are mapped to the real part of the constellation symbol, and b(8i+1), b(8i+3), b(8i+5), b(8i+7) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0058]

[0059] In a possible implementation, the input bit sequence under 1024QAM is b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9), b() represents a bit value, i represents the sequence number of the constellation symbol corresponding to the input bit sequence in the constellation diagram, b(10i), b(10i+2), b(10i+4), b(10i+6), b(10i+8) are mapped to the real part of the constellation symbol, and b(10i+1), b(10i+3), b(10i+5), b(10i+7), b(10i+9) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0060]

[0061] In a possible implementation, the input bit sequence under 4096QAM is b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), b(12i+11), b() represents a bit value, i represents the sequence number of the constellation symbol corresponding to the input bit sequence in the constellation diagram, b(12i), b(12i+2), b(12i+4), b(12i+6), b(12i+8), b(12i+10) are mapped to the real part of the constellation symbol, and b(12i+1), b(12i+3), b(12i+5), b(12i+7), b(12i+9), b(12i+11) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0062]

[0063]

[0064] In a possible implementation, the constellation symbol is one symbol in a constellation diagram obtained by modulating and mapping the output bit sequence in the first bit rearrangement version.

[0065] In a seventh aspect, the present application provides a communication method, which comprises: obtaining a bit rearrangement version table, the bit rearrangement version table comprising an output bit sequence corresponding to each bit rearrangement version number in at least one QAM, the at least one QAM comprising at least one of the following: 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; and determining an input bit sequence according to the bit rearrangement version table.

[0066] In a possible implementation, the process of determining the input bit sequence according to the bit rearrangement version table comprises: determining the input bit sequence according to the output bit sequence, the bit rearrangement version number and the bit rearrangement version table.

[0067] In an eighth aspect, the present application provides a communication method, which comprises: receiving bit rearrangement version information, the bit rearrangement version information indicating a first bit rearrangement version in a bit rearrangement version table; and performing bit rearrangement according to the bit rearrangement version information; wherein the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number in a first QAM, and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

[0068] In a possible implementation, the bit rearrangement version information is carried in scheduling type indication information; wherein the scheduling type indication information indicates that the retransmission or initial transmission and retransmission hybrid transmission based on a first retransmission data unit adopts a first encoding mode to determine a channel bit sequence of a first redundancy version and a first bit rearrangement version, and the first retransmission data unit is a transport block or a coded block group.

[0069] In a possible implementation, the bit rearrangement version information is bound to target information, and the target information is used to indicate a redundancy version number or a superframe number.

[0070] In a possible implementation, the bit rearrangement version information is carried in dynamic scheduling data control information, control signaling or a superframe header.

[0071] In a possible implementation, the input bit sequence in 16QAM is i1i2q1q2, i1, i2, q1 and q2 represent a bit value respectively, i1 and i2 are mapped to the real part of a constellation symbol, and q1 and q2 are mapped to the imaginary part of the constellation symbol; and the bit rearrangement version table comprises a first bit rearrangement version number, and the output bit sequence corresponding to the first bit rearrangement version number is i1i2q1q2.

[0072] In a possible implementation, the bit rearrangement version table further includes a second bit rearrangement version number, and the output bit sequence corresponding to the second bit rearrangement version number is

[0073] In a possible implementation, the bit rearrangement version table further includes a third bit rearrangement version number, and the output bit sequence corresponding to the third bit rearrangement version number is

[0074] In a possible implementation, the bit rearrangement version table further includes a fourth bit rearrangement version number, and the output bit sequence corresponding to the fourth bit rearrangement version number is i2i1q2q1.

[0075] In a possible implementation, the input bit sequence under 64QAM is i1i2i3q1q2q3, i1, i2, i3, q1, q2, and q3 represent a bit value respectively, i1, i2, i3 are mapped to the real part of a constellation symbol, and q1, q2, q3 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a fifth bit rearrangement version number, and the output bit sequence corresponding to the fifth bit rearrangement version number is i1i2i3q1q2q3.

[0076] In a possible implementation, the bit rearrangement version table further includes a sixth bit rearrangement version number, and the output bit sequence corresponding to the sixth bit rearrangement version number is

[0077] In a possible implementation, the bit rearrangement version table further includes a seventh bit rearrangement version number, and the output bit sequence corresponding to the seventh bit rearrangement version number is

[0078] In a possible implementation, the bit rearrangement version table further includes an eighth bit rearrangement version number, and the output bit sequence corresponding to the eighth bit rearrangement version number is

[0079] In a possible implementation, the input bit sequence under 256QAM is i1i2i3i4q1q2q3q4, i1, i2, i3, i4, q1, q2, q3, and q4 represent a bit value respectively, i1, i2, i3, i4 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a ninth bit rearrangement version number, and the output bit sequence corresponding to the ninth bit rearrangement version number is i1i2i3i4q1q2q3q4.

[0080] In a possible implementation, the bit rearrangement version table further includes a tenth bit rearrangement version number, and the output bit sequence corresponding to the tenth bit rearrangement version number is

[0081] In a possible implementation, the bit rearrangement version table further includes an eleventh bit rearrangement version number, and the output bit sequence corresponding to the eleventh bit rearrangement version number is i3i2i1i4q3q2q1q4.

[0082] In a possible implementation, the bit rearrangement version table further includes a twelfth bit rearrangement version number, and the output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

[0083] In a possible implementation, the input bit sequence under 1024QAM is i1i2i3i4i5q1q2q3q4q5, i1, i2, i3, i4, i5, q1, q2, q3, q4, and q5 represent a bit value respectively, i1, i2, i3, i4, i5 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4, q5 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a thirteenth bit rearrangement version number, and the output bit sequence corresponding to the thirteenth bit rearrangement version number is i1i2i3i4i5q1q2q3q4q5.

[0084] In a possible implementation, the bit rearrangement version table further includes a fourteenth bit rearrangement version number, and the output bit sequence corresponding to the fourteenth bit rearrangement version number is i5i4i3i2i1q5q4q3q2q1.

[0085] In a possible implementation, the bit rearrangement version table further includes a fifteenth bit rearrangement version number, and the output bit sequence corresponding to the fifteenth bit rearrangement version number is

[0086] In a possible implementation, the bit rearrangement version table further includes a sixteenth bit rearrangement version number, and the output bit sequence corresponding to the sixteenth bit rearrangement version number is

[0087] In a possible implementation, the input bit sequence under 4096QAM is i1i2i3i4i5i6q1q2q3q4q5q6, i1, i2, i3, i4, i5, i6, q1, q2, q3, q4, q5, and q6 represent a bit value respectively, i1, i2, i3, i4, i5, i6 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4, q5, q6 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a seventeenth bit rearrangement version number, and the output bit sequence corresponding to the seventeenth bit rearrangement version number is i1i2i3i4i5i6q1q2q3q4q5q6.

[0088] In a possible implementation, the bit rearrangement version table further includes an eighteenth bit rearrangement version number, and an output bit sequence corresponding to the eighteenth bit rearrangement version number is i6i5i4i3i2i1q6q5q4q3q2q1.

[0089] In a possible implementation, the bit rearrangement version table further includes a nineteenth bit rearrangement version number, and an output bit sequence corresponding to the nineteenth bit rearrangement version number is

[0090] In a possible implementation, the bit rearrangement version table further includes a twentieth bit rearrangement version number, and an output bit sequence corresponding to the twentieth bit rearrangement version number is i4i2i5i3i1i6q4q2q5q3q1q6.

[0091] In a ninth aspect, the present application provides a communication device, the communication device comprising a star flash module for implementing transmission of a star flash signal, the communication device further comprising: a module for obtaining a bit rearrangement version table, the bit rearrangement version table comprising an output bit sequence corresponding to each bit rearrangement version number under different QAMs, the different QAMs comprising 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; and a module for determining an output bit sequence according to the bit rearrangement version table.

[0092] In a possible implementation, the module for determining an output bit sequence according to the bit rearrangement version table is specifically configured to determine the output bit sequence according to an input bit sequence, a bit rearrangement version number and the bit rearrangement version table.

[0093] In a tenth aspect, the present application provides a communication device, the communication device comprising a star flash module for implementing transmission of a star flash signal, the communication device further comprising: a module for generating scheduling type indication information, the scheduling type indication information indicating hybrid transmission of retransmission based on a first retransmission data unit or initial transmission retransmission, determining a first redundancy version and a first bit rearrangement version of a channel bit sequence by using a first encoding mode, the first retransmission data unit being a transport block or a code block group; and a module for sending the scheduling type indication information; wherein the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number under a first QAM in a bit rearrangement version table, the first QAM being 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

[0094] In a possible implementation, the input bit sequence under 16QAM is b(4i), b(4i+1), b(4i+2), b(4i+3), where b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(4i), b(4i+2) are mapped to the real part of the constellation symbol, and b(4i+1), b(4i+3) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0095]

[0096] In a possible implementation, the input bit sequence under 64QAM is b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5), where b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(6i), b(6i+2), b(6i+4) are mapped to the real part of the constellation symbol, and b(6i+1), b(6i+3), b(6i+5) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0097]

[0098] In a possible implementation, the input bit sequence under 256QAM is b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7), where b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(8i), b(8i+2), b(8i+4), b(8i+6) are mapped to the real part of the constellation symbol, and b(8i+1), b(8i+3), b(8i+5), b(8i+7) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0099]

[0100] In a possible implementation, the input bit sequence under 1024QAM is b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9), b() representing a bit value, i representing the serial number of a constellation symbol corresponding to the input bit sequence in the constellation diagram, b(10i), b(10i+2), b(10i+4), b(10i+6), b(10i+8) being mapped to the real part of the constellation symbol, and b(10i+1), b(10i+3), b(10i+5), b(10i+7), b(10i+9) being mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0101]

[0102] In a possible implementation, the input bit sequence under 4096QAM is b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), b(12i+11), b() representing a bit value, i representing the serial number of a constellation symbol corresponding to the input bit sequence in the constellation diagram, b(12i), b(12i+2), b(12i+4), b(12i+6), b(12i+8), b(12i+10) being mapped to the real part of the constellation symbol, and b(12i+1), b(12i+3), b(12i+5), b(12i+7), b(12i+9), b(12i+11) being mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0103]

[0104]

[0105] In a possible implementation, the constellation symbol is a symbol in a constellation diagram obtained by modulating and mapping the output bit sequence in the first bit rearrangement version.

[0106] In a possible implementation, the module for determining the output bit sequence according to the bit rearrangement version table is specifically configured to: determine the output bit sequence according to the input bit sequence, the bit rearrangement version number, and the bit rearrangement version table.

[0107] In a possible implementation, the module for determining the output bit sequence according to the bit rearrangement version table is specifically configured to: determine the output bit sequence according to the input bit sequence, the bit rearrangement version number, and the bit rearrangement version table.

[0108] In a possible implementation, the module for determining the output bit sequence according to the bit rearrangement version table is specifically configured to: determine the output bit sequence according to the input bit sequence, the bit rearrangement version number, and the bit rearrangement version table.

[0109] In a possible implementation, the bit rearrangement version information is carried in scheduling type indication information, and the scheduling type indication information indicates that the retransmission or initial transmission and retransmission hybrid transmission based on a first retransmission data unit is used to determine the channel bit sequence of the first redundancy version and the first bit rearrangement version by using a first encoding mode, and the first retransmission data unit is a transport block or a code block group.

[0110] In a possible implementation, the bit rearrangement version information is bound to target information, and the target information is used to indicate a redundancy version number or a superframe number.

[0111] In a possible implementation, the bit rearrangement version information is carried in dynamic scheduling data control information, control signaling, or a superframe header.

[0112] In a possible implementation, the input bit sequence under 16QAM is i1i2q1q2, i1, i2, q1, and q2 respectively represent a bit value, i1 and i2 are mapped to the real part of a constellation symbol, and q1 and q2 are mapped to the imaginary part of the constellation symbol; and the bit rearrangement version table includes a first bit rearrangement version number, and the output bit sequence corresponding to the first bit rearrangement version number is i1i2q1q2.

[0113] In a possible implementation, the bit rearrangement version table further includes a second bit rearrangement version number, and the output bit sequence corresponding to the second bit rearrangement version number is

[0114] In a possible implementation, the bit rearrangement version table further includes a third bit rearrangement version number, and the output bit sequence corresponding to the third bit rearrangement version number is

[0115] In a possible implementation, the bit rearrangement version table further includes a fourth bit rearrangement version number, and the output bit sequence corresponding to the fourth bit rearrangement version number is i2i1q2q1.

[0116] In a possible implementation, the input bit sequence under 64QAM is i1i2i3q1q2q3, i1, i2, i3, q1, q2, and q3 represent a bit value respectively, i1, i2, i3 are mapped to the real part of a constellation symbol, and q1, q2, q3 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a fifth bit rearrangement version number, and the output bit sequence corresponding to the fifth bit rearrangement version number is i1i2i3q1q2q3.

[0117] In a possible implementation, the bit rearrangement version table further includes a sixth bit rearrangement version number, and the output bit sequence corresponding to the sixth bit rearrangement version number is

[0118] In a possible implementation, the bit rearrangement version table further includes a seventh bit rearrangement version number, and the output bit sequence corresponding to the seventh bit rearrangement version number is

[0119] In a possible implementation, the bit rearrangement version table further includes an eighth bit rearrangement version number, and the output bit sequence corresponding to the eighth bit rearrangement version number is

[0120] In a possible implementation, the input bit sequence under 256QAM is i1i2i3i4q1q2q3q4, i1, i2, i3, i4, q1, q2, q3, and q4 represent a bit value respectively, i1, i2, i3, i4 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a ninth bit rearrangement version number, and the output bit sequence corresponding to the ninth bit rearrangement version number is i1i2i3i4q1q2q3q4.

[0121] In a possible implementation, the bit rearrangement version table further includes a tenth bit rearrangement version number, and the output bit sequence corresponding to the tenth bit rearrangement version number is

[0122] In a possible implementation, the bit rearrangement version table further includes an eleventh bit rearrangement version number, and the output bit sequence corresponding to the eleventh bit rearrangement version number is i3i2i1i4q3q2q1q4.

[0123] In a possible implementation, the bit rearrangement version table further includes a twelfth bit rearrangement version number, and the output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

[0124] In a possible implementation, the input bit sequence under 1024QAM is i1i2i3i4i5q1q2q3q4q5, i1, i2, i3, i4, i5, q1, q2, q3, q4, and q5 represent a bit value respectively, i1, i2, i3, i4, i5 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4, q5 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a thirteenth bit rearrangement version number, and the output bit sequence corresponding to the thirteenth bit rearrangement version number is i1i2i3i4i5q1q2q3q4q5.

[0125] In a possible implementation, the bit rearrangement version table further includes a fourteenth bit rearrangement version number, and the output bit sequence corresponding to the fourteenth bit rearrangement version number is i5i4i3i2i1q5q4q3q2q1.

[0126] In a possible implementation, the bit rearrangement version table further includes a fifteenth bit rearrangement version number, and the output bit sequence corresponding to the fifteenth bit rearrangement version number is

[0127] In a possible implementation, the bit rearrangement version table further includes a sixteenth bit rearrangement version number, and the output bit sequence corresponding to the sixteenth bit rearrangement version number is

[0128] In a possible implementation, the input bit sequence under 4096QAM is i1i2i3i4i5i6q1q2q3q4q5q6, i1, i2, i3, i4, i5, i6, q1, q2, q3, q4, q5, and q6 represent a bit value respectively, i1, i2, i3, i4, i5, i6 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4, q5, q6 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a seventeenth bit rearrangement version number, and the output bit sequence corresponding to the seventeenth bit rearrangement version number is i1i2i3i4i5i6q1q2q3q4q5q6.

[0129] In a possible implementation, the bit rearrangement version table further includes an eighteenth bit rearrangement version number, and an output bit sequence corresponding to the eighteenth bit rearrangement version number is i6i5i4i3i2i1q6q5q4q3q2q1.

[0130] In a possible implementation, the bit rearrangement version table further includes a nineteenth bit rearrangement version number, and an output bit sequence corresponding to the nineteenth bit rearrangement version number is

[0131] In a possible implementation, the bit rearrangement version table further includes a twentieth bit rearrangement version number, and an output bit sequence corresponding to the twentieth bit rearrangement version number is i4i2i5i3i1i6q4q2q5q3q1q6.

[0132] In a possible implementation, the communication apparatus is further configured to perform modulation mapping on the output bit sequence in the first bit rearrangement version to obtain a constellation symbol in a constellation diagram.

[0133] In a thirteenth aspect, the present application provides a communication apparatus, the communication apparatus comprising a star flash module configured to implement transmission of a star flash signal, and the communication apparatus further comprising: a module configured to obtain a bit rearrangement version table, the bit rearrangement version table comprising output bit sequences corresponding to respective bit rearrangement version numbers under different QAMs, the different QAMs comprising 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; and a module configured to determine an input bit sequence according to the bit rearrangement version table.

[0134] In a possible implementation, the module configured to determine the input bit sequence according to the bit rearrangement version table is specifically configured to determine the input bit sequence according to the output bit sequence, the bit rearrangement version number and the bit rearrangement version table.

[0135] In a fourteenth aspect, the present application provides a communication apparatus, the communication apparatus comprising a star flash module configured to implement transmission of a star flash signal, and the communication apparatus further comprising: a module configured to receive scheduling type indication information, the scheduling type indication information indicating hybrid transmission of retransmission based on a first retransmission data unit or initial transmission retransmission, and the first coding mode being used to determine a first redundancy version and a first bit rearrangement version of a channel bit sequence, the first retransmission data unit being a transport block or a coded block group; and a module configured to decode and perform bit rearrangement on the channel bit sequence according to the scheduling type indication information; wherein the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number under a first QAM in a bit rearrangement version table, and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

[0136] In a possible implementation, the input bit sequence under 16QAM is b(4i), b(4i+1), b(4i+2), b(4i+3), b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(4i), b(4i+2) are mapped to the real part of the constellation symbol, and b(4i+1), b(4i+3) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0137]

[0138] In a possible implementation, the input bit sequence under 64QAM is b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5), b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(6i), b(6i+2), b(6i+4) are mapped to the real part of the constellation symbol, and b(6i+1), b(6i+3), b(6i+5) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0139]

[0140] In a possible implementation, the input bit sequence under 256QAM is b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7), b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(8i), b(8i+2), b(8i+4), b(8i+6) are mapped to the real part of the constellation symbol, and b(8i+1), b(8i+3), b(8i+5), b(8i+7) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0141]

[0142] In a possible implementation, the input bit sequence under 1024QAM is b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9), b(), where b represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(10i), b(10i+2), b(10i+4), b(10i+6), and b(10i+8) are mapped to the real part of the constellation symbol, and b(10i+1), b(10i+3), b(10i+5), b(10i+7), and b(10i+9) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0143]

[0144] In a possible implementation, the input bit sequence under 4096QAM is b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), b(12i+11), b(), where b represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(12i), b(12i+2), b(12i+4), b(12i+6), b(12i+8), and b(12i+10) are mapped to the real part of the constellation symbol, and b(12i+1), b(12i+3), b(12i+5), b(12i+7), b(12i+9), and b(12i+11) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0145]

[0146]

[0147] In a possible implementation, the constellation symbol is a symbol in a constellation diagram obtained by modulating and mapping the output bit sequence in the first bit rearrangement version.

[0148] In a fifteenth aspect, the present application provides a communication device, the communication device comprising a star flash module for implementing transmission of a star flash signal, the communication device further comprising: a module for obtaining a bit rearrangement version table, the bit rearrangement version table comprising an output bit sequence corresponding to each bit rearrangement version number under at least one QAM, the at least one QAM comprising at least one of 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; and a module for determining an input bit sequence according to the bit rearrangement version table.

[0149] In a possible implementation, the module for determining the input bit sequence according to the bit rearrangement version table is specifically configured to determine the input bit sequence according to the output bit sequence, the bit rearrangement version number and the bit rearrangement version table.

[0150] In a sixteenth aspect, the present application provides a communication device, the communication device comprising a star flash module for implementing transmission of a star flash signal, the communication device further comprising: a module for receiving bit rearrangement version information, the bit rearrangement version information indicating a first bit rearrangement version in a bit rearrangement version table; and a module for performing bit rearrangement according to the bit rearrangement version information; wherein the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number under a first QAM, the first QAM being 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

[0151] In a possible implementation, the bit rearrangement version information is carried in scheduling type indication information, wherein the scheduling type indication information indicates that a first redundancy version and a channel bit sequence of a first bit rearrangement version are determined using a first encoding mode based on retransmission or initial transmission retransmission hybrid transmission of a first retransmission data unit, the first retransmission data unit being a transport block or a code block group.

[0152] In a possible implementation, the bit rearrangement version information is bound to target information, the target information being used to indicate a redundancy version number or a superframe number.

[0153] In a possible implementation, the bit rearrangement version information is carried in dynamic scheduling data control information, control signaling or a superframe header.

[0154] In a possible implementation, the input bit sequence under 16QAM is i1i2q1q2, i1, i2, q1 and q2 each represent a bit value, i1 and i2 are mapped to a real part of a constellation symbol, and q1 and q2 are mapped to an imaginary part of the constellation symbol; and the bit rearrangement version table comprises a first bit rearrangement version number, the output bit sequence corresponding to the first bit rearrangement version number being i1i2q1q2.

[0155] In a possible implementation, the bit rearrangement version table further includes a second bit rearrangement version number, and the output bit sequence corresponding to the second bit rearrangement version number is

[0156] In a possible implementation, the bit rearrangement version table further includes a third bit rearrangement version number, and the output bit sequence corresponding to the third bit rearrangement version number is

[0157] In a possible implementation, the bit rearrangement version table further includes a fourth bit rearrangement version number, and the output bit sequence corresponding to the fourth bit rearrangement version number is i2i1q2q1.

[0158] In a possible implementation, the input bit sequence under 64QAM is i1i2i3q1q2q3, i1, i2, i3, q1, q2, and q3 represent a bit value respectively, i1, i2, i3 are mapped to the real part of a constellation symbol, and q1, q2, q3 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a fifth bit rearrangement version number, and the output bit sequence corresponding to the fifth bit rearrangement version number is i1i2i3q1q2q3.

[0159] In a possible implementation, the bit rearrangement version table further includes a sixth bit rearrangement version number, and the output bit sequence corresponding to the sixth bit rearrangement version number is

[0160] In a possible implementation, the bit rearrangement version table further includes a seventh bit rearrangement version number, and the output bit sequence corresponding to the seventh bit rearrangement version number is

[0161] In a possible implementation, the bit rearrangement version table further includes an eighth bit rearrangement version number, and the output bit sequence corresponding to the eighth bit rearrangement version number is

[0162] In a possible implementation, the input bit sequence under 256QAM is i1i2i3i4q1q2q3q4, i1, i2, i3, i4, q1, q2, q3, and q4 represent a bit value respectively, i1, i2, i3, i4 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a ninth bit rearrangement version number, and the output bit sequence corresponding to the ninth bit rearrangement version number is i1i2i3i4q1q2q3q4.

[0163] In a possible implementation, the bit rearrangement version table further includes a tenth bit rearrangement version number, and the output bit sequence corresponding to the tenth bit rearrangement version number is

[0164] In a possible implementation manner of the method In the formula The bit rearrangement version table further includes an eleventh bit rearrangement version number, and an output bit sequence corresponding to the eleventh bit rearrangement version number is i3i2i1i4q3q2q1q4.

[0165] In a possible implementation manner, the bit rearrangement version table further includes a twelfth bit rearrangement version number, and an output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

[0166] In a possible implementation manner, an input bit sequence under 1024QAM is i1i2i3i4i5q1q2q3q4q5, i1, i2, i3, i4, i5, q1, q2, q3, q4, and q5 respectively represent a bit value, i1, i2, i3, i4, i5 are mapped to a real part of a constellation symbol, and q1, q2, q3, q4, q5 are mapped to an imaginary part of the constellation symbol; the bit rearrangement version table includes a thirteenth bit rearrangement version number, and an output bit sequence corresponding to the thirteenth bit rearrangement version number is i1i2i3i4i5q1q2q3q4q5.

[0167] In a possible implementation manner, the bit rearrangement version table further includes a fourteenth bit rearrangement version number, and an output bit sequence corresponding to the fourteenth bit rearrangement version number is i5i4i3i2i1q5q4q3q2q1.

[0168] In a possible implementation manner In, The bit rearrangement version table further includes a fifteenth bit rearrangement version number, and an output bit sequence corresponding to the fifteenth bit rearrangement version number is i5i4i3i2i1q5q4q3q2q1.

[0169] In a possible implementation manner, the bit rearrangement version table further includes a sixteenth bit rearrangement version number, and an output bit sequence corresponding to the sixteenth bit rearrangement version number is i5i4i3i2i1q5q4q3q2q1.

[0170] In a possible implementation manner, an input bit sequence under 4096QAM is i1i2i3i4i5i6q1q2q3q4q5q6, i1, i2, i3, i4, i5, i6, q1, q2, q3, q4, q5, and q6 respectively represent a bit value, i1, i2, i3, i4, i5, i6 are mapped to a real part of a constellation symbol, and q1, q2, q3, q4, q5, q6 are mapped to an imaginary part of the constellation symbol; the bit rearrangement version table includes a seventeenth bit rearrangement version number, and an output bit sequence corresponding to the seventeenth bit rearrangement version number is i1i2i3i4i5i6q1q2q3q4q5q6.

[0171] In a possible implementation, the bit rearrangement version table further comprises an eighteenth bit rearrangement version number, and the output bit sequence corresponding to the eighteenth bit rearrangement version number is i6i5i4i3i2i1q6q5q4q3q2q1.

[0172] In a possible implementation ， The bit rearrangement version table further comprises a nineteenth bit rearrangement version number, and the output bit sequence corresponding to the nineteenth bit rearrangement version number is

[0173] In a possible implementation, the communication apparatus further comprises a Bluetooth module for implementing Bluetooth signal transmission and / or a WiFi module for implementing wireless fidelity (WiFi) signal transmission, and one or more of the sparklink module, the Bluetooth module, or the WiFi module share at least one of the following: a radio frequency (RF) unit, a modem unit, a MAC unit, a central processing unit (CPU).

[0174] In a possible implementation, the sparklink module and the WiFi module for implementing WiFi signal transmission are located in different subsystems of the communication apparatus, and the subsystem of the sparklink module and the subsystem of the WiFi module are integrated in the communication apparatus with at least one of the following: a Bluetooth system, a sparklink low energy (SLE) system, a global navigation satellite system (GNSS), an always-on system, a power management unit (PMU), a clock management unit (CMU), a flash memory, an application system, an audio system.

[0175] In a possible implementation, the sparklink module and the WiFi module for implementing WiFi signal transmission are located in the same subsystem of the communication apparatus, and the subsystem of the sparklink module and the subsystem of the WiFi module are integrated in the communication apparatus with at least one of the following: a Bluetooth system, a sparklink low energy (SLE) system, a global navigation satellite system (GNSS), an always-on system, a power management unit (PMU), a clock management unit (CMU), a flash memory, an application system, an audio system.

[0176] In a possible implementation, the communication apparatus further comprises a Bluetooth module for implementing Bluetooth signal transmission and / or a WiFi module for implementing WiFi signal transmission, at least one of the Bluetooth module or the WiFi module coexists with the StarFlash module through different antennas, and the coexistence strategy comprises at least one of frequency division multiplexing, code division multiplexing, time division multiplexing, channel avoidance, or aggregated scheduling.

[0177] In a possible implementation, the communication apparatus further comprises a Bluetooth module for implementing Bluetooth signal transmission and / or a WiFi module for implementing WiFi signal transmission, at least one of the Bluetooth module or the WiFi module coexists with the StarFlash module through different antennas, and the coexistence strategy comprises at least one of frequency division multiplexing, code division multiplexing, time division multiplexing, software static strategy, or package traffic arbitration (PTA) strategy.

[0178] In a seventeenth aspect, the present application provides a communication apparatus, comprising: one or more processors; a memory for storing one or more computer programs or instructions; when the one or more computer programs or instructions are executed by the one or more processors, the one or more processors implement the method in any one of the first aspect to the sixteenth aspect.

[0179] In an eighteenth aspect, the present application provides a communication apparatus, comprising: a processor for executing the method in any one of the first aspect to the sixteenth aspect.

[0180] In a nineteenth aspect, the present application provides a communication system, comprising: a management node and a terminal node; the management node is configured to execute the method in any one of the first aspect to the eighth aspect, and the terminal node is configured to execute the method in any one of the ninth aspect to the sixteenth aspect.

[0181] In a twentieth aspect, the present application provides a chip, comprising: a processing circuit and an interface circuit; wherein the interface circuit is configured to couple with a memory outside the chip and provide a communication interface for the processing circuit to access the memory; and the processing circuit is configured to execute program instructions in the memory to implement the method in any one of the first aspect to the sixteenth aspect.

[0182] In a specific implementation process, the interface circuit includes an input circuit and an output circuit, the input circuit can be an input pin, the output circuit can be an output pin, and the processing circuit can be a transistor, a gate circuit, a flip-flop, and various logic circuits, etc. The input signal received by the input circuit can be received and input by, for example but not limited to, a receiver, the output signal output by the output circuit can be output to and transmitted by, for example but not limited to, a transmitter, and the input circuit and the output circuit can be the same circuit which is used as the input circuit and the output circuit at different times. The specific implementation mode of the processor and various circuits is not limited in the embodiments of the present application.

[0183] In a twenty-first aspect, the present application provides a computer readable storage medium, wherein the computer readable storage medium stores program codes, and the program codes are executed by a processor to implement the method in any one of the first aspect to the sixteenth aspect.

[0184] In a twenty-second aspect, the present application provides a computer program product, wherein the computer program product contains instructions, and when the computer program product is run on a computer, the computer is caused to implement the method in any one of the first aspect to the sixteenth aspect. BRIEF DESCRIPTION OF DRAWINGS

[0185] Figure 1 A schematic diagram of a communication system provided by the embodiments of the present application;

[0186] Figure 2 A flowchart of a communication method provided by the embodiments of the present application;

[0187] Figure 3 A flowchart of another communication method provided by the embodiments of the present application;

[0188] Figure 4 A 16QAM constellation diagram of a WIFI system provided by the embodiments of the present application;

[0189] Figure 5 A flowchart of still another communication method provided by the embodiments of the present application;

[0190] Figure 6 A flowchart of still another communication method provided by the embodiments of the present application;

[0191] Figure 7 A flowchart of yet another communication method provided by the embodiments of the present application;

[0192] Figure 8 A flowchart of yet another communication method provided by the embodiments of the present application;

[0193] Figure 9A flowchart of another communication method provided by an embodiment of the present application;

[0194] Figure 10 A 64QAM constellation provided by an embodiment of the present application;

[0195] Figure 11 A 256QAM constellation provided by an embodiment of the present application;

[0196] Figure 12 A 1024QAM constellation provided by an embodiment of the present application;

[0197] Figure 13 A 4096QAM constellation provided by an embodiment of the present application;

[0198] Figure 14 A flowchart of another communication method provided by an embodiment of the present application;

[0199] Figure 15 A flowchart of another communication method provided by an embodiment of the present application;

[0200] Figure 16 A flowchart of another communication method provided by an embodiment of the present application;

[0201] Figure 17 A performance benefit diagram provided by an embodiment of the present application;

[0202] Figure 18 A structural diagram of an electronic device provided by an embodiment of the present application;

[0203] Figure 19 A block diagram of a communication device provided by an embodiment of the present application;

[0204] Figure 20 A chip architecture diagram provided by an embodiment of the present application;

[0205] Figure 21 Another chip architecture diagram provided by an embodiment of the present application;

[0206] Figure 22 Another chip architecture diagram provided by an embodiment of the present application;

[0207] Figure 23 Another chip architecture diagram provided by an embodiment of the present application;

[0208] Figure 24 A chip module framework diagram provided by an embodiment of the present application;

[0209] Figure 25 Another chip module framework diagram provided by an embodiment of the present application;

[0210] Figure 26 A software static policy framework schematic diagram provided for an embodiment of the present application;

[0211] Figure 27 A software static policy framework schematic diagram provided for an embodiment of the present application;

[0212] Figure 28 A message transmission arbitration policy framework schematic diagram provided for an embodiment of the present application. DETAILED DESCRIPTION

[0213] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0214] The terms "first", "second", etc. in the description of the embodiments of the present application and the claims and drawings are only used for distinguishing the purposes of description, and cannot be understood as indicating or implying relative importance, nor can be understood as indicating or implying sequence. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, inclusion of a series of steps or units. The method, system, product or device does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0215] It should be understood that in the present application, "at least one" refers to one or more, and "multiple" refers to two or more. "And / or" is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, "A and / or B" can represent three cases of only A, only B and A and B existing at the same time, where A and B can be singular or plural. The character " / " generally represents that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0216] The technical solutions provided by the embodiments of the present application can be applied to, but are not limited to, a wireless short-range communication system and a wireless communication system supporting longer distance transmission (such as 1-18 km, more than 18 km) (such as a next-generation star flash wireless communication system). The wireless short-range communication system can include a wireless short-range communication technology (also referred to as star flash 1.0 technology) with advantages of ultra-low latency, ultra-high reliability, precise synchronization, and the like, and is suitable for applications in scenarios such as intelligent vehicles, smart homes, intelligent terminals, and intelligent manufacturing. For example, applications in the intelligent vehicle scenario include immersive in-vehicle sound field & noise reduction, wireless interactive projection, and 360-degree panoramic view, which can achieve immersive interactive experience and improve vehicle safety.

[0217] The wireless communication system supporting longer distance transmission (such as 1-18 km) mainly includes a next-generation star flash wireless communication system, such as a star flash 2.0 wireless communication system, a star flash 3.0 wireless communication system, and the like, which is not only suitable for communication scenarios with low latency requirements, such as the above-mentioned vehicle communication, industrial control, and the like, but also suitable for communication scenarios with no high latency requirements.

[0218] In some possible implementations, the above-mentioned communication system or can be used in combination with a mobile communication system, which includes but is not limited to a 3rd generation partnership project (3GPP) related cellular system, such as a fourth generation (4G) communication system (for example, a long term evolution (LTE) system), a fifth generation (5G) communication system (for example, a new radio (NR) system), and a future-oriented evolution system (for example, a sixth generation (6G) mobile communication system). The communication system can also be an open radio access network (OORAN), a cloud radio access network (CRAN), or a WiFi system. The communication system can also be a communication system in which two or more of the above systems are integrated.

[0219] The wireless short-range communication system provided by the embodiments of the present application can include a management node (grant node, G node) and a terminal node (terminal node, T node). Figure 1 A possible, non-limiting schematic diagram of a wireless short-range communication system is shown. As shown in Figure 1 The communication system 100 includes at least one management node 110 and at least one terminal node 120.

[0220] G node can be a node with resource scheduling function in a wireless short-range communication system, and can send resource management information and / or data scheduling information and other control information. T node can be a node that receives resource management information and / or data scheduling information and other control information sent by G node in a wireless short-range communication system, and transmits or receives data according to the resource management information and / or data scheduling information and other control information. In order to facilitate description, the short-range protocol in the wireless short-range communication system is referred to as Starlink protocol in the disclosure.

[0221] In the Starlink protocol corresponding to the Starlink technology, there is uplink transmission and downlink transmission between the G node and the T node. The uplink transmission is realized through a T link, which is a link between the T node and the G node, and can also be referred to as an uplink. The downlink transmission is realized through a G link, which is a link between the G node and the T node, and can also be referred to as a downlink.

[0222] In the embodiments of the present application, the communication device has the capability of wireless communication, and can be configured with multiple antennas, which can include at least one transmitting antenna for transmitting signals and at least one receiving antenna for receiving signals. In addition, each communication device additionally includes a transmitter chain and a receiver chain, and those skilled in the art can understand that they can include a plurality of components (such as processors, modulators, multiplexers, demodulators, demultiplexers or antennas, etc.) related to signal transmission and reception. The communication device can be a network device or a terminal device, which is not limited.

[0223] The management node (G node) 110 is located at the network side of the above-mentioned communication system, and is used to help the terminal node to realize wireless access, and is a device with wireless transceiving function or a chip or chip system that can be arranged in the device. The management node 110 includes but is not limited to: a network device, a radio access network (RAN) node, an access network device, a RAN entity or an access node, etc. The plurality of management nodes 110 in the communication system can be nodes of the same type, or nodes of different types.

[0224] In a possible scenario, the management node 110 can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next generation NodeB (gNB), a next generation base station in a 6th generation (6G) mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc. The management node 110 can be a macro base station, a micro base station or an indoor station, a relay node or a donor node, or a wireless controller in a CRAN scenario. The management node 110 can be a macro base station, a micro base station or an indoor station, a relay node or a donor node, an open radio access network (ORAN), or a wireless controller in a centralized radio access network (CRAN) scenario. The management node 110 can also be one or a group of (including multiple antenna panels) antenna panels of a base station in a 5th generation (5G), or can also be a network node constituting a gNB, a TRP or a TP or a transmission measurement function (TMF), such as a central unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU), a road side unit (RSU) with base station functions. The CU and the DU can be separately arranged or can be included in the same network element, for example, a baseband unit (BBU). The RU can be included in a radio frequency device or a radio frequency unit, for example, included in a remote radio unit (RRU), an active antenna unit (AAU) or a remote radio head (RRH).

[0225] In different systems, the CU (or CU-control plane and CU-UP), DU or RU can also have different names, but those skilled in the art can understand their meanings. For example, in the ORAN system, the CU can also be referred to as O-CU (open CU), the DU can also be referred to as O-DU, the CU-control plane can also be referred to as O-CU-control plane, the CU-UP can also be referred to as O-CU-UP, and the RU can also be referred to as O-RU. For the convenience of description, the CU, CU-control plane, CU-UP, DU and RU are taken as examples for description in the embodiments of the present application. Any one of the CU (or CU-control plane, CU-UP), DU and RU in the embodiments of the present application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0226] Optionally, the management node 110 can also be a server, a wearable device, a vehicle or a vehicle-mounted device, etc. For example, the management node in the vehicle to everything (V2X) technology can be an RSU. Optionally, the management node can also be a control unit in unmanned driving, a central controller of a smart factory / smart home, a handheld or automatic control remote sensing device of a flight device, etc. Optionally, the management node can also be a control device such as a central control or a control panel, such as a controller of a drone, a control unit in industrial control. All or part of the functions of the management node in the present application can also be implemented by a software function running on hardware, or by a virtualized function instantiated on a platform (such as a cloud platform). The management node in the present application can also be a logical node, a logical module or software capable of implementing all or part of the functions of the management node.

[0227] The form of the management node in the embodiments of the present application is not limited, and the device for implementing the function of the management node can be the management node; or can be a device capable of supporting the management node to implement the function, such as a chip system. The device can be installed in the management node or used in matching with the management node.

[0228] The terminal node 120 (T node) is a device, apparatus, module, chip or chip system with transceiver function, which can also be referred to as a terminal device, user equipment (UE), access terminal, subscriber unit, user station, mobile station (MS), mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent or user equipment, etc. The terminal node can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), internet of things (IOT), virtual reality, augmented reality, industrial control, automatic driving, remote medical treatment, smart power grid, smart home, smart office, smart wear, smart transportation, smart city, etc.

[0229] The terminal node in the embodiments of the present application can be a mobile phone, a cellular phone, a smart phone, a Pad, a mouse, a remote controller, a stylus, a set-top box, a router, a camera, a screen, a smart screen, a wireless data card, a personal digital assistant computer (PDA), a wireless modem, a handset, a laptop computer, a smart watch, a smart bracelet, a wireless earphone, an electronic conference whiteboard, a machine type communication (MTC) terminal, a computer with wireless transceiver function, a virtual reality (VR) terminal, an augmented reality (AR) terminal, a smart home device (for example, a refrigerator, a television, an air conditioner, a washing machine, an electric rice cooker, a table lamp, an electric meter, etc.), a smart robot, a mechanical arm, a workshop device, a wireless terminal in self-driving, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, a vehicle-mounted terminal, a vehicle-mounted screen, a vehicle-mounted audio, a vehicle key, a roadside unit (RSU) with terminal function, etc., a flight device (for example, a smart robot, a hot air balloon, a drone, an airplane), etc. The terminal node of the present application can also be a vehicle-mounted module, a vehicle-mounted module, a vehicle-mounted component, a vehicle-mounted chip or a vehicle-mounted unit built into a vehicle as one or more components or units. The terminal node can also be other devices with terminal functions, for example, the terminal node can also be a device in device-to-device (D2D) communication that performs terminal functions.

[0230] The embodiments of the present application do not limit the device form of the terminal, and the device for realizing the function of the terminal node can be a terminal node; it can also be a device capable of supporting the terminal node to realize the function, such as a chip system. The device can be installed in the terminal node or used with the terminal node. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0231] It should be noted that the scheme in the embodiments of the present application can also be applied to other communication systems, and the corresponding names can also be replaced by the names of the corresponding functions in other communication systems.

[0232] It can be understood that, Figure 1 The structure of the illustrated communication system does not constitute a specific limitation on the communication system. In other embodiments of the present application, the communication system can include more or fewer components than illustrated, or combine certain components, or split certain components, or different component arrangements. The illustrated components can be implemented in hardware, software, or a combination of software and hardware.

[0233] The following first explains some key terms related to the embodiments of the present application:

[0234] G link (G Link): a communication link from a management node to a terminal node. This link can carry data channels, control channels, broadcast channels, synchronization signals, etc. from the management node to the terminal node.

[0235] T link (T Link): a communication link from a terminal node to a management node. This link can carry data channels, access channels, feedback signals, etc. from the terminal node to the management node.

[0236] Communication domain (communication domain): a resource of a G link and a T link composed of one G node and multiple T nodes scheduled by the G node.

[0237] Data transmission block (transport block, TB): a MAC protocol data unit (protocal data unit, PDU) received by the physical layer from the media access control (media access control, MAC) layer, one MAC PDU corresponds to one data transmission block, and the sending end can send one or two TBs to the receiving end within one transmission time interval (transmission time interval, TTI).

[0238] Embodiment one:

[0239] Please refer to Figure 2 , Figure 2 A flowchart of a communication method provided by the embodiments of the present application is shown. The method can include the following processes:

[0240] 201, generate scheduling type indication information, the scheduling type indication information indicates that the retransmission based on the first retransmission data unit or the initial transmission retransmission hybrid transmission adopts the first encoding mode to determine the first redundancy version and the first bit rearrangement version of the channel bit sequence, and the first retransmission data unit is a transport block or a code block group.

[0241] The first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number of the first QAM in the bit rearrangement version table. The first QAM is 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

[0242] For example, the management node can generate scheduling type indication information.

[0243] The scheduling type indication information can be located in dynamic scheduling data control information of G link control information (GCI). The G node sends G link control information for dynamic scheduling data control, semi-persistent scheduling data information transmission resource activation and deactivation information, sleep and wake-up indication, fast carrier switching indication, non-periodic channel sounding signal scheduling, etc. When the system occupies multiple 20MHz carriers (communication domains), the G node independently sends GCI information on each carrier (communication domain).

[0244] When the T node receives the GCI information, it uses the STS synchronization sequence and the G link control information phase adjustment signal (GCIPAS) sent by the G node to perform channel information estimation and channel information phase change compensation, respectively, and then demodulates (blind detection) the GCI information.

[0245] The GCI supports multiple formats (Format) and data bit (bit) lengths: 74 bits or 80 bits. The functions of each Format are shown in the following Table 1:

[0246] Table 1 Control resource overhead indication information bit definition

[0247]

[0248]

[0249] Format 0: Dynamic scheduling data control information

[0250] The G node configures the maximum number of CBGs contained in one TB as N through high-layer signaling. In one transmission, the number of CBGs actually contained in one TB is M = min(C, N), where C is the number of CBs contained in the TB. M1 = mod(C, M), K1 = ceil(C / M), and K2 = floor(C / M) if M1 > 0. In the M CBGs, the CBGs from #0 to #(M1-1) contain K1 CBs, the CBGs from #M1 to #(M1-1) contain K2 CBs, and each CBG contains (C / M) CBs if M1 = 0.

[0251] The dynamic scheduling data control information supports three Format subformats:

[0252] Format 0A: The node capability supports single code word, schedules single code word, and the information bit length is 74

[0253] Format 0B-1: The node capability supports double code word, schedules single code word, and the information bit length is 80

[0254] Format 0B-2: The node capability supports double code word, schedules double code word, and the information bit length is 80

[0255] When the T node reports the feedback of the node capability, the T node reports the number of supported sending code words and the number of received code words. The G node configures the GCI format for the T node through the gciBitLen (GCI bit length) information element in the physical layer dedicated configuration information physicalConfigDedicated, and indicates the T node to use 74-bit information or 80-bit information to blindly detect the GCI.

[0256] The length of the Format 0A dynamic scheduling data control information is 74 bits, and from the lowest bit to the highest bit, it contains the information shown in Table 2 as follows:

[0257] Table 2 Format 0A (dynamic scheduling data control information) bit definition

[0258]

[0259]

[0260]

[0261] The specific meaning indicated by the scheduling type indication information carried in the Format 0A dynamic scheduling data control information is shown in Table 2 as follows.

[0262] The length of the Format0B-1 dynamic scheduling data control information is 80 bits, and from the lowest bit to the highest bit, it specifically contains the information shown in Table 3 as follows:

[0263] Table 3 Format0B-1 (dynamic scheduling data control information) bit definition

[0264]

[0265]

[0266]

[0267] The specific meaning indicated by the scheduling type indication information carried in the Format0B-1 dynamic scheduling data control information is shown in Table 3 as follows.

[0268] As shown in the foregoing Table 2 and Table 3, in the case of the scheduling type indication information being 0, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 0. In the case of the scheduling type indication information being 1, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 1. In the case of the scheduling type indication information being 2, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 2. In the case of the scheduling type indication information being 3, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 3. In the case of the scheduling type indication information being 7, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 0. In the case of the scheduling type indication information being 8, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 1. In the case of the scheduling type indication information being 9, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 2. In the case of the scheduling type indication information being 10, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 3. In the case of the scheduling type indication information being 14, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 0. In the case of the scheduling type indication information being 15, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 1.

[0269] The length of the Format0B-2 dynamic scheduling data control information is 80 bits, and from the lowest bit to the highest bit, it specifically contains the information shown in Table 4 as follows:

[0270] Table 4 Format0B-2 (dynamic scheduling data control information) bit definition

[0271]

[0272]

[0273]

[0274] The specific meaning indicated by the scheduling type indication information carried in the Format0B-2 dynamic scheduling data control information is shown in Table 4. As shown in Table 4, when the scheduling type indication information is 0, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 0. When the scheduling type indication information is 1, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 1. When the scheduling type indication information is 2, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 2. When the scheduling type indication information is 3, the first bit rearrangement version indicates the output bit sequence corresponding to the bit rearrangement version 3.

[0275] The embodiments of the present application bind the bit rearrangement version and the redundancy version, and the redundancy version and the bit rearrangement version can be indicated simultaneously by the scheduling type indication information. The bit rearrangement version does not need to occupy other bit positions, thereby effectively saving the scheduling resources.

[0276] 202. Transmit the scheduling type indication information.

[0277] For example, the management node can transmit the scheduling type indication information to the terminal node.

[0278] Embodiment two:

[0279] For example, the management node can transmit the scheduling type indication information to the terminal node. Figure 3 Figure 3 Another flowchart of a communication method provided by the embodiments of the present application is shown in FIG. 4. The method is based on the modulation modes and constellation mapping modes supported by the communication system, and provides various bit rearrangement versions under various modulation modes to provide the performance of HARQ. The method can include the following processes:

[0280] 301. Obtain a bit rearrangement version table, which includes the output bit sequences corresponding to the bit rearrangement version numbers under different QAMs, wherein the different QAMs include 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM.

[0281] The output bit sequence corresponding to the bit rearrangement version number under any QAM can be the same as the input bit sequence under the QAM or obtained by rearranging the input bit sequence, wherein the rearranging operation includes reordering and / or inverting part of the bit positions.

[0282] ​For example, under 16QAM (i.e. when using 16QAM modulation), one symbol d(i) is mapped from 4 bits, the input bit sequence is b(4i), b(4i+1), b(4i+2), b(4i+3), b() represents a bit value, and i represents the serial number of the constellation symbol (also referred to as a modulation symbol) corresponding to the input bit sequence in the constellation diagram. For example, b(4i) and b(4i+2) can be mapped to the real part of the modulation symbol, and b(4i+1) and b(4i+3) can be mapped to the imaginary part of the modulation symbol. The bit rearrangement version table includes the following Table 5:

[0283] Table 5. Bit rearrangement version under 16QAM

[0284]

[0285] wherein, represents the logical value of bit b() being negated. The bit rearrangement version number corresponds to the rearrangement version (RV) number one-to-one. That is, at the nth time of retransmission, the bit rearrangement version n is used for bit rearrangement, 0≤n≤3, and the 0th time of retransmission refers to the first transmission.

[0286] BV0: The input bit sequence is b(4i), b(4i+1), b(4i+2), b(4i+3), and the output bit sequence is b(4i), b(4i+1), b(4i+2), b(4i+3), i.e. output = input.

[0287] BV1: The input bit sequence is b(4i), b(4i+1), b(4i+2), b(4i+3), and the output bit sequence is b(4i+2), b(4i+3), i.e. the high and low bit pairs (input sequence from left to right, two bits as a pair) are exchanged, and the lowest bit pair is negated.

[0288] By analogy, the specific operations of BV2 and BV3 can be obtained.

[0289] The first bit rearrangement version in the foregoing embodiment is one bit rearrangement version in the bit rearrangement version table. For example, it is bit rearrangement version 0, bit rearrangement version 1, bit rearrangement version 2, or bit rearrangement version 3 in the foregoing Table 1.

[0290] For example, under 64QAM (i.e. when 64QAM modulation is used), one symbol d(i) is mapped from 6 bits, and the input bit sequence is b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5), where b() represents a bit value, and i represents the serial number of the constellation symbol corresponding to the input bit sequence in the constellation diagram. For example, b(6i), b(6i+2), b(6i+4) can be mapped to the real part of the modulation symbol, and b(6i+1), b(6i+3), b(6i+5) can be mapped to the imaginary part of the modulation symbol. The bit rearrangement version table includes Table 6 as follows:

[0291] Table 6. Bit rearrangement version table for 64QAM

[0292]

[0293] The related description of Table 6 can refer to Table 5 described above, and the embodiments of the present application will not be repeated here.

[0294] For example, under 256QAM (i.e. when 256QAM modulation is used), one symbol d(i) is mapped from 8 bits, and the input bit sequence is b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7), where b() represents a bit value, and i represents the serial number of the constellation symbol corresponding to the input bit sequence in the constellation diagram. For example, b(8i), b(8i+2), b(8i+4), b(8i+6) can be mapped to the real part of the modulation symbol, and b(8i+1), b(8i+3), b(8i+5), b(8i+7) can be mapped to the imaginary part of the modulation symbol. The bit rearrangement version table includes Table 7 as follows:

[0295] Table 7. Bit rearrangement version table for 256QAM

[0296]

[0297]

[0298] The related description of Table 7 can refer to Table 5 described above, and the embodiments of the present application will not be repeated here.

[0299] For example, under 1024QAM (i.e., when 1024QAM modulation is used), one symbol d(i) is mapped by 10 bits, and the input bit sequence is b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9), where b() represents a bit value, and i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram. For example, b(10i), b(10i+2), b(10i+4), b(10i+6), b(10i+8) can be mapped to the real part of the modulation symbol, and b(10i+1), b(10i+3), b(10i+5), b(10i+7), b(10i+9) can be mapped to the imaginary part of the modulation symbol. The bit rearrangement version table includes Table 8 as follows:

[0300] Table 8. Bit rearrangement version of 1024QAM

[0301]

[0302] The related description of Table 8 can refer to Table 5 described above, and details are not described herein.

[0303] For example, under 4096QAM (i.e., when 4096QAM modulation is used), one symbol d(i) is mapped by 12 bits, and the input bit sequence is b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), b(12i+11), where b() represents a bit value, and i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram. For example, b(12i), b(12i+2), b(12i+4), b(12i+6), b(12i+8), b(12i+10) can be mapped to the real part of the modulation symbol, and b(12i+1), b(12i+3), b(12i+5), b(12i+7), b(12i+9), b(12i+11) can be mapped to the imaginary part of the modulation symbol. The bit rearrangement version table includes Table 9 as follows:

[0304] Table 9. Bit rearrangement version of 4096QAM

[0305]

[0306] It should be noted that the foregoing Tables 5 to 9 are only exemplary descriptions, and b() represents a bit value, which can also be represented in other ways. For example, i ()represents a bit value of a real part of a corresponding constellation symbol, q () represents a bit value of an imaginary part of a corresponding constellation symbol, which is not limited in the embodiments of the present application. In a possible implementation, Tables 5 to 9 can be combined into one table, and the bit rearrangement version numbers are arranged in descending order from 0. In a possible implementation, Table 5 to 9 can further include a column of "input bit sequence".

[0307] 302. determining an output bit sequence according to the bit rearrangement version table.

[0308] In a possible implementation, the output bit sequence is determined according to the input bit sequence, the bit rearrangement version number (i.e., the bit rearrangement version number indicated by the first bit rearrangement version in the first embodiment) and the bit rearrangement version table. For example, the input bit sequence is bit-rearranged according to the bit rearrangement version number and the bit rearrangement version table, to obtain the output bit sequence.

[0309] For example, referring to Table 5, it is assumed that the input bit sequence is 1001 under 16QAM, i.e., b(4i) is 1, b(4i+1) is 0, b(4i+2) is 0 and b(4i+3) is 1. If the bit rearrangement version number is 0, the output bit sequence is determined to be 1001. If the bit rearrangement version number is 1, the output bit sequence is determined to be 0101. If the bit rearrangement version number is 2, the output bit sequence is determined to be 1010. If the bit rearrangement version number is 3, the output bit sequence is determined to be 0110.

[0310] The embodiments of the present application can improve the HARQ gain by using different bit rearrangement versions at each transmission according to the bit rearrangement version table, and the higher the modulation mode is, the greater the gain is.

[0311] After the output bit sequence is determined according to the bit rearrangement version table, the output bit sequence is mapped to a constellation symbol when modulated by the first QAM. The constellation symbol is a symbol in a constellation diagram obtained by modulating and mapping the output bit sequence in the first bit rearrangement version.

[0312] The embodiments of the present application can be applied to a Gray mapping communication system, and the following is a possible implementation of a constellation diagram:

[0313] When 16QAM modulation is used, the output bit sequence obtained after bit reordering of the input bit sequence b(4i), b(4i+1), b(4i+2), b(4i+3) is represented as c(4i), c(4i+1), c(4i+2), c(4i+3), where c() represents a bit value. c(4i), c(4i+1), c(4i+2), c(4i+3) correspond to the 1st bit, the 2nd bit, the 3rd bit and the 4th bit of the output bit sequence respectively. For example, assuming that the first bit reordering version is bit reordering version 1, the output bit sequence indicated by bit reordering version 1 is determined by Table 1 as b(4i+2), b(4i+3), b(4i+1), b(4i+4). Then c(4i) is b(4i+2), c(4i+1) is b(4i+3), c(4i+2) is c(4i+3) is The output bit sequence (i.e. 4 bits) is mapped to a symbol d(i) (which can be regarded as a coordinate on a constellation diagram), and d(i) is represented as:

[0314]

[0315] For example, the output bit sequence obtained after bit reordering of the input bit sequence b(4i), b(4i+1), b(4i+2), b(4i+3) can also continue to be represented as b(4i), b(4i+1), b(4i+2), b(4i+3). The output bit sequence and the input bit sequence are represented in the same way, but are not the same. b(4i), b(4i+1), b(4i+2), b(4i+3) of the output bit sequence correspond to the 1st bit, the 2nd bit, the 3rd bit and the 4th bit after bit reordering of b(4i), b(4i+1), b(4i+2), b(4i+3) of the input bit sequence respectively. The output bit sequence obtained after bit reordering of the input bit sequence b(4i), b(4i+1), b(4i+2), b(4i+3) can also be represented in other ways, for example, represented as d(4i), d(4i+1), d(4i+2), d(4i+3), and the embodiments of the present application do not limit this.

[0316] When 64QAM modulation is used, the output bit sequence obtained after bit rearrangement of the input bit sequence b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5) is represented as c(6i), c(6i+1), c(6i+2), c(6i+3), c(6i+4), c(6i+5), where c() represents a bit value. The relevant description of the output bit sequence obtained after bit rearrangement can refer to the relevant explanation in the foregoing 16QAM. The output bit sequence (i.e., 6 bits) is mapped to a symbol d(i), and d(i) is represented as:

[0317]

[0318] For example, the output bit sequence obtained after bit rearrangement of the input bit sequence b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5) can also continue to be represented as b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5). The output bit sequence and the input bit sequence are not the same although they are represented in the same way. The b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5) of the output bit sequence correspond to the first bit, the second bit, the third bit, the fourth bit, the fifth bit, and the sixth bit of the input bit sequence b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5) after bit rearrangement, respectively. The output bit sequence obtained after bit rearrangement of the input bit sequence b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5) can also be represented in other ways, for example, represented as d(6i), d(6i+1), d(6i+2), d(6i+3), d(6i+4), d(6i+5), which is not limited in the embodiments of the present application.

[0319] When using 256QAM modulation, the output bit sequence obtained after bit rearrangement of the input bit sequence b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7) is represented as c(8i), c(8i+1), c(8i+2), c(8i+3), c(8i+4), c(8i+5), c(8i+6), b(8i+7), where c() represents a bit value. The relevant description of the output bit sequence obtained after bit rearrangement can refer to the relevant explanation in the foregoing 16QAM. The output bit sequence (i.e., 8 bits) is mapped to a symbol d(i), which is represented as:

[0320]

[0321] For example, the output bit sequence obtained after bit rearrangement of the input bit sequence b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7) can also continue to be represented as b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7). The output bit sequence and the input bit sequence have the same representation, but are not the same. The b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7) of the output bit sequence correspond to the first bit, the second bit, the third bit, the fourth bit, the fifth bit, the sixth bit, the seventh bit, and the eighth bit, respectively, of the input bit sequence b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7) after bit rearrangement. The output bit sequence obtained after bit rearrangement of the input bit sequence b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7) can also be represented in other ways, for example, represented as d(8i), d(8i+1), d(8i+2), d(8i+3), d(8i+4), d(8i+5), d(8i+6), d(8i+7), which is not limited in the embodiments of the present application.

[0322] When using 1024QAM modulation, the output bit sequence obtained after bit reordering of the input bit sequence b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9) is represented as c(10i), c(10i+1), c(10i+2), c(10i+3), c(10i+4), c(10i+5), c(10i+6), c(10i+7), c(10i+8), c(10i+9), c() representing a bit value. The relevant explanation of the output bit sequence obtained after bit reordering can refer to the relevant explanation in the foregoing 16QAM. The output bit sequence (i.e. 10 bits) is mapped to a symbol d(i), d(i) is represented as:

[0323]

[0324] For example, the output bit sequence obtained after the input bit sequence b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9) is subjected to bit rearrangement can also continue to be represented as b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9). The output bit sequence and the input bit sequence are not the same although the representation is the same. The b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9) of the output bit sequence correspond to the 1st bit, the 2nd bit, the 3rd bit, the 4th bit, the 5th bit, the 6th bit, the 7th bit, the 8th bit, the 9th bit, and the 10th bit, respectively, of the input bit sequence b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9) after bit rearrangement. The output bit sequence obtained after the input bit sequence b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9) is subjected to bit rearrangement can also be represented in other ways, for example, represented as d(10i), d(10i+1), d(10i+2), d(10i+3), d(10i+4), d(10i+5), d(10i+6), d(10i+7), d(10i+8), d(10i+9), and the embodiments of the present application do not limit this.

[0325] When using 4096QAM modulation, the output bit sequence after bit reordering of the input bit sequence b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), b(12i+11) is represented as c(12i), c(12i+1), c(12i+2), c(12i+3), c(12i+4), c(12i+5), c(12i+6), c(12i+7), c(12i+8), c(12i+9), c(12i+10), c(12i+11), c() represents a bit value. The related explanation of the output bit sequence after bit reordering can refer to the related explanation in the foregoing 16QAM. The output bit sequence (i.e. 12 bits) is mapped to a symbol d(i), d(i) is represented as:

[0326]

[0327] For example, the input bit sequence b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), b(12i+11), after bit rearrangement, can also be represented as b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), b(12i+11). Although the output bit sequence is represented in the same way as the input bit sequence, it is not the same. The output bit sequences b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), and b(12i+11) correspond to the input bit sequences b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), and b(12i+11), respectively. 4) The 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 9th, 10th, 11th, and 12th bits of the bit sequence b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), and b(12i+11) after bit rearrangement. Input bit sequence b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+11)

[0328] 7) The output bit sequence obtained after bit rearrangement of b(12i+8), b(12i+9), b(12i+10), and b(12i+11) can also be represented in other ways, such as d(12i), d(12i+1), d(12i+2), d(12i+3), d(12i+4), d(12i+5), d(12i+6), d(12i+7), d(12i+8), d(12i+9), d(12i+10), and d(12i+11). The embodiments of the application do not limit this.

[0329] The following explains the principle behind determining the bit rearranged versions in Tables 5 to 9 above.

[0330] Assume r = x + jy is the received signal (the signal after channel compensation), bi is the bit after encoding of the sending end, the formula of LLR is:

[0331]

[0332] The above formula indicates that when the received signal is r, according to the received signal, the probability of the sending signal being 1 is greater or the probability of the sending signal being 0 is greater, if That is, indicates that the probability of the sending signal being 1 is greater, and otherwise, the probability of the sending signal being 0 is greater.

[0333] Next, taking twice transmission as an example, the principle of bit rearrangement is introduced. Please refer to Figure 4 , Figure 4 A 16QAM constellation diagram of a WIFI system provided by the embodiment of the application, the horizontal axis I represents the real part, and the vertical axis Q represents the imaginary part, the bit mapping order is i1i2q1q2. Wherein i1, i2, q1, q2 correspond to 1-4 bit positions of the constellation symbol respectively, i1, i2 correspond to the real part of the constellation symbol, and q1, q2 correspond to the imaginary part of the constellation symbol.

[0334] When the channel is an additive white Gaussian noise (AWGN) channel, and the modulation mode is 16QAM as shown in the figure, Figure 4 The LLR value of bits i1 and i2 can be expressed as:

[0335]

[0336]

[0337] Wherein, K is a coefficient related to the signal to noise ratio (SNR), for 16QAM, in order to normalize the transmission channel power, the relationship between x1 and x0 satisfies x1=3x0, according to log(x+y)≈max(logx,logy), therefore, LLR(i1) and LLR(i2) can be approximately expressed as:

[0338]

[0339] Through the above formula, the average LLR of i1 and i2 in Figure 4 When the sending bits are '1 / 0 / q1 / q2', and the values of q1 and q2 are arbitrary, the real part average value of the received signal r is x1=3x0, then the average LLR(i1)=16Kx0 2 , the average LLR(i2)=-4Kx0 2 , let 4Kx0 2= Δ, then average LLR(i1) = 4Δ, average LLR(i2) = - Δ, it can be seen that the average value of LLR(i1) is much greater than the average value of LLR(i2). Similarly, when i1 and i2 send other values, the results of average LLR(i1) and average LLR(i2) are shown in Table 10.

[0340] Table 10. Average LLR values of i1 and i2

[0341] Constellation symbols (i1i2q1q2) Average value of x average of LLR(i1) average of LLR(i2) 1 / 1 / q1 / q2 x0 Delta Delta 1 / 0 / q1 / q2 x1 4 Delta - Delta [0 / 1 / q1 / q2] [-x0] - Delta Delta [0 / 0 / q1 / q2] [-x1] - 4 Delta - Delta

[0342] Here, q1 and q2 are symmetrical to i1 and i2, and the LLR value calculation formula is similar, which will not be described here.

[0343] Assuming that the transmitted symbols are equally distributed, the average value of LLR of i1 is 2.5 times that of i2, which indicates that in the aforementioned 16QAM modulation mode, the reliabilities of different bits are inconsistent. When HARQ retransmission adopts CC, assuming that the bits of initial transmission and retransmission are consistent, the reliabilities of the LLRs are the same, and iterative decoding of the LLRs will cause the reliability gap of different bits to become larger, affecting the retransmission benefit.

[0344] As described above, different mapping relationships can be adopted during retransmission to achieve the purpose of balancing the LLRs of different bits. There are two schemes for changing the mapping relationship, one is that the bit order is unchanged, and the mapping relationship from bits to symbols is changed, for example, 00 of 16QAM is originally mapped to -3, and 00 is mapped to +3 during retransmission. The second is that the mapping relationship is unchanged, and the bit position is changed or the bits are negated, for example, 00→-3, 01→-1, 10→+3, and 11→+1 of 16QAM during initial transmission, and “01” is exchanged to become “10” during retransmission, and “10” is still mapped to +3. The second scheme is adopted in the embodiments of the present application, and the implementation is simpler. It should be noted that after the mapping relationship is changed in the two schemes, it is still Gray mapping.

[0345] Assuming that i1 and i2 are transposed during retransmission, that is, “i1i2” is transmitted during initial transmission, and “i2i1” is transmitted during retransmission. These two different transmission orders are referred to as different bit versions.

[0346] The average values of the LLRs of i1 and i2 when the bits are not transposed after retransmission 1 time and when the bits are transposed are shown in Table 11.

[0347] Table 11. Average LLR values of i1 and i2 when the bits are transposed and not transposed after retransmission 1 time

[0348]

[0349] It can be seen that if the i1 and i2 bits are not swapped, the average values ​​of LLR(i1) and LLR(i2) differ by a maximum of 6Δ. If the i1 and i2 bits are swapped, the average values ​​of LLR(i1) and LLR(i2) differ by a maximum of 3Δ, showing a significant improvement. If the transmission is performed 4 times, and each time a different bit order is used (or a bit is inverted), the values ​​of LLR(i1) and LLR(i2) will be even more average.

[0350] Furthermore, as can be seen from Table 11, the reliability of i1 being 0 and i1 is the same. Therefore, when choosing different bit orders, the i1 bit does not need to be inverted, which can reduce the search range of the subsequent optimal rearrangement scheme.

[0351] Example 3:

[0352] Please refer to Figure 5 , Figure 5 A flowchart illustrating another communication method provided in an embodiment of this application is shown. The method may include the following steps:

[0353] 401. Receive scheduling type indication information. The scheduling type indication information indicates a retransmission or initial retransmission mixed transmission based on the first retransmission data unit. The channel bit sequence of the first redundancy version and the first bit rearrangement version is determined by the first coding mode. The first retransmission data unit is a transport block or a coding block group.

[0354] The first bit rearrangement version indicates the output bit sequence corresponding to a bit rearrangement version number under the first QAM in the bit rearrangement version table. The first QAM is 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

[0355] For example, the terminal node receives scheduling type indication information sent by the management node.

[0356] For details regarding the scheduling type indication information, please refer to the aforementioned process 201. This application embodiment will not repeat the details here.

[0357] 402. Decode and de-sort the channel bit sequence according to the scheduling type indication information.

[0358] De-bit rearrangement refers to obtaining the original input bit sequence based on the output bit sequence obtained from decoding (the output bit sequence obtained in the aforementioned process 302).

[0359] In one possible implementation, the input bit sequence can be determined based on the output bit sequence, the first bit rearrangement version, and a bit rearrangement version table. For example, the output bit sequence is de-bit rearranged according to the first bit rearrangement version to obtain the input bit sequence. The bit rearrangement version table can be referred to Tables 5 to 9 in the aforementioned Embodiment 2, and will not be repeated here.

[0360] For example, referring to Table 5 above, assuming the decoded output bit sequence is 1001, if the first bit rearrangement version is bit rearrangement version 0, then the input bit sequence obtained after de-bit rearrangement is 1001. If the first bit rearrangement version is bit rearrangement version 1, then the input bit sequence obtained after de-bit rearrangement is 1010. If the first bit rearrangement version is bit rearrangement version 2, then the input bit sequence obtained after de-bit rearrangement is 1010. If the first bit rearrangement version is bit rearrangement version 3, then the input bit sequence obtained after de-bit rearrangement is 0110.

[0361] Example 4:

[0362] Please refer to Figure 6 , Figure 6 A flowchart illustrating another communication method provided in an embodiment of this application is shown. The method may include the following steps:

[0363] 501. Obtain the bit rearrangement version table. The bit rearrangement version table includes the output bit sequence corresponding to each bit rearrangement version number under different QAMs. Different QAMs include 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM.

[0364] The bit rearrangement version table can be referred to Tables 5 to 9 in the aforementioned Embodiment 2, and will not be repeated here in the embodiments of this application.

[0365] 502. Determine the input bit sequence based on the bit rearrangement version table.

[0366] In one possible implementation, the input bit sequence is determined based on the output bit sequence, the bit rearrangement version number (i.e., the bit rearrangement version number indicated by the first bit rearrangement version in the aforementioned embodiment three), and the bit rearrangement version table. For example, the output bit sequence is de-bit rearranged based on the bit rearrangement version number and the bit rearrangement version table to obtain the input bit sequence.

[0367] This process can refer to the aforementioned process 402, and will not be repeated here in the embodiments of this application.

[0368] Example 5:

[0369] Please refer to Figure 7 , Figure 7A flowchart of another communication method provided by the embodiments of the present application is shown in FIG. 6, which can be applied to the star flash system. The method can include the following processes:

[0370] 601. The G node acquires a bit reordering version table, which includes output bit sequences corresponding to respective bit reordering version numbers under different QAMs, wherein the different QAMs include 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM.

[0371] The process can refer to the aforementioned process 301, and thus the embodiments of the present application will not be repeated here.

[0372] 602. The G node determines the output bit sequence according to the bit reordering version table.

[0373] The process can refer to the aforementioned process 302, and thus the embodiments of the present application will not be repeated here.

[0374] 603. The T node acquires the bit reordering version table.

[0375] The process can refer to the aforementioned process 501, and thus the embodiments of the present application will not be repeated here.

[0376] 604. The G node generates scheduling type indication information, which indicates that the retransmission based on the first retransmission data unit or the initial transmission retransmission hybrid transmission adopts the first encoding mode to determine the first redundancy version and the channel bit sequence of the first bit reordering version, and the first retransmission data unit is a transport block or a code block group.

[0377] The process can refer to the aforementioned process 201, and thus the embodiments of the present application will not be repeated here.

[0378] 605. The G node sends the scheduling type indication information to the T node.

[0379] The process can refer to the aforementioned process 202, and thus the embodiments of the present application will not be repeated here.

[0380] 606. The T node decodes and de-bit-reorders the channel bit sequence according to the scheduling type indication information and the bit reordering version table to obtain the input bit sequence.

[0381] The process can refer to the aforementioned processes 402 and 502, and thus the embodiments of the present application will not be repeated here.

[0382] The embodiments one to five of the present application can be applied to the star flash system.

[0383] In summary, the communication method, the management node and the terminal node provided by the embodiments of the present application respectively acquire a bit rearrangement version table, the bit rearrangement version table includes output bit sequences corresponding to respective bit rearrangement version numbers under different QAMs, the different QAMs include 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM, the management node determines the output bit sequence according to the bit rearrangement version table, and can subsequently encode and send a channel bit sequence. The terminal node decodes the received channel bit sequence to obtain the output bit sequence, and decodes and rearranges bits according to the bit rearrangement version table to obtain an input bit sequence. By using different bit rearrangement versions at each transmission through the bit rearrangement version table, the benefits of HARQ can be improved, and the higher the modulation mode, the greater the benefits.

[0384] The management node sends scheduling type indication information to the terminal node, the scheduling type indication information indicates hybrid transmission of retransmission based on a first retransmission data unit or initial transmission retransmission, the channel bit sequence is determined by using the first encoding mode to determine the first redundancy version and the first bit rearrangement version, the first retransmission data unit is a transport block or a code block group, the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number under the first QAM in the bit rearrangement version table, and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM. The terminal node decodes and decodes and rearranges bits of the channel bit sequence according to the scheduling type indication information. This method binds the bit rearrangement version with the redundancy version, and the scheduling type indication information can indicate the redundancy version and the bit rearrangement version at the same time, the bit rearrangement version does not need to separately occupy other bit positions, and the scheduling resources are effectively saved.

[0385] Embodiment six

[0386] Please refer to Figure 8 , Figure 8 The flowchart of another communication method provided by the embodiments of the present application can include the following processes:

[0387] 701, generate bit rearrangement version information, the bit rearrangement version information indicates a first bit rearrangement version in a bit rearrangement version table.

[0388] The first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number under the first QAM, and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

[0389] In a possible implementation, the bit rearrangement version information is carried in scheduling type indication information. The scheduling type indication information indicates retransmission based on a first retransmission data unit or initial transmission retransmission mixed transmission, and a channel bit sequence of a first redundancy version and a first bit rearrangement version is determined using a first encoding mode, the first retransmission data unit being a transport block or a code block group. The scheduling type indication information can refer to the foregoing process 201, and details are not described herein again.

[0390] In a possible implementation, the bit rearrangement version information is bound to target information, and the target information is used to indicate a redundancy version number or a superframe number. For example, the redundancy version number is the same as the bit rearrangement version number, and a bit rearrangement version number indicated by the first bit rearrangement version is the redundancy version number. For another example, a bit rearrangement version number indicated by the first bit rearrangement version is mod(superframe number, 4). In this way, the bit rearrangement version information is bound to the target information, and the first bit rearrangement version is indicated by the target information, so that the bit rearrangement version information does not need to occupy additional bits, and resources are effectively saved.

[0391] In a possible implementation, the bit rearrangement version information can be sent separately. For example, the bit rearrangement version information can be carried in dynamic scheduling data control information, control signaling, or a superframe header.

[0392] 702、sending the bit rearrangement version information.

[0393] The process can refer to the foregoing process 202, and details are not described herein again.

[0394] Embodiment seven:

[0395] Please refer to Figure 9 , Figure 9 A flowchart of another communication method provided by an embodiment of the present application is shown in FIG. 8. The method can include the following processes.

[0396] 801、obtaining a bit rearrangement version table, the bit rearrangement version table including output bit sequences corresponding to respective bit rearrangement version numbers in at least one QAM, the at least one QAM including at least one of 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM.

[0397] For example, when the at least one QAM includes 16QAM and 64QAM, the first QAM is 16QAM or 64QAM. When the at least one QAM includes 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM, the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM, or 4096QAM.

[0398] The output bit sequence corresponding to any QAM bit rearrangement version number can be the same as the input bit sequence under the QAM or obtained by rearranging the input bit sequence, and the rearranging operation includes reordering and / or inverting part of the bits.

[0399] For example, under 16QAM (i.e., when using 16QAM modulation), one symbol d(i) is mapped from 4 bits, and the input bit sequence is i1i2q1q2, where i1, i2, q1, and q2 represent a bit value, respectively. For example, i1 and i2 can be mapped to the real part of the modulation symbol, and q1 and q2 can be mapped to the imaginary part of the modulation symbol. The bit rearrangement version table includes a first bit rearrangement version number, and the output bit sequence corresponding to the first bit rearrangement version number is i1i2q1q2. For example, the first bit rearrangement version number can be 0, and the bit rearrangement version table can include Table 12 as follows:

[0400] Table 12

[0401] Bit rearrangement version number Output bit sequence 0 [i1 i2 q1 q2]

[0402] In a possible implementation, the bit rearrangement version table further includes a second bit rearrangement version number, and the output bit sequence corresponding to the second bit rearrangement version number is For example, the second bit rearrangement version number can be 1, and the bit rearrangement version table can include Table 13 as follows:

[0403] Table 13

[0404]

[0405] In a possible implementation, the bit rearrangement version table further includes a third bit rearrangement version number, and the output bit sequence corresponding to the third bit rearrangement version number is

[0406] For example, the bit rearrangement version table includes a first bit rearrangement version number and a third bit rearrangement version number, the third bit rearrangement version number is 1, and the bit rearrangement version table can include Table 14 as follows:

[0407] Table 14

[0408]

[0409] For another example, the bit rearrangement version table includes a first bit rearrangement version number, a second bit rearrangement version number, and a third bit rearrangement version number, the second bit rearrangement version number is 1, and the third bit rearrangement version number is 2, and the bit rearrangement version table can include Table 15 as follows:

[0410] Table 15

[0411]

[0412] Another example, the bit rearrangement version table includes the first bit rearrangement version number, the second bit rearrangement version number and the third bit rearrangement version number, the second bit rearrangement version number is 2, the third bit rearrangement version number is 1, and the bit rearrangement version table can include the following table 16:

[0413] Table 16

[0414]

[0415] In a possible implementation, the bit rearrangement version table further includes a fourth bit rearrangement version number, and the output bit sequence corresponding to the fourth bit rearrangement version number is i2i1q2q1.

[0416] Another example, the bit rearrangement version table includes the first bit rearrangement version number and the fourth bit rearrangement version number, the fourth bit rearrangement version number is 1, and the bit rearrangement version table can include the following table 17:

[0417] Table 17

[0418] Bit rearrangement version number Output bit sequence 0 [i1 i2 q1 q2] 1 [i2 i2 q2 q2]

[0419] Another example, the bit rearrangement version table includes the first bit rearrangement version number, the second bit rearrangement version number and the fourth bit rearrangement version number, the second bit rearrangement version number is 1, the fourth bit rearrangement version number is 2, and the bit rearrangement version table can include the following table 18:

[0420] Table 18

[0421]

[0422] Another example, the bit rearrangement version table includes the first bit rearrangement version number, the second bit rearrangement version number and the fourth bit rearrangement version number, the second bit rearrangement version number is 2, the fourth bit rearrangement version number is 1, and the bit rearrangement version table can include the following table 19:

[0423] Table 19

[0424]

[0425] Another example, the bit rearrangement version table includes the first bit rearrangement version number, the third bit rearrangement version number and the fourth bit rearrangement version number, the third bit rearrangement version number is 1, the fourth bit rearrangement version number is 2, and the bit rearrangement version table can include the following table 20:

[0426] Table 20

[0427]

[0428] Another example, the bit rearrangement version table includes the first bit rearrangement version number, the second bit rearrangement version number, the third bit rearrangement version number and the fourth bit rearrangement version number, the second bit rearrangement version number is 1, the third bit rearrangement version number is 3, and the fourth bit rearrangement version number is 2, the bit rearrangement version table can include the following table 24:

[0429] Table 24

[0430]

[0431] Another example, the bit rearrangement version table includes the first bit rearrangement version number, the second bit rearrangement version number, the third bit rearrangement version number and the fourth bit rearrangement version number, the second bit rearrangement version number is 1, the third bit rearrangement version number is 3, and the fourth bit rearrangement version number is 2, the bit rearrangement version table can include the following table 24:

[0432] Table 24

[0433]

[0434] Another example, the bit rearrangement version table includes the first bit rearrangement version number, the second bit rearrangement version number, the third bit rearrangement version number and the fourth bit rearrangement version number, the second bit rearrangement version number is 1, the third bit rearrangement version number is 3, and the fourth bit rearrangement version number is 2, the bit rearrangement version table can include the following table 24:

[0435] Table 24

[0436]

[0437] Another example, the bit rearrangement version table includes the first bit rearrangement version number, the second bit rearrangement version number, the third bit rearrangement version number and the fourth bit rearrangement version number, the second bit rearrangement version number is 1, the third bit rearrangement version number is 3, and the fourth bit rearrangement version number is 2, the bit rearrangement version table can include the following table 24:

[0438] Table 24

[0439]

[0440] Another example, the bit rearrangement version table includes the first bit rearrangement version number, the second bit rearrangement version number, the third bit rearrangement version number and the fourth bit rearrangement version number, the second bit rearrangement version number is 1, the third bit rearrangement version number is 3, and the fourth bit rearrangement version number is 2, the bit rearrangement version table can include the following table 24:

[0441] Table 24

[0442]

[0443] Another example, the bit rearrangement version table includes a first bit rearrangement version number, a second bit rearrangement version number, a third bit rearrangement version number and a fourth bit rearrangement version number, the second bit rearrangement version number is 3, the third bit rearrangement version number is 1, and the fourth bit rearrangement version number is 2. The bit rearrangement version table can include the following Table 26:

[0444] Table 26

[0445]

[0446] Another example, the bit rearrangement version table includes a first bit rearrangement version number, a second bit rearrangement version number, a third bit rearrangement version number and a fourth bit rearrangement version number, the second bit rearrangement version number is 3, the third bit rearrangement version number is 2, and the fourth bit rearrangement version number is 1. The bit rearrangement version table can include the following Table 27:

[0447] Table 27

[0448]

[0449] An example, under 64QAM (i.e. when using 64QAM modulation), one symbol d(i) is mapped from 6 bits, the input bit sequence is i1i2i3q1q2q3, i1, i2, i3, q1, q2 and q3 represent a bit value respectively. An example, i1, i2, i3 can be mapped to the real part of the modulation symbol, and q1, q2, q3 can be mapped to the imaginary part of the modulation symbol. The bit rearrangement version table includes a fifth bit rearrangement version number, and the output bit sequence corresponding to the fifth bit rearrangement version number is i1i2i3q1q2q3. An example, the fifth bit rearrangement version number can be 0, and the bit rearrangement version table can include the following Table 28:

[0450] Table 28

[0451] Bit rearrangement version number Output bit sequence 0 [i1 i2 i3 q1 q2 q3]

[0452] In a possible implementation, the bit rearrangement version table further includes a sixth bit rearrangement version number, and the output bit sequence corresponding to the sixth bit rearrangement version number is An example, the sixth bit rearrangement version number can be 1, and the bit rearrangement version table can include the following Table 29:

[0453] Table 29

[0454]

[0455] In a possible implementation, the bit rearrangement version table further includes a seventh bit rearrangement version number, and the output bit sequence corresponding to the seventh bit rearrangement version number is

[0456] In one example, the bit rearrangement version table includes the fifth bit rearrangement version number and the seventh bit rearrangement version number, the seventh bit rearrangement version number is 1, and the bit rearrangement version table can include the following Table 30:

[0457] Table 30

[0458]

[0459] In another example, the bit rearrangement version table includes the fifth bit rearrangement version number, the sixth bit rearrangement version number and the seventh bit rearrangement version number, the sixth bit rearrangement version number is 1, the seventh bit rearrangement version number is 2, and the bit rearrangement version table can include the following Table 31:

[0460] Table 31

[0461]

[0462] In another example, the bit rearrangement version table includes the fifth bit rearrangement version number, the sixth bit rearrangement version number and the seventh bit rearrangement version number, the sixth bit rearrangement version number is 2, the seventh bit rearrangement version number is 1, and the bit rearrangement version table can include the following Table 32:

[0463] Table 32

[0464]

[0465] In one possible implementation, the bit rearrangement version table further includes an eighth bit rearrangement version number, and the eighth bit rearrangement version number corresponds to an output bit sequence of

[0466] In one example, the bit rearrangement version table includes the fifth bit rearrangement version number and the eighth bit rearrangement version number, the eighth bit rearrangement version number is 1, and the bit rearrangement version table can include the following Table 33:

[0467] Table 33

[0468]

[0469] In another example, the bit rearrangement version table includes the fifth bit rearrangement version number, the sixth bit rearrangement version number and the eighth bit rearrangement version number, the sixth bit rearrangement version number is 1, the eighth bit rearrangement version number is 2, and the bit rearrangement version table can include the following Table 34:

[0470] Table 34

[0471]

[0472] Another example, the bit rearrangement version table includes a fifth bit rearrangement version number, a sixth bit rearrangement version number, and an eighth bit rearrangement version number, the sixth bit rearrangement version number is 2, the eighth bit rearrangement version number is 1, the bit rearrangement version table can include the following Table 35:

[0473] Table 35

[0474]

[0475]

[0476] Another example, the bit rearrangement version table includes a fifth bit rearrangement version number, a seventh bit rearrangement version number, and an eighth bit rearrangement version number, the seventh bit rearrangement version number is 1, the eighth bit rearrangement version number is 2, the bit rearrangement version table can include the following Table 36:

[0477] Table 36

[0478]

[0479] Another example, the bit rearrangement version table includes a fifth bit rearrangement version number, a seventh bit rearrangement version number, and an eighth bit rearrangement version number, the seventh bit rearrangement version number is 2, the eighth bit rearrangement version number is 1, the bit rearrangement version table can include the following Table 37:

[0480] Table 37

[0481]

[0482] Another example, the bit rearrangement version table includes a fifth bit rearrangement version number, a sixth bit rearrangement version number, a seventh bit rearrangement version number, and an eighth bit rearrangement version number, the sixth bit rearrangement version number is 1, the seventh bit rearrangement version number is 2, the eighth bit rearrangement version number is 3, the bit rearrangement version table can include the following Table 38:

[0483] Table 38

[0484]

[0485] Another example, the bit rearrangement version table includes a fifth bit rearrangement version number, a sixth bit rearrangement version number, a seventh bit rearrangement version number, and an eighth bit rearrangement version number, the sixth bit rearrangement version number is 2, the seventh bit rearrangement version number is 1, the eighth bit rearrangement version number is 3, the bit rearrangement version table can include the following Table 39:

[0486] Table 39

[0487]

[0488] Another example, the bit rearrangement version table includes a fifth bit rearrangement version number, a sixth bit rearrangement version number, a seventh bit rearrangement version number, and an eighth bit rearrangement version number, the sixth bit rearrangement version number is 1, the seventh bit rearrangement version number is 3, and the eighth bit rearrangement version number is 2, the bit rearrangement version table can include the following Table 40:

[0489] Table 40

[0490]

[0491] Another example, the bit rearrangement version table includes a fifth bit rearrangement version number, a sixth bit rearrangement version number, a seventh bit rearrangement version number, and an eighth bit rearrangement version number, the sixth bit rearrangement version number is 2, the seventh bit rearrangement version number is 3, and the eighth bit rearrangement version number is 1, the bit rearrangement version table can include the following Table 41:

[0492] Table 41

[0493]

[0494] Another example, the bit rearrangement version table includes a fifth bit rearrangement version number, a sixth bit rearrangement version number, a seventh bit rearrangement version number, and an eighth bit rearrangement version number, the sixth bit rearrangement version number is 3, the seventh bit rearrangement version number is 1, and the eighth bit rearrangement version number is 2, the bit rearrangement version table can include the following Table 42:

[0495] Table 42

[0496]

[0497] Another example, the bit rearrangement version table includes a fifth bit rearrangement version number, a sixth bit rearrangement version number, a seventh bit rearrangement version number, and an eighth bit rearrangement version number, the sixth bit rearrangement version number is 3, the seventh bit rearrangement version number is 2, and the eighth bit rearrangement version number is 1, the bit rearrangement version table can include the following Table 43:

[0498] Table 43

[0499]

[0500] For example, under 256QAM (i.e., when 256QAM modulation is used), one symbol d(i) is mapped from 8 bits, and the input bit sequence is i1i2i3i4q1q2q3q4, where i1, i2, i3, i4, q1, q2, q3, and q4 represent a bit value respectively. For example, i1, i2, i3, i4 can be mapped to the real part of the modulation symbol, and q1, q2, q3, q4 can be mapped to the imaginary part of the modulation symbol. The bit rearrangement version table includes a ninth bit rearrangement version number, and the output bit sequence corresponding to the ninth bit rearrangement version number is i1i2i3i4q1q2q3q4. For example, the ninth bit rearrangement version number can be 0, and the bit rearrangement version table can include the following Table 44:

[0501] Table 44

[0502] Bit rearrangement version number Output bit sequence 0 [i1 i2 i3 i4 q1 q2 q3 q4]

[0503] In a possible implementation, the bit rearrangement version table further includes a tenth bit rearrangement version number, and the output bit sequence corresponding to the tenth bit rearrangement version number is For example, the tenth bit rearrangement version number can be 1, and the bit rearrangement version table can include the following Table 45:

[0504] Table 45

[0505]

[0506] In a possible implementation, the bit rearrangement version table further includes an eleventh bit rearrangement version number, and the output bit sequence corresponding to the eleventh bit rearrangement version number is

[0507] For example, the bit rearrangement version table includes a ninth bit rearrangement version number and an eleventh bit rearrangement version number, the eleventh bit rearrangement version number is 1, and the bit rearrangement version table can include the following Table 46:

[0508] Table 46

[0509]

[0510]

[0511] For another example, the bit rearrangement version table includes a ninth bit rearrangement version number, a tenth bit rearrangement version number, and an eleventh bit rearrangement version number, the tenth bit rearrangement version number is 1, and the eleventh bit rearrangement version number is 2, and the bit rearrangement version table can include the following Table 47:

[0512] Table 47

[0513]

[0514] Another example bit rearrangement version table includes a ninth bit rearrangement version number, a tenth bit rearrangement version number, and an eleventh bit rearrangement version number, the tenth bit rearrangement version number is 2, and the eleventh bit rearrangement version number is 1. The bit rearrangement version table can include the following Table 48:

[0515] Table 48

[0516]

[0517] In a possible implementation, the bit rearrangement version table further includes a twelfth bit rearrangement version number, and the twelfth bit rearrangement version number corresponds to an output bit sequence of i3i2i1i4q3q2q1q4.

[0518] Another example bit rearrangement version table includes a ninth bit rearrangement version number and a twelfth bit rearrangement version number, the twelfth bit rearrangement version number is 1. The bit rearrangement version table can include the following Table 49:

[0519] Table 49

[0520] Bit rearrangement version number Output bit sequence 0 [i1 i2 i3 i4 q1 q2 q3 q4] 1 [i3 i2 i1 i4 q3 q2 q1 q4]

[0521] Another example bit rearrangement version table includes a ninth bit rearrangement version number, a tenth bit rearrangement version number, and a twelfth bit rearrangement version number, the tenth bit rearrangement version number is 1, and the twelfth bit rearrangement version number is 2. The bit rearrangement version table can include the following Table 50:

[0522] Table 50

[0523]

[0524] Another example bit rearrangement version table includes a ninth bit rearrangement version number, a tenth bit rearrangement version number, and a twelfth bit rearrangement version number, the tenth bit rearrangement version number is 2, and the twelfth bit rearrangement version number is 1. The bit rearrangement version table can include the following Table 51:

[0525] Table 51

[0526]

[0527] Another example bit rearrangement version table includes a ninth bit rearrangement version number, an eleventh bit rearrangement version number, and a twelfth bit rearrangement version number, the eleventh bit rearrangement version number is 1, and the twelfth bit rearrangement version number is 2. The bit rearrangement version table can include the following Table 52:

[0528] Table 52

[0529]

[0530] Another example, the bit rearrangement version table includes a ninth bit rearrangement version number, an eleventh bit rearrangement version number, and a twelfth bit rearrangement version number, the eleventh bit rearrangement version number is 2, the twelfth bit rearrangement version number is 1, the bit rearrangement version table can include the following Table 53:

[0531] Table 53

[0532]

[0533] Another example, the bit rearrangement version table includes a ninth bit rearrangement version number, a tenth bit rearrangement version number, an eleventh bit rearrangement version number, and a twelfth bit rearrangement version number, the tenth bit rearrangement version number is 1, the eleventh bit rearrangement version number is 2, the twelfth bit rearrangement version number is 3, the bit rearrangement version table can include the following Table 54:

[0534] Table 54

[0535]

[0536] Another example, the bit rearrangement version table includes a ninth bit rearrangement version number, a tenth bit rearrangement version number, an eleventh bit rearrangement version number, and a twelfth bit rearrangement version number, the tenth bit rearrangement version number is 2, the eleventh bit rearrangement version number is 1, the twelfth bit rearrangement version number is 3, the bit rearrangement version table can include the following Table 55:

[0537] Table 55

[0538]

[0539] Another example, the bit rearrangement version table includes a ninth bit rearrangement version number, a tenth bit rearrangement version number, an eleventh bit rearrangement version number, and a twelfth bit rearrangement version number, the tenth bit rearrangement version number is 1, the eleventh bit rearrangement version number is 3, the twelfth bit rearrangement version number is 2, the bit rearrangement version table can include the following Table 56:

[0540] Table 56

[0541]

[0542] Another example, the bit rearrangement version table includes a ninth bit rearrangement version number, a tenth bit rearrangement version number, an eleventh bit rearrangement version number, and a twelfth bit rearrangement version number, the tenth bit rearrangement version number is 2, the eleventh bit rearrangement version number is 3, the twelfth bit rearrangement version number is 1, the bit rearrangement version table can include the following Table 57:

[0543] Table 57

[0544]

[0545] Another example, the bit rearrangement version table includes a ninth bit rearrangement version number, a tenth bit rearrangement version number, an eleventh bit rearrangement version number and a twelfth bit rearrangement version number, the tenth bit rearrangement version number is 3, the eleventh bit rearrangement version number is 1, and the twelfth bit rearrangement version number is 2. The bit rearrangement version table can include the following table 58:

[0546] Table 58

[0547]

[0548]

[0549] Another example, the bit rearrangement version table includes a ninth bit rearrangement version number, a tenth bit rearrangement version number, an eleventh bit rearrangement version number and a twelfth bit rearrangement version number, the tenth bit rearrangement version number is 3, the eleventh bit rearrangement version number is 2, and the twelfth bit rearrangement version number is 1. The bit rearrangement version table can include the following table 59:

[0550] Table 59

[0551]

[0552] An example, under 1024QAM (i.e. when using 1024QAM modulation), one symbol d(i) is mapped by 10 bits, the input bit sequence is i1i2i3i4i5q1q2q3q4q5, i1, i2, i3, i4, i5, q1, q2, q3, q4 and q5 represent a bit value respectively. An example, i1, i2, i3, i4, i5 can be mapped to the real part of the modulation symbol, and q1, q2, q3, q4, q5 can be mapped to the imaginary part of the modulation symbol. The bit rearrangement version table includes a thirteenth bit rearrangement version number, and the output bit sequence corresponding to the thirteenth bit rearrangement version number is i1i2i3i4i5q1q2q3q4q5. An example, the thirteenth bit rearrangement version number can be 0, and the bit rearrangement version table can include the following table 60:

[0553] Table 60

[0554] Bit rearrangement version number Output bit sequence 0 [i1 i2 i3 i4 i5 q1 q2 q3 q4 q5]

[0555] In a possible implementation, the bit rearrangement version table further includes a fourteenth bit rearrangement version number, and the output bit sequence corresponding to the fourteenth bit rearrangement version number is i5i4i3i2i1q5q4q3q2q1. An example, the fourteenth bit rearrangement version number can be 1, and the bit rearrangement version table can include the following table 61:

[0556] Table 61

[0557] Bit rearrangement version number Output bit sequence 0 [i1 i2 i3 i4 i5 q1 q2 q3 q4 q5] 1 [i5 i4 i3 i2 i1 q5 q4 q3 q2 q1]

[0558] In a possible implementation, the bit rearrangement version table further includes a fifteenth bit rearrangement version number, and the output bit sequence corresponding to the fifteenth bit rearrangement version number is

[0559] For example, the bit rearrangement version table includes the thirteenth bit rearrangement version number and the fifteenth bit rearrangement version number, the fifteenth bit rearrangement version number is 1, and the bit rearrangement version table can include the following table 62:

[0560] Table 62

[0561]

[0562] For another example, the bit rearrangement version table includes the thirteenth bit rearrangement version number, the fourteenth bit rearrangement version number, and the fifteenth bit rearrangement version number, the fourteenth bit rearrangement version number is 1, the fifteenth bit rearrangement version number is 2, and the bit rearrangement version table can include the following table 63:

[0563] Table 63

[0564]

[0565] For another example, the bit rearrangement version table includes the thirteenth bit rearrangement version number, the fourteenth bit rearrangement version number, and the fifteenth bit rearrangement version number, the fourteenth bit rearrangement version number is 2, the fifteenth bit rearrangement version number is 1, and the bit rearrangement version table can include the following table 64:

[0566] Table 64

[0567]

[0568] In a possible implementation, the bit rearrangement version table further includes a sixteenth bit rearrangement version number, and the output bit sequence corresponding to the sixteenth bit rearrangement version number is

[0569] For example, the bit rearrangement version table includes the thirteenth bit rearrangement version number and the sixteenth bit rearrangement version number, the sixteenth bit rearrangement version number is 1, and the bit rearrangement version table can include the following table 65:

[0570] Table 65

[0571]

[0572] Another example, the bit rearrangement version table includes a thirteenth bit rearrangement version number, a fourteenth bit rearrangement version number, and a sixteenth bit rearrangement version number, the fourteenth bit rearrangement version number is 1, the sixteenth bit rearrangement version number is 2, the bit rearrangement version table can include the following table 66:

[0573] Table 66

[0574]

[0575] Another example, the bit rearrangement version table includes a thirteenth bit rearrangement version number, a fourteenth bit rearrangement version number, and a sixteenth bit rearrangement version number, the fourteenth bit rearrangement version number is 1, the sixteenth bit rearrangement version number is 2, the bit rearrangement version table can include the following table 66:

[0576] Table 67

[0577]

[0578] Another example, the bit rearrangement version table includes a thirteenth bit rearrangement version number, a fifteenth bit rearrangement version number, and a sixteenth bit rearrangement version number, the fifteenth bit rearrangement version number is 1, the sixteenth bit rearrangement version number is 2, the bit rearrangement version table can include the following table 68:

[0579] Table 68

[0580]

[0581] Another example, the bit rearrangement version table includes a thirteenth bit rearrangement version number, a fifteenth bit rearrangement version number, and a sixteenth bit rearrangement version number, the fifteenth bit rearrangement version number is 2, the sixteenth bit rearrangement version number is 1, the bit rearrangement version table can include the following table 69:

[0582] Table 69

[0583]

[0584] Another example, the bit rearrangement version table includes a thirteenth bit rearrangement version number, a fourteenth bit rearrangement version number, a fifteenth bit rearrangement version number, and a sixteenth bit rearrangement version number, the fourteenth bit rearrangement version number is 1, the fifteenth bit rearrangement version number is 2, the sixteenth bit rearrangement version number is 3, the bit rearrangement version table can include the following table 70:

[0585] Table 70

[0586]

[0587] Another example, the bit rearrangement version table includes a thirteenth bit rearrangement version number, a fourteenth bit rearrangement version number, a fifteenth bit rearrangement version number, and a sixteenth bit rearrangement version number, the fourteenth bit rearrangement version number is 2, the fifteenth bit rearrangement version number is 1, and the sixteenth bit rearrangement version number is 3, the bit rearrangement version table can include the following Table 71:

[0588] Table 71

[0589]

[0590] Another example, the bit rearrangement version table includes a thirteenth bit rearrangement version number, a fourteenth bit rearrangement version number, a fifteenth bit rearrangement version number, and a sixteenth bit rearrangement version number, the fourteenth bit rearrangement version number is 1, the fifteenth bit rearrangement version number is 3, and the sixteenth bit rearrangement version number is 2, the bit rearrangement version table can include the following Table 72:

[0591] Table 72

[0592]

[0593] Another example, the bit rearrangement version table includes a thirteenth bit rearrangement version number, a fourteenth bit rearrangement version number, a fifteenth bit rearrangement version number, and a sixteenth bit rearrangement version number, the fourteenth bit rearrangement version number is 2, the fifteenth bit rearrangement version number is 3, and the sixteenth bit rearrangement version number is 1, the bit rearrangement version table can include the following Table 73:

[0594] Table 73

[0595]

[0596] Another example, the bit rearrangement version table includes a thirteenth bit rearrangement version number, a fourteenth bit rearrangement version number, a fifteenth bit rearrangement version number, and a sixteenth bit rearrangement version number, the fourteenth bit rearrangement version number is 3, the fifteenth bit rearrangement version number is 1, and the sixteenth bit rearrangement version number is 2, the bit rearrangement version table can include the following Table 74:

[0597] Table 74

[0598]

[0599] Another example, the bit rearrangement version table includes a thirteenth bit rearrangement version number, a fourteenth bit rearrangement version number, a fifteenth bit rearrangement version number, and a sixteenth bit rearrangement version number, the fourteenth bit rearrangement version number is 3, the fifteenth bit rearrangement version number is 2, and the sixteenth bit rearrangement version number is 1, the bit rearrangement version table can include the following Table 75:

[0600] Table 75

[0601]

[0602] For example, under 4096QAM (i.e., when using 4096QAM modulation), the input bit sequence is i1i2i3i4i5i6q1q2q3q4q5q6, where i1, i2, i3, i4, i5, i6, q1, q2, q3, q4, q5, and q6 represent a bit value, respectively. For example, i1, i2, i3, i4, i5 can be mapped to the real part of the modulation symbol, and q1, q2, q3, q4, q5, q6 can be mapped to the imaginary part of the modulation symbol. The bit rearrangement version table includes a seventeenth bit rearrangement version number, and the output bit sequence corresponding to the seventeenth bit rearrangement version number is i1i2i3i4i5i6q1q2q3q4q5q6. For example, the seventeenth bit rearrangement version number can be 0, and the bit rearrangement version table can include the following Table 76:

[0603] Table 76

[0604] Bit rearrangement version number Output bit sequence 0 [i1 i2 i3 i4 i5 i6 q1 q2 q3 q4 q5 q6]

[0605] In a possible implementation, the bit rearrangement version table further includes an eighteenth bit rearrangement version number, and the output bit sequence corresponding to the eighteenth bit rearrangement version number is i6i5i4i3i2i1q6q5q4q3q2q1. For example, the eighteenth bit rearrangement version number can be 1, and the bit rearrangement version table can include the following Table 77:

[0606] Table 77

[0607] Bit rearrangement version number Output bit sequence 0 [i1 i2 i3 i4 i5 i6 q1 q2 q3 q4 q5 q6] 1 [i6 i5 i4 i3 i2 i1 q6 q5 q4 q3 q2 q1]

[0608] In a possible implementation, the bit rearrangement version table further includes a nineteenth bit rearrangement version number, and the output bit sequence corresponding to the nineteenth bit rearrangement version number is

[0609] For example, the bit rearrangement version table includes the seventeenth bit rearrangement version number and the nineteenth bit rearrangement version number, the nineteenth bit rearrangement version number is 1, and the bit rearrangement version table can include the following Table 78:

[0610] Table 78

[0611]

[0612] For another example, the bit rearrangement version table includes the seventeenth bit rearrangement version number, the eighteenth bit rearrangement version number, and the nineteenth bit rearrangement version number, the eighteenth bit rearrangement version number is 1, the nineteenth bit rearrangement version number is 2, and the bit rearrangement version table can include the following Table 79:

[0613] Table 79

[0614]

[0615] Another example, the bit rearrangement version table includes the seventeenth bit rearrangement version number, the eighteenth bit rearrangement version number and the twentieth bit rearrangement version number, the eighteenth bit rearrangement version number is 2, the twentieth bit rearrangement version number is 1, and the bit rearrangement version table can include the following table 80:

[0616] Table 80

[0617]

[0618]

[0619] In a possible implementation, the bit rearrangement version table further includes a twentieth bit rearrangement version number, and the output bit sequence corresponding to the twentieth bit rearrangement version number is i4i2i5i3i1i6q4q2q5q3q1q6.

[0620] Another example, the bit rearrangement version table includes the seventeenth bit rearrangement version number and the twentieth bit rearrangement version number, the twentieth bit rearrangement version number is 1, and the bit rearrangement version table can include the following table 81:

[0621] Table 81

[0622] Bit rearrangement version number Output bit sequence 0 [i1 i2 i3 i4 i5 i6 q1 q2 q3 q4 q5 q6] 1 [i4 i2 i5 i3 i1 i6 q4 q2 q5 q3 q1 q6]

[0623] Another example, the bit rearrangement version table includes the seventeenth bit rearrangement version number, the eighteenth bit rearrangement version number and the twentieth bit rearrangement version number, the eighteenth bit rearrangement version number is 1, the twentieth bit rearrangement version number is 2, and the bit rearrangement version table can include the following table 82:

[0624] Table 82

[0625] Bit rearrangement version number Output bit sequence 0 [i1 i2 i3 i4 i5 i6 q1 q2 q3 q4 q5 q6] 1 [i6 i5 i4 i3 i2 i1 q6 q5 q4 q3 q2 q1] 2 [i4 i2 i5 i3 i1 i6 q4 q2 q5 q3 q1 q6]

[0626] Another example, the bit rearrangement version table includes the seventeenth bit rearrangement version number, the eighteenth bit rearrangement version number and the twentieth bit rearrangement version number, the eighteenth bit rearrangement version number is 2, the twentieth bit rearrangement version number is 1, and the bit rearrangement version table can include the following table 83:

[0627] Table 83

[0628] Bit rearrangement version number Output bit sequence 0 [i1 i2 i3 i4 i5 i6 q1 q2 q3 q4 q5 q6] 1 [i4 i2 i5 i3 i1 i6 q4 q2 q5 q3 q1 q6] 2 [i6 i5 i4 i3 i2 i1 q6 q5 q4 q3 q2 q1]

[0629] Another example, the bit rearrangement version table includes a seventeenth bit rearrangement version number, a nineteenth bit rearrangement version number, and a twentieth bit rearrangement version number, the nineteenth bit rearrangement version number is 1, and the twentieth bit rearrangement version number is 2, the bit rearrangement version table can include the following Table 84:

[0630] Table 84

[0631]

[0632] Another example, the bit rearrangement version table includes a seventeenth bit rearrangement version number, a nineteenth bit rearrangement version number, and a twentieth bit rearrangement version number, the nineteenth bit rearrangement version number is 2, and the twentieth bit rearrangement version number is 1, the bit rearrangement version table can include the following Table 85:

[0633] Table 85

[0634]

[0635] Another example, the bit rearrangement version table includes a seventeenth bit rearrangement version number, an eighteenth bit rearrangement version number, a nineteenth bit rearrangement version number, and a twentieth bit rearrangement version number, the eighteenth bit rearrangement version number is 1, the nineteenth bit rearrangement version number is 2, and the twentieth bit rearrangement version number is 3, the bit rearrangement version table can include the following Table 86:

[0636] Table 86

[0637]

[0638]

[0639] Another example, the bit rearrangement version table includes a seventeenth bit rearrangement version number, an eighteenth bit rearrangement version number, a nineteenth bit rearrangement version number, and a twentieth bit rearrangement version number, the eighteenth bit rearrangement version number is 2, the nineteenth bit rearrangement version number is 1, and the twentieth bit rearrangement version number is 3, the bit rearrangement version table can include the following Table 87:

[0640] Table 87

[0641]

[0642] Another example, the bit rearrangement version table includes a seventeenth bit rearrangement version number, an eighteenth bit rearrangement version number, a nineteenth bit rearrangement version number, and a twentieth bit rearrangement version number, the eighteenth bit rearrangement version number is 1, the nineteenth bit rearrangement version number is 3, and the twentieth bit rearrangement version number is 2, the bit rearrangement version table can include the following Table 88:

[0643] Table 88

[0644]

[0645] Another example, the bit rearrangement version table includes a seventeenth bit rearrangement version number, an eighteenth bit rearrangement version number, a nineteenth bit rearrangement version number and a twentieth bit rearrangement version number, the eighteenth bit rearrangement version number is 2, the nineteenth bit rearrangement version number is 3, and the twentieth bit rearrangement version number is 1. The bit rearrangement version table can include the following table 89:

[0646] Table 89

[0647]

[0648] Another example, the bit rearrangement version table includes a seventeenth bit rearrangement version number, an eighteenth bit rearrangement version number, a nineteenth bit rearrangement version number and a twentieth bit rearrangement version number, the eighteenth bit rearrangement version number is 3, the nineteenth bit rearrangement version number is 1, and the twentieth bit rearrangement version number is 2. The bit rearrangement version table can include the following table 90:

[0649] Table 90

[0650]

[0651] Another example, the bit rearrangement version table includes a seventeenth bit rearrangement version number, an eighteenth bit rearrangement version number, a nineteenth bit rearrangement version number and a twentieth bit rearrangement version number, the eighteenth bit rearrangement version number is 3, the nineteenth bit rearrangement version number is 2, and the twentieth bit rearrangement version number is 1. The bit rearrangement version table can include the following table 91:

[0652] Table 91

[0653]

[0654]

[0655] In the foregoing table, represents bit i () Logical value negation. Bit rearrangement version number corresponds to retransmission version number one by one. That is, at the nth retransmission, bit retransmission version n is used for bit rearrangement, 0≤n≤3, the 0th retransmission refers to the first transmission.

[0656] Taking table 91 as an example, bit rearrangement version 0: input bit sequence is i1i2i3i4i5i6q1q2q3q4q5q6, and output bit sequence is i1i2i3i4i5i6q1q2q3q4q5q6, that is, output=input.

[0657] Bit rearrangement version 1: input bit sequence is i1i2i3i4i5i6q1q2q3q4q5q6, and output bit sequence is i4i2i5i3i1i6q4q2q5q3q1q6.

[0658] By analogy, the specific operations of bit rearrangement version 2 and bit rearrangement version 3 can be obtained.

[0659] It should be noted that the foregoing Table 12 to Table 91 are only exemplary descriptions, i () and q () represent a bit value, and other ways of representing a bit value can also be used. For example, a bit value can be represented by b(). The embodiments of the present application do not make any limitation in this regard. In a possible implementation manner, the bit rearrangement versions in each modulation mode can be combined into a table, and the bit rearrangement version numbers are sequentially arranged in descending order from 0. In a possible implementation manner, Table 12 to Table 91 can further include a column of table entries of input bit sequences.

[0660] 802. Determine the output bit sequence according to the bit rearrangement version table.

[0661] The process can refer to the foregoing process 302, and the embodiments of the present application do not make any limitation in this regard.

[0662] By using different bit rearrangement versions at each transmission through the bit rearrangement version table, the embodiments of the present application can improve the HARQ gain, and the higher the modulation mode is, the greater the gain is.

[0663] After obtaining the output bit sequence through bit rearrangement by using the bit rearrangement version table, the output bit sequence in the first bit rearrangement version is modulated and mapped to obtain a constellation symbol in a constellation diagram.

[0664] The embodiments of the present application can be applied to a communication system using Gray mapping, and the following is a possible implementation manner of a constellation diagram:

[0665] When 16QAM modulation is used, the constellation diagram can refer to the foregoing Figure 4 , i1, i2, q1, and q2 correspond to 1-4 bit positions of the constellation symbol respectively. i1 and i2 correspond to the real part of the constellation symbol, and q1 and q2 correspond to the imaginary part of the constellation symbol.

[0666] When 64QAM modulation is used, refer to Figure 10 , Figure 10 is a 64QAM constellation diagram provided by the embodiments of the present application. Bits i1, i2, i3, q1, q2, and q3 correspond to 1-6 bit positions of the constellation symbol respectively. i1, i2, and i3 correspond to the real part of the constellation symbol, and q1, q2, and q3 correspond to the imaginary part of the constellation symbol.

[0667] When using 256 QAM modulation, please refer to Figure 11 , Figure 11 a 256 QAM constellation provided by an embodiment of the present application. Bits i1, i2, i3, i4, q1, q2, q3, q4 correspond to 1-8 bit positions of a constellation symbol respectively. i1, i2, i3, i4 correspond to a real part of the constellation symbol, and q1, q2, q3, q4 correspond to an imaginary part of the constellation symbol.

[0668] When using 1024 QAM modulation, please refer to Figure 12 , Figure 12 a 1024 QAM constellation provided by an embodiment of the present application. Bits i1, i2, i3, i4, i5, q1, q2, q3, q4, q5 correspond to 1-10 bit positions of a constellation symbol respectively. i1, i2, i3, i4, i5 correspond to a real part of the constellation symbol, and q1, q2, q3, q4, q5 correspond to an imaginary part of the constellation symbol. As shown in Figure 12 , input bits represent 5 bit positions of a real part or an imaginary part of a corresponding constellation symbol. I-out represents a real part of the constellation symbol, and input bits B0, B1, B2, B3, and B4 corresponding to I-out refer to i1, i2, i3, i4, i5. Q-out represents an imaginary part of the constellation symbol, and input bits B0, B1, B2, B3, and B4 corresponding to Q-out refer to q1, q2, q3, q4, q5.

[0669] When using 4096 QAM modulation, please refer to Figure 13 , Figure 13 a 4096 QAM constellation provided by an embodiment of the present application. Bits i1, i2, i3, i4, i5, i6, q1, q2, q3, q4, q5, q6 correspond to 1-10 bit positions of a constellation symbol respectively. i1, i2, i3, i4, i5, i6 correspond to a real part of the constellation symbol, and q1, q2, q3, q4, q5, q6 correspond to an imaginary part of the constellation symbol. As shown in Figure 13 , input bits represent 6 bit positions of a real part or an imaginary part of a corresponding constellation symbol. I-out represents a real part of the constellation symbol, and input bits B0, B1, B2, B3, B4, and B5 corresponding to I-out refer to i1, i2, i3, i4, i5, i6. Q-out represents an imaginary part of the constellation symbol, and input bits B0, B1, B2, B3, B4, and B5 corresponding to Q-out refer to q1, q2, q3, q4, q5, q6.

[0670] Embodiment Eight:

[0671] Please refer to Figure 14 , Figure 14Another communication method flow diagram is provided in the embodiments of the present application. The method can include the following processes:

[0672] 901. Receiving bit rearrangement version information, the bit rearrangement version information indicating a first bit rearrangement version in a bit rearrangement version table.

[0673] The first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number in a first QAM. The first QAM is 16QAM, 64QAM, 256QAM, 1024QAM, or 4096QAM.

[0674] For example, the terminal node can receive the bit rearrangement version information sent by the management node.

[0675] In a possible implementation, the bit rearrangement version information is carried in scheduling type indication information. The scheduling type indication information indicates that the first redundancy version and the channel bit sequence of the first bit rearrangement version are determined by using the first encoding mode based on retransmission or initial transmission and retransmission hybrid transmission of a first retransmission data unit. The first retransmission data unit is a transport block or a code block group. The related description of the scheduling type indication information can be referred to the foregoing process 201, and will not be described here in detail.

[0676] In a possible implementation, the bit rearrangement version information is bound to target information. The target information is used to indicate a redundancy version number or a superframe number. For example, the redundancy version number is the same as the bit rearrangement version number. The bit rearrangement version number indicated by the first bit rearrangement version is the redundancy version number. For another example, the bit rearrangement version number indicated by the first bit rearrangement version is mod(superframe number, 4). In this way, the bit rearrangement version information is bound to the target information, and the first bit rearrangement version is indicated by the target information. The bit rearrangement version information does not need to occupy additional bits, thereby effectively saving resources.

[0677] In a possible implementation, the bit rearrangement version information can be sent separately. For example, the bit rearrangement version information can be carried in dynamic scheduling data control information, control signaling, or a superframe header.

[0678] The related description of the bit rearrangement version information can be referred to the foregoing process 701, and will not be described here in detail.

[0679] 902. Performing bit rearrangement according to the bit rearrangement version information.

[0680] The process can be referred to the foregoing process 402, and will not be described here in detail.

[0681] Embodiment nine:

[0682] Please refer to Figure 15 ,Figure 15 Another communication method flow diagram is provided for the embodiments of the present application. The method can include the following processes:

[0683] 1001. Obtain a bit rearrangement version table, the bit rearrangement version table including output bit sequences corresponding to respective bit rearrangement version numbers under at least one QAM, the at least one QAM including at least one of 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM.

[0684] The bit rearrangement version table can refer to Tables 12-91 in the aforementioned embodiment seven, and the embodiments of the present application will not be repeated here.

[0685] 1002. Determine the input bit sequence according to the bit rearrangement version table.

[0686] The process can refer to the aforementioned processes 402 and 502, and the embodiments of the present application will not be repeated here.

[0687] Embodiment ten:

[0688] Please refer to Figure 16 , Figure 16 Another communication method flow diagram is provided for the embodiments of the present application. The method can be applicable to a WiFi system, and can include the following processes:

[0689] 1101. The access node obtains a bit rearrangement version table, the bit rearrangement version table including output bit sequences corresponding to respective bit rearrangement version numbers under at least one QAM, the at least one QAM including at least one of 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM.

[0690] The process can refer to the aforementioned process 801, and the embodiments of the present application will not be repeated here.

[0691] 1102. The access node determines the output bit sequence according to the bit rearrangement version table.

[0692] The process can refer to the aforementioned process 802, and the embodiments of the present application will not be repeated here.

[0693] 1103. The terminal device obtains the bit rearrangement version table.

[0694] The process can refer to the aforementioned process 801, and the embodiments of the present application will not be repeated here.

[0695] 1104. The access node generates bit rearrangement version information, the bit rearrangement version information indicating a first bit rearrangement version in the bit rearrangement version table.

[0696] The process can refer to the foregoing process 701, and embodiments of the present application will not be described here.

[0697] 1105. The access node sends the bit rearrangement version information to the terminal device.

[0698] The process can refer to the foregoing process 702, and embodiments of the present application will not be described here.

[0699] 1106. The terminal device decodes and de-rearranges the bit sequence according to the bit rearrangement version information and the bit rearrangement version table to obtain the input bit sequence.

[0700] The process can refer to the foregoing processes 902 and 1002, and embodiments of the present application will not be described here.

[0701] Embodiments six to ten in the present application can be applied to a WiFi system.

[0702] In summary, the communication method, the management node and the terminal node provided by the embodiments of the present application can be summarized as follows: the management node and the terminal node respectively acquire a bit rearrangement version table, the bit rearrangement version table includes an output bit sequence corresponding to each bit rearrangement version number under at least one QAM, and the at least one QAM includes at least one of 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; the management node determines the output bit sequence according to the bit rearrangement version table, and can subsequently encode and send a channel bit sequence. The management node sends bit rearrangement version information to the terminal node, the bit rearrangement version information indicates a first bit rearrangement version in the bit rearrangement version table, the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number under a first QAM, and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM. The terminal node decodes and de-rearranges the channel bit sequence according to the bit rearrangement version information and the bit rearrangement version table. By using different bit rearrangement versions at each transmission through the bit rearrangement version table, the benefits of HARQ can be improved, and the higher the modulation mode, the greater the benefits.

[0703] Please refer to Figure 17 , Figure 17A performance benefit diagram provided by the embodiment of the present application is shown in FIG. 6, in which MCS represents modulation and coding scheme, and MCS0 to MCS31 represent different modulation and coding schemes respectively. The modulation mode of the modulation and coding schemes represented by MCS8 to MCS12 is 16QAM, and the greater the index value, the higher the coding rate. The modulation mode of the modulation and coding schemes represented by MCS13 to MCS19 is 64QAM, and the greater the index value, the higher the coding rate. The modulation mode of the modulation and coding schemes represented by MCS20 to MCS25 is 256QAM, and the greater the index value, the higher the coding rate. The modulation mode of the modulation and coding schemes represented by MCS26 to MCS28 is 1024QAM, and the greater the index value, the higher the coding rate. The modulation mode of the modulation and coding schemes represented by MCS29 to MCS31 is 4096QAM, and the greater the index value, the higher the coding rate. It can be seen from the diagram that the benefit of 1-time retransmission is about 0.2-9.8dB, and the benefit of 3-time retransmission is about 1.8-15.0dB, and the higher the modulation mode, the greater the benefit. Figure 17 It can be seen that the benefit of 1-time retransmission is about 0.2-9.8dB, and the benefit of 3-time retransmission is about 1.8-15.0dB, and the higher the modulation mode, the greater the benefit.

[0704] The communication method provided by the embodiment of the present application is mainly described from the perspective of the device. It can be understood that the device contains the hardware structure and / or software module corresponding to the execution of each function in order to realize the above functions. Those skilled in the art should easily realize that the algorithm steps of each example described in combination with the embodiments disclosed in the present text can be realized in the form of hardware or the combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. The professional technicians can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0705] Figure 18 A structural schematic diagram of an electronic device provided by the embodiment of the present application is shown in FIG. 7. The electronic device 1200 can be a management node or a chip or functional module in the management node, or a terminal node or a chip or functional module in the terminal node. As shown in the figure, the electronic device 1200 includes a processor 1201, a transceiver 1202 and a communication line 1203. Figure 18

[0706] The processor 1201 is configured to perform any step in the method embodiments shown in FIGS. 8-10, and when executing processes such as sending scheduling type indication information, the transceiver 1202 and the communication line 1203 can be selectively called to complete the corresponding operations. Figure 2 Figure 3 Figure 5 to Figure 9 The processor 1201 is configured to perform any step in the method embodiments shown in FIGS. 8-10, and when executing processes such as sending scheduling type indication information, the transceiver 1202 and the communication line 1203 can be selectively called to complete the corresponding operations. ​​​

[0707] Furthermore, the electronic device 1200 may also include a memory 1204. The processor 1201, the memory 1204, and the transceiver 1202 can be connected via a communication line 1203.

[0708] Transceiver 1202 is used to communicate with other devices or other communication networks, such as Ethernet, radio access network (RAN), wireless local area network (WLAN), etc. Transceiver 1202 can be a module, circuit, transceiver, or any device capable of enabling communication.

[0709] The transceiver 1202 is mainly used for sending and receiving data and information, and may include a transmitter and a receiver to send and receive data and information respectively; operations other than sending and receiving data and information are implemented by the processor, such as generating scheduling type indication information.

[0710] Communication line 1203 is used to transmit information between the various components included in electronic device 1200.

[0711] In one design, the processor can be viewed as a logic circuit, and the transceiver as an interface circuit.

[0712] Memory 1204 is used to store instructions. These instructions can be computer programs.

[0713] It should be noted that the memory 1204 can exist independently of the processor 1201, or it can be integrated with the processor 1201. The memory 1204 can be used to store instructions, program code, or some data, etc. The memory 1204 can be located inside or outside the electronic device 1200, without limitation. The processor 1201 is used to execute the instructions stored in the memory 1204 to implement the method provided in the above embodiments of this application.

[0714] In one example, processor 1201 may include one or more processors, for example Figure 18 Processor 0 and processor 1 in the system.

[0715] As an optional implementation, the electronic device 1200 includes multiple processors, for example, besides Figure 18 In addition to processor 1201, it may also include processor 1207.

[0716] As an optional implementation, the electronic device 1200 further includes an output device 1205 and an input device 1206. For example, the input device 1206 is a keyboard, a mouse, a microphone, a joystick, or the like, and the output device 1205 is a display screen, a speaker, or the like.

[0717] It should be noted that the electronic device 1200 can be a chip system or a device with a chip system. Figure 18 The actions, terms, and the like involved among the embodiments of the present application can be mutually referred to without limitation. The message name or the parameter name in the message exchanged between the devices in the embodiments of the present application is only an example, and other names can also be used in the specific implementation without limitation. In addition, Figure 18 The constituent structure shown in the foregoing is not a limitation on the electronic device 1200, and the electronic device 1200 can include more or fewer components than those shown, or combine certain components, or arrange the components differently. Figure 18 The electronic device 1200 can include more or fewer components than those shown, or combine certain components, or arrange the components differently. Figure 18 The electronic device 1200 can include more or fewer components than those shown, or combine certain components, or arrange the components differently.

[0718] The processor and the transceiver described in the present application can be implemented on an integrated circuit (IC), an analog IC, a radio frequency integrated circuit, a mixed signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, or the like. The processor and the transceiver can also be manufactured by various IC process technologies, such as complementary metal oxide semiconductor (CMOS), n metal-oxide-semiconductor (NMOS), positive channel metal oxide semiconductor (PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), or the like.

[0719] The embodiments of the present application can divide the functions of the device according to the above method examples, for example, each function module can be divided according to each function, or two or more functions can be integrated in a management node or a terminal node. The above integrated module can be realized in the form of hardware or in the form of a software function module. It should be noted that the division of the modules in the embodiments of the present application is illustrative, and is only a logical function division. In actual implementation, another division method can be used.

[0720] Figure 19 A block diagram of a communication device provided by the embodiments of the present application is shown in the above. In the case of dividing each function module according to each function, the communication device 1300 can include a communication module 1301 and a processing module 1302. Illustratively, the communication device can be a management node or a terminal node, or a chip or other combination device or component having the above communication device function in the management node or the terminal node. When the communication device 1300 is a management node or a terminal node, the communication module 1301 can be a transceiver, which can include an antenna and a radio frequency circuit, etc. The processing module 1302 can be a processor (or processing circuit), for example, a baseband processor, which can include one or more CPUs. When the communication device 1300 is a device or component having the above function, the communication module 1301 can be a radio frequency unit; the processing module 1302 can be a processor (or processing circuit), for example, a baseband processor. When the communication device 1300 is a chip system, the communication module 1301 can be an input and output interface of a chip (for example, a baseband chip); the processing module 1302 can be a processor (or processing circuit) of the chip system, which can include one or more central processing units. It should be understood that the communication module 1301 in the embodiments of the present application can be realized by a transceiver or a transceiver related circuit component; the processing module 1302 can be realized by a processor or a processor related circuit component (or processing circuit).

[0721] In some examples, the communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: a module for obtaining a bit rearrangement version table, the bit rearrangement version table including an output bit sequence corresponding to each bit rearrangement version number under different QAMs, the different QAMs including 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; and a module for determining the output bit sequence according to the bit rearrangement version table.

[0722] The above module for obtaining a bit rearrangement version table can be the processing module 1302;

[0723] The above module for determining the output bit sequence according to the bit rearrangement version table can be the processing module 1302.

[0724] In combination with the above scheme, the module for determining the output bit sequence according to the bit rearrangement version table is specifically used for determining the output bit sequence according to the input bit sequence, the bit rearrangement version number and the bit rearrangement version table.

[0725] In some examples, the communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: a module for generating scheduling type indication information, the scheduling type indication information indicating a retransmission or initial transmission and retransmission hybrid transmission based on a first retransmission data unit, a channel bit sequence determined using a first encoding mode and a first redundancy version and a first bit rearrangement version, the first retransmission data unit being a transport block or a coded block group; a module for sending the scheduling type indication information; wherein the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number in the first QAM in the bit rearrangement version table, the first QAM being 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

[0726] The module for generating the scheduling type indication information described above can be the processing module 1302;

[0727] The module for sending the scheduling type indication information described above can be the communication module 1301;

[0728] In combination with the above scheme, the input bit sequence under 16QAM is b(4i), b(4i+1), b(4i+2), b(4i+3), b() representing a bit value, i representing the sequence number of the constellation symbol corresponding to the input bit sequence in the constellation diagram, b(4i), b(4i+2) being mapped to the real part of the constellation symbol, and b(4i+1), b(4i+3) being mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0729]

[0730] In combination with the above scheme, the input bit sequence under 64QAM is b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5), b() representing a bit value, i representing the sequence number of the constellation symbol corresponding to the input bit sequence in the constellation diagram, b(6i), b(6i+2), b(6i+4) being mapped to the real part of the constellation symbol, and b(6i+1), b(6i+3), b(6i+5) being mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0731]

[0732] In combination with the foregoing scheme, the input bit sequence under 256QAM is b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7), where b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(8i), b(8i+2), b(8i+4), b(8i+6) are mapped to the real part of the constellation symbol, and b(8i+1), b(8i+3), b(8i+5), b(8i+7) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0733]

[0734] In combination with the foregoing scheme, the input bit sequence under 1024QAM is b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9), where b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(10i), b(10i+2), b(10i+4), b(10i+6), b(10i+8) are mapped to the real part of the constellation symbol, and b(10i+1), b(10i+3), b(10i+5), b(10i+7), b(10i+9) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0735]

[0736] In combination with the foregoing scheme, the input bit sequence under 4096QAM is b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), b(12i+11), where b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(12i), b(12i+2), b(12i+4), b(12i+6), b(12i+8), b(12i+10) are mapped to the real part of the constellation symbol, and b(12i+1), b(12i+3), b(12i+5), b(12i+7), b(12i+9), b(12i+11) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0737]

[0738]

[0739] In combination with the above scheme, the constellation symbol is one symbol in a constellation diagram obtained by modulating and mapping the output bit sequence in the first bit rearrangement version.

[0740] In some examples, the communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: a module for obtaining a bit rearrangement version table, the bit rearrangement version table including an output bit sequence corresponding to each bit rearrangement version number in at least one QAM, the at least one QAM including at least one of 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM; and a module for determining the output bit sequence according to the bit rearrangement version table.

[0741] The module for obtaining the bit rearrangement version table described above can be the processing module 1302.

[0742] The module for determining the output bit sequence according to the bit rearrangement version table described above can be the processing module 1302.

[0743] In combination with the above scheme, the module for determining the output bit sequence according to the bit rearrangement version table is specifically configured to determine the output bit sequence according to the input bit sequence, the bit rearrangement version number, and the bit rearrangement version table.

[0744] In some examples, the communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: a module for generating bit rearrangement version information, the bit rearrangement version information indicating a first bit rearrangement version in a bit rearrangement version table; and a module for sending the bit rearrangement version information; wherein the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number in a first QAM, and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM, or 4096QAM.

[0745] The module for generating the bit rearrangement version information described above can be the processing module 1302.

[0746] The module for sending the bit rearrangement version information described above can be the communication module 1301.

[0747] In combination with the above scheme, the bit rearrangement version information is carried in scheduling type indication information, and the scheduling type indication information indicates hybrid transmission of retransmission or initial transmission retransmission based on a first retransmission data unit, determines a channel bit sequence of a first redundancy version and a first bit rearrangement version using a first encoding mode, and the first retransmission data unit is a transport block or a coded block group.

[0748] In combination with the above scheme, the bit rearrangement version information is bound to target information, and the target information is used to indicate a redundancy version number or a superframe number.

[0749] In combination with the above scheme, the bit rearrangement version information is carried in dynamic scheduling data control information, control signaling or a superframe header.

[0750] In combination with the above scheme, the input bit sequence under 16QAM is i1i2q1q2, i1, i2, q1 and q2 represent a bit value respectively, i1 and i2 are mapped to the real part of a constellation symbol, and q1 and q2 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a first bit rearrangement version number, and the output bit sequence corresponding to the first bit rearrangement version number is i1i2q1q2.

[0751] In combination with the above scheme, the bit rearrangement version table further includes a second bit rearrangement version number, and the output bit sequence corresponding to the second bit rearrangement version number is

[0752] In combination with the above scheme, the bit rearrangement version table further includes a third bit rearrangement version number, and the output bit sequence corresponding to the third bit rearrangement version number is

[0753] In combination with the above scheme, the bit rearrangement version table further includes a fourth bit rearrangement version number, and the output bit sequence corresponding to the fourth bit rearrangement version number is i2i1q2q1.

[0754] In combination with the above scheme, the input bit sequence under 64QAM is i1i2i3q1q2q3, i1, i2, i3, q1, q2 and q3 represent a bit value respectively, i1, i2 and i3 are mapped to the real part of a constellation symbol, and q1, q2 and q3 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a fifth bit rearrangement version number, and the output bit sequence corresponding to the fifth bit rearrangement version number is i1i2i3q1q2q3.

[0755] In combination with the above scheme, the bit rearrangement version table further includes a sixth bit rearrangement version number, and the output bit sequence corresponding to the sixth bit rearrangement version number is

[0756] In combination with the above scheme, the bit rearrangement version table further includes a seventh bit rearrangement version number, and the output bit sequence corresponding to the seventh bit rearrangement version number is

[0757] In combination with the above scheme, the bit rearrangement version table further includes an eighth bit rearrangement version number, and the output bit sequence corresponding to the eighth bit rearrangement version number is

[0758] In combination with the foregoing scheme, the input bit sequence under 256QAM is i1i2i3i4q1q2q3q4, i1, i2, i3, i4, q1, q2, q3, and q4 represent a bit value respectively, i1, i2, i3, i4 are mapped to the real part of the constellation symbol, and q1, q2, q3, q4 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a ninth bit rearrangement version number, and the output bit sequence corresponding to the ninth bit rearrangement version number is i1i2i3i4q1q2q3q4.

[0759] In combination with the foregoing scheme, the bit rearrangement version table further includes a tenth bit rearrangement version number, and the output bit sequence corresponding to the tenth bit rearrangement version number is

[0760] In combination with the foregoing Scheme the bit rearrangement version table further includes an eleventh bit rearrangement version number, and the output bit sequence corresponding to the eleventh bit rearrangement version number is

[0761] In combination with the foregoing scheme, the bit rearrangement version table further includes a twelfth bit rearrangement version number, and the output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

[0762] In combination with the foregoing scheme, the input bit sequence under 1024QAM is i1i2i3i4i5q1q2q3q4q5, i1, i2, i3, i4, i5, q1, q2, q3, q4, and q5 represent a bit value respectively, i1, i2, i3, i4, i5 are mapped to the real part of the constellation symbol, and q1, q2, q3, q4, q5 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a thirteenth bit rearrangement version number, and the output bit sequence corresponding to the thirteenth bit rearrangement version number is i1i2i3i4i5q1q2q3q4q5.

[0763] In combination with the foregoing scheme, the bit rearrangement version table further includes a fourteenth bit rearrangement version number, and the output bit sequence corresponding to the fourteenth bit rearrangement version number is i5i4i3i2i1q5q4q3q2q1.

[0764] In combination with the foregoing Figure 19 the bit rearrangement version table further includes a fifteenth bit rearrangement version number, and the output bit sequence corresponding to the fifteenth bit rearrangement version number is

[0765] In combination with the foregoing scheme, the bit rearrangement version table further includes a sixteenth bit rearrangement version number, and the output bit sequence corresponding to the sixteenth bit rearrangement version number is

[0766] In combination with the foregoing scheme, the input bit sequence under 4096QAM is i1i2i3i4i5i6q1q2q3q4q5q6, i1, i2, i3, i4, i5, i6, q1, q2, q3, q4, q5, and q6 represent a bit value respectively, i1, i2, i3, i4, i5, i6 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4, q5, q6 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a seventeenth bit rearrangement version number, and the output bit sequence corresponding to the seventeenth bit rearrangement version number is i1i2i3i4i5i6q1q2q3q4q5q6.

[0767] In combination with the foregoing scheme, the bit rearrangement version table further includes an eighteenth bit rearrangement version number, and the output bit sequence corresponding to the eighteenth bit rearrangement version number is i6i5i4i3i2i1q6q5q4q3q2q1.

[0768] In combination with the foregoing scheme ， The bit rearrangement version table further includes a nineteenth bit rearrangement version number, and the output bit sequence corresponding to the nineteenth bit rearrangement version number is

[0769] In combination with the foregoing scheme, the bit rearrangement version table further includes a twentieth bit rearrangement version number, and the output bit sequence corresponding to the twentieth bit rearrangement version number is i4i2i5i3i1i6q4q2q5q3q1q6.

[0770] In combination with the foregoing scheme, the communication device is further configured to modulate and map the output bit sequence in the first bit rearrangement version to obtain a constellation symbol in a constellation diagram.

[0771] In some examples, the communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: a module for obtaining a bit rearrangement version table, the bit rearrangement version table including output bit sequences corresponding to respective bit rearrangement version numbers under different QAMs, the different QAMs including 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM; and a module for determining an input bit sequence according to the bit rearrangement version table.

[0772] The module for obtaining the bit rearrangement version table described above can be the processing module 1302.

[0773] The module for determining the input bit sequence according to the bit rearrangement version table described above can be the processing module 1302.

[0774] In combination with the foregoing scheme, the module for determining the input bit sequence according to the bit rearrangement version table is specifically configured to: determine the input bit sequence according to the output bit sequence, the bit rearrangement version number, and the bit rearrangement version table.

[0775] In some examples, the communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: a module for receiving scheduling type indication information, the scheduling type indication information indicating a retransmission based on a first retransmission data unit or a hybrid transmission of initial transmission and retransmission, a channel bit sequence determined in a first encoding mode, the first retransmission data unit being a transmission block or a coded block group; a module for decoding and de-bit rearranging the channel bit sequence according to the scheduling type indication information; wherein the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number in the first QAM in the bit rearrangement version table, the first QAM being 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

[0776] The module for receiving scheduling type indication information described above can be the communication module 1301.

[0777] The module for decoding and de-bit rearranging the channel bit sequence according to the scheduling type indication information described above can be the processing module 1302.

[0778] In combination with the above scheme, the input bit sequence under 16QAM is b(4i), b(4i+1), b(4i+2), b(4i+3), b() representing a bit value, i representing the serial number of the constellation symbol corresponding to the input bit sequence in the constellation diagram, b(4i), b(4i+2) being mapped to the real part of the constellation symbol, and b(4i+1), b(4i+3) being mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0779]

[0780] In combination with the above scheme, the input bit sequence under 64QAM is b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5), b() representing a bit value, i representing the serial number of the constellation symbol corresponding to the input bit sequence in the constellation diagram, b(6i), b(6i+2), b(6i+4) being mapped to the real part of the constellation symbol, and b(6i+1), b(6i+3), b(6i+5) being mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0781]

[0782] In combination with the above scheme, the input bit sequence under 256QAM is b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7), b() represents a bit value, i represents the sequence number of the constellation symbol corresponding to the input bit sequence in the constellation diagram, b(8i), b(8i+2), b(8i+4), b(8i+6) are mapped to the real part of the constellation symbol, and b(8i+1), b(8i+3), b(8i+5), b(8i+7) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0783]

[0784] In combination with the above scheme, the input bit sequence under 1024QAM is b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9), b() represents a bit value, i represents the sequence number of the constellation symbol corresponding to the input bit sequence in the constellation diagram, b(10i), b(10i+2), b(10i+4), b(10i+6), b(10i+8) are mapped to the real part of the constellation symbol, and b(10i+1), b(10i+3), b(10i+5), b(10i+7), b(10i+9) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0785]

[0786] In combination with the above scheme, the input bit sequence under 4096QAM is b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), b(12i+11), b() represents a bit value, i represents the sequence number of the constellation symbol corresponding to the input bit sequence in the constellation diagram, b(12i), b(12i+2), b(12i+4), b(12i+6), b(12i+8), b(12i+10) are mapped to the real part of the constellation symbol, and b(12i+1), b(12i+3), b(12i+5), b(12i+7), b(12i+9), b(12i+11) are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes:

[0787]

[0788] In combination with the foregoing scheme, the constellation symbol is one symbol in a constellation diagram obtained by modulating and mapping the output bit sequence in the first bit rearrangement version.

[0789] In some examples, the communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: a module for obtaining a bit rearrangement version table, the bit rearrangement version table including an output bit sequence corresponding to each bit rearrangement version number in at least one QAM, the at least one QAM including at least one of 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM; and a module for determining an input bit sequence according to the bit rearrangement version table.

[0790] The module for obtaining the bit rearrangement version table described above can be the processing module 1302.

[0791] The module for determining the input bit sequence according to the bit rearrangement version table described above can be the processing module 1302.

[0792] In combination with the foregoing scheme, the module for determining the input bit sequence according to the bit rearrangement version table is specifically configured to: determine the input bit sequence according to the output bit sequence, the bit rearrangement version number, and the bit rearrangement version table.

[0793] In some examples, the communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: a module for receiving bit rearrangement version information, the bit rearrangement version information indicating a first bit rearrangement version in a bit rearrangement version table; and a module for performing bit rearrangement according to the bit rearrangement version information; wherein the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number in a first QAM, and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM, or 4096QAM.

[0794] The module for receiving the bit rearrangement version information described above can be the communication module 1301.

[0795] The module for performing bit rearrangement according to the bit rearrangement version information described above can be the processing module 1302.

[0796] In combination with the foregoing scheme, the bit rearrangement version information is carried in scheduling type indication information; wherein the scheduling type indication information indicates hybrid transmission of retransmission or initial transmission retransmission based on a first retransmission data unit, and the channel bit sequence of the first redundancy version and the first bit rearrangement version is determined using a first encoding mode, and the first retransmission data unit is a transport block or a coded block group.

[0797] In combination with the foregoing scheme, the bit rearrangement version information is bound to target information, and the target information is used to indicate a redundancy version number or a superframe number.

[0798] In combination with the above scheme, the bit rearrangement version information is carried in dynamic scheduling data control information, control signaling or a superframe header.

[0799] In combination with the above scheme, the input bit sequence under 16QAM is i1i2q1q2, i1, i2, q1 and q2 represent a bit value respectively, i1 and i2 are mapped to the real part of a constellation symbol, and q1 and q2 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a first bit rearrangement version number, and the output bit sequence corresponding to the first bit rearrangement version number is i1i2q1q2.

[0800] In combination with the above scheme, the bit rearrangement version table further includes a second bit rearrangement version number, and the output bit sequence corresponding to the second bit rearrangement version number is

[0801] In combination with the above scheme, the bit rearrangement version table further includes a third bit rearrangement version number, and the output bit sequence corresponding to the third bit rearrangement version number is

[0802] In combination with the above scheme, the bit rearrangement version table further includes a fourth bit rearrangement version number, and the output bit sequence corresponding to the fourth bit rearrangement version number is i2i1q2q1.

[0803] In combination with the above scheme, the input bit sequence under 64QAM is i1i2i3q1q2q3, i1, i2, i3, q1, q2 and q3 represent a bit value respectively, i1, i2 and i3 are mapped to the real part of a constellation symbol, and q1, q2 and q3 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a fifth bit rearrangement version number, and the output bit sequence corresponding to the fifth bit rearrangement version number is i1i2i3q1q2q3.

[0804] In combination with the above scheme, the bit rearrangement version table further includes a sixth bit rearrangement version number, and the output bit sequence corresponding to the sixth bit rearrangement version number is

[0805] In combination with the above scheme, the bit rearrangement version table further includes a seventh bit rearrangement version number, and the output bit sequence corresponding to the seventh bit rearrangement version number is

[0806] In combination with the above scheme, the bit rearrangement version table further includes an eighth bit rearrangement version number, and the output bit sequence corresponding to the eighth bit rearrangement version number is

[0807] In combination with the foregoing scheme, the input bit sequence under 256QAM is i1i2i3i4q1q2q3q4, i1, i2, i3, i4, q1, q2, q3, and q4 represent a bit value respectively, i1, i2, i3, and i4 are mapped to the real part of the constellation symbol, and q1, q2, q3, and q4 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a ninth bit rearrangement version number, and the output bit sequence corresponding to the ninth bit rearrangement version number is i1i2i3i4q1q2q3q4.

[0808] In combination with the foregoing scheme, the bit rearrangement version table further includes a tenth bit rearrangement version number, and the output bit sequence corresponding to the tenth bit rearrangement version number is

[0809] In combination with the foregoing scheme, the bit rearrangement version table further includes an eleventh bit rearrangement version number, and the output bit sequence corresponding to the eleventh bit rearrangement version number is

[0810] In combination with the foregoing scheme, the bit rearrangement version table further includes a twelfth bit rearrangement version number, and the output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

[0811] In combination with the foregoing scheme, the input bit sequence under 1024QAM is i1i2i3i4i5q1q2q3q4q5, i1, i2, i3, i4, i5, q1, q2, q3, q4, and q5 represent a bit value respectively, i1, i2, i3, i4, and i5 are mapped to the real part of the constellation symbol, and q1, q2, q3, q4, and q5 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a thirteenth bit rearrangement version number, and the output bit sequence corresponding to the thirteenth bit rearrangement version number is i1i2i3i4i5q1q2q3q4q5.

[0812] In combination with the foregoing scheme, the bit rearrangement version table further includes a fourteenth bit rearrangement version number, and the output bit sequence corresponding to the fourteenth bit rearrangement version number is i5i4i3i2i1q5q4q3q2q1.

[0813] In combination with the foregoing scheme, the bit rearrangement version table further includes a fifteenth bit rearrangement version number, and the output bit sequence corresponding to the fifteenth bit rearrangement version number is

[0814] In combination with the foregoing scheme, the bit rearrangement version table further includes a sixteenth bit rearrangement version number, and the output bit sequence corresponding to the sixteenth bit rearrangement version number is

[0815] In combination with the above scheme, the input bit sequence under 4096QAM is i1i2i3i4i5i6q1q2q3q4q5q6, i1, i2, i3, i4, i5, i6, q1, q2, q3, q4, q5, and q6 represent a bit value respectively, i1, i2, i3, i4, i5, i6 are mapped to the real part of the constellation symbol, and q1, q2, q3, q4, q5, q6 are mapped to the imaginary part of the constellation symbol; the bit rearrangement version table includes a seventeenth bit rearrangement version number, and the output bit sequence corresponding to the seventeenth bit rearrangement version number is i1i2i3i4i5i6q1q2q3q4q5q6.

[0816] In combination with the above scheme, the bit rearrangement version table further includes an eighteenth bit rearrangement version number, and the output bit sequence corresponding to the eighteenth bit rearrangement version number is i6i5i4i3i2i1q6q5q4q3q2q1.

[0817] In combination with the above scheme, the bit rearrangement version table further includes a nineteenth bit rearrangement version number, and the output bit sequence corresponding to the nineteenth bit rearrangement version number is

[0818] In combination with the above scheme, the communication device further includes a Bluetooth module for implementing Bluetooth signal transmission and / or a WiFi module for implementing WiFi signal transmission, and one or more of the star flash module, the Bluetooth module, or the WiFi module share at least one of the following: an RF unit, a modem unit, a MAC unit, a CPU.

[0819] In combination with the above scheme, the star flash module and the WiFi module for implementing WiFi signal transmission are located in different subsystems of the communication device, and the subsystem of the star flash module and the subsystem of the WiFi module are integrated with at least one of the following in the communication device: a Bluetooth system, an SLE system, a GNSS, an always-on system, a PMU, a CMU, a flash memory, an application system, an audio system.

[0820] In combination with the above scheme, the star flash module and the WiFi module for implementing WiFi signal transmission are located in the same subsystem of the communication device, and the subsystem of the star flash module and the WiFi module are integrated with at least one of the following in the communication device: a Bluetooth system, an SLE system, a GNSS, an always-on system, a PMU, a CMU, a flash memory, an application system, an audio system.

[0821] In combination with the above scheme, the communication device further includes a Bluetooth module for implementing Bluetooth signal transmission and / or a WiFi module for implementing WiFi signal transmission, and at least one of the Bluetooth module or the WiFi module coexists with the star flash module through different antennas, and the coexistence strategy includes at least one of the following: frequency division multiplexing, code division multiplexing, time division multiplexing, channel avoidance, or aggregated scheduling.

[0822] In combination with the above scheme, the communication device further comprises a Bluetooth module for implementing Bluetooth signal transmission and / or a WiFi module for implementing WiFi signal transmission, at least one of the Bluetooth module or the WiFi module coexists with the star flash module through the same antenna, and the coexistence strategy comprises at least one of the following: frequency division multiplexing, code division multiplexing, time division multiplexing, software static strategy or PTA strategy.

[0823] The communication module 1301 and the processing module 1302 in the embodiments of the present application can be simultaneously deployed in the star flash module, the Bluetooth module or the WiFi module; or the communication module 1301 in the embodiments of the present application can be deployed in the star flash module, the Bluetooth module or the WiFi module, and the processing module 1302 in the embodiments of the present application can be deployed in other modules outside the star flash module, the Bluetooth module or the WiFi module; or the processing module 1302 in the embodiments of the present application can be deployed in the star flash module, the Bluetooth module or the WiFi module, and the communication module 1301 in the embodiments of the present application can be deployed in other modules outside the star flash module, the Bluetooth module or the WiFi module, and the embodiments of the present application do not make specific limitations thereon.

[0824] As another implementable manner, Figure 18 The communication module 1301 in the embodiments of the present application can be replaced by Figure 19 The transceiver 1202 in the embodiments of the present application can replace the communication module 1301, and the transceiver 1202 can integrate the function of the communication module 1301; the processor 1207 can replace the processing module 1302, and the processor 1207 can integrate the function of the processing module 1302. Further, Figure 18 The communication device 1300 shown in FIG. 13 can further comprise a memory (not shown in the figure). When the communication module 1301 is replaced by the transceiver 1202, and the processing module 1302 is replaced by the processor 1207, the communication device 1300 involved in the embodiments of the present application can be the electronic device 1200 shown in FIG. 12. Figure 20 The communication device 1300 shown in FIG. 13 can further comprise a memory (not shown in the figure). When the communication module 1301 is replaced by the transceiver 1202, and the processing module 1302 is replaced by the processor 1207, the communication device 1300 involved in the embodiments of the present application can be the electronic device 1200 shown in FIG. 12.

[0825] The scheme provided in the embodiments of the present application is applicable to at least one of Bluetooth (BT) communication, sparklink or nearlink communication, WIFI communication and the like. In the embodiments of the present application, BT and Bluetooth Low Energy (BLE) can be used to refer to each other. The sparklink can include at least one of sparklink low energy (SLE), sparklink basic (SLB) or sparklink position (SLP). In the embodiments of the present application, the sparklink can be used to refer to the sparklink low energy (SLE), the sparklink basic (SLB) or the sparklink position (SLP) to each other.

[0826] Some embodiments of the scheme provided in the present application are introduced below.

[0827] Embodiment one:

[0828] Bluetooth (BT), WIFI and sparklink can use 2.4 GHz or 5 GHz frequency bands, have similarities, and part of the modules can be multiplexed, so that the chip cost, area and power consumption can be saved. Chip resources can be highly multiplexed, and multiple chips can be quickly iterated.

[0829] WIFI and SLB can share a set of radio frequency architecture and paths. As shown in Figure 20 , it is a chip architecture schematic diagram provided in the embodiments of the present application. It can be known from Figure 21 that the central processing unit (CPU), the radio frequency (RF) unit, the analog baseband (ABB) unit or the Modem resource sharing can be realized by design, the media access control (MAC) layer part module is multiplexed, and the purpose of saving chip area, reducing chip cost and power consumption is achieved.

[0830] As shown in Figure 21 , it is another chip architecture schematic diagram provided in the embodiments of the present application. It can be known from Figure 22 that the MAC units of BT, SLB and wireless fidelity (WiFi) are respectively independently realized, and the RF units and Modem units of each mode are all shared.

[0831] As shown in Figure 22 , another chip architecture schematic diagram provided by the embodiment of the present application is shown. As can be seen from Figure 23 , the MAC units of BT, SLB and WiFi are independently implemented, the Modems of BT, SLB and WiFi are also independently implemented, and the RF units of each mode are all shared.

[0832] As shown in Figure 23 , another chip architecture schematic diagram provided by the embodiment of the present application is shown. As can be seen from Figure 24 , the MAC units of BT, SLB and WiFi are independently implemented, the Modems of some modes such as WiFi and SLB are shared, the Modems of other modes such as BT are independently implemented, and the RF units of each mode are all shared.

[0833] Embodiment two

[0834] The star flash chip can adopt 14 / 28 / 40nm process, use chip size package (CSP), ball grid array (BGA), quad flat no-lead (QFN) and the like packaging, and adopt built-in or external flash memory. According to the application scene, at least one of the power management unit (PMU), clock management unit (CMU), active optical network (AON), wireless local area network (WLAN) or BT, star flash, global navigation satellite system (GNSS), application (APP), audio and the like subsystems can be placed on a chip to realize area minimization, function maximization, and also improve performance and reliability.

[0835] The embodiment of the present application provides a chip design method, and the star flash subsystem and other subsystems are integrated on a chip. According to different products, the subsystems of the chip can be cut and combined, and different subsystems are connected through a bus.

[0836] As shown in Figure 24 , a chip module framework schematic diagram provided by the embodiment of the present application is shown. As can be seen from Figure 25It is understood that for products requiring BT or GNSS functional modules, and simultaneously needing to connect to WIFI and satellite flash devices, WIFI and SLB can be separated into different systems, and then combined with at least one of the following on a single chip: BT System, SLE System, GNSS System, Always On System, PMU, CMU, Flash memory, APP System, and Audio System. Different subsystems are connected via a bus.

[0837] like Figure 25 The diagram shown is a schematic representation of another chip module framework provided in an embodiment of this application. Figure 26 It is known that, in some embodiments, in order to save area and cost, WIFI and SLB can be combined into one subsystem, and then combined with at least one of BTSystem, SLE System, GNSS System, Always On System, PMU, CMU, Flash memory, APPSystem, Audio System, etc. on a single chip, with different subsystems connected to each other via a bus.

[0838] Example 3:

[0839] The WiFi / SLB 2.4GHz band operates in the 2412–2472MHz range, while the BT / BLE / SLE band operates in the 2402–2480MHz range, which may cause mutual interference. Within the same core, SLB and WiFi can allocate service time slots through software scheduling; however, there is a lack of unified scheduling for SLB and WiFi / BT / BLE / SLE on different cores.

[0840] This application provides a communication coexistence scheme for SLB / WIFI / SLE / BT / BLE. Based on whether SLB and WIFI / SLE / BT / BLE share an antenna, the coexistence scenario is divided into coexistence with different antennas (using different antennas) and coexistence with the same antenna (using the same antenna), and different coexistence strategies are given.

[0841] For the coexistence of different antennas, if SLB and Wi-Fi coexist, it can be ensured that the transmit and receive frequencies of SLB and Wi-Fi are different (i.e., frequency division multiplexing). The software can handle this from the aspects of code division multiplexing, service cycle, and interval (i.e., frequency division multiplexing). If SLB and SLE / BT / BLE coexist, and the isolation requirement cannot be met, it is necessary to avoid the channels where SLE / BT / BLE is located (i.e., channel avoidance) to reduce the impact of SLE / BT / BLE. At the same time, an aggregation scheduling mechanism can be added to aggregate and centrally send SLE / BT / BLE data packets (i.e., aggregation scheduling) to reduce the probability of interference from SLE / BT / BLE.

[0842] For shared antenna coexistence, software static strategies or hardware arbitration time-division strategies (such as packet traffic arbitration, PTA) can be used. Frequency division multiplexing, code division multiplexing, and time division multiplexing can also be employed. The advantages of software static strategies are: low hardware requirements, minimal software modifications, and no dynamic radio frequency (RF) switching (such as RF recovery). The advantages of PTA strategies are: faster service state switching and finer granularity of switching time. Packet traffic arbitration (PTA) can also be called data packet traffic arbitration.

[0843] Taking the coexistence of SLB and SLE / BT / BLE as an example, such as Figure 26 The diagram shown is a framework illustration of a software static strategy provided in an embodiment of this application. Figure 27 As can be seen, the software static strategy can include: after SLB starts, the software configures the host to notify SLE / BT / BLE to exit the current RF path. In this scenario, SLE / BT / BLE can check the SLB startup flag, and the software can be configured to switch from the current RF path to another RF path. The chip needs to support software-configured switching.

[0844] Taking the coexistence of SLB and WIFI as an example, such as Figure 27 The diagram shown is a framework illustration of a software static strategy provided in an embodiment of this application. Figure 28 As can be seen, the software static strategy can include: after the SLB starts, the software configures the host to notify the Wi-Fi to exit the current RF path. In this scenario, the Wi-Fi can check the SLB startup flag, and the software can be configured to switch from the current RF path to another RF path. The chip needs to support software-configured switching.

[0845] For example, such as Figure 9As shown, a frame diagram of a packet transmission arbitration (PTA) strategy provided by an embodiment of the present application is shown. The PTA can use an arbitrator to determine whether one or more of SLB / WIFI / SLE / BT / BLE uses a radio frequency (RF) and the RF occupancy. For example, if the SLB needs to use the RF, the SLB can request access to the arbitrator, and the arbitrator can determine whether the SLB is allowed to occupy the RF according to the access request of the SLB, the access strategy, and the actual occupancy. The architecture of the PTA can use a two-line architecture, a three-line architecture, or a four-line architecture, etc. The specific design and configuration can be determined according to the business situation. By ​ As can be seen, the packet transmission arbitration (PTA) strategy includes time division of any combination of transmission (TX) and reception (RX) of each party in SLB / WIFI / SLE / BT / BLE. The PTA module can deliver the occupancy of the radio frequency channel to each party respectively, and use different level signals to represent that the radio frequency channel is occupied by one or more of SLB / WIFI / SLE / BT / BLE respectively. The software or hardware is notified of the corresponding processing through the level signal. Different businesses can also set different PTA priorities, and the business with a high priority can preempt the air interface resource.

[0846] According to the method provided by the embodiment of the present application, the present application also provides a computer program product, which includes computer program code. When the computer program code runs on the computer, the computer executes the method according to any of the embodiments of the present application.

[0847] The embodiments of the present application further provide a computer readable storage medium. All or part of the processes in the above method embodiments can be executed by a computer or a device with communication capability to execute computer programs or instructions to control relevant hardware to complete, and the computer programs or the set of instructions can be stored in the computer readable storage medium. When executed, the computer programs or the set of instructions can include the processes of the above method embodiments. The computer readable storage medium can be an internal storage unit of the management node or the terminal node of any of the preceding embodiments, such as a hard disk or a memory of the management node or the terminal node. The computer readable storage medium can also be an external storage device of the management node or the terminal node, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the management node or the terminal node. Further, the computer readable storage medium can include both the internal storage unit and the external storage device of the management node or the terminal node. The computer readable storage medium is used to store the computer programs or instructions and other programs and data required by the management node or the terminal node. The computer readable storage medium can also be used to temporarily store data that has been output or will be output.

[0848] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0849] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working process of the device described above can refer to the corresponding process in the preceding method embodiments, which will not be described here.

[0850] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. In actual implementation, another division mode can be used. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0851] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0852] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit.

[0853] If the functions are realized in the form of software functional units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the part of the prior art that essentially contributes to the prior art or the part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, and various program code storage media.

[0854] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A communication method characterized by comprising: The method comprises: acquiring a bit rearrangement version table, the bit rearrangement version table comprising output bit sequences corresponding to respective bit rearrangement version numbers under different quadrature amplitude modulation (QAM), the different QAM comprising 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; determining an output bit sequence according to the bit rearrangement version table.

2. The method of claim 1, wherein, The determining of the output bit sequence according to the bit rearrangement version table comprises: determining the output bit sequence according to an input bit sequence, a bit rearrangement version number and the bit rearrangement version table.

3. A communication method characterized by comprising: The method comprises: generating scheduling type indication information, the scheduling type indication information indicating that a first redundancy version and a channel bit sequence of a first bit rearrangement version are determined using a first encoding mode based on retransmission or initial transmission retransmission hybrid transmission of a first retransmission data unit, the first retransmission data unit being a transport block or a code block group; sending the scheduling type indication information; wherein the first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number under a first quadrature amplitude modulation (QAM) in a bit rearrangement version table, the first QAM being 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

4. The method according to any one of claims 1 to 3, characterized in that, The input bit sequence under the 16QAM is b(4i), b(4i+1), b(4i+2), b(4i+3), b() representing a bit value, i representing a sequence number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(4i), b(4i+2) being mapped to a real part of the constellation symbol, and b(4i+1), b(4i+3) being mapped to an imaginary part of the constellation symbol. The bit rearrangement version table comprises:

5. The method according to any one of claims 1 to 4, characterized in that, The input bit sequence under the 64QAM is b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5), b() representing a bit value, i representing a sequence number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(6i), b(6i+2), b(6i+4) being mapped to a real part of the constellation symbol, and b(6i+1), b(6i+3), b(6i+5) being mapped to an imaginary part of the constellation symbol. The bit rearrangement version table comprises:

6. The method according to any one of claims 1 to 5, characterized in that, The input bit sequence under the 256QAM is b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7), b() representing a bit value, i representing a sequence number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(8i), b(8i+2), b(8i+4), b(8i+6) being mapped to a real part of the constellation symbol, and b(8i+1), b(8i+3), b(8i+5), b(8i+7) being mapped to an imaginary part of the constellation symbol. The bit rearrangement version table comprises:

7. The method according to any one of claims 1 to 6, characterized in that, The input bit sequence under the 1024QAM is b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9), b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in the constellation diagram, b(10i), b(10i+2), b(10i+4), b(10i+6), b(10i+8) are mapped to the real part of the constellation symbol, and b(10i+1), b(10i+3), b(10i+5), b(10i+7), b(10i+9) are mapped to the imaginary part of the constellation symbol; The bit rearrangement version table comprises:

8. The method according to any one of claims 1 to 7, characterized in that, The input bit sequence under the 4096QAM is b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), b(12i+11), b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in the constellation diagram, b(12i), b(12i+2), b(12i+4), b(12i+6), b(12i+8), b(12i+10) are mapped to the real part of the constellation symbol, and b(12i+1), b(12i+3), b(12i+5), b(12i+7), b(12i+9), b(12i+11) are mapped to the imaginary part of the constellation symbol; The bit rearrangement version table comprises:

9. The method according to any one of claims 4 to 8, characterized in that, The constellation symbol is a symbol in a constellation diagram obtained by modulating and mapping the output bit sequence in the first bit rearrangement version.

10. A communication method characterized by comprising: The method comprises: Obtaining a bit rearrangement version table, the bit rearrangement version table comprising an output bit sequence corresponding to each bit rearrangement version number under at least one quadrature amplitude modulation (QAM), the at least one QAM comprising at least one of 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; Determining an output bit sequence according to the bit rearrangement version table.

11. The method of claim 11, wherein, The determining of the output bit sequence according to the bit rearrangement version table comprises: Determining an output bit sequence according to an input bit sequence, a bit rearrangement version number and the bit rearrangement version table.

12. A communication method, comprising: The method comprises: Generating bit rearrangement version information, the bit rearrangement version information indicating a first bit rearrangement version in a bit rearrangement version table; Sending the bit rearrangement version information; The first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number under a first quadrature amplitude modulation (QAM), and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

13. The method of claim 12, wherein, The bit rearrangement version information is carried in scheduling type indication information. The scheduling type indication information indicates a first retransmission data unit based retransmission or initial transmission retransmission hybrid transmission, and a first encoding mode is used to determine a first redundancy version and a first bit rearrangement version of a channel bit sequence.

14. The method of claim 12, wherein, The bit rearrangement version information is bound to target information, and the target information is used to indicate a redundancy version number or a superframe number.

15. The method of claim 12, wherein, The bit rearrangement version information is carried in dynamic scheduling data control information, control signaling or a superframe header.

16. The method according to any one of claims 10 to 15, characterized in that, The input bit sequence under the 16QAM is i1i2q1q2, i1, i2, q1 and q2 represent a bit value respectively, i1 and i2 are mapped to the real part of a constellation symbol, and q1 and q2 are mapped to the imaginary part of the constellation symbol. The bit rearrangement version table further includes a fourth bit rearrangement version number, and the output bit sequence corresponding to the fourth bit rearrangement version number is i2i1q2q1.

17. The method of claim 16, wherein, The bit rearrangement version table further comprises a second bit rearrangement version number, and the output bit sequence corresponding to the second bit rearrangement version number is 18. The method according to claim 16 or 17, characterized in that, The bit rearrangement version table further comprises a third bit rearrangement version number, and a corresponding output bit sequence of the third bit rearrangement version number is 19. The method of any one of claims 16-18, wherein, The input bit sequence under the 64QAM is i1i2i3q1q2q3, i1, i2, i3, q1, q2 and q3 represent a bit value respectively, i1, i2 and i3 are mapped to the real part of a constellation symbol, and q1, q2 and q3 are mapped to the imaginary part of the constellation symbol.

20. The method according to any one of claims 10 to 19, characterized in that, The bit rearrangement version table further includes a fourth bit rearrangement version number, and the output bit sequence corresponding to the fourth bit rearrangement version number is i2i1q2q1. The input bit sequence under the 256QAM is i1i2i3i4q1q2q3q4, i1, i2, i3, i4, q1, q2, q3 and q4 represent a bit value respectively, i1, i2, i3 and i4 are mapped to the real part of a constellation symbol, and q1, q2, q3 and q4 are mapped to the imaginary part of the constellation symbol.

21. The method of claim 20, wherein, The bit rearrangement version table further comprises a sixth bit rearrangement version number, and the output bit sequence corresponding to the sixth bit rearrangement version number is 22. The method of claim 20 or 21, wherein, The bit rearrangement version table further comprises a seventh bit rearrangement version number, and the output bit sequence corresponding to the seventh bit rearrangement version number is 23. The method of any one of claims 20-22, wherein, The bit rearrangement version table further comprises an eighth bit rearrangement version number, the output bit sequence corresponding to the eighth bit rearrangement version number is 24. The method of any one of claims 10-23, wherein, The bit rearrangement version table further includes a twelfth bit rearrangement version number, and the output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4. The input bit sequence under the 1024QAM is i1i2i3i4i5q1q2q3q4q5, i1, i2, i3, i4, i5, q1, q2, q3, q4 and q5 represent a bit value respectively, i1, i2, i3, i4 and i5 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4 and q5 are mapped to the imaginary part of the constellation symbol.

25. The method of claim 24, wherein, The bit rearrangement version table further comprises a tenth bit rearrangement version number, and a corresponding output bit sequence of the tenth bit rearrangement version number is 26. The method of claim 24 or 25, wherein, The bit rearrangement version table further comprises an eleventh bit rearrangement version number, and a corresponding output bit sequence of the eleventh bit rearrangement version number is 27. The method of any one of claims 24-26, wherein, The bit rearrangement version table further includes a twelfth bit rearrangement version number, and the output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

28. The method of any one of claims 10-27, wherein, The bit rearrangement version table further includes a twelfth bit rearrangement version number, and the output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4. ​ 29. The method of claim 28, wherein, ​ 30. The method of claim 28 or 29, wherein, The bit rearrangement version table further comprises a fifteenth bit rearrangement version number, and a corresponding output bit sequence of the fifteenth bit rearrangement version number is 31. The method of any one of claims 28-30, wherein, The bit rearrangement version table further comprises a sixteenth bit rearrangement version number, and a corresponding output bit sequence of the sixteenth bit rearrangement version number is 32. The method of any one of claims 10-31, wherein, The input bit sequence under the 4096QAM is i1i2i3i4i5i6q1q2q3q4q5q6, i1, i2, i3, i4, i5, i6, q1, q2, q3, q4, q5, and q6 represent a bit value respectively, i1, i2, i3, i4, i5, i6 are mapped to the real part of the constellation symbol, and q1, q2, q3, q4, q5, q6 are mapped to the imaginary part of the constellation symbol; The bit rearrangement version table further includes an eighteenth bit rearrangement version number, and the output bit sequence corresponding to the eighteenth bit rearrangement version number is i6i5i4i3i2i1q6q5q4q3q2q1.

33. The method of claim 32, wherein, The bit rearrangement version table further includes a twentieth bit rearrangement version number, and the output bit sequence corresponding to the twentieth bit rearrangement version number is i4i2i5i3i1i6q4q2q5q3q1q6.

34. The method of claim 32 or 33, wherein, The bit rearrangement version table further comprises a nineteenth bit rearrangement version number, and a corresponding output bit sequence of the nineteenth bit rearrangement version number is 35. The method of any one of claims 32-34, wherein, 36. The method of any one of claims 10 to 35, further comprising: modulation mapping the output bit sequence in the first bit rearrangement version to obtain a constellation symbol in a constellation diagram. The method comprises:

37. A method of communication, the method comprising: obtaining a bit rearrangement version table, the bit rearrangement version table comprising output bit sequences corresponding to respective bit rearrangement version numbers under different quadrature amplitude modulation (QAM), the different QAM comprising 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM; determining an input bit sequence according to the bit rearrangement version table. The determining an input bit sequence according to the bit rearrangement version table comprises:

38. The method of claim 37, wherein, determining an input bit sequence according to an output bit sequence, a bit rearrangement version number, and the bit rearrangement version table. The method comprises:

39. A method of communication, comprising: receiving scheduling type indication information, the scheduling type indication information indicating that a first retransmission data unit is used for retransmission or initial transmission retransmission hybrid transmission, a first encoding mode is used to determine a first redundancy version and a channel bit sequence of a first bit rearrangement version, and the first retransmission data unit is a transport block or a code block group; decoding and de-bit rearranging the channel bit sequence according to the scheduling type indication information; The first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number under a first quadrature amplitude modulation (QAM) in a bit rearrangement version table, and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM, or 4096QAM. The input bit sequence under the 16QAM is b(4i), b(4i+1), b(4i+2), b(4i+3), b() represents a bit value, i represents the serial number of a constellation symbol corresponding to the input bit sequence in a constellation diagram, b(4i), b(4i+2) are mapped to the real part of the constellation symbol, and b(4i+1), b(4i+3) are mapped to the imaginary part of the constellation symbol.

40. The method of any one of claims 37-39, wherein, The bit rearrangement version table comprises: ​ 41. The method of any one of claims 37-40, wherein, The input bit sequence under the 64QAM is b(6i), b(6i+1), b(6i+2), b(6i+3), b(6i+4), b(6i+5), b() represents a bit value, i represents the serial number of the constellation symbol corresponding to the input bit sequence in the constellation, b(6i), b(6i+2), b(6i+4) are mapped to the real part of the constellation symbol, and b(6i+1), b(6i+3), b(6i+5) are mapped to the imaginary part of the constellation symbol; The bit rearrangement version table comprises:

42. The method of any one of claims 37-41, wherein, The input bit sequence under the 256QAM is b(8i), b(8i+1), b(8i+2), b(8i+3), b(8i+4), b(8i+5), b(8i+6), b(8i+7), b() represents a bit value, i represents the serial number of the constellation symbol corresponding to the input bit sequence in the constellation, b(8i), b(8i+2), b(8i+4), b(8i+6) are mapped to the real part of the constellation symbol, and b(8i+1), b(8i+3), b(8i+5), b(8i+7) are mapped to the imaginary part of the constellation symbol; The bit rearrangement version table comprises:

43. The method of any one of claims 37-42, wherein, The input bit sequence under the 1024QAM is b(10i), b(10i+1), b(10i+2), b(10i+3), b(10i+4), b(10i+5), b(10i+6), b(10i+7), b(10i+8), b(10i+9), b() represents a bit value, i represents the serial number of the constellation symbol corresponding to the input bit sequence in the constellation, b(10i), b(10i+2), b(10i+4), b(10i+6), b(10i+8) are mapped to the real part of the constellation symbol, and b(10i+1), b(10i+3), b(10i+5), b(10i+7), b(10i+9) are mapped to the imaginary part of the constellation symbol; The bit rearrangement version table comprises:

44. The method of any one of claims 37-43, wherein, The input bit sequence under the 4096QAM is b(12i), b(12i+1), b(12i+2), b(12i+3), b(12i+4), b(12i+5), b(12i+6), b(12i+7), b(12i+8), b(12i+9), b(12i+10), b(12i+11), b() represents a bit value, i represents the serial number of the constellation symbol corresponding to the input bit sequence in the constellation, b(12i), b(12i+2), b(12i+4), b(12i+6), b(12i+8), b(12i+10) are mapped to the real part of the constellation symbol, and b(12i+1), b(12i+3), b(12i+5), b(12i+7), b(12i+9), b(12i+11) are mapped to the imaginary part of the constellation symbol; The bit rearrangement version table comprises:

45. The method of any one of claims 40-44, wherein, The constellation symbol is a symbol in a constellation obtained by modulating and mapping the output bit sequence in the first bit rearrangement version.

46. A method of communication, the method comprising: The method comprises: acquiring a bit rearrangement version table, the bit rearrangement version table comprising an output bit sequence corresponding to each bit rearrangement version number under at least one quadrature amplitude modulation (QAM), the at least one QAM comprising at least one of 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; determining an input bit sequence according to the bit rearrangement version table.

47. The method of claim 46, wherein, The determination of the input bit sequence according to the bit rearrangement version table comprises: determining the input bit sequence according to the output bit sequence, the bit rearrangement version number and the bit rearrangement version table.

48. A method of communication, the method comprising: The method comprises: receiving bit rearrangement version information, the bit rearrangement version information indicating a first bit rearrangement version in a bit rearrangement version table; performing bit rearrangement according to the bit rearrangement version information; The first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number under a first quadrature amplitude modulation (QAM), and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

49. The method of claim 48, wherein, The bit rearrangement version information is carried in scheduling type indication information. The scheduling type indication information indicates that a first redundancy version and a first bit rearrangement version of a channel bit sequence are determined by using a first encoding mode based on retransmission or initial transmission retransmission hybrid transmission of a first retransmission data unit, and the first retransmission data unit is a transport block or a code block group.

50. The method of claim 48, wherein, The bit rearrangement version information is bound to target information, and the target information is used to indicate a redundancy version number or a superframe number.

51. The method of claim 48, wherein, The bit rearrangement version information is carried in dynamic scheduling data control information, control signaling or a superframe header.

52. The method of any one of claims 46-51, wherein, The input bit sequence under the 16QAM is i1i2q1q2, i1, i2, q1 and q2 represent a bit value respectively, i1 and i2 are mapped to the real part of a constellation symbol, and q1 and q2 are mapped to the imaginary part of the constellation symbol. The bit rearrangement version table comprises a first bit rearrangement version number, and the output bit sequence corresponding to the first bit rearrangement version number is i1i2q1q2.

53. The method of claim 52, wherein, The bit rearrangement version table further comprises a second bit rearrangement version number, and the output bit sequence corresponding to the second bit rearrangement version number is 54. The method of claim 52 or 53, wherein, The bit rearrangement version table further comprises a third bit rearrangement version number, and a corresponding output bit sequence of the third bit rearrangement version number is 55. The method of any one of claims 52-54, wherein, The bit rearrangement version table further comprises a fourth bit rearrangement version number, and the output bit sequence corresponding to the fourth bit rearrangement version number is i2i1q2q1.

56. The method of any one of claims 46-55, wherein, The input bit sequence under the 64QAM is i1i2i3q1q2q3, i1, i2, i3, q1, q2 and q3 represent a bit value respectively, i1, i2 and i3 are mapped to the real part of a constellation symbol, and q1, q2 and q3 are mapped to the imaginary part of the constellation symbol. The bit rearrangement version table comprises a fifth bit rearrangement version number, and the output bit sequence corresponding to the fifth bit rearrangement version number is i1i2i3q1q2q3.

57. The method of claim 56, wherein, The bit rearrangement version table further includes a sixth bit rearrangement version number, and a corresponding output bit sequence of the sixth bit rearrangement version number is 58. The method of claim 56 or 57, wherein, The bit rearrangement version table further comprises a seventh bit rearrangement version number, and the output bit sequence corresponding to the seventh bit rearrangement version number is 59. The method of any one of claims 56-58, wherein ， The bit rearrangement version table further comprises an eighth bit rearrangement version number, the output bit sequence corresponding to the eighth bit rearrangement version number is 60. The method of any one of claims 46-59, wherein, The input bit sequence under the 256QAM is i1i2i3i4q1q2q3q4, i1, i2, i3, i4, q1, q2, q3 and q4 represent a bit value respectively, i1, i2, i3 and i4 are mapped to the real part of a constellation symbol, and q1, q2, q3 and q4 are mapped to the imaginary part of the constellation symbol. The bit rearrangement version table further includes a twelfth bit rearrangement version number, and an output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

61. The method of claim 60, wherein, The bit rearrangement version table further comprises a tenth bit rearrangement version number, and the output bit sequence corresponding to the tenth bit rearrangement version number is 62. The method of claim 60 or 61, wherein, The bit rearrangement version table further comprises an eleventh bit rearrangement version number, and a corresponding output bit sequence of the eleventh bit rearrangement version number is 63. The method of any one of claims 60-62, wherein, The bit rearrangement version table further includes a twelfth bit rearrangement version number, and an output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

64. The method of any one of claims 46-63, wherein, The input bit sequence under the 1024QAM is i1i2i3i4i5q1q2q3q4q5, i1, i2, i3, i4, i5, q1, q2, q3, q4 and q5 represent a bit value respectively, i1, i2, i3, i4, i5 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4, q5 are mapped to the imaginary part of the constellation symbol. The bit rearrangement version table further includes a twelfth bit rearrangement version number, and an output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

65. The method of claim 64, wherein, The bit rearrangement version table further includes a twelfth bit rearrangement version number, and an output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

66. The method of claim 64 or 65, wherein, The bit rearrangement version table further comprises a fifteenth bit rearrangement version number, and a corresponding output bit sequence of the fifteenth bit rearrangement version number is 67. The method of any one of claims 64-66, wherein, The bit rearrangement version table further comprises a sixteenth bit rearrangement version number, and a corresponding output bit sequence of the sixteenth bit rearrangement version number is 68. The method of any one of claims 46-67, wherein, The input bit sequence under the 4096QAM is i1i2i3i4i5i6q1q2q3q4q5q6, i1, i2, i3, i4, i5, i6, q1, q2, q3, q4, q5 and q6 represent a bit value respectively, i1, i2, i3, i4, i5, i6 are mapped to the real part of a constellation symbol, and q1, q2, q3, q4, q5, q6 are mapped to the imaginary part of the constellation symbol. The bit rearrangement version table further includes a twelfth bit rearrangement version number, and an output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

69. The method of claim 68, wherein, The bit rearrangement version table further includes a twelfth bit rearrangement version number, and an output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

70. The method of claim 68 or 69, wherein, The bit rearrangement version table further comprises a nineteenth bit rearrangement version number, and a corresponding output bit sequence of the nineteenth bit rearrangement version number is 71. The method of any one of claims 68-70, wherein, The bit rearrangement version table further includes a twelfth bit rearrangement version number, and an output bit sequence corresponding to the twelfth bit rearrangement version number is i3i2i1i4q3q2q1q4.

72. A communications device, characterized by The communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: A module for obtaining a bit rearrangement version table, the bit rearrangement version table including output bit sequences corresponding to respective bit rearrangement version numbers under different quadrature amplitude modulation (QAM), and the different QAM including 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; A module for determining an output bit sequence according to the bit rearrangement version table.

73. The communication apparatus of claim 73, wherein The communication device is further configured to implement the method of claim 2.

74. A communications device, characterized by The communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: The module for generating scheduling type indication information, the scheduling type indication information indicates that the retransmission or initial transmission retransmission hybrid transmission based on the first retransmission data unit adopts the first encoding mode to determine the first redundancy version and the first bit rearrangement version of the channel bit sequence, and the first retransmission data unit is a transport block or a coded block group; The module for sending the scheduling type indication information; The first bit rearrangement version indicates the output bit sequence corresponding to a bit rearrangement version number of the first quadrature amplitude modulation (QAM) in a bit rearrangement version table, and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

75. The communication apparatus according to any one of claims 72-73, wherein, The communication device is also used to implement the method in any one of claims 4 to 9.

76. A communications device, characterized by The communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: The module for obtaining a bit rearrangement version table, the bit rearrangement version table includes output bit sequences corresponding to respective bit rearrangement version numbers of at least one quadrature amplitude modulation (QAM), and the at least one QAM includes at least one of 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; The module for determining an output bit sequence according to the bit rearrangement version table.

77. The communication apparatus of claim 76, wherein The communication device is also used to implement the method in claim 11.

78. A communications device, characterized by The communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: The module for generating bit rearrangement version information, the bit rearrangement version information indicates a first bit rearrangement version in a bit rearrangement version table; The module for sending the bit rearrangement version information; The first bit rearrangement version indicates an output bit sequence corresponding to a bit rearrangement version number of the first quadrature amplitude modulation (QAM), and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM or 4096QAM.

79. The communication apparatus of claim 78, wherein, The communication device is also used to implement the method in any one of claims 13 to 15.

80. The communication apparatus according to any of claims 76-79, wherein, The communication device is also used to implement the method in any one of claims 16 to 36.

81. A communications device, characterized by The communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: The module for obtaining a bit rearrangement version table, the bit rearrangement version table includes output bit sequences corresponding to respective bit rearrangement version numbers of different quadrature amplitude modulations (QAM), and the different QAM includes 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM; The module for determining an input bit sequence according to the bit rearrangement version table.

82. The communication apparatus of claim 81, wherein The communication device is also used to implement the method in claim 38.

83. A communications device, characterized by The communication device includes a star flash module for implementing transmission of a star flash signal, and the communication device further includes: The module for receiving scheduling type indication information, the scheduling type indication information indicates that the retransmission is based on a first retransmission data unit or a hybrid transmission of initial transmission and retransmission, a first coding mode is used to determine a first redundancy version and a first bit rearrangement version of a channel bit sequence, and the first retransmission data unit is a transport block or a coded block group; The module for decoding and bit rearranging the channel bit sequence according to the scheduling type indication information; The first bit rearrangement version indicates an output bit sequence corresponding to a first quadrature amplitude modulation (QAM) bit rearrangement version number in a bit rearrangement version table, and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM, or 4096QAM.

84. The communication apparatus according to any of claims 81-83, characterized by The communication device is also configured to implement the method in any of claims 40 to 45.

85. A communications device, characterized by The communication device comprises a star flash module for implementing transmission of a star flash signal, and the communication device further comprises: A module for obtaining a bit rearrangement version table, the bit rearrangement version table comprising output bit sequences corresponding to respective bit rearrangement version numbers in at least one quadrature amplitude modulation (QAM), and the at least one QAM comprises at least one of 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM; A module for determining an input bit sequence according to the bit rearrangement version table.

86. The communication apparatus of claim 85, wherein The communication device is also configured to implement the method in claim 47.

87. A communications device, characterized by The communication device comprises a star flash module for implementing transmission of a star flash signal, and the communication device further comprises: A module for receiving bit rearrangement version information, the bit rearrangement version information indicating a first bit rearrangement version in a bit rearrangement version table; A module for bit rearranging according to the bit rearrangement version information; The first bit rearrangement version indicates an output bit sequence corresponding to a first quadrature amplitude modulation (QAM) bit rearrangement version number, and the first QAM is 16QAM, 64QAM, 256QAM, 1024QAM, or 4096QAM.

88. The communication apparatus of claim 87, wherein The communication device is also configured to implement the method in any of claims 49 to 51.

89. The communication apparatus according to any one of claims 85-88, wherein, The communication device is also configured to implement the method in any of claims 52 to 71. 90.The communication apparatus according to any one of claims 72-89, characterized by, The communication device further comprises a Bluetooth module for implementing transmission of a Bluetooth signal and / or a WiFi module for implementing transmission of a WiFi signal, and one or more of the star flash module, the Bluetooth module, or the WiFi module share a radio frequency (RF) unit.

91. The communication apparatus according to any one of claims 72-90, wherein, The star flash module and the WiFi module for implementing transmission of a WiFi signal are located in different subsystems of the communication device, and the subsystem of the star flash module and the subsystem of the WiFi module are integrated in the communication device with at least one of a Bluetooth system, a star flash low energy (SLE) system, a global navigation satellite system (GNSS), an always-on system, a power management unit (PMU), a clock management unit (CMU), a flash memory, an application system, and an audio system.

92. The communication apparatus according to any one of claims 72-90, wherein, The star flash module and the WiFi module for implementing WiFi signal transmission are located in the same subsystem of the communication device, and the subsystem of the star flash module and the WiFi module is integrated in the communication device with at least one of the following: a Bluetooth system, a star flash low power consumption SLE system, a global navigation satellite system GNSS, an always-on system, a power management unit PMU, a clock management unit CMU, a flash memory, an application system, and an audio system.

93. The communication apparatus according to any one of claims 72-92, wherein, The communication device further comprises a Bluetooth module for implementing Bluetooth signal transmission and / or a WiFi module for implementing WiFi signal transmission, and at least one of the Bluetooth module or the WiFi module coexists with the star flash module through different antennas, and the coexistence strategy comprises at least one of the following: frequency division multiplexing, code division multiplexing, time division multiplexing, channel avoidance, or aggregated scheduling.

94. The communication apparatus according to any one of claims 72-92, wherein, The communication device further comprises a Bluetooth module for implementing Bluetooth signal transmission and / or a WiFi module for implementing WiFi signal transmission, and at least one of the Bluetooth module or the WiFi module coexists with the star flash module through the same antenna, and the coexistence strategy comprises at least one of the following: frequency division multiplexing, code division multiplexing, time division multiplexing, a software static strategy, or a packet transmission arbitration PTA strategy.

95. A communications device, characterized by The device comprises: one or more processors; a memory for storing one or more computer programs or instructions; when the one or more computer programs or instructions are executed by the one or more processors, the one or more processors implement the method of any one of claims 1 to 71.

96. A communication system, characterized by The system comprises: a management node and a terminal node; the management node is configured to execute the method of any one of claims 1 to 36, and the terminal node is configured to execute the method of any one of claims 37 to 71.

97. A chip, comprising: The chip comprises: processing circuitry and interface circuitry; the interface circuitry is configured to couple with a memory outside the chip and provide a communication interface for the processing circuitry to access the memory; the processing circuitry is configured to execute program instructions in the memory to implement the method of any one of claims 1 to 71. 98.A computer readable storage medium, characterized in that, the computer readable storage medium stores program codes, and the program codes are executed by a processor to implement the method of any one of claims 1 to 71.

99. A computer program product, characterized in that, The computer program product comprises instructions, which, when the computer program product is run on a computer, cause the computer to implement the method of any one of claims 1 to 71.

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