Random MAC address generation and application method for server

Abstract

The invention discloses a random MAC (Media Access Control) address generation and application method for a server, which comprises the following steps: after a mainboard is powered on, a BIOS (Basic Input Output System) accesses an MAC address controller of a processor or a bridge chip, acquires an original MAC address of equipment, and stores the original MAC address to a specified storage area; the BIOS calls a random number interface of the platform processor to generate a group of random MAC addresses; the generated random MAC address is subjected to double verification, the double verification comprises MAC validity verification and difference verification with the original MAC address, independent EEPROM, FLASH and other storage chips do not need to be additionally added, the original MAC address is stored by directly utilizing an SRAM area of the processor, meanwhile, a random number interface built in the processor is multiplexed to generate the random MAC address, and the random MAC address is stored in the random number interface of the processor. The cost of hardware purchase and mainboard PCB layout is reduced, and the hardware architecture is simplified.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of server management, and particularly relates to a random MAC address generation and application method for a server. BACKGROUND

[0002] A random MAC address is a temporary and non-unique network device identifier, which is different from a real MAC address fixed at the factory. The core role of the random MAC address is to prevent other devices or services in the network from tracking the user device through the unique identifier, thereby enhancing user privacy protection. At present, in various network communication scenarios of hardware platforms, the MAC address is a necessary identifier for device network connection, and is usually stored in a fixed manner. Most platforms will fix the original MAC address in an independent EEPROM or FLASH chip, so that the BIOS can stably read the address and write it into the MAC controller when the device is powered on each time, so as to ensure the normal initialization of the network function. At the same time, the random MAC address technology has been applied in some scenarios. The original fixed MAC address is replaced by a software tool at the operating system level after the device enters the system running stage, which is used for daily network data transmission and reduces the risk of being uniquely identified.

[0003] However, the prior art has obvious deficiencies, which are in sharp contrast to the beneficial effects of the foregoing technical solutions. First, the hardware cost control is insufficient. An independent EEPROM or FLASH chip is needed to store the original MAC address, which not only increases the hardware procurement cost, but also occupies the PCB layout space of the mainboard, and cannot simplify the architecture by using existing hardware resources such as the processor SRAM of the platform. Second, the privacy protection is not comprehensive. The random MAC address can only be generated by software after the operating system is loaded. The original fixed MAC address still needs to be used in the BIOS startup stage (device network initialization and network startup process), which leads to the exposure of the unique identifier of the device in this critical stage, and cannot achieve privacy protection in the whole network startup process. Third, the reliability and adaptability are lacking. There is no effective validity check (such as format compliance) of the generated random MAC address and no difference check with the original MAC address, which is easy to cause network disconnection due to invalid addresses, and the adaptability to different bus types (such as HT, PCIE) and Ethernet interfaces (such as RGMII, SGMII, MDI) is insufficient, which is difficult to meet the application requirements of diversified hardware platforms. SUMMARY

[0004] In order to overcome the above-mentioned defects of the prior art, the application provides a random MAC address generation and application method for a server, which solves the problem that the MAC exists in an external chip and the BIOS has no random MAC, resulting in exposure of the device identifier.

[0005] To achieve the above-mentioned purpose, the application provides the following technical solutions:

[0006] A random MAC address generation and application method for a server, comprising the following steps:

[0007] S1: After the mainboard is powered on, the BIOS accesses the MAC address controller of the processor or bridge, obtains the original MAC address of the device, and stores the original MAC address in a specified storage area;

[0008] S2: The BIOS calls the random number interface of the platform processor to generate a set of random MAC addresses;

[0009] S3: Double-checking the generated random MAC addresses, which includes MAC validity checking and difference checking with the original MAC address;

[0010] S4: When both double-checking passes, the BIOS writes the random MAC address to the MAC controller of the processor or bridge through the bus; when double-checking fails, return to step S2 to generate a random MAC address again, and the retry count is not more than 5 times; if it still fails after 5 retries, the BIOS maintains the storage state of the original MAC address in the MAC controller to ensure the normal startup of the network function of the device.

[0011] Preferably, the specified storage area in step S1 is the SRAM area of the processor, which is a storage area provided by the mainboard chip itself, and the BIOS can directly access it after the mainboard is powered on.

[0012] Preferably, the interface for generating random MAC addresses in step S2 is the random number interface built-in the platform processor, without the need to additionally add a random number generation hardware module on the mainboard.

[0013] Preferably, the execution order of double-checking in step S3 is: first perform MAC validity checking, then perform difference checking with the original MAC address after confirming that the random MAC address conforms to the format specification of the Ethernet MAC address, and finally confirm that the byte data of the random MAC address is completely different from that of the original MAC address.

[0014] Preferably, the bus in step S4 is the HT bus or PCIE bus, and the BIOS transmits the random MAC address to the address register of the MAC controller of the processor or bridge through the bus.

[0015] Preferably, the method is applied in the BIOS startup stage, and the generation and writing of the random MAC address are completed before the device initializes the network function and initiates the network connection, ensuring that the random MAC address is used when the device starts the network.

[0016] Preferably, the MAC validity check in step S3 includes two aspects: confirming that the byte length of the random MAC address is 6 bytes, and confirming that the byte data of the random MAC address conforms to the coding specification of the MAC address of the Ethernet device.

[0017] Preferably, the SRAM area for storing the original MAC address is a temporary storage area activated after the processor is powered on, and the original MAC address data stored in the area is automatically erased after the mainboard is powered off and cannot be retained.

[0018] Preferably, the random MAC address generated by the random number interface in step S2 is 6-byte continuous binary data, and the format of the binary data is completely matched with the address writing format of the MAC controller of the processor or the bridge, and can be directly written.

[0019] Preferably, the method is suitable for two types of hardware platforms: one is a processor platform integrated with an Ethernet controller, and the other is a hardware platform equipped with a bridge; the interface provided by the Ethernet controller is an RGMII interface, an SGMII interface or an MDI interface.

[0020] The technical effects and advantages of the random MAC address generation and application method for a server are as follows:

[0021] 1. The application does not need to add independent EEPROM, FLASH and other storage chips, but directly uses the SRAM area of the processor to store the original MAC address, and simultaneously uses the random number interface of the processor to generate a random MAC address, thereby reducing the hardware procurement and mainboard PCB layout cost and simplifying the hardware architecture.

[0022] 2. The application generates and writes the random MAC address in the BIOS startup phase (before the network function of the device is initialized), avoids exposure of the original MAC address during the network startup process of the device, prevents the network device or service from tracking the device through the original MAC unique identifier, and further reduces the risk of residual leakage of the original MAC by using the SRAM area for temporarily storing the original MAC address and automatically erasing the data after the mainboard is powered off.

[0023] 3. The application ensures that the generated random MAC address conforms to the Ethernet specification and is not repeated with the original MAC address through double verification (MAC validity check + difference check with the original MAC address), avoids network failures caused by invalid addresses, and maintains the use of the original MAC address in an extreme case, thereby guaranteeing the normal startup of the network function of the device and avoiding the risk of disconnection.

[0024] 4、The application supports writing random MAC addresses into the MAC controller of the processor or bridge through the HT bus or PCIE bus, adapts to the processor platform with integrated Ethernet controller and the hardware platform with bridge, and is compatible with the RGMII interface, SGMII interface and MDI interface provided by the Ethernet controller, so as to meet the diversified hardware architecture and application scene requirements.

[0025] Optimizing start timing and network experience: the random MAC address is configured in the BIOS start phase, covering the whole process of device network start, without waiting for the random MAC generated by software after the operating system is loaded, avoiding the privacy exposure gap caused by timing lag, and ensuring that the device can use a safe random MAC address from the start of network start, without affecting the network connection speed and stability. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a simplified flowchart of a server random MAC address generation and application method proposed by the application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, not all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the application.

[0028] It should be noted that in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations, and the terms include, contain or any other variant are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed or inherent to such process, method, article or device. Without more limitation, the elements limited by the statement include… do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0029] Embodiment 1

[0030] Reference Figure 1 The embodiment provides a server random MAC address generation and application method based on an integrated Ethernet controller processor platform, and the specific implementation content includes:

[0031] Implementation purposes:

[0032] Solve the problem of "MAC address fixed storage in independent EEPROM, BIOS stage cannot use random MAC, resulting in original address exposure", under the premise of no additional hardware cost, realize the random MAC configuration in the BIOS startup stage (before network PXE startup), adapt to the general processor platform integrated with Ethernet controller.

[0033] Implementation steps:

[0034] S1: After the motherboard is powered on, the BIOS (version V3.2) accesses the MAC address controller built-in X1 series processor, reads the original MAC address (example: 00-1A-2B-3C-4D-5E) fixed at the factory; then stores the original MAC address in the SRAM area (address segment 0x00010000-0x00010005) of the processor, which is a chip built-in motherboard, and BIOS can directly access without additional storage chip.

[0035] S2: Random MAC address generation BIOS calls the random number interface (model X1-RNG, interface address 0x00F00020) built-in X1 series processor to generate a set of 6-byte continuous binary data as random MAC address (example: 11-22-33-44-55-66).

[0036] S3: Double check The generated random MAC address is double checked: first, MAC validity check is performed to confirm that the random MAC address is 6 bytes long and meets the Ethernet MAC address format specification (excluding broadcast address, multicast address); then, difference check with the original MAC address is performed to confirm that the random MAC address is completely different from the original MAC address stored in SRAM, and this double check is passed.

[0037] S4: After the double check is passed, BIOS writes the random MAC address to the MAC controller of X1 series processor through HT bus (transmission rate 2.0GHz); if the double check is not passed, return to S2 to generate a new random MAC address, the retry number is not more than 5 times; if it still fails after 5 retries, maintain the storage state of the original MAC address in the MAC controller to ensure the normal startup of network function (in this embodiment, the check is passed once, no need to retry).

[0038] Implementation effect:

[0039] Without additional addition of EEPROM or FLASH chip, hardware cost is not increased; BIOS stage completes random MAC configuration, and the time consumption is about 800 ms, in 100 times of repeated tests, the success rate of random MAC generation and verification is 100%, no original MAC address is exposed when the network is started, and the network connection stability is consistent with the fixed MAC scheme.

[0040] Embodiment 2

[0041] The embodiment provides a random MAC address generation and application method for a server, and is based on a PCIE bus adaptation implementation of a bridge piece, and the specific implementation content comprises the following steps:

[0042] Implementation purposes:

[0043] The hardware platform of the “processor + bridge piece” architecture is adapted, the compatibility problem of transmitting the random MAC address through the PCIE bus of the platform is solved, and the stable writing of the random MAC in the external Ethernet controller scene is ensured.

[0044] Implementation steps:

[0045] S1: After the original MAC address is obtained and stored, the motherboard is powered on, the BIOS accesses the external Ethernet controller of the Z2 series bridge piece, and reads the original MAC address (example: 00-2C-3D-4E-5F-6A); the original MAC address is stored in the SRAM area (address segment 0x00012000-0x00012005) of the Y2 series processor.

[0046] S2: Random MAC address generation BIOS calls the random number interface built in the Y2 series processor to generate a set of random MAC addresses (example: 22-33-44-55-66-77).

[0047] S3: Double-checking is performed, and it is first confirmed that the random MAC address meets the Ethernet format specification (6 bytes, non-broadcast / multicast), and then it is confirmed that it is different from the original MAC address in the SRAM, and the double-checking is passed.

[0048] S4: Random MAC address writing and exception bottoming After the double-checking is passed, the BIOS writes the random MAC address into the Ethernet controller of the Z2 series bridge piece through the PCIE bus (PCIE3.0, x1 link, rate 8Gbps); if the verification is not passed, return to S2 for retry (one time in this embodiment).

[0049] Implementation effects:

[0050] PCIE bus transmission delay ≤10μs, random MAC write success rate 100%, compatible with Intel I210, Realtek RTL8111 and other external Ethernet controllers and Z series, H series bridge, better than single HT bus solution, while maintaining the advantage of "no additional hardware cost".

[0051] Embodiment 3

[0052] This embodiment provides a server random MAC address generation and application method, based on the privacy protection of SRAM temporary storage characteristics, the specific implementation content includes:

[0053] Implementation purposes:

[0054] Strengthen the privacy protection of the original MAC address, solve the problem of "non-volatile storage medium retains the original MAC address leading to leakage", adapt to the platform scene of government, finance and other privacy sensitive platforms.

[0055] Implementation steps:

[0056] S1: After the original MAC address is obtained and stored, the BIOS accesses the MAC address controller of the A3 series processor, reads the original MAC address (example: 00-3D-4E-5F-6A-7B); The original MAC address is stored in the SRAM area (address segment 0x00020000-0x00020005) of the processor, which is a temporary storage area that can be activated after the processor is powered on.

[0057] S2: Random MAC address generation BIOS calls the random number interface of the A3 series processor to generate a random MAC address (example: 33-44-55-66-77-88).

[0058] S3: Double check Execute MAC validity check (6 bytes, conform to Ethernet specification) and difference check (different from original MAC), double check passed.

[0059] S4: Random MAC address write and exception bottom BIOS writes the random MAC address to the MAC controller through the HT bus; At the same time, record the SRAM storage state, monitor the SRAM data retention after power off.

[0060] Implementation effects:

[0061] 50 times of power off-power on cycle test shows that the original MAC address stored in the SRAM area is automatically erased (read value is 0xFFFF) after power off, without data residue; Random MAC generation and verification success rate 100%, fully meet the privacy protection requirements of government, financial scenarios, without additional software erasing steps.

[0062] Embodiment 4

[0063] This embodiment provides a method for generating and applying random MAC address for a server, based on the MDI interface adaptation implementation of the processor platform, and the specific implementation content includes:

[0064] Implementation purposes:

[0065] Adapt the MDI interface of the Ethernet controller to solve the compatibility problem of random MAC address in MDI interface communication in scenarios such as home gateway and industrial terminal, and ensure normal network connection.

[0066] Implementation steps:

[0067] S1: After the motherboard is powered on, BIOS accesses the MAC address controller (supports MDI interface) integrated in the B4 series processor, reads the original MAC address (example: 00-4E-5F-6A-7B-8C), and stores the original MAC address in the processor SRAM area (address segment 0x00015000-0x00015005).

[0068] S2: Random MAC address generation BIOS calls the random number interface of the B4 series processor to generate a random MAC address that meets the byte sequence requirements of the MDI interface (example: 44-55-66-77-88-99, stored in the order of "low byte first").

[0069] S3: Double-checking to confirm that the random MAC address meets the Ethernet format specification (6 bytes, non-broadcast / multicast) and is different from the original MAC address, and double-checking is passed.

[0070] S4: Random MAC address writing and exception bottom BIOS writes the random MAC address to the MAC controller through the HT bus, and configures the MDI interface parameters (half-duplex mode, rate 100Mbps); if the check fails, return to S2 for retry (one pass in this embodiment).

[0071] Implementation effects:

[0072] When the MDI interface is connected to a broadband modem or industrial switch, the random MAC address can normally participate in DHCP allocation and PPPoE dialing, and the network rate is stable at 100Mbps without packet loss or disconnection phenomenon, and adapts to Profinet industrial protocol, meeting the network needs of home and industrial scenarios.

[0073] Embodiment 5

[0074] The embodiment provides a random MAC address generation and application method for a server, and the reliability of a retry mechanism based on random MAC is optimized and implemented, and the specific implementation content comprises the following steps:

[0075] The implementation purpose is:

[0076] The problem of "single random MAC generation invalidity leading to network startup failure" is solved, the network reliability of the server and the industrial control platform is improved through the retry mechanism, and abnormal traceability is realized.

[0077] The implementation steps are:

[0078] S1: After the motherboard is powered on, the BIOS accesses the MAC address controller of the C5 series processor, reads the original MAC address (example: 00-5F-6A-7B-8C-9D), and stores the original MAC address in the SRAM area (address segment 0x00018000-0x00018005) of the processor.

[0079] S2: Random MAC address generation BIOS calls the random number interface of the C5 series processor (enables the hardware entropy source enhancement mode, and the entropy value is greater than or equal to 128 bits), and generates a random MAC address as a multicast address (01-00-5E-00-00-01) for the first time, which does not meet the validity requirement.

[0080] S3: Double-checking is performed on the random MAC address generated for the first time, and the random MAC address generated for the first time does not pass the validity check, and the process returns to S2 to generate the random MAC address again; the random MAC address (example: 55-66-77-88-99-AA) generated for the third time passes the validity check and the difference check.

[0081] S4: Random MAC address writing and abnormal bottom BIOS writes the random MAC address into the MAC controller through the PCIE bus; if the random MAC address still does not pass after 5 retries, the original MAC address is maintained and a fault log (log ID: 0x001A) is recorded, and the network is ensured to start normally (the third retry in the embodiment passes).

[0082] The implementation effect is:

[0083] In 1000 tests, the repetition rate of the random MAC address is less than or equal to 0.01%, the trigger rate of the retry mechanism is about 1.2%, and a valid random MAC can be generated within 5 retries; the network startup success rate is 100% under extreme abnormal conditions, the fault log is traceable, and the reliability requirements of the server and the industrial control scene are met.

[0084] Comparative Example 1

[0085] The comparative example provides an existing fixed MAC address technical solution, and the specific content comprises the following steps:

[0086] Prior art solution:

[0087] The current mainstream solution is "fixed MAC stored in independent EEPROM + random MAC in system stage": the original MAC address is fixed in an independent EEPROM chip (model 24C08), and the BIOS reads the original MAC from the EEPROM and writes it to the MAC controller after the motherboard is powered on; only after the operating system (such as Kirin system) is started, a random MAC is generated through software tools to cover the fixed address, without double check mechanism.

[0088] Defect analysis:

[0089] Increased hardware cost: additional EEPROM and supporting circuit need to be purchased, increasing the cost of a single platform by about $0.6;

[0090] Original MAC exposure: the fixed MAC is still used in the BIOS stage (before network startup), which is easy to be tracked;

[0091] Low reliability: about 4 times of network disconnection due to invalid MAC generated by software in 100 times of test;

[0092] Privacy risk: the original MAC is stored after the EEPROM is powered off, which is easy to be leaked;

[0093] Timing lag: random MAC only takes effect in the system stage, and cannot cover the network demand in the BIOS stage.

[0094] Compared with Example 1-5 and Comparative Example 1, Examples 1-5 are all around "platform random MAC address generation and application method", the core is to use the SRAM of the processor to store the original MAC, the built-in random number interface to generate the random MAC, and after double check (validity + difference from the original MAC), write it to the MAC controller in the BIOS stage through HT / PCIE bus, without additional storage chip; Comparative Example 1 is the prior art, which uses independent EEPROM to store fixed MAC, only generates random MAC in the system stage through software, without check mechanism, the difference between the two is significant.

[0095] In terms of hardware cost, Examples 1-5 reuse the SRAM and random number interface of the processor, without additional hardware expenditure; Comparative Example 1 needs to additionally carry EEPROM chip and supporting circuit, increasing the cost of a single platform by about $0.6, also occupying the PCB space of the motherboard, which violates the "cost saving" requirement.

[0096] Regarding the timing of the random MAC activation, Examples 1-5 complete the configuration during the BIOS startup phase (before network startup). For example, Example 1 writes the configuration before PXE startup, ensuring that the random MAC is used immediately upon network startup. In contrast, Example 1 can only be generated by software after the operating system starts up. The MAC is still fixed in the EEPROM during the BIOS phase, which exposes the original MAC during network startup and poses a risk of being tracked.

[0097] Regarding privacy protection, the SRAM in Examples 1-5 is temporary storage, and the original MAC is automatically erased after power failure. Example 3 showed no data residue after 50 power failure cycles. In contrast, the EEPROM in Comparative Example 1 still retains the original MAC after power failure, which is easily leaked when the device is scrapped or repaired, posing a high privacy risk.

[0098] Regarding network reliability, Examples 1-5 have a dual verification + retry mechanism (retrying no more than 5 times), with a 100% success rate in 100 tests; Comparative Example 1 has no verification, and the random MAC generated by the software may be in an invalid format (such as a broadcast address), resulting in 4 disconnections in 100 tests, with a reliability of only 96%, requiring manual repair.

[0099] In terms of interface compatibility, Examples 1-5 cover RGMII, SGMII, and MDI interfaces, and are compatible with architectures such as "processor + bridge chip"; Comparative Example 1 is only compatible with a single Ethernet controller, and the MAC needs to be re-programmed when the hardware is replaced, resulting in poor compatibility.

[0100] In summary, Examples 1-5 are superior to Comparative Example 1 in terms of cost, timing, privacy, reliability, and adaptability, completely solving the shortcomings of the existing technology and being more suitable for diverse platform scenarios.

[0101] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0102] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the claims.

[0103] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for generating and applying random MAC address for a server, characterized in that, The method comprises the following steps: S1: after the mainboard is powered on, the BIOS accesses the MAC address controller of the processor or bridge, obtains the original MAC address of the device, and stores the original MAC address in a specified storage area; S2: the BIOS calls the random number interface of the platform processor to generate a set of random MAC addresses; S3: the generated random MAC addresses are subjected to double verification, which includes MAC validity verification and difference verification with the original MAC address; S4: when the double verification passes, the BIOS writes the random MAC address into the MAC controller of the processor or bridge through a bus; when the double verification fails, the step S2 is returned to generate random MAC addresses again, and the retry number is not more than 5 times; When the retry is still not passed for 5 times, the BIOS maintains the storage state of the original MAC address in the MAC controller, and ensures that the network function of the device is normally started.

2. The method for generating and applying random MAC addresses for servers as described in claim 1, characterized in that, The specified storage area in step S1 is an SRAM area of the processor, which is a storage area of the mainboard chip itself, and the BIOS can directly access it after the mainboard is powered on.

3. The method for generating and applying random MAC addresses for servers as described in claim 1, characterized in that, The interface for generating random MAC addresses in step S2 is a random number interface built-in the platform processor, and no additional random number generation hardware module needs to be added on the mainboard.

4. The method for generating and applying random MAC addresses for servers as described in claim 1, characterized in that, The execution sequence of the double verification in step S3 is: first, the MAC validity verification is performed, and then the difference verification with the original MAC address is performed after confirming that the random MAC address meets the format specification of the Ethernet MAC address, and it is confirmed that the byte data of the random MAC address is completely different from that of the original MAC address.

5. The method of claim 1, wherein the method further comprises: generating a random MAC address; and applying the random MAC address to the server. 5 The bus in step S4 is an HT bus or a PCIE bus, and the BIOS transmits the random MAC address to the address register of the MAC controller of the processor or bridge through the bus.

6. The method of claim 1, wherein the method further comprises: generating a random MAC address; and applying the random MAC address to the server. 5 The method is applied to the BIOS startup stage, and the generation and writing of the random MAC address are completed before the device initializes the network function and initiates the network connection, so that the random MAC address is used when the device network starts.

7. The method for generating and applying random MAC addresses for a server as described in claim 1, characterized in that, The MAC validity verification in step S3 includes two contents: confirming that the byte length of the random MAC address is 6 bytes, and confirming that the byte data of the random MAC address meets the coding specification of the Ethernet device MAC address.

8. The method of claim 2, wherein the method further comprises: generating a random MAC address; and applying the random MAC address to the server. 8 The SRAM area for storing the original MAC address is a temporary storage area that can be activated after the processor is powered on, and the original MAC address data stored in the area is automatically erased after the mainboard is powered off and cannot be retained.

9. The method for generating and applying random MAC addresses for servers as described in claim 1, characterized in that, The random MAC address generated by the random number interface in step S2 is 6-byte continuous binary data, and the format of the binary data is completely matched with the address writing format of the MAC controller of the processor or bridge, and can be directly written.

10. The method for generating and applying random MAC addresses for a server as described in claim 1, characterized in that, The method is suitable for two types of hardware platforms: one is a processor platform integrated with an Ethernet controller, and the other is a hardware platform with a bridge; the interface provided by the Ethernet controller is an RGMII interface, an SGMII interface or an MDI interface.

Images