Electronic device oriented accelerated test parameter response method and system

Abstract

The application discloses a method and system for electronic device stress test parameter response, and relates to the technical field of electronic device testing. The method comprises the following steps: obtaining a basic test scheme sequence based on basic attribute characteristic parameters of an electronic device to be tested; obtaining a test item importance sequence, and obtaining a correction test scheme based on the test item importance sequence; obtaining interference coefficients of multiple test item pairs in the correction test scheme, iteratively optimizing the test item sequence in the correction test scheme, and obtaining an optimized test scheme; and performing stress test on the electronic device based on the optimized test scheme. The application solves the technical problem of inaccurate test results caused by insufficient test scheme pertinence in the prior art.

Description

Technical Field

[0001] This invention relates to the field of electronic device testing technology, and more specifically to a method and system for enhancing the response of test parameters for electronic devices. Background Technology

[0002] Electronic devices must undergo rigorous testing during production and application to verify their performance and reliability. With the rapid development of electronic technology, the complexity and integration of devices are constantly increasing, placing higher demands on testing methods. Existing electronic device testing methods largely rely on standardized testing procedures. These procedures are designed based on general device specifications and historical experience, aiming to cover common functional and electrical characteristic tests. However, this one-size-fits-all approach is difficult to adapt to the specific attributes of different types of electronic devices, such as differences in core functions or electrical characteristics, resulting in a lack of targeted testing solutions. Furthermore, interference may exist between test items, such as electrical stress accumulation, thermal effect superposition, or signal crosstalk. These interferences can distort test results, mask true failure modes, and lead to low testing efficiency and poor consistency. In balancing testing time and test effectiveness, existing methods often fail to achieve an intelligent balance, either over-testing, increasing costs, or under-testing, increasing risks. Summary of the Invention

[0003] This application provides a method and system for enhancing test parameter response for electronic devices, which addresses the technical problem of inaccurate test results due to insufficient targeting of test schemes in the testing of electronic devices in the prior art.

[0004] In view of the above problems, this application provides a method and system for enhancing the response of test parameters for electronic devices.

[0005] In a first aspect, this application provides a method for enhancing test parameter response of electronic devices, the method comprising:

[0006] Based on the basic attribute and characteristic parameters of the electronic device under test, obtain a basic test scheme sequence;

[0007] Obtain the importance sequence of test items, and based on the importance sequence of test items, obtain a corrective test plan;

[0008] Obtain the interference coefficients of multiple test item pairs in the calibration test plan, iteratively optimize the order of test items in the calibration test plan, and obtain the optimized test plan;

[0009] Based on the optimized testing scheme, enhanced testing of electronic devices is carried out.

[0010] Secondly, this application provides an enhanced test parameter response system for electronic devices, including:

[0011] The basic scheme acquisition module is used to acquire a basic test scheme sequence based on the basic attribute characteristic parameters of the electronic device under test;

[0012] The scheme importance assessment module is used to obtain the importance sequence of test items and, based on the importance sequence of test items, obtain the corrected test scheme.

[0013] The test order optimization module is used to obtain the interference coefficients of multiple test item pairs in the calibration test plan, iteratively optimize the order of test items in the calibration test plan, and obtain the optimized test plan.

[0014] The enhanced testing module is used to perform enhanced testing on electronic devices based on the optimized testing scheme.

[0015] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0016] This application proposes an enhanced test parameter response method and system for electronic devices. By dynamically generating basic test sequences based on the fundamental properties of the device, and then combining the importance assessment of test items with iterative optimization of interference between test items, the method significantly improves the relevance of the test scheme, the accuracy of the test process, and the utilization efficiency of test resources. Compared with traditional methods, the technical solution provided in this application significantly overcomes the problem of low relevance of test schemes in traditional methods, achieving the technical effect of improving the accuracy, reliability, and overall efficiency of electronic device testing, while optimizing the test process and ensuring the consistency of test results. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating the enhanced test parameter response method for electronic devices provided in an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of the structure of an enhanced test parameter response system for electronic devices provided in an embodiment of this application.

[0020] The components represented by each number in the attached diagram are explained below:

[0021] The module includes: Basic Solution Acquisition Module 100, Solution Importance Assessment Module 200, Test Order Optimization Module 300, and Enhanced Testing Module 400. Detailed Implementation

[0022] This application provides a method and system for enhancing the response of test parameters for electronic devices, which addresses the technical problem of inaccurate test results due to insufficient targeting of test schemes in the testing of electronic devices in the prior art.

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0024] It should be noted that the terms "comprising" and "having" are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or server that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or modules that are not explicitly listed or that are inherent to these processes, methods, products, or devices.

[0025] Example 1, as Figure 1 As shown, this application provides a method for enhancing test parameter response for electronic devices, wherein the method includes:

[0026] S10: Based on the basic attribute and characteristic parameters of the electronic device under test, obtain the basic test scheme sequence.

[0027] In the field of electronic device testing, existing technologies typically employ general or fixed test schemes. However, different electronic devices exhibit significant differences in core functions and other aspects, and traditional methods cannot provide more targeted test planning based on these specific fundamental attribute parameters. This often leads to the initial test scheme development relying on engineers' experience or a broad standard library, resulting in a degree of uncertainty.

[0028] Step S10 in the method provided in this application embodiment includes:

[0029] Obtain the basic attribute and characteristic parameters of the electronic device under test, including core functional attributes and electrical characteristic attributes.

[0030] Obtain a test scheme library, and based on the core functional attributes of the electronic device under test, filter test items with a relevance greater than or equal to the relevance threshold to obtain a basic test scheme sequence;

[0031] The construction of the test scheme library includes:

[0032] Obtain and annotate the test items from the historical test plans of electronic devices, with the annotations focusing on the core functional attributes of the electronic devices.

[0033] The probability of occurrence of core functional attributes corresponding to multiple test items in the test scheme library is used as the relevance, and the test scheme library is obtained by integrating them.

[0034] In this embodiment, the basic attribute characteristics of the electronic device under test are obtained. These basic attribute characteristics include core functional attributes and electrical characteristic attributes. Core functional attributes refer to the core functions that the electronic device under test can perform. For example, based on the classification and design documents of the electronic device under test, its core function is obtained; if the electronic device is classified as an amplifier, then its core functional attribute is signal amplification. Electrical characteristic attributes refer to the rated electrical parameters of the electronic device in its design documents. For example, if the electronic device under test is classified as an amplifier, its rated electrical parameters include rated voltage, gain-bandwidth product, etc.

[0035] Build a test scheme library. Specifically, obtain historical test schemes for electronic devices, which include various types of electronic devices, and historical test schemes include various test items. Label the test items in the historical test schemes; for example, if a test item is a voltage test, the corresponding label could be "transformer," "power supply," etc.

[0036] The test scheme library is obtained by integrating the occurrence probabilities of core functional attributes corresponding to multiple test items in the test scheme library as relevance. For example, in the basic attribute feature parameters corresponding to a test item, "transformer" appears 40 times, "power supply" appears 20 times, and "amplifier" appears 40 times. Then the relevance of "transformer" for this test item is 40 ÷ (40 + 20 + 40) = 0.4. Using the same method, the relevance of "power supply" is calculated to be 0.2, and the relevance of "amplifier" is 0.4.

[0037] The test scheme library is retrieved. Based on the core functional attributes of the electronic device under test, test items with a relevance greater than or equal to a relevance threshold are filtered to obtain a basic test scheme sequence. The relevance threshold is a pre-set threshold used to filter out test items with higher relevance; for example, it can be set to 0.2 to filter out test items with too low relevance, improving testing efficiency. Test items with a relevance greater than or equal to 0.2 to the electronic device under test are added to the basic test scheme sequence to obtain the basic test scheme sequence.

[0038] By introducing a method to generate a basic test scheme sequence based on the basic attribute characteristics of the electronic device under test, targeted configuration of the initial test planning is achieved. The formulation of test schemes is transformed from relying on subjective experience to being driven by objective data. By selecting test items that are highly correlated with the core functions of the device, the initial test sequence is ensured to have good basic coverage. Test items that are irrelevant to the device under test can be effectively discarded, reducing test redundancy from the source and optimizing the allocation of test resources.

[0039] S20: Obtain the importance sequence of test items, and based on the importance sequence of test items, obtain a corrective test plan.

[0040] Once a basic test plan is established, existing test methods are typically executed in a fixed sequence. However, in actual testing, the importance of different test items in revealing potential failure modes of a device varies significantly. Some test items may be related to the core function of the device, or their test conditions may impose more severe electrical or thermal stresses on the device. Therefore, these test items are more likely to trigger early failures of the device or expose weaknesses in its reliability.

[0041] Step S20 in the method provided in this application embodiment includes:

[0042] Obtain the failure analyzer;

[0043] The failure analyzer acquisition includes:

[0044] Based on historical data, obtain historical core functional attributes, historical test items, and historical failure risk parameters;

[0045] Construct a failure analyzer and train it based on the historical core functional attributes, the historical test items, and the historical failure risk parameters until convergence.

[0046] The test items in the basic test scheme sequence and the core functional attributes of the electronic device under test are input into the failure analyzer to obtain failure risk parameters, and based on the failure risk parameters, functional correlation parameters are obtained.

[0047] Based on electrical characteristics, stress sensitivity parameters are obtained;

[0048] The importance parameters of the test items are obtained by weighted calculation based on the functional correlation parameter and the stress sensitivity parameter;

[0049] Based on the importance parameters of the test items, a correction test plan is obtained, wherein the test items in the correction test plan are arranged in descending order of importance parameters.

[0050] In this embodiment, a failure analyzer is obtained. Specifically, based on historical data, historical core functional attributes, historical test items, and historical failure risk parameters are obtained. Historical test data refers to historical data on electronic device testing obtained through historical test logs, including historical test items and historical failure risk parameters. Historical failure risk parameters refer to the probability of triggering electronic device failure during the testing process of a particular test item, which can be calculated by dividing the number of times the test has triggered electronic device failure by the total number of times the test has been performed.

[0051] A failure analyzer is constructed based on machine learning. The input layer receives core functional attributes and test items, the hidden layer uses 32 nodes activated by the ReLU function, and the output layer outputs the failure probability of the electronic device. Historical core functional attributes and test items are used as input, and historical failure risk parameters are used as supervision to train the failure analyzer until convergence. For example, if a set of historical core functional attributes and test items not used in the training are input, and the deviation between the output failure risk and the historical failure risk is less than or equal to ±0.05, the training is considered complete.

[0052] The test items in the basic test scheme sequence and the core functional attributes of the electronic device under test are input into the failure analyzer to obtain failure risk parameters. Based on the failure risk parameters, functional correlation parameters are obtained. The functional correlation parameter is calculated as follows: Failure Risk Parameter of Test Item ÷ Sum of Failure Risk Parameters of All Test Items in the Sequence. This allows for a better assessment of the functional correlation between each test item and the electronic device under test. A higher functional correlation indicates greater significance for testing the functionality of the electronic device, and thus a greater need for this test.

[0053] Based on electrical characteristics, stress sensitivity parameters are obtained. For example, the stress sensitivity parameter = (test stress of the test item - rated stress of the electronic device under test) ÷ rated stress of the electronic device under test, where the upper limit of the test stress of the test item is obtained by acquiring the average test stress of the test item. A larger stress sensitivity parameter indicates a more stringent test on the electronic device under test.

[0054] The importance parameter of the test item is obtained by weighted calculation based on the functional relevance parameter and the stress sensitivity parameter. Test item importance parameter = Functional weight × Functional relevance + Sensitivity weight × Stress sensitivity parameter. Where, Functional weight + Sensitivity weight = 1. The allocation of functional weight and sensitivity weight is based on the importance assessment of functional relevance and stress sensitivity in the current test. For example, if the electronic device under test needs to be used in an unconventional environment, a higher sensitivity weight is assigned, for example, 0.6, then the functional weight = 1 - 0.6 = 0.4.

[0055] Based on the importance parameters of the test items, a corrective test plan is obtained. The test items in the corrective test plan are arranged in descending order of importance.

[0056] By constructing a test item importance sequence and generating corrective test plans accordingly, the allocation of test resources and proactive management of test risks were achieved. By introducing a quantitative assessment dimension for test item importance, and comprehensively considering factors such as failure risk, functional relevance, and stress sensitivity, critical test items with a greater impact on device reliability can be accurately identified. Based on this, by prioritizing highly important test items in the plan, the testing process is ensured to focus on the stages most likely to expose defects. This prioritization significantly increases the probability of discovering major defects early in the testing process, enabling faster identification of defective devices and effectively avoiding the potential masking or delayed discovery of critical defects due to the execution of secondary test items first. Overall, this improves the efficiency of the testing process and the fault detection capability.

[0057] S30: Obtain the interference coefficients of multiple test item pairs in the calibration test plan, iteratively optimize the order of test items in the calibration test plan, and obtain the optimized test plan.

[0058] The execution order of test items can still significantly impact the accuracy of the final test results. During continuous testing, the electrical stress, heat accumulation, or physical state changes caused by the previous test item may continue to affect the test environment and device state of subsequent tests, thus introducing interference. For example, if a high-power test is immediately followed by a high-precision parameter measurement, the residual stress from the former may cause inaccurate measurement results in the latter. In existing technologies, the test order is often fixed or randomly arranged, making it difficult to guarantee the reliability and consistency of test results. Some true device performance may be masked, while some false fault phenomena may be triggered, ultimately leading to biased test conclusions.

[0059] Step S30 in the method provided in this application embodiment includes:

[0060] Obtain multiple test item pairs according to the order of the calibration test plan;

[0061] Calculate and obtain the interference coefficients of multiple test item pairs;

[0062] The calculation of interference coefficients for multiple test item pairs includes:

[0063] Based on historical test data, the concentrated values ​​of performance parameters tested sequentially according to test items are obtained as interference performance parameters;

[0064] Obtain the set values ​​of the performance parameters of each test item when tested individually, and use them as the basic performance parameters;

[0065] The deviation between the obtained interference performance parameters and the basic performance parameters is calculated and used as the interference coefficient for multiple test item pairs;

[0066] If the interference coefficient is greater than the interference coefficient threshold, the order of the test items in the test item pair is changed to obtain an adjusted test plan.

[0067] Following the order of adjusting the test plan, continue to obtain multiple test item pairs and obtain the interference coefficient, perform iterative optimization, and obtain an optimized test plan;

[0068] This includes obtaining multiple test item pairs and interference coefficients according to the adjusted test plan order, performing iterative optimization, and obtaining an optimized test plan.

[0069] If, when the number of iterations reaches the preset number, there are still interference coefficients greater than the interference coefficient threshold, then a stress release time is added between the test items with interference coefficients greater than the interference threshold. The stress release time length is obtained based on the preset stress release length and the interference coefficient.

[0070] In this embodiment of the application, multiple test item pairs are obtained according to the order of the calibration test scheme. For example, if the order of test items in the calibration test scheme is "high temperature test, low temperature test, input offset voltage test, common mode rejection ratio test", then multiple test item pairs such as "high temperature test, low temperature test", "low temperature test, input offset voltage test", and "input offset voltage test, common mode rejection ratio test" can be obtained.

[0071] The interference coefficients for multiple test item pairs are calculated. Specifically, based on historical test data, the set of performance parameters obtained when testing in order of test item pairs, such as the arithmetic mean, are obtained as interference performance parameters. The set of performance parameters obtained when testing each test item individually, such as the arithmetic mean, are also obtained as the baseline performance parameters.

[0072] The deviation between the obtained interference performance parameters and the baseline performance parameters is calculated and used as the interference coefficient for multiple test item pairs. Interference coefficient = |interference performance parameter - baseline performance parameter| ÷ baseline performance parameter. The larger the interference coefficient, the greater the impact of the test item pair order on the test. When there are no historical data records showing performance parameters obtained when testing in the order of the test item pairs, the interference performance parameter is set to 0.15 to account for potential interference due to incomplete data.

[0073] If the interference coefficient is greater than the interference coefficient threshold, the order of the test items in the test item pair is changed to obtain an adjusted test plan. For example, if the interference coefficient threshold is set to 0.2, and the interference coefficient of a test item pair such as "high temperature test, low temperature test" is 0.6, then the order of the test items in the test item pair is changed, that is, the test item pair is adjusted to "low temperature test, high temperature test".

[0074] Following the order of adjusting the test plan, continue to obtain multiple test item pairs and their interference coefficients, perform iterative optimization, and obtain an optimized test plan with the minimum interference coefficient of the test item pair as the optimization objective.

[0075] When the number of iterations reaches a preset number, for example, 200, if there are still interference coefficients greater than the interference coefficient threshold, a stress release time is added between test items with interference coefficients greater than the threshold. The stress release time length is obtained based on a preset stress release length and the interference coefficient. For example, the preset stress release time length is set to 600 seconds, and the stress release time = preset stress release time length × interference coefficient, to eliminate potential interference from the test item order and obtain more accurate test results.

[0076] By analyzing the interference coefficients between test item pairs and iteratively optimizing their order, the problem of mutual interference between test items affecting the accuracy of results is effectively solved. By quantitatively evaluating the degree of mutual influence between consecutive test items, the planning of the test sequence is upgraded from a simple static arrangement to a dynamic optimization process aimed at eliminating interference. By identifying highly interfering test item pairs and adjusting their execution order, or introducing buffers when necessary, the impact of preceding tests on the state of subsequent tests can be minimized, ensuring that each test item is executed under relatively independent and stable conditions. This greatly improves the reliability of individual test item results and the consistency of the entire test dataset, providing a solid and reliable data foundation for accurate device defect identification and performance and reliability assessment.

[0077] S40: Based on the optimized test scheme, perform enhanced testing on the electronic devices.

[0078] In this embodiment of the application, enhanced testing of electronic devices is carried out based on an optimized testing scheme.

[0079] Example 2, as Figure 2 As shown, based on the same inventive concept as the enhanced test parameter response method for electronic devices provided in Embodiment 1, this embodiment of the invention also provides an enhanced test parameter response system for electronic devices, including:

[0080] The basic scheme acquisition module 100 is used to acquire a basic test scheme sequence based on the basic attribute characteristic parameters of the electronic device under test.

[0081] The scheme importance assessment module 200 is used to obtain the test item importance sequence and obtain the corrected test scheme based on the test item importance sequence;

[0082] The test order optimization module 300 is used to obtain the interference coefficients of multiple test item pairs in the calibration test plan, iteratively optimize the test item order in the calibration test plan, and obtain the optimized test plan.

[0083] The enhanced testing module 400 is used to perform enhanced testing on electronic devices based on the optimized testing scheme.

[0084] In one embodiment, the basic scheme acquisition module 100 is further configured to:

[0085] Obtain the basic attribute and characteristic parameters of the electronic device under test, including core functional attributes and electrical characteristic attributes.

[0086] Obtain a test scheme library, and based on the core functional attributes of the electronic device under test, filter test items with a relevance greater than or equal to the relevance threshold to obtain a basic test scheme sequence;

[0087] The construction of the test scheme library includes:

[0088] Obtain and annotate the test items from the historical test plans of electronic devices, with the annotations focusing on the core functional attributes of the electronic devices.

[0089] The probability of occurrence of core functional attributes corresponding to multiple test items in the test scheme library is used as the relevance, and the test scheme library is obtained by integrating them.

[0090] In one embodiment, the scheme importance assessment module 200 is further configured to:

[0091] Obtain the failure analyzer;

[0092] The failure analyzer acquisition includes:

[0093] Based on historical data, obtain historical core functional attributes, historical test items, and historical failure risk parameters;

[0094] Construct a failure analyzer and train it based on the historical core functional attributes, the historical test items, and the historical failure risk parameters until convergence.

[0095] The test items in the basic test scheme sequence and the core functional attributes of the electronic device under test are input into the failure analyzer to obtain failure risk parameters, and based on the failure risk parameters, functional correlation parameters are obtained.

[0096] Based on electrical characteristics, stress sensitivity parameters are obtained;

[0097] The importance parameters of the test items are obtained by weighted calculation based on the functional correlation parameter and the stress sensitivity parameter;

[0098] Based on the importance parameters of the test items, a correction test plan is obtained, wherein the test items in the correction test plan are arranged in descending order of importance parameters.

[0099] In one embodiment, the test sequence optimization module 300 is further configured to:

[0100] Obtain multiple test item pairs according to the order of the calibration test plan;

[0101] Calculate and obtain the interference coefficients of multiple test item pairs;

[0102] The calculation of interference coefficients for multiple test item pairs includes:

[0103] Based on historical test data, the concentrated values ​​of performance parameters tested sequentially according to test items are obtained as interference performance parameters;

[0104] Obtain the set values ​​of the performance parameters of each test item when tested individually, and use them as the basic performance parameters;

[0105] The deviation between the obtained interference performance parameters and the basic performance parameters is calculated and used as the interference coefficient for multiple test item pairs;

[0106] If the interference coefficient is greater than the interference coefficient threshold, the order of the test items in the test item pair is changed to obtain an adjusted test plan.

[0107] Following the order of adjusting the test plan, continue to obtain multiple test item pairs and obtain the interference coefficient, perform iterative optimization, and obtain an optimized test plan;

[0108] This includes obtaining multiple test item pairs and interference coefficients according to the adjusted test plan order, performing iterative optimization, and obtaining an optimized test plan.

[0109] If, when the number of iterations reaches the preset number, there are still interference coefficients greater than the interference coefficient threshold, then a stress release time is added between the test items with interference coefficients greater than the interference threshold. The stress release time length is obtained based on the preset stress release length and the interference coefficient.

[0110] In summary, the embodiments of this application have at least the following technical effects:

[0111] This application proposes an enhanced test parameter response method and system for electronic devices. By dynamically generating basic test sequences based on the basic properties of the device, and then combining the importance assessment of test items with iterative optimization of interference between test items, the method significantly improves the relevance of the test scheme, the accuracy of the test process, and the utilization efficiency of test resources. Specifically, this application can adaptively and intelligently select highly relevant test items from the test scheme library based on the core functions and electrical characteristics of different electronic devices, ensuring the basic rationality of the test coverage. Furthermore, by introducing a failure analyzer to quantify the functional correlation and stress sensitivity of each test item, it identifies key test items that have a greater impact on device reliability and assigns them priority in the test sequence. This allows test resources to focus on the links most likely to expose potential faults, effectively improving defect detection capabilities, especially in identifying high-risk failure modes in the early stages of testing, avoiding secondary tests masking key tests and wasting resources. More importantly, by analyzing the performance deviations between test item pairs in historical test data, it quantitatively assesses the mutual interference caused by the test order and uses an iterative optimization algorithm to dynamically adjust the execution order of test items, effectively suppressing test result distortion caused by factors such as electrical stress accumulation, thermal effects, or signal residue. This ensures that each test item can be performed in a relatively independent and stable device state, significantly improving the reliability and consistency of test data. This not only enhances the test adaptability to complex and diverse electronic devices but also makes the entire testing process more intelligent. Compared with traditional methods, the technical solution provided in this application significantly overcomes the problem of low targeting of test schemes in traditional methods, and achieves the technical effect of improving the accuracy, reliability and overall efficiency of electronic device testing, while optimizing the test process and ensuring the consistency of test results.

[0112] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this specification. Additionally, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are possible or may be advantageous.

[0113] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0114] This specification and accompanying drawings are merely illustrative examples of this application and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from its scope. Therefore, if such modifications and modifications fall within the scope of this application and its equivalents, this application intends to include such modifications and modifications.

Claims

1. A method for enhancing the test parameter response of electronic devices, characterized in that, include: Based on the basic attribute and characteristic parameters of the electronic device under test, obtain a basic test scheme sequence; Obtain the importance sequence of test items, and based on the importance sequence of test items, obtain a corrective test plan; Obtain the interference coefficients of multiple test item pairs in the calibration test plan, iteratively optimize the order of test items in the calibration test plan, and obtain the optimized test plan, including: Obtain multiple test item pairs according to the order of the calibration test plan; Calculate and obtain the interference coefficients for multiple test item pairs, including: Based on historical test data, the concentrated values ​​of performance parameters tested sequentially according to test items are obtained as interference performance parameters; Obtain the set values ​​of the performance parameters of each test item when tested individually, and use them as the basic performance parameters; The deviation between the obtained interference performance parameters and the basic performance parameters is calculated and used as the interference coefficient for multiple test item pairs; If the interference coefficient is greater than the interference coefficient threshold, the order of the test items in the test item pair is changed to obtain an adjusted test plan. Following the order of adjusting the test plan, continue to obtain multiple test item pairs and obtain the interference coefficient, perform iterative optimization, and obtain an optimized test plan; Based on the optimized testing scheme, enhanced testing of electronic devices is carried out.

2. The enhanced test parameter response method for electronic devices according to claim 1, characterized in that, Based on the fundamental attribute characteristics of the electronic device under test, a basic test scheme sequence is obtained, including: Obtain the basic attribute and characteristic parameters of the electronic device under test, including core functional attributes and electrical characteristic attributes. Obtain a test scheme library, and based on the core functional attributes of the electronic device under test, filter test items with a relevance greater than or equal to the relevance threshold to obtain a basic test scheme sequence.

3. The enhanced test parameter response method for electronic devices according to claim 2, characterized in that, The construction of the test scheme library includes: Obtain and annotate the test items from the historical test plans of electronic devices, with the annotations focusing on the core functional attributes of the electronic devices. The probability of occurrence of core functional attributes corresponding to multiple test items in the test scheme library is used as the relevance, and the test scheme library is obtained by integrating them.

4. The enhanced test parameter response method for electronic devices according to claim 1, characterized in that, Obtain the importance sequence of test items, and based on the importance sequence, obtain a corrective test plan, including: Obtain the failure analyzer; The test items in the basic test scheme sequence and the core functional attributes of the electronic device under test are input into the failure analyzer to obtain failure risk parameters, and based on the failure risk parameters, functional correlation parameters are obtained. Based on electrical characteristics, stress sensitivity parameters are obtained; The importance parameters of the test items are obtained by weighted calculation based on the functional correlation parameter and the stress sensitivity parameter; Based on the importance parameters of the test items, a correction test plan is obtained, wherein the test items in the correction test plan are arranged in descending order of importance parameters.

5. The enhanced test parameter response method for electronic devices according to claim 4, characterized in that, Acquire the failure analyzer, including: Based on historical data, obtain historical core functional attributes, historical test items, and historical failure risk parameters; A failure analyzer is constructed and trained based on the historical core functional attributes, the historical test items, and the historical failure risk parameters until convergence.

6. The enhanced test parameter response method for electronic devices according to claim 1, characterized in that, Following the order of adjusting the test plan, continue to obtain multiple test item pairs and interference coefficients, perform iterative optimization, and obtain an optimized test plan, which also includes: If, when the number of iterations reaches the preset number, there are still interference coefficients greater than the interference coefficient threshold, then a stress release time is added between the test items with interference coefficients greater than the interference threshold. The stress release time length is obtained based on the preset stress release length and the interference coefficient.

7. A system for enhancing test parameter response for electronic devices, characterized in that, The system is used to implement the enhanced test parameter response method for electronic devices according to any one of claims 1-6, the system comprising: The basic scheme acquisition module is used to acquire a basic test scheme sequence based on the basic attribute characteristic parameters of the electronic device under test; The scheme importance assessment module is used to obtain the importance sequence of test items and, based on the importance sequence of test items, obtain the corrected test scheme. The test order optimization module is used to obtain the interference coefficients of multiple test item pairs in the calibration test plan, iteratively optimize the order of test items in the calibration test plan, and obtain the optimized test plan. The enhanced testing module is used to perform enhanced testing on electronic devices based on the optimized testing scheme.

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