Entering system of chip test sub-mode

Abstract

The invention relates to the technical field of chip testing, in particular to a chip testing sub-mode entry system, which is characterized in that a mode decoder sets a signal of a corresponding testing sub-mode as a preset second level according to sub-mode entry information and coding information corresponding to M testing sub-modes, the signal of the test sub-mode and the signal of the test mode serve as the input of an AND gate corresponding to the test sub-mode, the AND gate corresponding to the test sub-mode serves as the input of a test selector, and when the signal of the test sub-mode and the signal of the test mode are both preset second levels, the test selector enters the test sub-mode; the mode register can be configured and the test sub-mode can be entered only by two interfaces of the first communication port, and the two interfaces can be released after entering the test sub-mode and used for participating in test excitation input, so that the reusability of the interfaces is improved, the chip area is effectively saved, the chip design and manufacturing cost is reduced, and the test efficiency is improved. And the convenience of entering the chip sub-test mode is also improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, in particular to a chip test sub-mode entering system. BACKGROUND

[0002] In a chip testing scenario, in order to improve the security of chip test mode entering and save chip area and chip design and manufacturing cost, a chip test mode entering method is as follows: a power-on reset signal is monitored through a reset pin of a chip, a time point at which the power-on reset signal is changed from a preset first level to a preset second level is taken as a first time point, a second time point is determined according to the first time point and a preset delay duration, a first time interval is formed by the first time point and the second time point, and if N pulse signals are received by a first interface in the chip within the first time interval, the chip enters a test mode.

[0003] However, after the chip enters the test mode, it still needs to enter a test sub-mode to perform specific testing, and a common test sub-mode entering method is to control the level state of a specific pin or use a test tool, etc. Since the number of test sub-modes is large, using the above method will increase the chip area and improve the chip design and manufacturing cost.

[0004] Therefore, how to more simply enter the chip test sub-mode has become a problem to be solved. SUMMARY

[0005] In view of the above technical problems, the technical solution adopted by the present application is as follows: A chip test sub-mode entering system, the system comprising: a first communication module and its corresponding second interface and third interface, M test sub-modes respectively corresponding AND gates, and a test selector, wherein M is a positive integer; The first communication module comprises a mode input decoder, a mode register and a mode decoder; The second interface is used for inputting encoding information corresponding to the M test sub-modes into the mode input decoder; The mode input decoder is used for writing the encoding information corresponding to the M test sub-modes into the mode register; The third interface is used for inputting sub-mode entering information into the first communication module; The mode decoder sets the signal of the test sub-mode corresponding to the sub-mode entering information to a preset second level according to the sub-mode entering information and the encoding information corresponding to the M test sub-modes in the mode register; The signal of the test sub-mode and a test mode signal are inputs of an AND gate corresponding to the test sub-mode, and the AND gate is an input of the test selector. When the signal of the test sub-mode and the test mode signal are both preset second levels, the test selector enters the test sub-mode.

[0006] Compared with the prior art, the entering system of the chip test sub-mode has obvious beneficial effects, and can achieve considerable technical progress and practicability, and has wide industrial utilization value, and at least has the following beneficial effects: The entering system of the chip test sub-mode comprises a first communication module and corresponding second and third interfaces, M test sub-modes corresponding AND gates, and a test selector, wherein M is a positive integer. The first communication module comprises a mode input decoder, a mode register, and a mode decoder. The second interface is used for inputting encoded information corresponding to the M test sub-modes into the mode input decoder. The mode input decoder is used for writing the encoded information corresponding to the M test sub-modes into the mode register. The third interface is used for inputting sub-mode entering information into the first communication module. The mode decoder sets a signal of a test sub-mode corresponding to the sub-mode entering information to a preset second level according to the sub-mode entering information and the encoded information corresponding to the M test sub-modes in the mode register. For any test sub-mode, the signal of the test sub-mode and a test mode signal are inputs of an AND gate corresponding to the test sub-mode, and the AND gate is an input of the test selector. When the signal of the test sub-mode and the test mode signal are both preset second levels, the test selector enters the test sub-mode.

[0007] It can be known that only two interfaces of the first communication port are needed to configure the mode register and enter the test sub-mode. After entering the test sub-mode, the two interfaces can be released to participate in test excitation input, improve the multiplexing of the interfaces, effectively save the chip area, reduce the cost of chip design and manufacturing, and improve the convenience of entering the chip sub-test mode. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0009] Figure 1 A flowchart of a chip test mode entering method provided by the embodiment one of the present application is shown in the figure; Figure 2 A first circuit structure diagram in a power-on reset monitoring circuit provided by the embodiment two of the present application is shown in the figure; Figure 3 A structure diagram of a chip test sub-mode entering system provided by the embodiment three of the present application is shown in the figure; Figure 4 A circuit structure diagram of a chip reset circuit provided by the embodiment four of the present application is shown in the figure; Figure 5 A circuit structure diagram of a chip scan circuit provided by the embodiment five of the present application is shown in the figure; Figure 6 A structure diagram of a system-in-package chip test system provided by the embodiment six of the present application is shown in the figure; Figure 7 A structure diagram of a system-in-package chip connection test circuit provided by the embodiment seven of the present application is shown in the figure; Figure 8 A structure diagram of a chip forced test circuit provided by the embodiment eight of the present application is shown in the figure; Figure 9 A structure diagram of a chip forced test signal generation circuit provided by the embodiment nine of the present application is shown in the figure. DETAILED DESCRIPTION

[0010] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0011] The embodiment one provides a chip test mode entering method, referring to Figure 1 A flowchart of a chip test mode entering method provided by the embodiment one of the present application is shown in the figure, the method comprises: S101, a power-on reset signal is monitored through a reset pin of a chip, and a time point at which the power-on reset signal is changed from a preset first level to a preset second level is taken as a first time point; S102, a second time point is determined according to the first time point and a preset delay duration; S103, a first time interval is formed by the first time point and the second time point; S104, if a first interface in the chip receives N pulse signals within the first time interval, the chip enters a test mode, and N is a positive integer.

[0012] The chip can be a digital chip or an analog chip, and the chip can be packaged or unpackaged. The power-on reset signal output by the power-on reset circuit cannot be directly accessed from the outside, so the power-on reset signal is monitored through the reset pin outside the tube shell. Further, when the chip is one of the chips in the system package, the reset pin can be connected to the output end of the power-on reset circuit or connected to the reset pin of other chips. When the chip is independently packaged, the reset pin can be connected to the output end of the power-on reset circuit. For example, the chips in the system package can include digital chips and analog chips, and the ports for interconnection between the digital chips and the analog chips are packaged inside the tube shell and cannot be seen, which makes it difficult to test the digital chips. In the embodiment, the power-on reset signal can still be monitored to enter the test mode of the chip when the port of the digital chip is not visible.

[0013] In the embodiment, the power-on reset signal is initially preset to a first level, and the time point at which the power-on reset signal is removed, i.e., the time point at which the power-on reset ends, is the time point at which the power-on reset signal changes from the preset first level to a preset second level.

[0014] The delay duration can be determined by the actual performance of the power-on reset circuit in the chip after production, and the actual performance of the power-on reset circuit is determined by design and manufacturing. According to the monitoring of the power-on reset signal inside the chip, the first time interval can be dynamically determined. It can be known that even if the delay duration is consistent, the first time interval of different chips can be different due to different time points at which the power-on reset signal is removed.

[0015] The first interface can be used to receive input information of the tester. In the case where the chip is packaged, the first interface is outside the packaging tube shell and can be directly accessed. The pulse signal can be generated by an external button connected to the first interface or a clock signal connected to the first interface, without limitation.

[0016] The first time interval and the number N of pulse signals need to be informed to the tester by the chip designer. In the embodiment, N is set to 32, i.e., the tester can only enter the test mode by inputting 32 pulse signals to the first interface within the first time interval. If the number of pulse signals input within the first time interval is not 32, the test mode cannot be entered.

[0017] Specifically, the chip design can also inform the tester of the fixed first sub-interval and the number of pulse signals in the first sub-interval, which belongs to the first time interval, without informing the tester of the determination method of the first time interval and the delay duration, so that the general user cannot enter the test mode of the chip, and the tester can enter the test mode of the chip in the case of permission of the chip design party, further improving the security of entering the test mode of the chip.

[0018] In a specific embodiment, the step S102 comprises: S1021, counting the number of pulses generated by the oscillator from the first time point to obtain a first pulse number; S1022, when the first pulse number is equal to a preset number, changing the reset extension signal from the preset first level to the preset second level, the preset number corresponding to the delay duration; S1023, determining the time point when the reset extension signal is changed from the preset first level to the preset second level as a second time point.

[0019] In the delay duration, the delay duration is realized by the reset extension signal, and the reset extension signal is also generated by the oscillator and the first counter in the chip. The first counter can be used to count the number of pulses generated by the oscillator. The preset number can be determined by the chip design, and the preset number corresponds to the delay duration.

[0020] Specifically, when the chip is powered on, each part in the chip gradually reaches a working state, and the power-on reset signal is withdrawn after ensuring the normal power-on of the chip. In order to ensure that the chip can work normally, it is necessary to set the reset extension signal, so that the chip still maintains a reset state for a period of time after the power-on reset signal is withdrawn, so as to wait for each part in the chip to reach a normal working state. The duration of the maintained reset state is the delay duration. The initial level of the reset extension signal is the preset first level.

[0021] However, since the circuit in the chip after power-on is not necessarily in a working state, the clock generated by the circuit in the chip cannot be used to control the reset extension signal. In the present embodiment, the oscillator is used to realize the reset extension signal. The oscillator starts to work after the chip is powered on, and can output stable pulse signals after a certain period of time. Therefore, in the case that the chip design party has prior information of a general power-on waiting duration, the delay duration can be freely set under the condition that the delay duration is greater than or equal to the general power-on waiting duration. At this time, the duration before the oscillator outputs stable pulse signals can not be considered, and the reset extension signal can be realized by the oscillator after the chip is powered on.

[0022] In a specific embodiment, the oscillator is an LC oscillator.

[0023] The oscillator can also be an RC oscillator. The implementer can select the type of oscillator according to the actual situation. The frequency of the oscillator can be lower than the working frequency of the chip, so as to reduce the number of counts of the first counter corresponding to the delay time. For example, the frequency of the oscillator can be set to 12 MHZ.

[0024] In a specific embodiment, the first interface is a general-purpose interface.

[0025] The general-purpose interface can be a general-purpose input output port (GPIO), which can be configured to be in an input, output, bidirectional, or high-impedance state to meet different application requirements. The working mode of the general-purpose interface can include an input mode, an output mode, a multiplexing function mode, and an analog input mode.

[0026] In a specific embodiment, the preset first level is a low level, and the preset second level is a high level.

[0027] The implementer can determine the level information corresponding to the preset first level and the preset second level according to the specific circuit designed.

[0028] In a specific embodiment, the method further includes: S105, after entering the test mode of the chip, configuring the first communication module to enter a test sub-mode, the test sub-mode at least including a scan mode and a memory self-test.

[0029] The chip includes a first communication module, which can use I2C protocol, UART protocol, SPI protocol, etc. The first communication module includes at least two interfaces. The tester configures the first communication module through the two interfaces in the first communication module to enter the test sub-mode. It should be noted that the above-mentioned protocols usually require at least two interfaces. If the implementer uses a single interface protocol, the first communication module can also include only one interface. The present embodiment aims to ensure that the number of interfaces is as small as possible, thereby saving the number of chip interfaces.

[0030] The test sub-mode can also include self-test, scan test, boundary scan test, etc. In the system-in-package scenario, the test sub-mode can also include scan test and memory self-test corresponding to each chip.

[0031] In a specific embodiment, the test mode corresponds to a first register, and the method further includes: S106, when the read-only memory program of the chip detects that the first register is the first preset value, changing the second register to the second preset value to wait for the first communication module configuration to be completed, the initial value of the second register being the third preset value.

[0032] The first register can be used to record whether the chip enters the test mode. When the chip enters the test mode, the first register is the first preset value, otherwise, the first register is the fourth preset value. When the second register is not the third preset value, the chip does not continue to execute the read-only memory program (ROM program). The read-only memory program can be a program that is executed first after the chip is powered on.

[0033] Specifically, the first preset value can be set to one, the second preset value can be a non-zero positive integer, and the third preset value and the fourth preset value can both be zero.

[0034] The embodiment can effectively avoid the situation that when the first communication module configuration time is too long, the read-only memory program of the chip runs before the test sub-mode, thereby causing the interface of the first communication module to be reconfigured, and ensures the normal operation of the test sub-mode.

[0035] In a specific embodiment, the method further comprises: S107, writing a performance test program into a random access memory; S108, writing the performance test program in the random access memory into the second register corresponding to the address; S109, when the read-only memory program of the chip detects that the second register is not the third preset value, jumping to the address in the random access memory.

[0036] The performance test program can be a program that needs to be executed when the chip performs performance test. The performance test program usually needs to be tested in the functional mode of the chip rather than in the test mode, so it cannot enter the performance test through the test mode.

[0037] The embodiment writes the performance test program into the random access memory (RAM), and then writes the performance test program in the random access memory into the second register corresponding to the address. When the ROM program is executed, the performance test program is executed by jumping to the address.

[0038] In the first embodiment, the first time interval is determined by the power-on reset signal monitored by the reset pin of the chip and the delay time, the tester inputs a specified number of pulse signals in the first time interval to enter the test mode of the chip, without entering the test mode of the chip through the test mode interface, and the first time interval is dynamically determined by the power-on reset signal of the chip itself, and only when the specified number of pulse signals are input in the first time interval, the test mode of the chip can be entered, the safety of the test mode entering process is improved, and without the interface provided by the chip for entering the test mode, the cost of the chip is effectively saved.

[0039] The second embodiment provides a power-on reset monitoring circuit, referring to Figure 2 The second embodiment provides a first circuit structure diagram of a power-on reset monitoring circuit, the circuit comprises a power supply, a pull-up resistor, a first inverter, a first tri-state gate, a second tri-state gate, a first pad and a second pad corresponding to a reset pin; The output end of the power-on reset circuit is connected with the input end of the first inverter; The output end of the first inverter is connected with the first output enable end of the first tri-state gate; The input end of the first tri-state gate is grounded, the output end of the first tri-state gate is connected with the first pad, the first pad is bidirectionally connected with the second pad, and the first pad is further connected with the input end of the second tri-state gate; The input enable end of the second tri-state gate is connected with a preset second level; The second pad is further connected with the power supply through a pull-up resistor; When the power-on reset signal output by the power-on reset circuit is a preset first level, the first tri-state gate is turned on, and the second pad corresponding to the reset pin is the preset first level; When the power-on reset signal output by the power-on reset circuit is changed from the preset first level to the preset second level, the first tri-state gate is closed, and the second pad corresponding to the reset pin is gradually changed from the preset first level to the preset second level.

[0040] When the power-on reset signal output by the power-on reset circuit is a preset first level, it can be indicated that the chip is in a power-on reset state, when the power-on reset signal output by the power-on reset circuit is changed from the preset first level to the preset second level, it can be indicated that the power-on reset signal of the chip is removed, and when the power-on reset signal output by the power-on reset circuit is the preset second level, it can be indicated that the chip is not in a power-on reset state.

[0041] However, since the power-on reset signal is usually inside the chip, the power-on reset signal can be sent from one chip to another chip in the package, or generated by the power-on reset circuit inside the chip, and it is difficult to effectively monitor the change of the power-on reset signal outside the chip, thereby causing the first time point to be difficult to accurately determine in the entering method of the chip test mode provided in Embodiment One, so that even the chip designer cannot accurately determine the first time interval, and further causing the entering method of the chip test mode to be unreliable.

[0042] Specifically, when the power-on reset signal output by the power-on reset circuit is a preset first level, the first tri-state gate is turned on, and since the input end of the first tri-state gate is grounded, the second pad corresponding to the reset pin will remain at the preset first level.

[0043] When the power-on reset signal output by the power-on reset circuit changes from the preset first level to a preset second level, the first tri-state gate is closed, and the second pad corresponding to the reset pin gradually changes from the preset first level to the preset second level. It can be seen that the change of the power-on reset signal corresponds to the change of the level of the second pad corresponding to the reset pin.

[0044] In addition, the second pad corresponding to the reset pin is reused to monitor the power-on reset signal, without the need to additionally add a pin for monitoring, thereby effectively saving the design and manufacturing cost of the chip and the area of the chip.

[0045] In a specific embodiment, when the power-on reset monitoring circuit is powered on, the second pad corresponding to the reset pin is at the preset second level.

[0046] In order to maintain the preset level state of the second pad when the power-on reset signal does not act on the power-on reset monitoring circuit, the second pad is connected to the power supply through a pull-up resistor in this embodiment. Before the power-on reset monitoring circuit is powered on and the power-on reset signal acts on the power-on reset monitoring circuit, the second pad maintains a stable preset second level.

[0047] In a specific embodiment, the power-on reset monitoring circuit is disposed in a chip, and the second pad corresponding to the reset pin is disposed outside the chip.

[0048] In a specific embodiment, the reset pin is also used for thermal reset. When the reset pin is used for thermal reset, a preset first level is input to the reset pin, and the preset first level is transmitted to the chip through the output end of the second tri-state gate.

[0049] The second pad corresponding to the reset pin is located outside the chip, and can be monitored conveniently, thereby facilitating the chip designer or tester to accurately determine the removal time point of the power-on reset signal.

[0050] In a specific embodiment, the preset first level is a low level, and the preset second level is a high level.

[0051] In a specific embodiment, the power-on reset monitoring circuit is configured to monitor the power-on reset signal by monitoring the reset pin, and determine the first time point as a time point at which the power-on reset signal is changed from the preset first level to the preset second level. According to the first time point and a preset delay duration, a second time point is determined. A first time interval is formed by the first time point and the second time point. If the first interface in the chip receives N pulse signals within the first time interval, the chip enters a test mode, and N is a positive integer.

[0052] In a specific embodiment, the first interface is a general interface.

[0053] In a specific embodiment, N is 32.

[0054] In the second embodiment, the power-on reset signal change corresponds to the level change of the reset pin through the power-on reset monitoring circuit, so that the power-on reset signal that cannot be directly monitored in the chip can be monitored by monitoring the level change of the reset pin, a more accurate removal time point of the chip power-on reset signal can be obtained, and the reliability of entering the chip test mode is improved.

[0055] The third embodiment provides a system for entering a chip test sub-mode, which includes a first communication module and a second interface and a third interface corresponding thereto, M test sub-modes corresponding to an AND gate, and a test selector, wherein M is a positive integer. The first communication module includes a mode input decoder, a mode register, and a mode decoder. The second interface is configured to input encoded information corresponding to the M test sub-modes to the mode input decoder. The mode input decoder is configured to write the encoded information corresponding to the M test sub-modes to the mode register. The third interface is configured to input sub-mode entering information to the first communication module. The mode decoder sets the signal of the test sub-mode corresponding to the sub-mode entering information as a preset second level according to the sub-mode entering information, the M test sub-modes respectively corresponding to the encoding information in the mode register; For any test sub-mode, the signal of the test sub-mode and the test mode signal are inputs of an AND gate corresponding to the test sub-mode, and the AND gate corresponding to the test sub-mode is an input of the test selector; When the signal of the test sub-mode and the test mode signal are both preset second levels, the test selector enters the test sub-mode.

[0056] When the test mode signal is a preset second level, it indicates that the chip is currently in the test mode. At this time, if the signal of any test sub-mode is also a preset second level, the AND gate corresponding to the test sub-mode outputs a preset second level.

[0057] When the test mode signal is not a preset second level, it indicates that the chip is not currently in the test mode. At this time, even if there is a test sub-mode signal that is a preset second level, the output of the AND gate corresponding to the test sub-mode is still a preset first level, and the test sub-mode cannot be entered.

[0058] In a specific embodiment, the encoding information is represented by K-bit binary encoding. Correspondingly, the mode register includes K sub-registers. Wherein, K satisfies the condition: 2 K+1 ≥M, K is a positive integer and min(K).

[0059] For example, when M=4, two-bit binary encoding is needed to represent, at this time, two sub-registers are needed to represent the encoding information, when M=5, three-bit binary encoding is needed to represent, at this time, three sub-registers are needed to represent the encoding information.

[0060] In a specific embodiment, the encoding information is represented by one-hot encoding. Correspondingly, the mode register includes M sub-registers, each of which corresponds to the encoding information of a test sub-mode.

[0061] Wherein, one-hot encoding is also called one-bit effective encoding. In this embodiment, M M-bit registers are used to encode M test sub-modes, each test sub-mode has a unique corresponding register bit, and only one register bit is effective in a single encoding information.

[0062] In a specific embodiment, the first communication module adopts I2C protocol.

[0063] The first communication module can also adopt I2C protocol, UART protocol, SPI protocol, etc., and the implementer needs to ensure that the first communication module includes at least two interfaces as the second interface and the third interface.

[0064] In a specific embodiment, the preset second level is a high level.

[0065] In a specific embodiment, the second interface and the third interface are both general interfaces.

[0066] The general interface can be a general purpose input output port (GPIO) and can be configured as an input, an output, bidirectional, or high impedance, etc. to meet different application requirements. The working mode of the general interface can include an input mode, an output mode, a multiplexing function mode, and an analog input mode, etc.

[0067] In a specific embodiment, when entering any test sub-mode, the second interface and the third interface are both mapped to the required interface of the test sub-mode.

[0068] In this embodiment, the second interface and the third interface are multiplexed to serve as the required interface of the test sub-mode after entering the test sub-mode, thereby further saving the number of interfaces, saving the chip area, and reducing the cost of chip design and manufacturing.

[0069] In a specific embodiment, the M test sub-modes include at least a scan mode and a memory self-test.

[0070] The test sub-mode can also include self-test, scan test, boundary scan test, etc. In the system-in-package scenario, the test sub-mode can also include scan test and memory self-test corresponding to each chip, etc.

[0071] Referring to Figure 3 The entering system of a chip test sub-mode provided in Embodiment Three of the present application is shown in the structural schematic diagram. The entering system can be applied in the system-in-package chip scenario. Taking the system-in-package chip scenario including a first chip and a second chip as an example, the entering system can be applied in the first chip. In such a case, the test sub-mode can include a first chip scan mode, a first chip memory self-test mode, a second chip test mode, etc.

[0072] In the third embodiment, only two interfaces of the first communication port are needed to configure the mode register and enter the test sub-mode, and the two interfaces are released after entering the test sub-mode to participate in the test excitation input, thereby improving the multiplexing of the interface, effectively saving the chip area, reducing the cost of chip design and manufacturing, and improving the convenience of entering the chip sub-test mode.

[0073] The fourth embodiment provides a chip reset circuit. Figure 4 The fourth embodiment provides a circuit structure schematic diagram of a chip reset circuit, the circuit comprises a hot reset signal, a power-on reset signal, a first AND gate, an oscillator, a first communication module, a register corresponding to a test mode, and M registers corresponding to M test sub-modes, wherein M is a positive integer. The power-on reset signal is connected with the oscillator, the register corresponding to the test mode, and the first input end of the first AND gate. The hot reset signal is connected with the second input end of the first AND gate. The output end of the first AND gate is used to output a global reset signal. The global reset signal is connected with the first communication module and the M registers corresponding to the M test sub-modes.

[0074] The oscillator can be used to count the number of pulses in combination with the first counter, and then determine the delay duration, the delay duration and the first time point at which the monitoring power-on reset signal changes from a preset first level to a preset second level form a first time interval, and when the first interface in the chip receives N pulse signals within the first time interval, the chip enters the test mode. In this embodiment, the register corresponding to the test mode can include a first counter, a second counter for counting the number of pulse signals of the first interface, a first register corresponding to the test mode, etc.

[0075] The M registers corresponding to the M test sub-modes can include mode registers corresponding to the test sub-modes.

[0076] In a specific implementation, when the power-on reset signal is a preset first level, the oscillator and the register corresponding to the test mode are both in a reset state.

[0077] The power-on reset signal being a preset first level can indicate that the power-on reset signal is in an active state, and at this time the oscillator and the register corresponding to the test mode are both in a reset state.

[0078] Specifically, the power-on reset signal is connected with the oscillator and the register corresponding to the test mode through a NOT gate, and when the power-on reset signal is a preset first level, the oscillator and the register corresponding to the test mode receive a preset second level.

[0079] In a specific embodiment, the global reset signal is the preset first level when the power-on reset signal or the thermal reset signal is the preset first level. When the global reset signal is the preset first level, the registers corresponding to the first communication module and the M test sub-modes are all in the reset state.

[0080] In the embodiment, the global reset signal being the preset first level means that the global reset signal is in the active state. The global reset signal is connected to the registers corresponding to the first communication module and the M test sub-modes through NAND gates. When the global reset signal is the preset first level, the registers corresponding to the first communication module and the M test sub-modes receive the preset second level.

[0081] In a specific embodiment, the preset first level is a low level.

[0082] In a specific embodiment, the registers corresponding to the oscillator and the test mode are not in the reset state when the power-on reset signal is the preset second level.

[0083] In the embodiment, the power-on reset signal being the preset second level means that the power-on reset signal is not in the active state. At this time, the registers corresponding to the oscillator and the test mode are not in the reset state.

[0084] In a specific embodiment, the global reset signal is the preset second level when the power-on reset signal and the thermal reset signal are both the preset second level. When the global reset signal is the preset second level, the registers corresponding to the first communication module and the M test sub-modes are not in the reset state.

[0085] In the embodiment, the global reset signal being the preset second level means that the global reset signal is not in the active state. At this time, the registers corresponding to the first communication module and the M test sub-modes are not in the reset state.

[0086] In a specific embodiment, the preset second level is a high level.

[0087] In a specific embodiment, the power-on reset signal is output by a power-on reset circuit, and the thermal reset signal corresponds to a reset pin.

[0088] In the embodiment, the chip reset system can be deployed in a chip. Generally, the power-on reset circuit is located in the chip and cannot directly obtain the power-on reset signal. The reset pin can be located outside the chip and can directly input the thermal reset signal by a user or a tester.

[0089] In this embodiment four, the circuit design is made so that the power-on reset signal can act on the test mode related registers and oscillators, and the test sub-mode related registers and the first communication module, ensuring the effectiveness of the power-on reset, the hot reset signal can only act on the test sub-mode related registers and the first communication module, without resetting the test mode related registers and oscillators, thereby avoiding the hot reset signal affecting the normal operation of the test mode, improving the stability of the chip reset system, and further improving the stability of entering the chip test mode and the test sub-mode. In addition, the implementer can quickly switch between sub-test modes through hot reset without switching modes through power-on and power-off, avoiding the introduction of additional time consumption when switching modes through power-on reset, thereby introducing additional test costs.

[0090] This embodiment five provides a chip scan circuit, see Figure 5 , a circuit structure schematic diagram of a chip scan circuit provided by the embodiment five of the application, the circuit comprises: a scan mode selection signal, P first scan units {q1, q2, …, q p , …, q P}, S second scan units {r1, r2, …, r s , …, r S}, a second interface, a third interface, a fourth interface, a fifth interface, a first selector and a second selector, wherein q p is the pth first scan unit, p is an integer in the range of [1, P], r s is the sth second scan unit, s is an integer in the range of [1, S], the first selector comprises a first enable end, a first selection input port, a second selection input port and a first selection output port, and the second selector comprises a second enable end, a third selection input port, a fourth selection input port and a second selection output port. The scan mode selection signal is connected with the first enable end of the first selector and the second enable end of the second selector respectively. The second interface is connected with the input end of the first first scan unit q1. The output end of the u th first scan unit q u is connected with the input end of the u+1 th first scan unit q u+1 , wherein u is an integer in the range of [1, P-1]. The output end of the P th first scan unit q P is connected with the second selection input port of the first selector and the third selection input port of the second selector respectively. The fourth interface is connected with the fourth selection input port of the second selector. The second selection output port of the second selector is connected with the input end of the first second scan unit r1; The output end of the vth second scan unit q v is connected with the input end of the (v+1)th second scan unit q v+1 , wherein v is an integer in the range of [1, S-1]; The output end of the Sth second scan unit r S is connected with the fifth interface and the first selection input port of the first selector respectively; The first selection output port of the first selector is connected with the third interface.

[0091] When the chip is in the test mode, the chip can be configured to perform the scan mode in the test sub-mode through the second interface and the third interface. When the chip is in the scan mode, the second interface can be configured to receive the scan input signal, and the third interface can be configured to output the scan output signal.

[0092] The first scan unit and the second scan unit are scan units, which can include a data selector and a flip-flop. In the embodiment, the data selector can be a two-way data selector, the input of the data selector can include a function input and a scan input, the scan input can be connected with the second interface, the previous scan unit or the second selection output port of the second selector, and the flip-flop can be a D flip-flop.

[0093] In a specific embodiment, when the scan mode selection signal is a preset first level, a first path formed by the first selection input port and the first selection output port in the first selector is turned on, and a second path formed by the second selection input port and the first selection output port in the first selector is turned off.

[0094] In a specific embodiment, when the scan mode selection signal is the preset first level, a third path formed by the third selection input port and the second selection output port in the second selector is turned on, and a fourth path formed by the fourth selection input port and the second selection output port in the second selector is turned off.

[0095] In a specific embodiment, when the scan mode selection signal is the preset first level, a first scan chain is formed by the second interface, all the first scan units, all the second scan units and the third interface, and the first scan chain is used to perform the full scan mode.

[0096] The preset first level can be a low level. When the second path formed by the second selection input port and the first selection output port in the first selector is closed, and the third path formed by the third selection input port and the second selection output port in the second selector is turned on, the output end of the Pth first scan unit q P is connected with the input end of the first second scan unit r1 through the third path. In this case, the second interface can be used to input the scan input signal of the first scan chain, and the third interface can be used to output the scan output signal of the first scan chain.

[0097] In a specific embodiment, when the scan mode selection signal is a preset second level, the first path formed by the first selection input port and the first selection output port in the first selector is closed, and the second path formed by the second selection input port and the first selection output port in the first selector is turned on.

[0098] In a specific embodiment, when the scan mode selection signal is the preset second level, the third path formed by the third selection input port and the second selection output port in the second selector is closed, and the fourth path formed by the fourth selection input port and the second selection output port in the second selector is turned on.

[0099] In a specific embodiment, when the scan mode selection signal is the preset second level, a second scan chain is formed by the second interface, all the first scan units, and the third interface. When the scan mode selection signal is the preset second level, a third scan chain is formed by the fourth interface, all the second scan units, and the fifth interface. The second scan chain and the third scan chain are used to perform a compressed scan mode.

[0100] The preset second level can be a high level. When the second path formed by the second selection input port and the first selection output port in the first selector is turned on, the output end of the Pth first scan unit q P is connected with the third interface through the second path. In this case, the second interface can be used to input the scan input signal of the second scan chain, and the third interface can be used to output the scan output signal of the second scan chain.

[0101] When the fourth path formed by the fourth selection input port and the second selection output port in the second selector is turned on, the second selection output port of the second selector is connected with the input end of the first second scan unit r1. In this case, the fourth interface can be used to input the scan input signal of the third scan chain, and the fifth interface can be used to output the scan output signal of the third scan chain.

[0102] In the fifth embodiment, the circuit in the designed scan mode is used, so that the connection mode of the scan chain can be switched by switching the level of the scan mode selection signal, thereby adapting to the full scan mode and the compressed scan mode, greatly improving the flexibility of the scan test, and thereby being applicable to complex test requirements.

[0103] The sixth embodiment provides a test system of a systemized package chip. Figure 6 A structural schematic diagram of a test system of a systemized package chip is provided in the sixth embodiment of the application, and the system comprises a second interface, a third interface, a first chip, a second chip and a metal layer. The second interface transmits a first clock signal to the first communication module, and the third interface transmits a first data signal to the first communication module. The first clock signal and a second clock signal output by the second communication module are connected to the third pad through the third selector, and the third pad transmits the selection result of the third selector to the fifth pad through the metal layer. The first data signal and a second data signal output by the second communication module are connected to the fourth pad through the fourth selector, and the fourth pad transmits the selection result of the fourth selector to the sixth pad through the metal layer, and the second clock signal and the second data signal are used to configure the third communication module to enter a test sub-mode of the second chip. When the system is in a first test state, the selection result of the third selector is the same as the first clock signal, and the selection result of the fourth selector is the same as the first data signal. When the system is in a second test state, the second communication module is controlled by the first communication module, the selection result of the third selector is the same as the second clock signal, and the selection result of the fourth selector is the same as the second data signal.

[0104] The metal layer can be a redistribution layer (RDL) metal layer, the first chip can be a chip containing an interface outside a package shell, the second chip can be a chip not containing an interface outside a package shell, and in general, the second chip is controlled by the first chip. In the present embodiment, the first chip can be a digital chip, and the second chip can be an analog chip.

[0105] In the embodiment, when the tester needs to test the second chip, the first test state or the second test state is entered.

[0106] Specifically, when the system is in the first test state, the connection line between the second interface and the third selector or the connection line between the third interface and the fourth selector can be faulty, so that the second chip cannot normally enter the test sub-mode.

[0107] When the system is in the second test state, the control logic of the first communication module and the second communication module or the control logic of the second communication module and the third communication module can also be faulty, so that the second chip cannot normally enter the test sub-mode. Therefore, the embodiment adopts a test state switchable manner, effectively improving the reliability and flexibility of the second chip entering the test sub-mode.

[0108] In a specific implementation, the first chip and the second chip are located inside a package tube shell, and the pad corresponding to the second interface and the pad corresponding to the third interface are located outside the package tube shell.

[0109] In a specific implementation, the test sub-mode includes at least a scan mode and a memory self-test.

[0110] The test sub-mode can further include self-checking test, scan test, boundary scan test, etc. In a specific implementation, the third communication module further includes a seventh pad.

[0111] In the embodiment, the test sub-mode of the first chip contains the second chip test mode, the seventh pad is connected with a signal corresponding to the second chip test mode, the seventh pad serves as a test mode trigger of the second chip, and the seventh pad is not packaged outside the chip tube shell, thereby saving a large amount of cost.

[0112] In a specific implementation, the third communication module includes a mode input decoder, a mode register and a mode decoder. The selection result of the third selector is used to input coding information corresponding to M test sub-modes to the mode input decoder, M being a positive integer. The mode input decoder is used to write the coding information corresponding to the M test sub-modes into the mode register. The selection result of the fourth selector is used to input sub-mode entering information to the third communication module. The mode decoder makes the second chip enter a test sub-mode corresponding to the sub-mode entering information according to the sub-mode entering information and the coding information corresponding to the M test sub-modes in the mode register.

[0113] Wherein, the M test sub-modes correspond to the encoding information and the signal corresponding to the seventh pad after the signal corresponding to the seventh pad is ANDed, the test sub-mode entered by the second chip is determined, when the signal corresponding to the seventh pad is a preset first level, the second chip is in a function mode, at this time, the test sub-mode cannot be entered, when the signal corresponding to the seventh pad is a preset second level, the second chip is in a test mode, at this time, the test sub-mode can be normally entered.

[0114] In a specific embodiment, the encoding information is represented by K-bit binary coding; Correspondingly, the mode register comprises K sub-registers; Wherein, K satisfies the condition: 2 K+1 ≥M, K is a positive integer and min(K).

[0115] For example, when M=4, two-bit binary coding is needed to represent, at this time, two sub-registers are needed to represent the encoding information, when M=5, three-bit binary coding is needed to represent, at this time, three sub-registers are needed to represent the encoding information.

[0116] In a specific embodiment, the encoding information is represented by one-hot coding; Correspondingly, the mode register comprises M sub-registers, each of which corresponds to the encoding information of a test sub-mode.

[0117] In this embodiment, M M-bit registers are used to encode M test sub-modes, each test sub-mode has a unique corresponding register bit, and only one register bit is valid in a single encoding information.

[0118] In this embodiment, only the second interface and the third interface of the first chip are needed to control the second chip to enter the test sub-mode, which improves the convenience of chip testing in the system packaging scenario, and the test system can select the first test state and the second test state to realize different second chip test sub-mode entering modes, effectively avoiding the second chip from being unable to enter the test sub-mode due to connection faults between chips, and improving the reliability and flexibility of chip testing in the system packaging scenario.

[0119] This embodiment seven provides a connection test circuit of a system packaging chip, referring to Figure 7 This embodiment seven provides a structure schematic diagram of a connection test circuit of a system packaging chip, the circuit comprises a first chip and a second chip, wherein the first chip comprises a second interface, a third interface and A first connection units {b1, b2, …, b a , …, b A}, the second chip includes A second connection units {c1, c2, …, c a , …, c A}, b a is the a-th first connection unit in the first chip, a is an integer within the range of [1, A], c a is the a-th second connection unit in the second chip, and A is an even number; The input end of the second interface is used to receive the connection test sample signal, and the output end of the second interface is connected to b1; For the f-th second connection unit c f , if f is an odd number, then c f is connected to c f+1 , f is an integer within the range of [1, A]; If f is an even number, then c f is connected to b f ; For the e-th first connection unit b e , if e is an odd number, then b e is connected to c e ; If e is an even number and e < A, then b e is connected to b e+1 ; If e = A, then b e is connected to the input end of the third interface, and the output end of the third interface is used to output the connection test real signal, and the connection test real signal is used to be compared with the connection test sample signal to obtain the connection test result of the first chip and the second chip.

[0120] Among them, the second interface is configured as the input of the connection test in the connection test system, and the third interface is configured as the output of the connection test in the connection test system.

[0121] Specifically, when the connection test real signal is consistent with the connection test sample signal, it can indicate that the connection test between the first chip and the second chip passes, and when the connection test real signal is inconsistent with the connection test sample signal, it can indicate that the connection test between the first chip and the second chip fails.

[0122] Since the second chip does not include pins exposed outside the package case, the second chip needs to receive signals sent to it through the first chip. Similarly, the second chip also needs to output signals to the first chip. It can be seen that the number A of the second connection units included in the second chip is an even number. Since the connection between chips is tested in this embodiment, and any second connection unit in the second chip has a first connection unit with a unique connection relationship with it, the number of first connection units in the first chip that have a connection relationship with the second chip is also A.

[0123] It should be noted that in the embodiment, when the connection similar to b e The expression of connection is specifically referring to sending signals from b e to c e , instead of sending signals from c e to b e . e

[0124] In a specific embodiment, the first connection unit comprises a first reference input end, a first reference output end, a first reference tri-state gate, a first reference enable end and a first connection end; The first reference input end is connected with the input end of the first reference tri-state gate; The first reference enable end is connected with the enable end of the first reference tri-state gate; The output end of the first reference tri-state gate is bidirectionally connected with the first connection end; The output end of the first reference tri-state gate is also connected with the first reference output end.

[0125] In a specific embodiment, the second connection unit comprises a second reference input end, a second reference output end, a second reference tri-state gate, a second reference enable end and a second connection end; The second reference input end is connected with the input end of the second reference tri-state gate; The second reference enable end is connected with the enable end of the second reference tri-state gate; The output end of the second reference tri-state gate is bidirectionally connected with the second connection end; The output end of the second reference tri-state gate is also connected with the second reference output end.

[0126] In a specific embodiment, for the e-th first connection unit b e , if b e is connected with c e , then b e is connected with the second connection end included in c e through the first connection end included in b , if b e is connected with b e+1 , then b e is connected with the first reference input end included in b e+1 through the first reference output end included in b e , if b e is connected with the input end of the third interface, then b e is connected with the input end of the third interface through the first reference output end included in b

[0127] ​Among them, the first reference tri-state gate can be enabled by a high level, and correspondingly, if b e With b e+1 If connected, then b e The first reference enable pin is low, b e+1 The first reference enable pin is high, if b e With c e If connected, then b e The first reference enable pin is high.

[0128] In one specific implementation, for the f-th second connection unit c f If c f With b f If connected, then c f Through its included second connection end and b f Includes a second connection end connection; If c f With c f+1 If connected, then c f Through its included second reference output terminal and c f+1 Includes a second reference input connection.

[0129] Among them, the second reference tri-state gate can be enabled by a high level, and correspondingly, if c f With b f If connected, then c f The second reference enable pin is high, if c f The second reference enable pin is low, c f+1 The second reference enable pin is high.

[0130] In one specific implementation, the first chip further includes a third connection unit; The output of the second interface is connected to b1, and includes: The output of the second interface is connected to b1 through the third connection unit.

[0131] In one specific implementation, the third connection unit includes a third reference input terminal, a third reference output terminal, a third reference tri-state gate, a third reference enable terminal, and a third connection terminal; The third reference input terminal is connected to the input terminal of the third reference tri-state gate; The third reference enable terminal is connected to the enable terminal of the third reference tri-state gate; The output terminal of the third reference tri-state gate is bidirectionally connected to the third connection terminal; The output terminal of the third reference tri-state gate is also connected to the third reference output terminal; The output end of the second interface is connected with the third connection end.

[0132] The third reference tri-state gate can be high level enabled, and the third reference enable end is low level.

[0133] In a specific embodiment, the first chip further comprises a fourth connection unit. The b e The input end of the third interface is connected with the fourth connection unit. The b e The input end of the third interface is connected with the fourth connection unit.

[0134] The fourth connection unit comprises a fourth reference input end, a fourth reference output end, a fourth reference tri-state gate, a fourth reference enable end and a fourth connection end. e The first reference output end is connected with the fourth reference input end, the fourth reference enable end is connected with the enable end of the fourth reference tri-state gate, the output end of the fourth reference tri-state gate is bidirectionally connected with the fourth connection end, the output end of the fourth reference tri-state gate is further connected with the fourth reference output end, and the fourth connection end is connected with the input end of the third interface.

[0135] The fourth reference tri-state gate can be high level enabled, and the fourth reference enable end is high level.

[0136] In the seventh embodiment, the connection relationship between the first chip and the second chip is tested through a path, so that whether the connection between the first chip and the second chip is abnormal can be quickly and effectively determined, thereby the effectiveness of the connection between the chips can be accurately tested, it is ensured that the interconnection between the first chip and the second chip is not invalid due to defects in the production process such as inter-chip interconnection and packaging, and the reliability of the test sub-mode entering in the system packaging scene is improved.

[0137] The eighth embodiment of the present application provides a forced test circuit of a chip. Figure 8 The forced test circuit of the chip provided in the eighth embodiment of the present application is a structural schematic diagram of the forced test circuit of the chip, and the circuit comprises a target interface, a forced test signal, a first target tri-state gate, a second target tri-state gate, a first target AND gate, a first target OR gate, a first target inverter, a second target inverter, a first target output end, a first target input end, a first control signal and a second control signal. The forced test signal is connected with the first input end of the first target AND gate through the first target inverter. The first control signal is connected with the second input end of the first target AND gate. The output end of the first target AND gate is connected with the enable end of the first target tri-state gate through the second target inverter. the first target output end and an input end of the first target tri-state gate are connected; an output end of the first target tri-state gate is connected with the target interface bidirectionally; the output end of the first target tri-state gate is also connected with an input end of the second target tri-state gate; the forced test signal is also connected with a first input end of the first target OR gate; the second control signal is connected with a second input end of the first target OR gate; an output end of the first target OR gate is connected with an enable end of the second target tri-state gate; an output end of the second target tri-state gate is connected with the first target input end.

[0138] In a specific embodiment, the chip comprises a second interface and a third interface, and the target interface is the second interface or the third interface.

[0139] In the chip, the second interface and the third interface each have a corresponding forced test circuit to ensure that the second interface and the third interface are in a conducting state when controlled by the forced test signal.

[0140] In a specific embodiment, the pad corresponding to the target interface is exposed outside the package shell of the chip.

[0141] In the chip, the pad corresponding to the target interface can be accessed by a user or a tester.

[0142] In a specific embodiment, when the forced test signal is high, the first target AND gate outputs low, and the first target tri-state gate is in a cut-off state.

[0143] In the chip, the first target tri-state gate is low-level enabled, when the forced test signal is high, low is outputted through the first target inverter, low is outputted through the first target AND gate, high is outputted through the second target inverter, and the first target tri-state gate is in a cut-off state, i.e., the first target output end cannot send a signal to the target interface.

[0144] In a specific embodiment, when the forced test signal is high, the first target OR gate outputs high, and the first target tri-state gate is in a conducting state.

[0145] In the chip, the second target tri-state gate is high-level enabled, when the forced test signal is high, high is outputted through the first target OR gate, and the first target tri-state gate is in a conducting state, i.e., the target interface can send a signal to the first target input end.

[0146] In a specific embodiment, when the forced test signal is low, the circuit state of the first target tri-state gate is determined by the first control signal, and the circuit state includes the off state and the on state.

[0147] When the forced test signal is low, if the first control signal is high, the first target tri-state gate is in the on state, and if the first control signal is low, the first target tri-state gate is in the off state.

[0148] In a specific embodiment, when the forced test signal is low, the circuit state of the second target tri-state gate is determined by the second control signal.

[0149] When the forced test signal is low, if the second control signal is high, the second target tri-state gate is in the on state, and if the second control signal is low, the second target tri-state gate is in the off state.

[0150] It should be noted that in the present embodiment, the forced test signal is high, which means that the forced test signal is effective. The implementer can adjust the forced test signal to be low to indicate that the forced test signal is effective according to the actual situation. Correspondingly, the forced test signal can be directly connected to the first input terminal of the first target AND gate. Similarly, the forced test signal can be connected to the first input terminal of the first target OR gate through an inverter. In particular, the implementer can also adjust the enablement of the first target tri-state gate and the second target tri-state gate to ensure that the target interface is in the input state when the forced test signal is effective. Details are not described herein again. The implementer should know that the adjustment of the above circuit is within the protection scope of the present application.

[0151] In a specific embodiment, the forced test signal is generated by a forced test signal generation circuit.

[0152] In the eighth embodiment, a forced test signal is introduced into the test circuit. When the forced test signal is high, the first target tri-state gate is in the off state, and the second target tri-state gate is in the on state, thereby ensuring that the target interface is in the input state. The target interface can be the second interface and the third interface, thereby ensuring that the second interface and the third interface remain in the input state in the test mode to receive the configuration of the test sub-mode, i.e., improving the priority of the test sub-mode configuration.

[0153] The ninth embodiment provides a forced test signal generation circuit of a chip. Referring to Figure 9 The ninth embodiment provides a structure schematic diagram of the forced test signal generation circuit of the chip. The circuit includes a first target pad corresponding to an interactive interface, a second target pad, a target pull-up resistor, a third target tri-state gate, a fourth target tri-state gate, a power-on reset signal, a power-on reset delay signal, a third target inverter, and a latch. the first target pad is connected with the target pull-up resistor; the first target pad is also bidirectionally connected with the second target pad; the second target pad is connected with the output end of the third target tri-state gate and the input end of the fourth target tri-state gate respectively; the power-on reset delay signal is connected with the enable end of the third target tri-state gate through the third target inverter; the power-on reset delay signal is also connected with the enable end of the fourth target tri-state gate; the output end of the fourth target tri-state gate is connected with the input end of the latch; the power-on reset signal is connected with the control end of the latch; the output end of the latch is used for outputting the forced test signal.

[0154] Wherein, the target pull-up resistor is connected with the power supply, when the power-on reset delay signal is high, the third target tri-state gate is cut off, the fourth target tri-state gate is turned on, and the latch can receive the signal sent by the interactive interface, when the power-on reset delay signal is low, the third target tri-state gate is turned on, the fourth target tri-state gate is cut off, and the latch cannot receive the signal sent by the interactive interface.

[0155] In a specific embodiment, the first target pad is exposed outside the package shell of the chip.

[0156] In a specific embodiment, the circuit further comprises an oscillator, a first target flip-flop, a second target flip-flop and a fourth target inverter; the oscillator is connected with the clock end of the first target flip-flop and the clock end of the second target flip-flop respectively; the power-on reset signal is connected with the input end of the first target flip-flop; the output end of the first target flip-flop is connected with the input end of the second target flip-flop; the output end of the second target flip-flop is used for outputting the power-on reset delay signal through the fourth target inverter.

[0157] Wherein, the oscillator starts to work after the chip is powered on, therefore, in order to ensure that the forced test signal can respond to the generation demand in time, the oscillator is used as the clock source of the first target flip-flop and the second target flip-flop to delay the power-on reset signal.

[0158] In a specific embodiment, the oscillator is an LC oscillator.

[0159] The oscillator can also be an RC oscillator, and the implementer can select the type of oscillator according to actual conditions, which is not limited herein.

[0160] In a specific embodiment, the interaction interface is a general interface, and accordingly, the circuit further includes a second target input end and a second target output end. The output end of the fourth target tri-state gate is connected to the input end of the latch through the second target input end. The second target output end is connected to the input end of the third target tri-state gate.

[0161] The general interface can be a general purpose input output port (GPIO) that can be configured to be in an input, output, bidirectional, or high impedance state to meet different application requirements, and therefore, the second target input end and the second target output end are needed to facilitate user or tester configuration.

[0162] In a specific embodiment, the time point when the power-on reset signal changes from low to high is taken as a first target time point, the time point when the power-on reset delay signal changes from high to low is taken as a second target time point, and a first target time interval is formed by the first target time point and the second target time point. If the first target pad is grounded at any time point before the first target time point or at any time point in the first target time interval, the latch outputs a high-level forced test signal.

[0163] The latch can be triggered by low level. When the power-on reset signal as a control signal changes from low to high, the signal received by the interaction interface is sampled. Since the power-on reset delay signal is delayed compared to the power-on reset signal, the power-on reset delay signal is still high at this time, i.e., the fourth target tri-state gate is still in the on state, and the signal received by the interaction interface can continue to be sent to the latch. Therefore, when the first target pad is grounded at any time point before the first target time point or at any time point in the first target time interval, the latch outputs a high-level forced test signal, so that the level of the signal received by the interaction interface needs to be maintained for a certain period of time to be accurately sampled, thereby improving the reliability of the forced test signal generation.

[0164] In a specific embodiment, if the first target pad is not grounded at any time point before the first target time point or at any time point in the first target time interval, the second target pad is high, and the latch outputs a low-level forced test signal.

[0165] When the first target pad is not grounded, the first target pad is connected with the power supply through a target pull-up resistor, and the level of the first target pad gradually rises to a high level, and correspondingly, the second target pad is at a high level, and the latch outputs a low level forced test signal.

[0166] In a specific embodiment, the forced test signal is used to control the forced test circuit.

[0167] In this embodiment, the generation of the forced test signal is controlled by the power-on reset signal and the power-on reset delay signal obtained by delaying the power-on reset signal, without the aid of other signals, ensuring that the forced test signal can respond to the generation requirement in time, and furthermore, the power-on reset signal is used as the clock input of the latch to sample the signal received by the interactive interface, so that the level of the signal received by the interactive interface needs to be maintained for a certain time length to be accurately sampled, improving the reliability of the generation of the forced test signal.

[0168] Although some specific embodiments of the present application have been described in detail by examples, those skilled in the art should understand that the above examples are only for illustration, but not for limiting the scope of the present application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A system for entering a chip test submode, characterized by The system comprises a first communication module, a second interface and a third interface corresponding to the first communication module, M test sub-modes corresponding to respective AND gates and a test selector, wherein M is a positive integer; The first communication module comprises a mode input decoder, a mode register and a mode decoder; The second interface is configured to input encoded information corresponding to the M test sub-modes into the mode input decoder; The mode input decoder is configured to write the encoded information corresponding to the M test sub-modes into the mode register; The third interface is configured to input sub-mode entering information into the first communication module; The mode decoder is configured to set a signal of a test sub-mode corresponding to the sub-mode entering information to a preset second level according to the sub-mode entering information and the encoded information corresponding to the M test sub-modes in the mode register; For any test sub-mode, the signal of the test sub-mode and a test mode signal are input into the AND gate corresponding to the test sub-mode, and the AND gate corresponding to the test sub-mode is input into the test selector; When the signal of the test sub-mode and the test mode signal are both the preset second level, the test selector enters the test sub-mode.

2. The system for entering a chip test sub-mode according to claim 1, characterized in that, The encoded information is represented by K-bit binary encoding; Correspondingly, the mode register comprises K sub-registers; where K satisfies the condition: 2 K+1 ≥M, K are positive integers and min(K) 3. The system for entering a chip test sub-mode according to claim 1, wherein, The encoded information is represented by one-hot encoding; Correspondingly, the mode register comprises M sub-registers, and each sub-register corresponds to encoded information of a test sub-mode.

4. The system for entering a chip test sub-mode according to claim 1, wherein, The first communication module adopts an I2C protocol.

5. The system for entering a chip test sub-mode according to claim 1, wherein, The preset second level is a high level.

6. The system for entering a chip test sub-mode according to claim 1, wherein, The second interface and the third interface are both general interfaces.

7. The system for entering a chip test sub-mode according to claim 6, characterized in that, When entering any test sub-mode, the second interface and the third interface are both mapped into interfaces required by the test sub-mode.

8. The system for entering a submode of a chip test according to claim 1, characterized in that, The M test sub-modes at least comprise a scan mode and a memory self-test.

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