2D structure core particle test layout design method

Abstract

The application provides a 2D structure chiplet test layout design method. The method uses a hexagonal arrangement for each test point, and uses a test PIN to connect six signal pins to reduce the signal lead-out end. The test circuit with switching function is designed to realize independent control of each test PIN. The test process is designed according to the control signal of the test circuit to realize single chiplet self-test and cascade test, thereby judging the signal connectivity. Under this design method, the test PIN and the adjacent signal PIN are arranged at equal distances, the single test PIN is controlled, the test can be performed one by one, and the cascade test is performed after the single chiplet self-test, so as to improve the test efficiency and accuracy. In addition, the chiplet layout is arranged in a hexagonal manner, the signal pin coverage is improved, the number of test PINs is reduced, and the signal transmission efficiency under the same area is improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit testing, and more specifically relates to a 2D structure chip test layout design method. Background Technology

[0002] Chiplet-based integrated circuit design has become one of the mainstream methods for designing very large-scale integrated circuit products. Compared with traditional integrated circuits, chiplet-based integrated circuits have advantages such as higher integration density and faster speed, but they also have problems such as fewer leads and more complex testing.

[0003] The main testing points for chiplet structures include two aspects: first, whether there are short circuits or open circuits between adjacent signals after integration; and second, whether the signal quality can be effectively guaranteed after integration. Currently, most chiplet interconnects are implemented using a rectangular distribution, while some use a hexagonal design. Due to the limited number of pins in a chiplet design, effectively designing the test structure, determining the test pin locations, and improving test efficiency have become key issues in chiplet product design.

[0004] Current chiplet designs typically employ redundant signals. For example, a group of 64 signals (8x8 structure) can be supplemented with 8x1 signals. When a signal in a group fails, a redundant signal replaces it. However, if multiple signals fail within a group, the chip will not function properly. Furthermore, current test designs cannot perform self-testing on a single chiplet; two chiplets with identical functions must be connected to achieve functional testing.

[0005] The probability of problems occurring between two adjacent signals is usually highest. Therefore, the design should avoid situations where two adjacent signals are not tested. For rectangular and hexagonal structures, under the same area and coverage conditions, the hexagonal structure requires fewer test signals, resulting in higher overall system efficiency. Summary of the Invention

[0006] This invention aims to solve the testing problems of current chiplet designs. Specifically, this includes how to improve the coverage of test signals to enhance system efficiency, and how to achieve self-testing of a single chiplet without connecting to other chiplets with the same functionality. Furthermore, this invention also addresses how to design test structures and determine test PIN positions to optimize signal coverage efficiency under the same area and coverage conditions.

[0007] To achieve the above objectives, the present invention employs the following technical solution: The method comprises the following steps: a. Design each test point to be arranged in a hexagonal pattern, with 1 test PIN connecting 6 signal PINs to ensure signal test coverage of all cores and reduce signal output terminals; b. Design a test circuit with switching function to independently control each test PIN; c. Design the test process, and implement self-testing and cascading testing of individual chiplets based on the control signals of the test circuit, and determine the signal connectivity based on the test results.

[0008] In one embodiment, the test PIN is arranged equidistantly from the adjacent signal PIN.

[0009] In one embodiment, each test PIN of the test circuit contains a control signal for controlling whether the test PIN is turned on.

[0010] In one embodiment, the testing process includes: when a test PIN needs to be tested, turning on the test PIN and turning off other test PINs, then inputting a test signal and checking the output signal.

[0011] In one embodiment, the testing process further includes: after a single chiplet self-test, performing a cascading test, i.e., turning on two adjacent test pins and turning off other test pins, then inputting test signals and checking the output signals.

[0012] In one approach, using a hexagonal layout for the chip can improve signal pin coverage by 50%, reduce the number of test pins, and improve signal transmission efficiency within the same area.

[0013] In one approach, the method can enable self-testing of a single chiplet while also accommodating cascade testing, thus improving testing efficiency and accuracy.

[0014] Beneficial effects of this invention: By employing a hexagonal arrangement for test points, connecting six signal pins with one test pin, signal coverage can be effectively improved, and the number of signal outputs can be reduced, offering significant advantages. Compared to the traditional rectangular arrangement of test pins, this design can increase signal pin coverage by 50% and improve signal transmission efficiency within the same area.

[0015] The test circuit with switching function designed in this invention can independently control each test PIN, so that opening or closing any test point will not affect other test points, thus improving the flexibility of testing.

[0016] The test process designed in this invention can realize self-testing of a single chiplet and cascade testing, and judge signal connectivity through test results. It has high accuracy and efficiency, can balance resource allocation in the test, and further improves the test effect.

[0017] In the design and manufacturing of large-scale integrated circuits, the technical solution of this invention can improve production capacity, optimize power consumption, enhance product performance, and reduce production costs, thus possessing high practical value and broad application prospects. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the connection between A0 and B0 in the 2D package of the present invention; Figure 2 This is a schematic diagram of the connection of A0, C0, D0, and B0 in the stacked package of the present invention. Detailed Implementation

[0019] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Typical embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0020] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. To facilitate understanding, the invention will now be described more fully with reference to the accompanying drawings. Typical embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the invention more thorough and complete.

[0021] To achieve full signal coverage and optimized test resources for 2D structure core testing, this implementation method first designs the layout structure of the test points: like Figure 1 As shown, each test point is arranged in a hexagonal pattern, connecting one test pin to six signal pins, with the test pin and the six adjacent signal pins arranged at equal intervals. This equidistant design ensures a uniform transmission path for the test signal among the six signal pins, avoiding uneven signal attenuation due to distance differences, thereby improving the consistency and accuracy of signal testing.

[0022] Furthermore, this hexagonal arrangement has significant technical advantages: on the one hand, the design of one test pin covering six signal pins can significantly reduce the number of signal leads and reduce the pin resource occupation of the chip package while ensuring that all chip signals are tested and covered; on the other hand, compared with the traditional rectangular arrangement, this hexagonal layout can increase the signal pin coverage by 50%, while reducing the total number of test pins and significantly improving the signal transmission efficiency of the chip in the same area, which is especially suitable for scenarios with high integration of 2D structure chips and limited pin resources.

[0023] To achieve precise control over each test pin and avoid signal interference between different test pins during testing, this embodiment designs a test circuit with switching functionality, specifically as follows: Figure 2 As shown: The test circuit is configured with an independent control signal for each test PIN, which can individually control the opening or closing of the corresponding test PIN.

[0024] The core effect of this circuit design is that when a target test PIN needs to be tested, it can be turned on through its dedicated control signal, and all non-target test PINs can be turned off synchronously through the control signals of other test PINs. This independent control logic can completely isolate the interference of non-target test PINs on the current test signal, ensuring that the test signal is transmitted only in the target test path. This not only improves the flexibility of testing (any test PIN can be selected as needed), but also avoids the signal crosstalk problem caused by the simultaneous opening of multiple PINs in the traditional method, laying the foundation for the accuracy of subsequent tests.

[0025] Based on the above test point layout and test circuit, this embodiment designs a phased test process, which can achieve seamless connection between individual chiplet self-test and cascade test. The test logic of each stage is as follows: Single chiplet self-test: When it is necessary to perform preliminary verification of the signal connectivity of a single chiplet, perform a single chiplet self-test: First, turn on the target test PIN to be tested and turn off all other test PINs through the control signal of the test circuit; then input the preset test signal to the target test PIN and check its output signal.

[0026] In the output signal judgment stage, a clear judgment standard is adopted: if the consistency between the output signal and the preset standard test signal meets the test requirements (such as no missing signal, no interruption, and deviation not exceeding the preset threshold), then it is determined that all 6 signal pins connected to the target test pin are connected normally; if the output signal has missing, interruption, or deviation exceeding the threshold, then the corresponding signal pin can be accurately located to have an open circuit or short circuit problem.

[0027] The core effect of this self-test process is that it can independently complete the test of the internal signal path of a single chiplet without relying on other chiplets, which solves the pain point of the traditional solution that "two chiplets with the same function need to be connected to test". At the same time, it eliminates the internal faults of a single chiplet for subsequent cascade testing, thus improving the overall testing efficiency.

[0028] Cascading test: After completing the self-test of a single chiplet and confirming that the internal signals of a single chiplet are normal, a cascade test is further performed to verify the signal connectivity between different chiplets: the test circuit turns on two adjacent test pins and turns off all other test pins; a preset test signal is input to one of the turned-on test pins, while the output signal of the other turned-on test pin is checked, and the connectivity between the chips is determined by comparing the input and output signals.

[0029] To adapt to different packaging scenarios for 2D structured chips, this implementation method designs two sub-schemes for cascade testing, further expanding the applicability of the method: In 2D packaging scenarios: In a 2D planar package chip, open the switch between two adjacent test pins (denoted as A0 and B0), and close other test pins; input a preset test signal to A0. If the signal output by B0 matches the preset test signal, the chip signal connection between A0 and B0 is considered normal; if they do not match, an open circuit or short circuit problem between A0 and B0 can be directly located. The advantages of this solution are: it adapts to the planar connection characteristics of 2D packaging, provides a short test path, and allows for direct judgment, significantly improving the testing efficiency of 2D package chips.

[0030] Stacked Packaging Scenario: In a stacked chip packaging scenario, open the switch between the test pins (denoted as A0 and B0) at both ends of the target transmission path, while simultaneously closing the switches between other test pins (denoted as C0 and D0) in the stacked path. Input a preset test signal to A0. If the signal output by B0 matches the preset test signal, the signal continuity of the A0-C0-D0-B0 stacked path is considered normal. If they do not match, the faulty segment in the stacked path can be quickly located. The effect of this solution is that it solves the problems of complex signal paths and difficult fault location in stacked packaging, ensuring the comprehensiveness of testing for stacked chip structures.

[0031] Time-saving testing method: To further improve testing efficiency, this embodiment also provides a time-saving testing method: At the initial stage of testing, the switch between two adjacent test pins (A0 and B0) is closed, while the switches of other test pins (C0 and D0) in the stacking path are opened. A test signal is input to A0; if the output signal of C0 is normal, it can be directly determined that the signal connection between A0 and B0 is normal. Subsequently, the switch between A0 and B0 is opened, the switch between C0 and D0 is closed, and a test signal is input to A0. If the output signal of B0 is normal, it is determined that the stacking path A0-C0-D0-B0 is normal. The core effect of this method is that by "segmenting and reusing the test path," repeated testing steps are reduced, significantly shortening the testing time while ensuring testing accuracy. This is particularly suitable for batch testing scenarios of large-scale 2D structure particles.

[0032] Through the coordinated design of the above-mentioned test point layout, test circuit, and test process, the implementation of this invention can achieve multi-dimensional technical effects: No redundant signal design required: Compared to the traditional approach of "adding redundant signals to deal with signal failures", this invention uses a hexagonal layout for full signal coverage and step-by-step testing for precise positioning. Even if there are multiple failure signals in a set of chips, the failure location can be identified through test results and targeted treatment can be carried out. This avoids the problem of "multiple signal failures leading to chip scrapping" and significantly reduces chip design and manufacturing costs.

[0033] Both testing efficiency and accuracy are improved: The combination of individual chiplet self-testing and cascade testing not only eliminates internal faults in individual chips but also verifies connection problems between chips; the independently controlled test circuit and clear output judgment criteria further ensure the accuracy of test results, and the overall testing efficiency is significantly improved compared with traditional solutions.

[0034] Wide adaptability and cost optimization: Dual-scenario adaptability of 2D packaging and stacked packaging can meet the testing needs of different 2D structure chips; the reduction of the number of test pins and the omission of redundant signals not only reduces the pin resource occupation of the chip, but also reduces the design pressure of designers and saves a lot of design and testing costs.

[0035] In summary, the specific embodiments of the present invention fully cover the technical features of each claim, and the resulting improvements in testing efficiency, accuracy assurance, and cost optimization make the testing method for 2D structured chips highly practical and have broad application prospects in the field of ultra-large-scale integrated circuit testing.

[0036] It should be understood that the above detailed description of the technical solutions of the present invention with reference to preferred embodiments is illustrative and not restrictive. Those skilled in the art can modify the technical solutions described in the embodiments or make equivalent substitutions for some of the technical features based on reading this specification; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for designing a test layout for 2D structured core particles, characterized in that, The method includes the following steps: a. Design each test point to be arranged in a hexagonal pattern, with 1 test PIN connecting 6 signal PINs to ensure signal test coverage of all chips, while reducing the number of signal output terminals; b. Design a test circuit with switching function to independently control each test PIN; c. Design the test process, and implement self-testing and cascade testing of individual cores based on the control signals of the test circuit, and determine the signal connectivity between cores based on the test results.

2. The 2D structure core testing layout design method according to claim 1, characterized in that, The test PIN is arranged equidistantly from the six adjacent signal PINs.

3. The 2D structure core particle test layout design method according to claim 1, characterized in that, The test circuit is configured with an independent control signal for each test PIN, which is used to individually control the opening or closing of the corresponding test PIN.

4. The 2D structure core testing layout design method according to claim 1, characterized in that, The specific process of the single chip self-test is as follows: when a target test PIN needs to be tested, the target test PIN is turned on through the test circuit and all other test PINs are turned off. Then, a test signal is input to the target test PIN, and the output signal of the test PIN is checked at the same time.

5. The 2D structure core testing layout design method according to claim 1, characterized in that, The specific process of the cascade test is as follows: after completing the self-test of a single chip, the switch between adjacent test PIN A0 and test PIB0 in different chips is turned on through the test circuit, and all other test PINs are turned off. Then, a test signal is input to one of the turned-on test PINs, while the output signal of the other turned-on test PIN is checked.

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