A method and apparatus for adjusting DDR frequency, an electronic device, and a storage medium

Abstract

This application provides a method, apparatus, electronic device, and storage medium for adjusting DDR frequency. The method includes: upon receiving a frequency adjustment command from the CPU, waiting for an indication signal from the display controller; the indication signal is generated by the display controller when it finishes reading a frame of image to be displayed from the DDR memory and is sent to the DDR memory controller; upon receiving the indication signal, immediately initiating DDR frequency adjustment so that the adjustment is performed and completed within a vertical blanking period immediately following the indication signal; the vertical blanking period begins after receiving the indication signal and ends before the display controller begins pre-fetching the next frame of image to be displayed, thereby restoring the DDR memory's response to the display controller's image reading before the end of the vertical blanking period. This method avoids screen flickering or black screen phenomena.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method, apparatus, electronic device and storage medium for adjusting DDR frequency. Background Technology

[0002] For electronic devices with display functions, their chips typically include a CPU (central controller), a display controller, and a DDR memory controller, with DDR memory also located externally. During the display process, the display controller needs to retrieve each frame to be displayed from the DDR memory.

[0003] The CPU adjusts the DDR frequency based on the needs of the current application, which means adjusting the data transfer rate between the DDR memory controller and the DDR memory. For example, when playing high-definition movies or large games, the DDR frequency needs to be increased; when the device is in standby mode, the DDR frequency can be decreased to reduce power consumption.

[0004] During the adjustment of the DDR frequency, the display controller cannot obtain the next frame to be displayed from the DDR memory. This may result in incorrect content being displayed, leading to screen flickering or black screen, which affects the user's viewing experience.

[0005] The current general solution is as follows: Figure 1 As shown, when the display controller finishes reading the current frame to be displayed, it reports a frame end signal to the CPU. Upon receiving this signal, the CPU initiates DDR frequency modulation. Because the display controller has already completely read the current frame and begun outputting it to the display screen at the moment the "current frame to be displayed finishes reading" occurs, its need to read DDR memory temporarily ceases. While outputting the current frame, the display controller does not immediately begin reading the next frame. It waits until the current frame is completely output and a brief "vertical blanking period (safety window)" has passed before preparing for the next frame.

[0006] Ideally, when the display controller finishes reading the current frame to be displayed, it reports a signal to the CPU. After the CPU detects the end-of-frame signal, it promptly initiates DDR frequency modulation during the "vertical blank period." Since the display controller does not need to read any data from DDR memory at this time, even if the DDR memory is temporarily inaccessible due to frequency modulation, it will not have any negative impact.

[0007] However, in practice, because the CPU needs to handle various high-priority tasks, it is usually unable to process the frame end signal reported by the display controller in a timely manner, and therefore cannot start DDR frequency modulation in time during the "vertical blank period". By the time the CPU starts DDR frequency modulation, the "vertical blank period" may have been missed, and the display controller has already begun to read the next frame to be displayed from the DDR memory. If the CPU is in the process of DDR frequency modulation at this time, the display controller will not be able to read the next frame to be displayed, which will result in screen distortion or black screen. Summary of the Invention

[0008] In view of this, the purpose of this application is to provide a method, apparatus, electronic device and storage medium for adjusting DDR frequency, so as to ensure that the timing of DDR frequency adjustment is the moment when "one frame of the screen to be displayed is finished reading", thereby ensuring that the DDR frequency adjustment process occurs within the vertical blank period, improving the accuracy of the timing of DDR frequency adjustment, and thus avoiding the phenomenon of screen flickering or black screen.

[0009] In a first aspect, embodiments of this application provide a method for adjusting the DDR frequency, the method being applied to a DDR memory controller in a chip; the chip further includes a CPU and a display controller; DDR memory is externally disposed on the chip; the method includes:

[0010] Upon receiving the frequency adjustment command from the CPU, the system waits for an indication signal from the display controller; wherein the indication signal is generated by the display controller and sent to the DDR memory controller when it finishes reading a frame of the image to be displayed from the DDR memory.

[0011] Upon receiving the indication signal, DDR frequency adjustment is immediately initiated so that the DDR frequency adjustment is performed and completed within the vertical blank period immediately following the indication signal; the duration of the vertical blank period is longer than the duration required for DDR frequency adjustment; the vertical blank period begins after receiving the indication signal and ends before the display controller begins prefetching the next frame to be displayed, thereby restoring the DDR memory's response to the display controller's reading of the frame to be displayed before the end of the vertical blank period.

[0012] In conjunction with the first aspect, embodiments of this application provide a first possible implementation of the first aspect, wherein, before waiting for an indication signal from the display controller, the method further includes:

[0013] The CPU sends a display data preparation instruction to temporarily store multiple consecutive frames of images to be displayed, which are required for the current display task and are contained in the display data preparation instruction, into the DDR memory.

[0014] In conjunction with the first possible implementation of the first aspect, this application provides a second possible implementation of the first aspect, wherein the method further includes:

[0015] Upon receiving the display task completion instruction sent by the CPU, the multiple consecutive frames of images to be displayed, temporarily stored in the DDR memory, are deleted from the DDR memory.

[0016] In conjunction with the first aspect, embodiments of this application provide a third possible implementation of the first aspect, wherein, during the waiting for an indication signal from the display controller, the method further includes:

[0017] The system receives a data read request sent by the display controller, reads the corresponding screen to be displayed from the DDR memory, and returns the read screen to be displayed to the display controller.

[0018] In conjunction with the first aspect, this application provides a fourth possible implementation of the first aspect, wherein the display controller and the DDR memory controller are connected via a physical connection line; and the indication signal is a pulse signal transmitted via the physical connection line.

[0019] In conjunction with the first possible implementation of the first aspect, this application provides a fifth possible implementation of the first aspect, wherein the chip includes a DDR configuration register; the method further includes:

[0020] Upon receiving the frequency adjustment command sent by the CPU, the target frequency configured by the CPU in the DDR configuration register based on the current display task is read;

[0021] The DDR frequency adjustment includes:

[0022] Using the target frequency read, the interface clock frequency between the DDR memory controller and the DDR memory is adjusted to change the data transfer rate between the DDR memory controller and the DDR memory.

[0023] Secondly, embodiments of this application also provide a method for adjusting the DDR frequency, the method being applied to a chip, the chip including a DDR memory controller, a CPU, and a display controller; DDR memory is externally disposed on the chip; the method includes:

[0024] When the DDR memory controller receives the frequency adjustment command sent by the CPU, it waits for an indication signal from the display controller.

[0025] The display controller generates the indication signal when it finishes reading a frame of image to be displayed from the DDR memory, and sends the indication signal to the DDR memory controller;

[0026] Upon receiving the indication signal, the DDR memory controller immediately initiates DDR frequency adjustment so that the DDR frequency adjustment is performed and completed within the vertical blank period immediately following the indication signal; the duration of the vertical blank period is longer than the duration required for DDR frequency adjustment; the vertical blank period begins after receiving the indication signal and ends before the display controller begins pre-fetching the next frame to be displayed, thereby restoring the DDR memory's response to the display controller's reading of the frame to be displayed before the end of the vertical blank period.

[0027] Thirdly, embodiments of this application also provide a DDR frequency adjustment device, the device being applied to a DDR memory controller in a chip; the chip further includes a CPU and a display controller; DDR memory is disposed externally on the chip; the device includes:

[0028] A waiting module is used to wait for an indication signal from the display controller when it receives a frequency adjustment command sent by the CPU; wherein the indication signal is generated by the display controller and sent to the DDR memory controller when it finishes reading a frame of image to be displayed from the DDR memory;

[0029] A startup module is configured to immediately initiate DDR frequency adjustment upon receiving the indication signal, so that the DDR frequency adjustment is performed and completed within a vertical blanking period immediately following the indication signal; the duration of the vertical blanking period is longer than the duration required for DDR frequency adjustment; the vertical blanking period begins after receiving the indication signal and ends before the display controller begins prefetching the next frame to be displayed, thereby restoring the DDR memory's response to the display controller's reading of the frame to be displayed before the end of the vertical blanking period.

[0030] Fourthly, embodiments of this application also provide an electronic device, including: a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the memory via the bus, and when the machine-readable instructions are executed by the processor, the steps in any of the possible implementations of the first aspect described above are performed.

[0031] Fifthly, embodiments of this application also provide a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps in any of the possible implementations of the first aspect described above.

[0032] This application provides a method, apparatus, electronic device, and storage medium for adjusting DDR frequency. The DDR memory controller, upon receiving a frequency adjustment command from the CPU, waits for an indication signal from the display controller. The display controller generates an indication signal upon completing the reading of a frame of image to be displayed from the DDR memory and sends the indication signal to the DDR memory controller. Upon receiving the indication signal, the DDR memory controller immediately initiates DDR frequency adjustment, ensuring that the adjustment is performed and completed within a vertical blanking period immediately following the indication signal. The duration of the vertical blanking period is longer than the duration required for DDR frequency adjustment. The vertical blanking period begins after receiving the indication signal and ends before the display controller begins pre-fetching the next frame of image to be displayed, thereby restoring the DDR memory's response to the display controller's image reading before the end of the vertical blanking period. In this embodiment, the moment the DDR memory controller receives the indication signal is actually the moment when the display controller finishes reading a frame of the image to be displayed (i.e., the current frame of the image to be displayed). The following period is a vertical blank period. At this time, the DDR frequency is adjusted, which ensures that the timing of the DDR frequency adjustment is the moment when the reading of a frame of the image to be displayed (i.e., the current frame of the image to be displayed) is completed. This ensures that the DDR frequency adjustment process occurs during the vertical blank period. During the vertical blank period, the display controller will not read the image to be displayed from the DDR memory, so there will be no problem of screen flickering or black screen.

[0033] Meanwhile, in this embodiment, since the indication signal is sent directly from the display controller to the DDR memory controller without going through the CPU, the timing of DDR frequency adjustment can be guaranteed to be the moment when "one frame of the screen to be displayed (i.e., the current frame of the screen to be displayed) is finished reading" regardless of whether the CPU's current load is high or low. It can be seen that the method of this embodiment can guarantee the accuracy of DDR frequency adjustment timing.

[0034] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic diagram of a prior art DDR frequency adjustment process is shown;

[0037] Figure 2 A schematic diagram illustrating a DDR frequency adjustment process provided in an embodiment of this application is shown;

[0038] Figure 3 A flowchart illustrating a method for adjusting DDR frequency provided in an embodiment of this application is shown;

[0039] Figure 4 A schematic diagram illustrating another DDR frequency adjustment process provided in an embodiment of this application is shown;

[0040] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0042] Based on this, embodiments of this application provide a method, apparatus, electronic device, and storage medium for adjusting DDR frequency. The purpose is to ensure that the timing of DDR frequency adjustment is the moment when "the current frame to be displayed finishes reading," thereby guaranteeing that the DDR frequency adjustment process occurs during the vertical blank period. The following is a description through embodiments.

[0043] To facilitate understanding of this embodiment, a method for adjusting the DDR frequency disclosed in this application will first be described in detail. This DDR frequency adjustment method is applied to the DDR memory controller in a chip; such as Figure 2 As shown, the chip also includes a CPU and a display controller; DDR memory is externally located on the chip; the DDR memory stores multiple consecutive frames of images to be displayed required for the current display task.

[0044] The chip in this embodiment is typically a chip installed in an electronic device with display functionality. The chip integrates a CPU (Central Processing Unit), a display controller, and a DDR memory controller. DDR memory is located on the circuit board where the chip is situated. The DDR memory temporarily stores multiple consecutive frames of images to be displayed, required for the current display task.

[0045] It is worth noting that, Figure 2 The positions of the various hardware components (CPU, display controller, DDR memory controller, DDR memory) do not represent their actual locations within the chip. Figure 2 This is merely for illustrative purposes.

[0046] like Figure 3 As shown, the method for adjusting the DDR frequency includes the following steps S101-S102:

[0047] S101: Upon receiving a frequency modulation command from the CPU, wait for an indication signal from the display controller; the indication signal is generated by the display controller when it finishes reading a frame of the image to be displayed from the DDR memory and sends it to the DDR memory controller.

[0048] S102: Upon receiving the indication signal, immediately initiate DDR frequency adjustment so that the DDR frequency adjustment is performed and completed within the vertical blank period immediately following the indication signal; the duration of the vertical blank period is longer than the duration required for DDR frequency adjustment; the vertical blank period begins after receiving the indication signal and ends before the display controller begins prefetching the next frame to be displayed, thereby restoring the DDR memory's response to the display controller's reading of the frame to be displayed before the end of the vertical blank period.

[0049] In step S101, the display controller reads a frame of the current frame to be displayed from the DDR memory in sequence through the DDR memory controller. Each time the display controller finishes reading a frame of the current frame from the DDR memory (i.e., the moment when a frame of the current frame is read), it generates an indication signal to indicate that the reading is complete and sends the indication signal to the DDR memory controller.

[0050] At the moment when "one frame of the image to be displayed is read completely", the display controller has finished reading all the data required for the current frame of the image to be displayed and begins to output it to the display screen. At this point, the display controller's need to read DDR memory temporarily comes to an end.

[0051] Specifically, while the display controller outputs the current frame of the image to be displayed to the screen, it does not immediately read the next frame. It waits until the current frame has been completely output and a brief "vertical blanking period" (safety window) has passed before preparing for the next frame. In other words, there is a vertical blanking period between when the display controller finishes reading the current frame and when it reads the next frame; during this period, the display controller does not read the image from DDR memory.

[0052] When the CPU determines that the DDR frequency needs to be adjusted, it sends a frequency adjustment command to the DDR memory controller. Upon receiving the frequency adjustment command, the DDR memory controller does not immediately begin adjusting the DDR frequency. Instead, it waits for an indication signal from the display controller as a start signal.

[0053] In step S102, since the display controller sends the indication signal at the moment when "one frame of the image to be displayed is read out (i.e., the moment the display controller finishes reading one frame of the image to be displayed from the DDR memory)," this embodiment can precisely control the start time of DDR frequency adjustment to "the moment when one frame of the image to be displayed is read out." Simultaneously, since the duration of the vertical blank period is longer than the duration required for DDR frequency adjustment, this ensures that the DDR frequency adjustment process occurs within the vertical blank period. Because the display controller does not read the image to be displayed from the DDR memory during the vertical blank period, it will not affect the image displayed on the screen.

[0054] Furthermore, since the start time of DDR frequency adjustment is precisely controlled at the moment when "one frame of the image to be displayed is read out", and the DDR frequency adjustment process can be executed and completed within the vertical blank period, the DDR memory's response to the display controller's image reading can be restored before the end of the vertical blank period, which means that it does not affect the display controller's reading of the next frame of the image to be displayed from the DDR memory.

[0055] In one possible implementation, the multiple consecutive frames of images to be displayed required by the current display task and stored in the DDR memory are achieved through the following step S201:

[0056] S201: Receives the display data preparation instruction sent by the CPU, and temporarily stores the multiple consecutive frames of images to be displayed required by the current display task contained in the display data preparation instruction into DDR memory.

[0057] In this embodiment, after the CPU determines the current display task of the electronic device (e.g., displaying a high-definition movie), it obtains multiple consecutive frames of images to be displayed required for the current display task from a website, webpage, or hard drive, and generates a display data preparation instruction containing the multiple consecutive frames of images to be displayed required for the current display task. The CPU sends the display data preparation instruction to the DDR memory controller. When the DDR memory controller receives the display data preparation instruction sent by the CPU, it temporarily stores (i.e. caches) the multiple consecutive frames of images to be displayed required for the current display task contained in the display data preparation instruction into the DDR memory.

[0058] In one possible implementation, after the current display task is completed, the frames to be displayed that are temporarily stored in the DDR memory can be deleted from the DDR memory through the following step S202:

[0059] S202: When receiving the display task completion instruction sent by the CPU, delete the multiple consecutive frames of images to be displayed that are temporarily stored in the DDR memory from the DDR memory.

[0060] In one possible implementation, during step S101, while waiting for an indication signal from the display controller, the following steps may be performed:

[0061] It receives data read requests sent by the display controller, reads the corresponding screen to be displayed from the DDR memory, and returns the read screen to be displayed to the display controller.

[0062] In this embodiment, such as Figure 2 As shown, the display controller is connected to the DDR memory controller, which in turn is connected to external DDR memory. The display controller sends a data acquisition request to the DDR memory controller, which then reads the corresponding image to be displayed from the DDR memory and returns the image to the display controller. After receiving the image, the display controller displays it on the screen.

[0063] In one possible implementation, the display controller and the DDR memory controller are connected via a physical connection line; the indication signal is a pulse signal transmitted via the physical connection line.

[0064] In this embodiment, when the display controller finishes reading each frame of the image to be displayed, it sends a pulse signal to the DDR memory controller via a physical connection line to indicate that the reading is complete. The data transmission process is not limited by the network, which helps to ensure the timeliness of the pulse signal transmission, thereby helping to ensure that the DDR memory controller can obtain the "moment when a frame of the image to be displayed is read in a timely manner".

[0065] In one possible implementation, such as Figure 4 As shown, the chip contains a DDR configuration register; the following steps can also be performed:

[0066] Upon receiving a frequency adjustment command from the CPU, the target frequency configured by the CPU in the DDR configuration register based on the current display task is read.

[0067] When performing step S102 DDR frequency adjustment, the specific steps can be followed:

[0068] By adjusting the interface clock frequency between the DDR memory controller and the DDR memory using the target reading frequency, the data transfer rate between the DDR memory controller and the DDR memory can be changed.

[0069] S1023: When the DDR memory controller receives the frequency adjustment command sent by the CPU, it starts listening to the indication signal sent by the display controller. When the indication signal is heard, it starts reading the target frequency configured in the DDR configuration register and uses the target frequency to adjust the DDR frequency to the target frequency during the vertical blank period.

[0070] In this embodiment, the CPU determines the DDR frequency that needs to be adjusted based on the application (e.g., a mobile app) currently running on the electronic device. For example, if the application currently running on the electronic device is a video playback application, the DDR frequency needs to be increased, meaning the current target frequency is set relatively high. If the electronic device is not currently running any applications, i.e., the electronic device is currently in standby mode, then, in order to reduce power consumption, the target frequency is set lower. Therefore, when the CPU detects that the DDR frequency needs to be adjusted, it determines the target frequency to be adjusted.

[0071] After determining the target frequency, the CPU sends a frequency adjustment command to the DDR memory controller and configures the target frequency in the DDR configuration register. Upon receiving the frequency adjustment command from the CPU, the DDR memory controller waits and listens for an indication signal from the display controller. When it receives the indication signal, it reads the target frequency configured in the DDR configuration register and uses it to adjust the interface clock frequency between the DDR memory and the DDR memory. This changes the data transfer rate between the DDR memory controller and the DDR memory, thereby adjusting the DDR frequency to the target frequency during the vertical dead zone, completing the DDR frequency adjustment.

[0072] Based on the same technical concept, this application also provides a method for adjusting the DDR frequency. The method is applied to a chip, which includes a DDR memory controller, a CPU, and a display controller; DDR memory is externally disposed on the chip; the method includes:

[0073] When the DDR memory controller receives the frequency adjustment command sent by the CPU, it waits for an indication signal from the display controller.

[0074] The display controller generates the indication signal when it finishes reading a frame of image to be displayed from the DDR memory, and sends the indication signal to the DDR memory controller;

[0075] Upon receiving the indication signal, the DDR memory controller immediately initiates DDR frequency adjustment so that the DDR frequency adjustment is performed and completed within the vertical blank period immediately following the indication signal; the duration of the vertical blank period is longer than the duration required for DDR frequency adjustment; the vertical blank period begins after receiving the indication signal and ends before the display controller begins pre-fetching the next frame to be displayed, thereby restoring the DDR memory's response to the display controller's reading of the frame to be displayed before the end of the vertical blank period.

[0076] Optionally, before waiting for an indication signal from the display controller, the DDR memory controller further includes:

[0077] The DDR memory controller receives a display data preparation instruction sent by the CPU, and temporarily stores the multiple consecutive frames of images to be displayed required by the current display task contained in the display data preparation instruction into the DDR memory.

[0078] Optionally, the method further includes:

[0079] When the DDR memory controller receives the display task completion instruction sent by the CPU, it deletes the multiple consecutive frames of images to be displayed that are temporarily stored in the DDR memory from the DDR memory.

[0080] Optionally, while waiting for an indication signal from the display controller, the DDR memory controller further includes:

[0081] The DDR memory controller receives a data read request sent by the display controller, reads the corresponding screen to be displayed from the DDR memory, and returns the read screen to be displayed to the display controller.

[0082] Optionally, the display controller and the DDR memory controller are connected via a physical connection line; the indication signal is a pulse signal transmitted through the physical connection line.

[0083] Optionally, the chip includes a DDR configuration register; the method further includes:

[0084] When the DDR memory controller receives a frequency adjustment command from the CPU, it reads the target frequency configured by the CPU in the DDR configuration register based on the current display task.

[0085] The DDR memory controller DDR frequency adjustment includes:

[0086] The DDR memory controller uses the read target frequency to adjust the interface clock frequency between the DDR memory controller and the DDR memory, thereby changing the data transfer rate between the DDR memory controller and the DDR memory.

[0087] Based on the same technical concept, this application also provides a DDR frequency adjustment device, which is applied to a DDR memory controller in a chip; the chip also includes a CPU and a display controller; DDR memory is disposed externally on the chip; the device includes:

[0088] A waiting module is used to wait for an indication signal from the display controller when it receives a frequency adjustment command sent by the CPU; wherein the indication signal is generated by the display controller and sent to the DDR memory controller when it finishes reading a frame of image to be displayed from the DDR memory;

[0089] A startup module is configured to immediately initiate DDR frequency adjustment upon receiving the indication signal, so that the DDR frequency adjustment is performed and completed within a vertical blanking period immediately following the indication signal; the duration of the vertical blanking period is longer than the duration required for DDR frequency adjustment; the vertical blanking period begins after receiving the indication signal and ends before the display controller begins prefetching the next frame to be displayed, thereby restoring the DDR memory's response to the display controller's reading of the frame to be displayed before the end of the vertical blanking period.

[0090] Optionally, the device further includes:

[0091] The receiving module is configured to receive a display data preparation instruction sent by the CPU before the waiting module receives the frequency modulation instruction sent by the CPU and waits for the indication signal from the display controller, so as to temporarily store the multiple consecutive frames of images to be displayed required by the current display task contained in the display data preparation instruction into the DDR memory.

[0092] Optionally, the device further includes:

[0093] The deletion module is used to delete multiple consecutive frames of images to be displayed that are temporarily stored in the DDR memory from the DDR memory when the CPU sends a display task completion instruction.

[0094] Optionally, the waiting module is further configured to: while waiting for an indication signal from the display controller.

[0095] The system receives a data read request sent by the display controller, reads the corresponding screen to be displayed from the DDR memory, and returns the read screen to be displayed to the display controller.

[0096] Optionally, the display controller and the DDR memory controller are connected via a physical connection line; the indication signal is a pulse signal transmitted through the physical connection line.

[0097] Optionally, the chip includes a DDR configuration register; the device further includes:

[0098] The reading module is used to read the target frequency configured by the CPU in the DDR configuration register based on the current display task when it receives the frequency adjustment command sent by the CPU;

[0099] When used for DDR frequency adjustment, the startup module is specifically used for:

[0100] Using the target frequency read, the interface clock frequency between the DDR memory controller and the DDR memory is adjusted to change the data transfer rate between the DDR memory controller and the DDR memory.

[0101] Figure 5 A schematic diagram of an electronic device provided in this application embodiment includes: a processor 501, a memory 502, and a bus 503. The memory 502 stores machine-readable instructions executable by the processor 501. When the electronic device runs the above-described information processing method, the processor 501 and the memory 502 communicate through the bus 503. The processor 501 executes the machine-readable instructions to perform the steps of the method described in Embodiment 1.

[0102] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps described in Embodiment 1.

[0103] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the methods, apparatuses, electronic devices, and computer-readable storage media described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0104] In the several embodiments provided in this application, it should be understood that the disclosed methods, apparatuses, electronic devices, and computer-readable storage media can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or modules may be electrical, mechanical, or other forms.

[0105] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0106] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0107] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0108] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the claims.

Claims

1. A method for adjusting DDR frequency, characterized in that, The method is applied to a DDR memory controller in a chip; the chip also includes a CPU and a display controller; DDR memory is externally disposed on the chip; the method includes: Upon receiving the frequency adjustment command from the CPU, the system waits for an indication signal from the display controller; wherein the indication signal is generated by the display controller and sent to the DDR memory controller when it finishes reading a frame of the image to be displayed from the DDR memory. Upon receiving the indication signal, DDR frequency adjustment is immediately initiated so that the DDR frequency adjustment is performed and completed within the vertical blank period immediately following the indication signal; the duration of the vertical blank period is longer than the duration required for DDR frequency adjustment; the vertical blank period begins after receiving the indication signal and ends before the display controller begins prefetching the next frame to be displayed, thereby restoring the DDR memory's response to the display controller's reading of the frame to be displayed before the end of the vertical blank period.

2. The method according to claim 1, characterized in that, Before waiting for an indication signal from the display controller, the process also includes: The CPU sends a display data preparation instruction to temporarily store multiple consecutive frames of images to be displayed, which are required for the current display task and are contained in the display data preparation instruction, into the DDR memory.

3. The method according to claim 2, characterized in that, The method further includes: Upon receiving the display task completion instruction sent by the CPU, the multiple consecutive frames of images to be displayed, temporarily stored in the DDR memory, are deleted from the DDR memory.

4. The method according to claim 1, characterized in that, During the waiting period for the indication signal from the display controller, the method further includes: The system receives a data read request sent by the display controller, reads the corresponding screen to be displayed from the DDR memory, and returns the read screen to be displayed to the display controller.

5. The method according to claim 1, characterized in that, The display controller and the DDR memory controller are connected via a physical connection line; the indication signal is a pulse signal transmitted through the physical connection line.

6. The method according to claim 2, characterized in that, The chip includes a DDR configuration register; the method further includes: Upon receiving the frequency adjustment command sent by the CPU, the target frequency configured by the CPU in the DDR configuration register based on the current display task is read; The DDR frequency adjustment includes: Using the target frequency read, the interface clock frequency between the DDR memory controller and the DDR memory is adjusted to change the data transfer rate between the DDR memory controller and the DDR memory.

7. A DDR frequency adjustment device, characterized in that, The device is used in a DDR memory controller within a chip; the chip also includes a CPU and a display controller; DDR memory is externally disposed on the chip; the device includes: A waiting module is used to wait for an indication signal from the display controller when it receives a frequency adjustment command sent by the CPU; wherein the indication signal is generated by the display controller and sent to the DDR memory controller when it finishes reading a frame of image to be displayed from the DDR memory; A startup module is configured to immediately initiate DDR frequency adjustment upon receiving the indication signal, so that the DDR frequency adjustment is performed and completed within a vertical blanking period immediately following the indication signal; the duration of the vertical blanking period is longer than the duration required for DDR frequency adjustment; the vertical blanking period begins after receiving the indication signal and ends before the display controller begins prefetching the next frame to be displayed, thereby restoring the DDR memory's response to the display controller's reading of the frame to be displayed before the end of the vertical blanking period.

8. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is in operation, the processor communicates with the memory via the bus, and the machine-readable instructions, when executed by the processor, perform the steps of the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the method as described in any one of claims 1 to 6.

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