Processor operation performance improving method and electronic equipment

Abstract

The invention discloses a processor operation performance improving method and electronic equipment, and relates to the technical field of processors. According to the scheme, the single-instruction multi-data-stream extension option of the processor under the target architecture is firstly started, the option serves as a single-instruction multi-data-stream instruction set, multiple pieces of data can be processed in parallel at the same time, and the calculation speed of an application program is remarkably increased. On the basis, target parameters in a function library at the bottom layer of the compiler are modified, a floating point optimization strategy is executed, and meanwhile, an intermediate variable use strategy and a byte alignment strategy of an application program code to be executed on a user layer are modified, so that the code generation quality and the floating point operation speed of the compiler are improved; and moreover, the running speed of the application program is improved, and the operation performance of the processor is improved to the maximum extent, so that the cost increase caused by upgrading the processor architecture is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processors, in particular to a processor operation performance improvement method and an electronic device. BACKGROUND

[0002] The baseboard management controller (BMC) of a server is a kind of key component, which monitors and manages each subsystem of the server through multiple buses and modules associated with the server mainboard.

[0003] However, with the continuous increase of server system submodules and the vigorous development of artificial intelligence technology, the performance of the server BMC also faces higher requirements. In this background, the architecture of the BMC is usually upgraded to improve performance. However, the cost of using more advanced architecture is also increasing significantly. For many enterprises, this undoubtedly means that more funds need to be invested to upgrade the architecture.

[0004] In view of the above, how to solve the problem that the current way of upgrading the corresponding architecture to improve the performance of the BMC is costly is a problem that technicians in the field need to solve. SUMMARY

[0005] The present application provides a processor operation performance improvement method and an electronic device to at least solve the problem that the current way of upgrading the corresponding architecture to improve the performance of the BMC is costly.

[0006] The present application provides a processor operation performance improvement method applied to a processor using a target architecture; the method comprises:

[0007] Turning on the single instruction multiple data stream extension option under the target architecture;

[0008] Obtaining the underlying function library of the compiler of the target architecture, and modifying the target parameters in the underlying function library according to the optimization target; wherein the optimization target is to improve the code generation quality of the compiler;

[0009] Executing the floating point optimization strategy based on the optimized compiler to improve the floating point operation speed;

[0010] Modifying the intermediate variable usage strategy and the byte alignment strategy of the application code to be executed by the user layer to improve the application running speed.

[0011] The present application also provides an electronic device comprising a memory for storing a computer program and a processor for executing the computer program to implement the steps of any of the above processor operation performance improvement methods.

[0012] The application has the beneficial effect that firstly, the single instruction multiple data stream expansion option of the processor under the target architecture is opened, the option is used as a single instruction multiple data stream instruction set, and multiple data can be processed simultaneously and in parallel, so that the calculation speed of the application program is significantly accelerated.

[0013] In addition, the application also provides an electronic device, and the effect is the same as above. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0015] Figure 1 A flowchart of a processor operation performance improvement method provided by the embodiments of the present application is shown in the figure.

[0016] Figure 2 A schematic diagram of a processor operation performance improvement device provided by the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0018] It should be noted that in the description of the present application, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the processes, methods, articles or devices comprising a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. The terms "first", "second" and the like in the present application are used to distinguish similar objects, not to describe a specific order or sequence.

[0019] In order to enable those skilled in the art to better understand the technical scheme of the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0020] Currently, the performance of the server BMC is facing higher requirements. In order to improve the BMC computing power, the architecture thereof is usually upgraded to obtain performance improvement. However, the cost of using a more advanced architecture is also increasing significantly. Therefore, in order to solve the problem of high cost of upgrading the corresponding architecture to improve the BMC performance, the present application provides a processor operation performance improvement method. It should be noted that the method provided by the present application is applied to a processor using a target architecture, and the specific type of the processor is not limited in the embodiment, and the specific type of the target architecture is also not limited, as long as the processor using the target architecture supports a single instruction multiple data stream (Single Instruction, Multiple Data, SIMD) instruction set.

[0021] Figure 1 A flowchart of a processor operation performance improvement method provided by an embodiment of the present application is shown in FIG. 1. Figure 1 As shown in FIG. 1, the method comprises the following steps.

[0022] S10: Turn on the single instruction multiple data stream extension option under the target architecture.

[0023] In order to improve the performance of the processor, the single instruction multiple data stream extension (NEON) option under the target architecture is first turned on in the embodiment. The NEON unit mainly consists of a NEON register file, an integer execution pipeline, a single-precision floating-point execution pipeline, and a data loading and rearrangement pipeline. Among them, the NEON register file is mainly used to store concurrent instruction multiple data stream (Concurrent Instruction, Multiple Data, CIMD) data to maximize register reuse and reduce memory access times. The integer execution pipeline is mainly used to accelerate integer-intensive operations while using saturation operations to avoid overflow checks and reduce branches. The single-precision floating-point execution pipeline uses vector fused multiply-add (Vector Fused Multiply-Add, VFMA) instructions first to reduce instruction count and latency, which is effective in high-precision operation and model inference scenarios. Therefore, by turning on the NEON component in the processor, the embodiment can significantly accelerate compute-intensive tasks such as image processing, machine learning, and signal processing. It should be noted that the specific process of turning on the NEON option is not limited in the embodiment, but is determined according to the specific implementation.

[0024] S11: Obtain the underlying function library of the compiler of the target architecture, and modify the target parameters in the underlying function library according to the optimization target; wherein the optimization target is to improve the code generation quality of the compiler.

[0025] After the NEON option is enabled, in order to maximize the performance of NEON, the underlying code of the processor architecture compiler needs to be further modified. Specifically, the underlying function library of the compiler of the target architecture is obtained, and the target parameters in the underlying function library are modified according to the optimization target. It should be noted that the optimization target is to improve the code generation quality of the compiler, including but not limited to reducing the overflow of the memory of the register, maximizing the utilization rate of the processor execution unit, improving the instruction throughput, etc. In the present embodiment, the type of the target parameter to be modified is not limited, and is determined according to the specific implementation.

[0026] S12: Perform a floating point optimization strategy based on the optimized compiler to improve the floating point operation speed.

[0027] S13: Modify the intermediate variable usage strategy and byte alignment strategy of the application program code to be executed at the user layer to improve the running speed of the application program.

[0028] Subsequently, based on the optimized compiler, a floating point optimization strategy is performed to improve the floating point operation speed, so as to maximize the optimization effect of the underlying code of the compiler. In the present embodiment, the specific process of performing the floating point optimization strategy is not limited, and is determined according to the specific implementation. Finally, the application program code to be executed at the user layer is modified, and the intermediate variable usage strategy and byte alignment strategy are specifically modified, the use of intermediate variables is reduced, and the byte alignment is optimized, so as to improve the running speed of the user layer application program. In the present embodiment, the specific process of modifying the intermediate variable usage strategy and byte alignment strategy of the application program is not limited, and is determined according to the specific implementation.

[0029] In the present embodiment, the single instruction multiple data stream extension option of the processor under the target architecture is first enabled, which is used as a single instruction multiple data stream instruction set and can simultaneously and in parallel process multiple data, thereby significantly accelerating the calculation speed of the application program. On this basis, by modifying the target parameters in the underlying function library of the compiler and performing the floating point optimization strategy, and modifying the intermediate variable usage strategy and byte alignment strategy of the application program code to be executed at the user layer, not only the code generation quality of the compiler and the floating point operation speed are improved, but also the running speed of the application program is improved, the calculation performance of the processor is maximally improved, and the cost increase caused by upgrading the processor architecture is avoided.

[0030] On the basis of the above-mentioned embodiments, in some embodiments, the single instruction multiple data stream extension option under the target architecture is enabled, including:

[0031] S101: Based on the cross-compiler of the target architecture, enable the target processor option and the single instruction multiple data instruction set enabling option.

[0032] S102: based on the kernel configuration of the processor, add the options of enabling the floating point operation unit and enabling the single instruction multiple data instruction set.

[0033] S103: in the application code to be executed in the user layer, add the header file of the single instruction multiple data instruction set, and add the application programming interface function of the single instruction multiple data instruction set.

[0034] In order to enable the NEON option, in the embodiment, first, the cross-compiler of the target architecture is opened, the target processor option (-mcpu) and the single instruction multiple data instruction set enabling option (-march=armv8-a+simd) are enabled. Among them, -mcpu is used to specify the target processor architecture, -march=armv8-a+simd is used to ensure the generation of SIMD instructions.

[0035] Subsequently, based on the kernel configuration (config) of the processor, the options of enabling the floating point operation unit (CONFIG_FPU=y) and enabling the single instruction multiple data instruction set (CONFIG_NEON=y) are added. Among them, CONFIG_FPU=y is used to open the floating point operation unit of the target architecture, and CONFIG_NEON=y is used to ensure that the kernel supports NEON; after opening the above options, the code can set the bits 20-23 of the CPACR_EL1 register provided in the target architecture to 1 to open the permission of hardware access to FPU / NEON, and at the same time, ensure that the permission of running NEON in EL0 and EL1 stages is opened.

[0036] Finally, in order to ensure that the user layer application can normally call NEON, the header file (arm / neon.h) of the single instruction multiple data instruction set is added in the application code to be executed in the user layer, and the application programming interface (Application Programming Interface, API) function of the single instruction multiple data instruction set is added.

[0037] In this way, the NEON option is enabled, and it is ensured that the user layer application can normally call NEON.

[0038] On the basis of the above embodiment, in some embodiments, after enabling the single instruction multiple data stream extension option under the target architecture, the following steps are further included:

[0039] S111: when the application program in the user layer is running, input the single instruction multiple data instruction set query instruction in the system command line, and obtain the corresponding output result.

[0040] S112: according to the output result, it is judged whether the single instruction multiple data stream extension option is normally enabled; if yes, the process ends; if not, step S113 is entered.

[0041] S113: outputting alarm information indicating that the single instruction multiple data stream extension option is not enabled.

[0042] To ensure that the NEON option has been normally enabled, after enabling the NEON option under the target architecture, when the application program of the user layer runs, a single instruction multiple data instruction set query instruction (cat / proc / cpu / info | grep neon) is input in the system command line, and the corresponding output result is obtained. It is determined according to the output result whether the NEON option is normally enabled. For example, when the result output is Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt, it is considered that the processor supports the NEON option, and the NEON option is normally enabled. If there is no any output, it is considered that the processor does not support the NEON option, and alarm information indicating that the NEON option is not enabled is output. In this way, the user can be explicitly informed whether the NEON option is normally enabled in the current processor, and further processing measures can be taken according to the alarm information.

[0043] On the basis of the above embodiment, in some embodiments, the target parameter in the underlying function library is modified according to the optimization target, including:

[0044] S121: increasing the overflow cost variable threshold in the underlying function library, and reducing the instruction delay time in the underlying function library.

[0045] S122: adding a scheduler for machine instructions in the underlying code of the compiler; wherein the machine instruction is an instruction for operating on a hardware register.

[0046] S123: rearranging each machine instruction in the instruction window based on the scheduler and the priority of each machine instruction.

[0047] To optimize the compiler, in this embodiment, the overflow cost variable (spillcost) threshold in the underlying function library of the compiler is specifically increased, and the instruction delay time in the underlying function library is reduced. It should be noted that increasing the overflow variable threshold (for example, increasing by 20%) can reduce the overflow of registers to memory. This method adjusts the allocation algorithm of the registers to ensure that the frequently used variables are in the registers. The benefit of reducing the instruction delay time (for example, reducing by 20%) is to maximize the utilization of the processor execution unit, thereby improving the instruction throughput, and finally significantly improving the program performance.

[0048] Subsequently, a scheduler for machine instructions is added in the underlying code of the compiler. It is to be noted that the machine instructions are instructions operating on hardware registers. Based on the scheduler and the priority of each machine instruction, the machine instructions in the instruction window are intelligently rearranged, and those instructions whose results need more time to be ready (such as LOAD instructions) are preferentially scheduled. The specific manner of intelligently rearranging the machine instructions in this embodiment is not limited and is determined according to the specific implementation.

[0049] In this way, it is ensured that the results of instructions such as LOAD instructions have enough time to reach the registers before they are used, while the arithmetic logic unit is kept in a saturated working state all the time, effectively hiding instruction delays.

[0050] On the basis of the above-mentioned embodiments, in some embodiments, based on the scheduler and the priority of each machine instruction, the machine instructions in the instruction window are rearranged, including:

[0051] S131: Obtain an instruction execution time threshold value, and determine the execution time of each machine instruction through a development tool.

[0052] S132: Determine whether the execution time of each machine instruction is greater than the instruction execution time threshold value; if yes, go to step S133; if no, go to step S134.

[0053] S133: Confirm that the priority of the corresponding machine instruction is the first priority.

[0054] S134: Confirm that the priority of the corresponding machine instruction is the second priority; wherein the first priority is higher than the second priority.

[0055] S135: Preferentially schedule the machine instructions of the first priority through the scheduler, and after the machine instructions of the first priority are completed, schedule the machine instructions of the second priority.

[0056] In order to intelligently rearrange each machine instruction, in this embodiment, a pre-set instruction execution time threshold value is specifically obtained, and the execution time of each machine instruction is determined through a development tool (such as an ARM DS tool). The size of the instruction execution time threshold value in this embodiment is not limited.

[0057] Further determine whether the execution time of each machine instruction is greater than the instruction execution time threshold value. If it is confirmed that the execution time of the machine instruction is greater than the instruction execution time threshold value, it is confirmed that the priority of the corresponding machine instruction is the first priority, otherwise it is confirmed that the priority of the corresponding machine instruction is the second priority. It is to be noted that the first priority is higher than the second priority.

[0058] Finally, the scheduler schedules the machine instructions of the first priority first, and after the machine instructions of the first priority are completed, the machine instructions of the second priority are scheduled. In this way, instructions with longer execution times are executed first, improving instruction execution efficiency.

[0059] On this basis, when there are multiple machine instructions of the first priority, in order to further optimize the machine instruction rearrangement order, the machine instructions of the first priority are also arranged in descending order according to the corresponding execution time to generate a first priority machine instruction execution sequence, and finally the scheduler schedules each machine instruction in the first priority machine instruction execution sequence in turn, thereby strictly ensuring that machine instructions with longer execution times are executed first, improving instruction execution efficiency.

[0060] On the basis of the above embodiment, in some embodiments, the optimized compiler executes a floating point optimization strategy, including:

[0061] S144: Add a mathematical optimization enable option in the underlying code of the compiler to allow floating point operation rearrangement.

[0062] S145: Add a three-level optimization option in the underlying code of the compiler.

[0063] In order to achieve the best code optimization effect, in this embodiment, a mathematical optimization enable option (-funsafe-math-optimizations) is added in the underlying code of the optimized compiler to allow floating point operation rearrangement. It should be noted that -funsafe-math-optimizations enables some optimizations that may violate the IEEE floating point standard to improve the performance of floating point operations. These optimizations may sacrifice precision or standard compliance, but can significantly improve performance. At the same time, a three-level optimization option (-O3) is added in the underlying code of the compiler. -O3 enables all high-level optimization techniques of the compiler to improve the running efficiency and performance of the program, which is the highest level optimization option provided by the compiler.

[0064] In this embodiment, by adding the funsafe-math-optimizations and -O3 options, the highest level of optimization is enabled, maximizing the overall performance of the application.

[0065] On the basis of the above embodiment, in some embodiments, the user layer application code intermediate variable usage strategy and byte alignment strategy are modified, including:

[0066] S151: Eliminate loops in the application code and set accumulators for the application code.

[0067] S152: set the processor cache to be aligned according to a preset byte; wherein the preset byte is not less than 4 bytes.

[0068] After the optimization of the compiler bottom layer code is completed, the user layer to-be-executed application code can also be optimized. Specifically, through loop unrolling and expression fusion of the compiler, the loop in the application code is eliminated, the intermediate result originally needed to be written into the memory is directly retained in the register (R0-R12 general register) and passed to the next operation, and the accumulator is set for the application code for operation.

[0069] Meanwhile, the processor cache is set to be aligned according to the preset byte. In this embodiment, the preset byte size is not limited, and it is required to ensure that the preset byte is not less than 4 bytes, for example, it can be 16 bytes or 64 bytes. Since the cache of the processor is totally divided into L1, L2 and L3, the total of three levels of cache, wherein L1 is the fastest and has the smallest capacity (usually 32 KB), and the access delay is only 3-4 clock cycles; the L2 cache has a larger capacity (256 KB-512 KB), and the access delay is 10-12 cycles; the L3 cache is a shared cache (8-32 MB), and the access delay is 30-40 cycles. In the specific implementation, no matter which level of cache is aligned according to the preset byte. In this way, through byte alignment, it is ensured that each memory access is completely located in a single cache line, and single cache line transmission can meet the access requirement, maximize the memory bandwidth utilization, avoid unnecessary cache line loading, reduce the average access delay, and ensure the best interaction between the data result and the processor cache subsystem.

[0070] On this basis, in order to further improve the processor operation performance and the cache use efficiency, after the processor cache is set to be aligned according to the preset byte, when the application code is running, the corresponding operation data amount can also be determined in real time. When the operation data amount is less than a first threshold, the first level cache is controlled to be used by the application code; when the operation data amount is not less than the first threshold and not more than a second threshold, the second level cache is controlled to be used by the application code; and when the operation data amount is greater than the second threshold, the third level cache is controlled to be used by the application code. It should be noted that the first threshold is less than the second threshold. In this embodiment, the size of the first threshold and the second threshold is not limited, and is determined according to the specific implementation.

[0071] In addition, after the operations for improving the processor operation performance in the above embodiment are completed, in order to monitor the improved performance in real time, the performance monitoring unit inside the processor is used to collect parameters of target monitoring items. The target monitoring items include at least the number of NEON instructions executed, which is used to confirm whether the NEON instructions are used in large quantities; the number of cycles and the number of instruction retirement, which are used to calculate the number of instruction clock cycles (Cycles Per Instruction, CPI) and judge the efficiency; the cache hit rate, including the L1 / L2 cache hit rate; and the pipeline stall cycle, which is used to check whether there is performance loss caused by data dependency or resource conflict. Through the collection of the above target monitoring items, the user can view the specific performance indicators of the improved processor in real time, and adjust and optimize the performance according to the performance indicators, thereby improving the user experience.

[0072] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiment can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment.

[0073] Figure 2 A schematic diagram of a processor operation performance improvement device provided by an embodiment of the present application is shown in the figure. The device is applied to a processor using a target architecture. Figure 2 As shown in the figure, the device includes:

[0074] The starting module 10 is used to start the single instruction multiple data stream extension option under the target architecture.

[0075] The first optimization module 11 is used to obtain the underlying function library of the compiler of the target architecture, and modify the target parameters in the underlying function library according to the optimization target; wherein the optimization target is to improve the code generation quality of the compiler.

[0076] The second optimization module 12 is used to execute a floating point optimization strategy based on the optimized compiler, so as to improve the floating point operation speed.

[0077] The third optimization module 13 is used to modify the intermediate variable usage strategy and the byte alignment strategy of the application program code to be executed by the user layer, so as to improve the application program running speed.

[0078] In some embodiments, the starting module 10 includes:

[0079] The first starting submodule is used to start the target processor option and the single instruction multiple data instruction set enable option based on the cross-compiler of the target architecture.

[0080] The first adding submodule is used to add the starting floating point operation unit option and the starting single instruction multiple data instruction set option based on the kernel configuration of the processor.

[0081] a second adding sub-module, configured to add a header file of the single instruction multiple data instruction set and an application programming interface function of the single instruction multiple data instruction set in application program code to be executed at the user layer.

[0082] In some embodiments, the first optimization module 11 further comprises:

[0083] a querying sub-module, configured to input a single instruction multiple data instruction set query instruction in a system command line when the application program at the user layer is running, and acquire a corresponding output result;

[0084] a first judging sub-module, configured to judge whether the single instruction multiple data stream expansion option is normally started according to the output result; if not, output alarm information representing that the single instruction multiple data stream expansion option is not started.

[0085] In some embodiments, the first optimization module 11 comprises:

[0086] a first modifying sub-module, configured to increase an overflow cost variable threshold in a bottom function library and reduce an instruction delay time in the bottom function library;

[0087] a third adding sub-module, configured to add a scheduler for machine instructions in bottom code of a compiler; wherein the machine instructions are instructions for operating on hardware registers;

[0088] a rearranging sub-module, configured to rearrange the machine instructions in an instruction window based on the scheduler and priorities of the machine instructions.

[0089] In some embodiments, the rearranging sub-module comprises:

[0090] a first determining sub-module, configured to acquire an instruction execution time threshold and determine execution times of the machine instructions through a development tool;

[0091] a second judging sub-module, configured to judge whether the execution times of the machine instructions are greater than the instruction execution time threshold; if yes, confirm that a priority of a corresponding machine instruction is a first priority; if not, confirm that the priority of the corresponding machine instruction is a second priority; wherein the first priority is higher than the second priority;

[0092] a first scheduling sub-module, configured to preferentially schedule the machine instructions of the first priority through the scheduler, and schedule the machine instructions of the second priority after the machine instructions of the first priority are completed.

[0093] In some embodiments, the first scheduling sub-module comprises:

[0094] a third judging sub-module, configured to judge whether the number of the machine instructions of the first priority is multiple; if yes, trigger a descending sorting module.

[0095] a descending order sorting module, configured to arrange the machine instructions of the first priority in descending order according to the corresponding execution time, to generate a first priority machine instruction execution sequence;

[0096] a second scheduling sub-module, configured to sequentially schedule each machine instruction in the first priority machine instruction execution sequence by a scheduler.

[0097] In some embodiments, the second optimization module 12 comprises:

[0098] a third adding sub-module, configured to add a mathematical optimization enabling option in the underlying code of the compiler to allow the rearrangement of floating point operations;

[0099] a fourth adding sub-module, configured to add a three-level optimization option in the underlying code of the compiler.

[0100] In some embodiments, the third optimization module 13 comprises:

[0101] a second modifying sub-module, configured to eliminate loops in the application code and set accumulators for the application code;

[0102] a third modifying sub-module, configured to set the processor cache to be aligned according to a preset byte, wherein the preset byte is not less than 4 bytes.

[0103] In some embodiments, the device further comprises:

[0104] a second determining sub-module, configured to determine the corresponding operation data amount in real time when the application code is running;

[0105] a first control sub-module, configured to control the application code to use the first level cache when the operation data amount is less than a first threshold value;

[0106] a second control sub-module, configured to control the application code to use the second level cache when the operation data amount is not less than the first threshold value and not greater than a second threshold value;

[0107] a third control sub-module, configured to control the application code to use the third level cache when the operation data amount is greater than the second threshold value;

[0108] wherein the first threshold value is less than the second threshold value.

[0109] The features of the embodiments of the processor operation performance improvement device can be referred to the related descriptions of the embodiments of the processor operation performance improvement method, which will not be repeated here.

[0110] The embodiment of the present application also provides an electronic device, comprising a memory and a processor, the memory stores a computer program, and the processor is arranged to run the computer program to execute the steps in any of the processor operation performance improvement method embodiments.

[0111] The embodiment of the present application also provides a computer readable storage medium, which stores a computer program, and the computer program is arranged to execute the steps in any of the processor operation performance improvement method embodiments when running.

[0112] In an example embodiment, the computer readable storage medium can include but is not limited to a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0113] The embodiment of the present application also provides a computer program product, which comprises a computer program, and the computer program is arranged to execute the steps in any of the processor operation performance improvement method embodiments when running by a processor.

[0114] The embodiment of the present application also provides another computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is arranged to execute the steps in any of the processor operation performance improvement method embodiments when running by a processor.

[0115] The skilled person can further realize that the units and algorithm steps of the examples described in connection with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0116] The above describes in detail a processor operation performance improvement method and an electronic device provided by the present application. The principles and implementation manners of the present application are described by using specific examples in this paper, and the above example description is only applicable to help understand the method and core idea of the present application. It should be pointed out that, for the ordinary skilled person in the technical field, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for improving the performance of a processor, characterized by, The method is applied to a processor using a target architecture, and the method comprises: enabling a single instruction multiple data stream extension option under the target architecture; obtaining a bottom function library of a compiler of the target architecture, and modifying a target parameter in the bottom function library according to an optimization target; wherein the optimization target is to improve code generation quality of the compiler; performing a floating point optimization strategy based on the optimized compiler to improve floating point operation speed; modifying an intermediate variable usage strategy and a byte alignment strategy of an application program code to be executed by a user layer to improve application program running speed.

2. The method of claim 1, wherein enabling a single instruction multiple data stream extension option under the target architecture, comprising: enabling a target processor option and a single instruction multiple data instruction set enable option based on a cross-compiler of the target architecture; adding an enabling floating point operation unit option and an enabling single instruction multiple data instruction set option based on a kernel configuration of the processor; adding a header file of a single instruction multiple data instruction set and adding an application program interface function of the single instruction multiple data instruction set in the application program code to be executed by the user layer.

3. The method of claim 2, wherein After enabling the single instruction multiple data stream extension option under the target architecture, further comprising: when the application program of the user layer is running, inputting a single instruction multiple data instruction set query instruction in a system command line and obtaining a corresponding output result; judging whether the single instruction multiple data stream extension option is normally enabled according to the output result; if not, outputting alarm information representing that the single instruction multiple data stream extension option is not enabled.

4. The method of claim 1, wherein modifying the target parameter in the bottom function library according to the optimization target, comprising: increasing an overflow cost variable threshold in the bottom function library and decreasing an instruction delay time in the bottom function library; adding a scheduler for machine instructions in a bottom code of the compiler; wherein the machine instructions are instructions for operating hardware registers; rearranging each machine instruction in an instruction window based on the scheduler and a priority of each machine instruction.

5. The method of claim 4, wherein, rearranging each machine instruction in an instruction window based on the scheduler and a priority of each machine instruction, comprising: obtaining an instruction execution time threshold and determining an execution time of each machine instruction through a development tool; judging whether the execution time of each machine instruction is greater than the instruction execution time threshold; if yes, confirming that the priority of the corresponding machine instruction is a first priority; if no, confirming that the priority of the corresponding machine instruction is a second priority; wherein the first priority is higher than the second priority; preferentially scheduling the machine instruction of the first priority through the scheduler, and scheduling the machine instruction of the second priority after the machine instruction of the first priority is completed.

6. The method of claim 5, wherein preferentially scheduling the machine instruction of the first priority through the scheduler, comprising: judging whether the number of the machine instruction of the first priority is multiple; if yes, arranging each machine instruction of the first priority in descending order according to the corresponding execution time to generate a first priority machine instruction execution sequence; Scheduling each of the machine instructions in the first priority machine instruction execution sequence in turn by the scheduler.

7. The method of claim 1, wherein Based on the optimized compiler, a floating point optimization strategy is executed, including: Adding a mathematical optimization enabling option in the underlying code of the compiler to allow floating point operation rearrangement; Adding a three-level optimization option in the underlying code of the compiler.

8. The method of claim 1, wherein Modifying the intermediate variable usage strategy and byte alignment strategy of the application code to be executed by the user layer, including: Eliminating loops in the application code and setting accumulators for the application code; Setting the processor cache to follow a preset byte alignment; wherein the preset byte is not less than 4 bytes.

9. The method of claim 8, wherein, After setting the processor cache to follow the preset byte alignment, further including: When the application code is running, determining the corresponding operation data amount in real time; When the operation data amount is less than a first threshold, controlling the application code to use a level one cache; When the operation data amount is not less than the first threshold and not more than a second threshold, controlling the application code to use a level two cache; When the operation data amount is more than the second threshold, controlling the application code to use a level three cache; Wherein the first threshold is less than the second threshold.

10. An electronic device, comprising: Including: A memory for storing a computer program; A processor for executing the computer program to implement the steps of the processor operation performance improvement method according to any one of claims 1 to 9.

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