Instruction processing method, apparatus, device, and storage medium
By generating an immediate value in the processor as the program counter value, and after the instruction is judged in the pre-decoding unit, only the preset instruction is fetched, decoded, and executed, thus solving the problem of reduced processor clock frequency and achieving higher processing efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 芯来智融半导体科技(上海)股份有限公司
- Filing Date
- 2025-12-24
- Publication Date
- 2026-06-30
AI Technical Summary
Existing processors need to process excessively long combinational logic cycles, leading to increased circuit latency and reduced clock speed.
An immediate value is generated by the program counter as the program counter value. The pre-decode unit decodes and judges the instruction. If it is a preset instruction, the instruction fetch unit and/or branch prediction unit fetch, decode and execute the instruction, avoiding the need to process all instructions in their entirety.
It reduces the amount of computation in combinational logic, lowers latency caused by processing complex instructions, and increases the processor's clock speed.
Smart Images
Figure CN121387370B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of processor technology, and in particular to an instruction processing method, apparatus, device, and storage medium. Background Technology
[0002] Existing processors need to complete a series of logic operations within the same cycle, including instruction fetching, partial decoding, branch prediction, and generating the program counter value for the next instruction fetch. Excessive combinational logic increases circuit latency, leading to a reduction in the processor's clock speed.
[0003] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention
[0004] The main objective of this application is to provide an instruction processing method, apparatus, device, and storage medium, which aims to solve the technical problem that current processors need to process excessively long combinational logic, resulting in a reduction in processor clock speed.
[0005] To achieve the above objectives, this application proposes an instruction processing method applied to a processor, the method comprising the following steps:
[0006] A first immediate value is generated using the program counter, and the first immediate value is used as the first program counter value.
[0007] The processor fetch unit reads the first instruction from the memory unit according to the first program counter value;
[0008] The first instruction is passed to the pre-decoding unit so that the pre-decoding unit can decode and judge the first instruction.
[0009] If the first instruction is a first preset instruction, then the instruction fetch unit and / or branch prediction unit of the processor are used for instruction fetching, decoding and execution.
[0010] In one embodiment, fetching instructions via the processor instruction fetch unit includes:
[0011] In the first clock cycle, the processor instruction fetch unit reads a first instruction from the memory unit based on the first program counter value.
[0012] In one embodiment, decoding via the processor's instruction fetch unit and branch prediction unit includes:
[0013] The processor fetch unit sends the first instruction to the pre-decode unit, so that the pre-decode unit decodes the first instruction, determines whether the first instruction is a first preset instruction, and predicts whether the first instruction is a jump instruction through the branch prediction unit.
[0014] If so, the first immediate value and the first program counter value are delayed by one clock cycle to execute the corresponding operation in the second clock cycle;
[0015] Set a second program counter value, which is generated by incrementing the first program counter value.
[0016] The second program counter value is sent to the program counter generation unit.
[0017] In one embodiment, executing the first instruction via the processor instruction fetch unit includes:
[0018] The first instruction is sent to the instruction register, so that the instruction register sends the first instruction to the execution unit, and the execution unit executes the first instruction.
[0019] In one embodiment, the step of sending the first instruction to the instruction register, causing the instruction register to send the first instruction to the execution unit, and executing the first instruction by the execution unit, includes the following:
[0020] In the second clock cycle, the second program counter value is obtained from the program counter generation unit;
[0021] The first jump target address is generated by calculating the first immediate value and the first program counter value using an adder;
[0022] The pipeline is flushed by the processor's instruction fetch unit to flush out the second program counter value.
[0023] Using the first jump target address as the first program counter value, the execution steps are returned: In the first clock cycle, the processor instruction fetch unit reads the first instruction from the memory unit based on the first program counter value.
[0024] In one embodiment, the step of passing the first instruction to the pre-decoding unit is followed by:
[0025] If the first instruction is a second preset instruction, then the instruction fetching unit of the processor will fetch, decode, and execute the instruction.
[0026] In one embodiment, the instruction fetching, decoding, and execution via the processor instruction fetching unit includes:
[0027] In the first clock cycle, the processor fetch unit reads a first instruction from the memory unit based on the first program counter value;
[0028] The first instruction is sent to the pre-decoding unit so that the pre-decoding unit can decode and judge the first instruction. If the first instruction is a second preset instruction, the second program counter value is set. The second program counter value is generated by incrementing the first program counter value.
[0029] Send the second program counter value to the program counter generation unit;
[0030] The first instruction is sent to the instruction register, so that the instruction register sends the first instruction to the execution unit, and the execution unit executes the first instruction.
[0031] In the second clock cycle, the second program counter value is obtained from the program counter generation unit;
[0032] Using the second program counter value as the first program counter value, the execution steps are returned: In the first clock cycle, the processor instruction fetch unit reads the first instruction from the memory unit based on the first program counter value.
[0033] Furthermore, to achieve the above objectives, this application also proposes an instruction processing apparatus disposed in a processor, the apparatus comprising:
[0034] The data generation module is used to generate a first immediate value through a program counter and use the first immediate value as the first program counter value.
[0035] The instruction fetch module is used to fetch the first instruction from the memory unit according to the first program counter value through the processor instruction fetch unit;
[0036] A decoding module is used to pass the first instruction to a pre-decoding unit so that the pre-decoding unit can decode and judge the first instruction;
[0037] The instruction processing module is used to fetch, decode, and execute instructions through the processor instruction fetch unit and / or branch prediction unit if the first instruction is a first preset instruction.
[0038] In addition, to achieve the above objectives, this application also proposes an instruction processing apparatus, the apparatus comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the instruction processing method as described above.
[0039] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and which, when executed by a processor, implements the steps of the instruction processing method described above.
[0040] One or more technical solutions proposed in this application have at least the following technical effects:
[0041] This application decodes and judges instructions in the pre-decoding unit. If it is the first preset instruction, the subsequent instruction fetch, decoding, and execution are performed through the processor's instruction fetch unit and / or branch prediction unit. This avoids performing a complete instruction fetch, decoding, and execution process for all instructions. For non-preset instructions, certain unnecessary steps can be skipped or processed quickly, reducing the computational load of combinational logic and thus reducing latency caused by processing complex instructions, which is beneficial for increasing the processor's clock speed. Attached Figure Description
[0042] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0044] Figure 1 This is a flowchart illustrating the processing of the original instruction;
[0045] Figure 2 This is a flowchart illustrating an embodiment of the instruction processing method of this application.
[0046] Figure 3 This is a flowchart illustrating the instruction processing method of this application;
[0047] Figure 4 This is a schematic diagram of the module structure of the instruction processing device according to an embodiment of this application;
[0048] Figure 5 This is a schematic diagram of the device structure of the hardware operating environment involved in the instruction processing method in the embodiments of this application.
[0049] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0050] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.
[0051] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.
[0052] The main solution of this application embodiment is as follows: a first immediate value is generated by the program counter, and the first immediate value is used as the first program counter value; the processor instruction fetch unit reads a first instruction from the memory unit according to the first program counter value; the first instruction is passed to the pre-decoding unit so that the pre-decoding unit decodes and judges the first instruction; if the first instruction is a first preset instruction, the processor instruction fetch unit and / or branch prediction unit fetch, decode and execute the instruction.
[0053] In this embodiment, for ease of description, the processor will be used as the execution subject in the following description.
[0054] Because existing processors need to complete a series of logic operations within the same cycle, such as instruction fetching (from ILM and I-Cache), partial decoding, branch prediction, and generating the program counter value for the next instruction fetch, excessively long combinational logic will increase circuit latency and lead to a reduction in the processor's clock frequency.
[0055] This application provides a solution where instructions are decoded and evaluated in the pre-decoding unit. If the instruction is a first preset instruction, subsequent instruction fetching, decoding, and execution are performed through the processor's instruction fetch unit and / or branch prediction unit. This avoids performing a complete instruction fetch, decoding, and execution process for all instructions. For non-preset instructions, certain unnecessary steps can be skipped or processed quickly, reducing the computational load of combinational logic and thus lowering latency caused by processing complex instructions, which is beneficial for increasing the processor's clock speed.
[0056] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or instruction processing device capable of performing the above functions. The following description uses a processor as an example to illustrate this embodiment and the subsequent embodiments.
[0057] Reference Figure 1 , Figure 1 This is a flowchart illustrating the processing of the original instruction. (Example:) Figure 1 As shown, the Instruction Fetch Unit (IFU) is a key component in the CPU responsible for fetching instructions. Its main functions include simple decoding of the fetched instruction address, performing simple branch prediction, generating the program counter (PC) value required for instruction fetching, and accessing memory units based on the program counter value.
[0058] After the CPU undergoes a reset operation, the reset unit generates an immediate value for the program counter (PC), which serves as the initial instruction fetch program counter value. Subsequently, based on this initial value, the program counter connects to the bus via the instruction fetch unit and accesses the instruction cache (I-Cache) and instruction local memory (ILM) in memory via the bus. The corresponding address data in memory is read and transferred to the processor's instruction fetch unit (IFU) via the bus.
[0059] Inside the processor's Instruction Fetch Unit (IFU), the accessed address data is simply decoded. The decoded instruction information is combined with the prediction result of the branch prediction unit to determine whether the current instruction requires a jump operation. If a jump is required, the IFU uses an adder to calculate the PC value of the next instruction, performs a clock operation, and then issues another instruction fetch request. Simultaneously, the information of the current instruction is transferred to the Instruction Register (IR) for use by subsequent execution units.
[0060] After the IFU successfully fetches the instruction, the instruction is temporarily stored in the instruction register (IR) connected to the execution unit, awaiting further processing and execution.
[0061] However, in modern CPU architectures, the instruction fetch unit (IFU) plays a crucial role in continuously fetching instructions, requiring it to generate the program counter (PC) value for the next instruction every clock cycle. This process necessitates first determining the type of the current instruction, classifying it as either a normal instruction or a branch instruction; therefore, decoding the currently fetched instruction is essential.
[0062] Once the decoding result indicates that the current instruction is a branch jump instruction, the IFU (Initial Function Unit) must perform branch prediction within the same clock cycle. Finally, based on the decoding information and the branch prediction result, the IFU calculates and generates the PC (Program Counter) value for the next instruction.
[0063] In other words, within a single clock cycle, the IFU needs to complete a series of operations, including reading instructions from the Instruction Local Memory (ILM) and the Instruction Cache (I-Cache), partially decoding, branch prediction, and generating the PC value for the next instruction. However, this entire set of complex combinational logic significantly increases circuit latency. As circuit latency increases, the processor's clock frequency inevitably decreases, thus affecting the overall system performance.
[0064] Based on this, embodiments of this application provide an instruction processing method, referring to... Figure 2 , Figure 2 This is a flowchart illustrating an embodiment of the instruction processing method of this application.
[0065] In this embodiment, the instruction processing method is applied to the processor and includes steps S1 to S4:
[0066] Step S1: Generate a first immediate value using the program counter, and use the first immediate value as the first program counter value;
[0067] You can refer to Figure 3 , Figure 3 This is a flowchart illustrating the instruction processing method of this application.
[0068] When the CPU performs a reset operation, an immediate value is generated during the first instruction fetch. This immediate value serves as the initial value of the program counter (PC). The PC stores the address of the next instruction to be executed, and the CPU fetches the corresponding instruction from memory based on the value of the PC.
[0069] Step S2: The processor instruction fetch unit reads the first instruction from the memory unit according to the first program counter value;
[0070] Step S3: The first instruction is passed to the pre-decoding unit so that the pre-decoding unit can decode and judge the first instruction;
[0071] Step S4: If the first instruction is a first preset instruction, then the instruction fetch unit and / or branch prediction unit of the processor are used to fetch, decode and execute the instruction.
[0072] It should be noted that the branch prediction unit is a hardware module in the processor used to predict the execution direction of program branch instructions (such as conditional jumps and loops). Its core function is to predict the jump target address of branch instructions in advance by analyzing historical execution records and instruction characteristics, thereby reducing pipeline stalls caused by branch uncertainty and improving instruction execution efficiency.
[0073] As one implementation method, it can be determined whether the first instruction is a first preset instruction or a second preset instruction.
[0074] Optionally, the first preset instruction is the instruction to be jumped to in the jump instruction, and the second preset instruction is a sequential instruction or a jump instruction that does not jump.
[0075] For sequentially executed instructions and jump instructions that do not involve a jump, the CPU will not perform any additional operations; it will simply fetch and execute instructions in the natural ascending order of the PC.
[0076] When the CPU encounters a jump instruction that requires a jump, it will take special measures to ensure that the program can correctly jump to the target address and continue execution.
[0077] This embodiment provides an instruction processing method. The method involves decoding and judging the instruction in the pre-decoding unit. If the instruction is a first preset instruction, subsequent instruction fetching, decoding, and execution are performed through the processor's instruction fetch unit and / or branch prediction unit. This avoids performing a complete instruction fetch, decoding, and execution process for all instructions. For non-preset instructions, rapid processing or skipping of unnecessary steps can be achieved, reducing the computational load of combinational logic and thus lowering latency caused by processing complex instructions, which is beneficial for increasing the processor's clock speed.
[0078] Based on Embodiment 1 of this application, in Embodiment 2 of this application, the content that is the same as or similar to that in Embodiment 1 can be referred to the above description, and will not be repeated hereafter. On this basis, step S4, which involves fetching, decoding, and executing instructions through the processor instruction fetch unit and / or branch prediction unit, includes steps S41 to S410:
[0079] Step S41: In the first clock cycle, the processor instruction fetch unit reads the first instruction from the memory unit based on the first program counter value.
[0080] It should be noted that IFU accesses memory units based on the current PC value and reads the corresponding instruction data.
[0081] The decoding process via the processor's instruction fetch unit and branch prediction unit includes steps S42-S45:
[0082] Step S42: The first instruction is sent to the pre-decoding unit through the processor instruction fetch unit, so that the pre-decoding unit decodes the first instruction, determines whether the first instruction is a first preset instruction, and predicts whether the first instruction is a jump instruction through the branch prediction unit.
[0083] Step S43, if yes, then delay the first immediate value and the first program counter value by one clock cycle to perform the corresponding operation in the second clock cycle;
[0084] Step S44: Set the second program counter value, which is generated by incrementing the first program counter value.
[0085] Step S45: Send the second program counter value to the program counter generation unit.
[0086] It should be noted that the IFU fetches instructions from memory units, and the pre-decode unit Mini-Decode decodes them into jump instructions.
[0087] The branch prediction unit (BPU) works in parallel to predict whether the jump instruction will result in a jump. If the prediction result is a jump, the PC and the decoded immediate value are timed (timed operation means storing the data for one clock cycle, which serves as a buffer and synchronization function).
[0088] The execution of the first instruction by the processor instruction fetch unit includes step S46:
[0089] Step S46: Send the first instruction to the instruction register so that the instruction register sends the first instruction to the execution unit and executes the first instruction through the execution unit.
[0090] Step S46, which involves sending the first instruction to the instruction register so that the instruction register sends the first instruction to the execution unit and the execution unit executes the first instruction, includes steps S47-S410:
[0091] Step S47: In the second clock cycle, obtain the second program counter value from the program counter generation unit;
[0092] Step S48: Calculate the first immediate value and the first program counter value using an adder to generate the first jump target address;
[0093] Step S49: The pipeline is flushed by the processor instruction fetch unit to flush away the second program counter value;
[0094] Step S410: Using the first jump target address as the first program counter value, return to the execution step: In the first clock cycle, the processor instruction fetch unit reads the first instruction from the memory unit based on the first program counter value.
[0095] It should be noted that in the second clock cycle, the target PC value for the jump is calculated. Specifically, the immediate value after the clock tick and the PC are added together to obtain the target PC value after the jump.
[0096] Then, a flushing operation is generated to cancel the instruction fetch operation corresponding to the previously sent default incremented PC value, thereby ensuring that the next instruction fetch starts from the target address after the jump.
[0097] This application embodiment effectively reduces the clock latency of combinational circuits by separating the instruction decoding and PC generation into different clock cycles. Since the latency of combinational circuits affects the CPU's clock speed, a smaller latency allows the CPU to complete operations in a shorter clock cycle, thereby increasing the CPU's clock speed.
[0098] Based on Embodiment 1 of this application, in Embodiment 3 of this application, the content that is the same as or similar to that in Embodiment 1 can be referred to the above description, and will not be repeated hereafter. Based on this, step S3, which transmits the first instruction to the pre-decoding unit, and after the pre-decoding unit decodes and judges the first instruction, further includes step S5:
[0099] Step S5: If the first instruction is a second preset instruction, then the instruction fetching unit of the processor performs instruction fetching, decoding, and execution, specifically including steps S51 to S56:
[0100] 51. In the first clock cycle, the processor fetch unit reads the first instruction from the memory unit based on the first program counter value;
[0101] 52. The first instruction is sent to the pre-decoding unit so that the pre-decoding unit decodes and judges the first instruction. If the first instruction is a second preset instruction, the second program counter value is set. The second program counter value is generated by incrementing the first program counter value.
[0102] 53. Send the second program counter value to the program counter generation unit;
[0103] 54. The first instruction is sent to the instruction register, so that the instruction register sends the first instruction to the execution unit, and the execution unit executes the first instruction;
[0104] It should be noted that in the first clock cycle, the Instruction Fetch Unit (IFU) accesses the memory location based on the current program counter (PC) value and reads the corresponding instruction data from it. This process is no different from the instruction fetch operation for jump instructions.
[0105] Then, the read instruction is passed to the pre-decode unit (Mini-Decode) for simple decoding. This unit determines whether the instruction is a jump instruction. If the result is a sequential instruction or a non-jump jump instruction, the result will be used to determine the subsequent processing method.
[0106] The instruction information read from memory is sent to the instruction register, which then passes the instruction to the execution unit so that the execution unit can begin executing the instruction. At the same time, the PC value of the next instruction is assumed to be the sequential PC value obtained by incrementing the current PC value, and this sequential PC value is sent to the PC generation unit to prepare for the instruction fetch operation in the second clock cycle.
[0107] 55. In the second clock cycle, the second program counter value is obtained from the program counter generation unit;
[0108] 56. Using the second program counter value as the first program counter value, return to the execution step: In the first clock cycle, the processor instruction fetch unit reads the first instruction from the memory unit based on the first program counter value.
[0109] It should be noted that in the second clock cycle, the PC generation unit, based on the sequential PC value passed from the first clock cycle, begins the instruction fetch operation for the second instruction. The IFU accesses memory based on the new PC value to read the next instruction. This process continues to cycle, enabling the CPU to fetch and execute instructions sequentially.
[0110] It's important to note that, unlike jump instructions, processing sequential instructions or non-jump jump instructions does not trigger a special jump handling mechanism. That is, the branch prediction unit (BPU) is not required to predict jumps, and there is no calculation of the jump PC value or pipeline flushing. The CPU will continuously fetch and execute instructions sequentially according to the naturally increasing PC value, ensuring the sequential execution of the program.
[0111] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the instructions for processing this application. Any simple modifications based on this technical concept are within the protection scope of this application.
[0112] This application also provides an instruction processing apparatus, please refer to... Figure 4 The device, located in the processor, includes:
[0113] The data generation module 10 is used to generate a first immediate value through a program counter and use the first immediate value as the first program counter value.
[0114] The instruction fetch module 20 is used to fetch a first instruction from a memory unit based on the first program counter value through the processor instruction fetch unit;
[0115] Decoding module 30 is used to transmit the first instruction to the pre-decoding unit so that the pre-decoding unit can decode and judge the first instruction;
[0116] The instruction processing module 40 is used to fetch, decode, and execute instructions through the processor instruction fetch unit and / or branch prediction unit if the first instruction is a first preset instruction.
[0117] The instruction processing apparatus provided in this application, employing the instruction processing method in the above embodiments, can solve the technical problem that current processors need to process excessively long combinational logic, leading to a reduction in processor clock speed. Compared with the prior art, the beneficial effects of the instruction processing apparatus provided in this application are the same as those of the instruction processing method provided in the above embodiments, and other technical features in the instruction processing apparatus are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.
[0118] This application provides an instruction processing device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the instruction processing method in Embodiment 1 above.
[0119] The following is for reference. Figure 5 The diagram illustrates a structural schematic of an instruction processing device suitable for implementing embodiments of this application. The instruction processing device in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The instruction processing device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.
[0120] like Figure 5As shown, the instruction processing device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in the read-only memory 1002 or a program loaded from the storage device 1003 into the random access memory 1004. The random access memory 1004 also stores various programs and data required for the operation of the instruction processing device. The processing unit 1001, the read-only memory 1002, and the random access memory 1004 are interconnected via a bus 1005. An input / output interface 1006 is also connected to the bus. Typically, the following systems can be connected to the input / output interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. The communication device 1009 allows the instruction processing device to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows instruction processing devices with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.
[0121] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.
[0122] The instruction processing device provided in this application, employing the instruction processing method in the above embodiments, can solve the technical problem that current processors need to process excessively long combinational logic, leading to a reduction in processor clock speed. Compared with the prior art, the beneficial effects of the instruction processing device provided in this application are the same as those of the instruction processing method provided in the above embodiments, and other technical features in this instruction processing device are the same as those disclosed in the previous embodiment method, and will not be repeated here.
[0123] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.
[0124] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0125] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the instruction processing method in the above embodiments.
[0126] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.
[0127] The aforementioned computer-readable storage medium may be included in the instruction processing device or may exist independently and not assembled into the instruction processing device.
[0128] The aforementioned computer-readable storage medium carries one or more programs. When the one or more programs are executed by an instruction processing device, the instruction processing device: generates a first immediate value through a program counter and uses the first immediate value as a first program counter value; reads a first instruction from a memory unit according to the first program counter value through a processor instruction fetch unit; passes the first instruction to a pre-decoding unit so that the pre-decoding unit decodes and judges the first instruction; if the first instruction is a first preset instruction, then the processor instruction fetch unit and / or branch prediction unit fetch, decode, and execute the instruction.
[0129] Computer program code for performing the operations of this application can be written in one or more programming languages or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, and C++, and conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0130] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0131] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.
[0132] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described instruction processing method. This solves the technical problem that current processors need to process excessively long combinational logic, leading to a decrease in processor clock speed. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the instruction processing method provided in the above embodiments, and will not be repeated here.
[0133] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.
Claims
1. An instruction processing method, characterized in that, Applied to a processor, the method includes the following steps: A first immediate value is generated using the program counter, and the first immediate value is used as the first program counter value. The processor fetch unit reads the first instruction from the memory unit according to the first program counter value; The first instruction is passed to the pre-decoding unit so that the pre-decoding unit can decode and judge the first instruction. If the first instruction is a first preset instruction, then the instruction fetch unit and branch prediction unit of the processor perform instruction fetching, decoding, and execution, specifically including: in the first clock cycle, the instruction fetch unit of the processor reads the first instruction from the memory unit based on the first program counter value; delays the first immediate value and the first program counter value by one clock cycle to execute the corresponding operation in the second clock cycle; sets a second program counter value, which is generated by incrementing the first program counter value; sends the second program counter value to the program counter generation unit; sends the first instruction to the instruction register, so that the instruction register sends the first instruction to the execution unit, and the execution unit executes the first instruction; in the second clock cycle, obtains the second program counter value from the program counter generation unit; calculates the first immediate value and the first program counter value using an adder to generate a first jump target address; flushes the pipeline through the instruction fetch unit of the processor so that the second program counter value is flushed away; and uses the first jump target address as the first program counter value to return to the execution step: in the first clock cycle, the instruction fetch unit of the processor reads the first instruction from the memory unit based on the first program counter value; If the first instruction is a second preset instruction, then the instruction fetching unit of the processor performs instruction fetching, decoding, and execution, specifically including: in the first clock cycle, the instruction fetching unit of the processor reads the first instruction from the memory unit based on the first program counter value; sets a second program counter value, which is generated by incrementing the first program counter value; sends the second program counter value to the program counter generation unit; sends the first instruction to the instruction register, so that the instruction register sends the first instruction to the execution unit, and the execution unit executes the first instruction; in the second clock cycle, obtains the second program counter value from the program counter generation unit; uses the second program counter value as the first program counter value, and returns to the execution step: in the first clock cycle, the instruction fetching unit of the processor reads the first instruction from the memory unit based on the first program counter value; The first preset instruction is the instruction to be jumped to in the jump instruction, and the second preset instruction is a sequential instruction or a jump instruction that does not jump.
2. An instruction processing device, characterized in that, Located in a processor, the device includes: The data generation module is used to generate a first immediate value through a program counter and use the first immediate value as the first program counter value. The instruction fetch module is used to fetch the first instruction from the memory unit according to the first program counter value through the processor instruction fetch unit; A decoding module is used to pass the first instruction to a pre-decoding unit so that the pre-decoding unit can decode and judge the first instruction; An instruction processing module is configured to fetch, decode, and execute instructions through the processor instruction fetch unit and branch prediction unit if the first instruction is a first preset instruction. Specifically, this includes: in a first clock cycle, the processor instruction fetch unit reads the first instruction from the memory unit based on the first program counter value; delays the first immediate value and the first program counter value by one clock cycle to execute the corresponding operation in a second clock cycle; sets a second program counter value, which is generated by incrementing the first program counter value; sends the second program counter value to a program counter generation unit; sends the first instruction to an instruction register, causing the instruction register to send the first instruction to an execution unit, and the execution unit executes the first instruction; in a second clock cycle, obtains the second program counter value from the program counter generation unit; calculates the first immediate value and the first program counter value using an adder to generate a first jump target address; flushes the pipeline through the processor instruction fetch unit to flush away the second program counter value; and returns to the execution step, using the first jump target address as the first program counter value. The instruction processing module is further configured to, if the first instruction is a second preset instruction, fetch, decode, and execute the instruction through the processor instruction fetch unit, specifically including: in a first clock cycle, reading the first instruction from the memory unit based on the first program counter value through the processor instruction fetch unit; setting a second program counter value, the second program counter value being generated by incrementing the first program counter value; sending the second program counter value to the program counter generation unit; sending the first instruction to the instruction register, so that the instruction register sends the first instruction to the execution unit, and the execution unit executes the first instruction; in a second clock cycle, obtaining the second program counter value from the program counter generation unit; using the second program counter value as the first program counter value, and returning to the execution step: in the first clock cycle, reading the first instruction from the memory unit based on the first program counter value through the processor instruction fetch unit; the first preset instruction is the instruction to be jumped to in a jump instruction, and the second preset instruction is a sequential instruction or a non-jump jump instruction.
3. An instruction processing device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the instruction processing method as described in claim 1.
4. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the instruction processing method as described in claim 1.