Non-volatile memory controller, control method, and computer program product

Abstract

The invention relates to reliable control techniques for non-volatile memories. Specifically, the invention relates to a non-volatile memory controller, a control method and a computer program product. The non-volatile memory is provided with a plurality of blocks. A processor of a non-volatile memory controller includes a time tag for recording at least one page in each block for programming. The processor executes a reliability check on a target block corresponding to a target block whose time label exceeds a critical time limit, and moves data of the target block to the standby area when the reliability of the target block is lower than a critical standard.

Description

Technical Field

[0001] This invention relates to control technology for non-volatile memory. Background Technology

[0002] Non-volatile memory comes in various forms—for example, flash memory, magnetoresistive RAM, ferroelectric RAM, resistive RAM, spin transfer torque-RAM (STT-RAM), etc.—and is used for long-term data storage and can be used as a storage medium to realize a data storage device.

[0003] The storage media mentioned above may change over time, and the data becomes increasingly unreliable with age. How to efficiently control non-volatile memory and ensure its data retention is an important issue in this technical field. Summary of the Invention

[0004] This technical field proposes a non-volatile memory control technology to effectively ensure data retention.

[0005] A non-volatile memory controller according to one embodiment of the present invention includes a communication interface and a processor. The communication interface is coupled to a non-volatile memory having multiple blocks. The processor executes program code to operate the non-volatile memory through the communication interface. The processor records a time stamp when at least one page in each block is programmed. For a target block whose corresponding time stamp exceeds a critical time limit, the processor performs a reliability check on the target block. If the reliability of the target block is lower than a critical criterion, the data of the target block is moved to a spare area.

[0006] In one implementation, the write / erase count for the corresponding block has an adaptively set critical time limit. Alternatively, the critical time limit may be set differently depending on the type of block (e.g., a three-level storage unit and a single-level storage unit).

[0007] In one implementation, reliability checks employ error correction code (ECC) technology.

[0008] In one implementation, the processor scans through blocks whose timestamps have exceeded the critical time limit, selecting those for which reliability checks are performed.

[0009] In one implementation, the scan queue defines a single block. When the scan queue is not empty, the processor uses the block recorded in the scan queue as the target block and performs a reliability check on the target block. When the scan queue is empty and the timestamp of an active block exceeds the critical time limit, a reliability check is performed on the active block; wherein, if the reliability of the active block is lower than the critical standard, the data of the active block is moved to a spare area. The processor further finds a data block according to a write order chain, and pushes the data block into the scan queue when the timestamp of the data block exceeds the critical time limit.

[0010] When the scan queue is empty and the timestamp of the active block has not exceeded the critical time limit, the processor can find a data block according to a write order chain. If the timestamp of the data block exceeds the critical time limit, the data block is pushed into the scan queue. If the processor subsequently discovers that the scan queue is not empty, it can use the block recorded in the scan queue as the target block, perform a reliability check, and then perform a secure migration.

[0011] In one implementation, when the processor performs a reliability check on the target block, it checks at least one page of special interest in the target block.

[0012] In one implementation, the processor dynamically updates the timestamps of each block on a volatile memory, then archives them from the volatile memory to the non-volatile memory, forming a timestamp table, which is stored in a system block of the non-volatile memory. Upon startup, the processor first performs reliability checks and secure migrations on the pages of particular interest for all blocks in the non-volatile memory, and then loads the timestamp table stored in the system block back to the volatile memory for management.

[0013] The present invention improves the waste recycling technology and is used to implement a non-volatile memory control method.

[0014] The present invention further implements program code according to the non-volatile memory control method to produce a computer program product.

[0015] The following detailed description of the invention is illustrated with specific examples and accompanying drawings. Attached Figure Description

[0016] Figure 1 Illustrated physical structure of a block Blk in flash memory;

[0017] Figure 2 The diagram illustrates an electronic system 200 implemented according to an embodiment of the present invention, including a flash memory 202 constituting a data storage device, a controller 204, and a host 206 operating the data storage device.

[0018] Figure 3 The flowchart illustrates the operations performed by processor 212 upon triggering, involving a time stamp check.

[0019] Figure 4 This is a flowchart illustrating the details of reliability checks and safe handling according to one embodiment of the present invention.

[0020] [Symbol Explanation]

[0021] 200: Electronic Systems

[0022] 202: Flash memory

[0023] 204: Controller

[0024] 206: Host

[0025] 208: Flash Memory Interface

[0026] 210: Host Interface

[0027] 212: Processor

[0028] 214: Volatile Memory

[0029] 216: Register

[0030] 218: Program Code

[0031] 220: Memory

[0032] ABlk: Active Block Pool

[0033] Blk: Block

[0034] DataBlk: Data Block Pool

[0035] LinkList: Write-order linked list

[0036] Meta_Area: Metadata area

[0037] MU0_0…MU0_3: Management Unit

[0038] S0_0…S0_31: Section

[0039] S302…S318、S402…S414: Steps

[0040] SpareBlk: Spare Block Pool

[0041] SQ: Scan queue

[0042] SysBlk: System Block Pool

[0043] time_stamp: Scan stamp

[0044] TS_table: Time stamp table Detailed Implementation

[0045] The following description illustrates various embodiments of the present invention. The following description introduces the basic concepts of the invention and is not intended to limit the scope of the invention. The actual scope of the invention should be defined according to the scope of the patent application. The various functional blocks mentioned below can be implemented by a combination of hardware, software, and firmware, and may also include special circuits. The various functional blocks are not limited to separate implementations; they can also be combined to share certain functions.

[0046] Non-volatile memory can be flash memory, magnetoresistive RAM, ferroelectric RAM, resistive RAM (RRAM), spin transfer torque RAM (STT-RAM), etc., providing storage media for long-term data retention. The following discussion focuses on flash memory as an example, but the technology can also be used in other types of non-volatile memory.

[0047] Today, data storage devices commonly use flash memory as the storage medium to realize products such as memory cards, USB flash devices, solid-state drives (SSDs), and universal flash memory devices (UFSDevice). One application is to use multi-chip packaging, combining the flash memory and its controller together—this is called an embedded flash memory module (such as eMMC).

[0048] Data storage devices using flash memory as the storage medium can be applied to a variety of electronic devices. These electronic devices include smartphones, wearable devices, tablets, virtual reality devices, etc. The processor of the electronic device can be regarded as a host, which operates the data storage device configured in the electronic device and accesses the flash memory as the storage medium through the controller therein.

[0049] Data storage devices that use flash memory as the storage medium can also be used to build data centers. For example, servers can operate solid-state drive (SSD) arrays to form a data center. The server can be regarded as a host, operating the connected SSDs and accessing the flash memory as the storage medium through the controllers within them.

[0050] In-vehicle systems can also use flash memory as a data storage device. The various sensors in an in-vehicle system can be considered as host devices, and they will also have a need to access data storage devices.

[0051] Flash memory has unique storage characteristics. The host issues read and write requests to the flash memory using logical addresses (e.g., Logical Block Address (LBA) or Global Host Page Number (GHP)). Logical addresses must be mapped to physical addresses to correspond to the physical space of the flash memory.

[0052] The physical space of flash memory is divided into multiple blocks for configuration and use. Figure 1 Illustrated diagram of the physical structure of a block Blk in flash memory.

[0053] A block (Blk) comprises multiple pages; for example, pages 0 through 255. Each page comprises multiple sectors, for example, page 0 has 32 sectors S0_0 through S0_31. Each sector can store 512 bytes of user data; a page provides 16KB of storage space. The four sectors can be managed uniformly, as shown in the diagram as management units MU0_0 / MU0_1 / MU0_2 / MU0_3. A block (Blk) includes a meta data area (Meta_Area), composed of the space at the end of each page, which stores meta data.

[0054] One implementation uses the storage space of block Blk sequentially according to page number—from low number (page 0) to high number (page 255). Alternatively, some implementations use multi-channel technology, which significantly improves data throughput, treating blocks accessed through different channels as a single superblock; pages with the same number in blocks across different channels are considered superpages. Multi-channel technology can use the storage space of a superblock sequentially according to superpage number—from low to high. In some applications, a block refers to a superblock. This invention does not limit the size of blocks, pages, or segments. The discussion of specific sizes is for illustrative purposes only.

[0055] In particular, flash memory has an important characteristic: storage space must be erased in blocks before it can be reused. Data updates at the same logical address do not overwrite the old data's storage space. The new version of the data must be written to the spare space. The contents of the old space become invalid. After scattered valid data is removed by garbage collection, only blocks of invalid data remain to be erased and reconfigured as active data blocks to handle subsequent write requests from the host. When an active block is full, it is closed with end-of-block information (EoB; for example, page 255 at the end of block Blk), making it a data block. This closure is recorded at the end of a write order link (hereinafter referred to as LinkList). The write order link (LinkList) displays the closing order of the data blocks.

[0056] However, the data retention capability of flash memory weakens over time, and the stored content may change. This invention records a timestamp (e.g., the starting page) of at least one page from each block during programming. This timestamp is used to identify outdated or unreliable target blocks, and a reliability check is performed on them. When the reliability of a target block falls below a critical criterion, the data in that target block is moved to a spare area. This data migration based on the results of the reliability check is called secure migration.

[0057] Figure 2The diagram illustrates an electronic system 200 implemented according to an embodiment of the present invention, including a flash memory 202, a (non-volatile memory) controller 204, and a host 206. The controller 204 includes a flash interface 208 coupled to the flash memory 202, a host interface 210 coupled to the host 206, and a processor 212. Upon request from the host 206, the processor 212 operates to access the flash memory 202 through the flash interface 208. The flash interface 208 is provided for the flash memory 202; if other types of storage media are used, a corresponding communication interface can be used instead. The flash interface 208 and the flash memory 202 can communicate with each other using a Double Data Rate (DDR) communication protocol; for example, Open NAND Flash Interface (ONFI), DDR Toggle, or other communication protocols. The controller 204 can communicate with the host 206 via the host interface 210 using communication protocols such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), Universal Flash Storage (UFS), and Embedded Multi-Media Card (eMMC).

[0058] The flash memory 202 may include a system block pool SysBlk, a data block pool DataBlk, a spare block pool SpareBlk, and an active block pool ABlk. The non-volatile storage of timestamps for each block in this invention can be implemented using the system block pool SysBlk. User data is stored in the data block pool DataBlk. The spare block pool SpareBlk does not contain valid data; blocks in this pool can be selected, erased, and pushed into the active block pool ABlk as active blocks. Active blocks can be used to receive data written by the host 206 or to collect valid data for garbage collection (GC).

[0059] As shown in the figure, the controller 204 may further include volatile memory (DRAM or SRAM) 214. With the use of active blocks, the processor 212 records a time stamp (time_stamp) of at least one page, such as the starting page, in the volatile memory 214 during programming. One implementation arranges these timestamps into a time stamp table (TS_table) displaying the time stamps corresponding to each block. For a target block (potentially an active block or a data block) whose corresponding time stamp (time_stamp) exceeds a critical time limit, the processor 212 performs a reliability check on the target block. If the reliability of the target block falls below a critical criterion, the data of the target block is moved to a spare area (e.g., a spare block in a spare block pool, SpareBlk).

[0060] As shown in the figure, processor 212 can dynamically manage the write order link list in volatile memory 214. Processor 212 can perform time_stamp checks on data blocks according to the block closing order based on the write order link list, and perform reliability checks based on the check results. In particular, time_stamp checks of active blocks can be inserted between checks of different data blocks, and reliability checks can be performed based on the check results, as well as possible safe relocation after the reliability checks. This invention not only ensures the reliability of closed (written EOB) data blocks, but also improves the reliability of open (not yet written EOB) active blocks.

[0061] Reliability assessment can be achieved using Error Correction Code (ECC) technology. ECC technology detects erroneous blocks of data and safely moves them before the data becomes irreparable.

[0062] The critical timeout used can be adaptively adjusted according to the condition of the flash memory 202. In one embodiment, the critical timeout is adaptively set according to the erase count of the checked block; for example, different levels of erase count correspond to different critical timeouts, wherein a higher erase count corresponds to a shorter critical timeout, enabling timely reliability checks and safe relocation that may be performed after the reliability check. In one embodiment, the critical timeout is set differently for three-level cell (TLC) and single-level cell (SLC). For example, the critical timeout of a three-level cell (TLC) is shorter than that of a single-level cell (SLC), enabling timely reliability checks and safe relocation that may be performed after the reliability check.

[0063] In one implementation, when the processor 212 performs a reliability check on the target block, it only checks pages of particular interest. For example, the first five pages.

[0064] The illustrated processor 212 is equipped with register 216, allowing the designer to enter adaptive critical timeouts (e.g., a table showing the critical timeout lengths corresponding to different erase count levels) and the numbers of pages of special concern. In this way, different regions of flash memory 202 can correspond to different critical timeouts depending on their state. The pages of special concern for local checks can also be determined by the designer.

[0065] The non-volatile memory control method implemented by the processor 212 based on the aforementioned concept also falls within the scope of protection of this invention. The processor 212 executes program code 218 to implement the non-volatile memory control method of this invention. Program code 218 can be packaged into a computer program product, loaded into memory 220, and executed by the processor 212.

[0066] One implementation further limits the execution of reliability checks and subsequent secure transfers, ensuring that time-consuming secure transfers are not performed consecutively on several blocks while still meeting the host 206's access requirements to the flash memory 202. The illustration shows a scan queue SQ managed in the volatile memory 214, recording data blocks whose timestamps exceed a critical time limit. The limited depth of the scan queue SQ restricts the execution of reliability checks and subsequent secure transfers.

[0067] One implementation further limits the scanning queue SQ to only a single block. This will be explained below.

[0068] Figure 3 The flowchart illustrates the operations performed by processor 212 upon triggering, involving a timestamp check. Upon triggering, processor 212 checks in step S302 whether the scan queue SQ is empty. If so, processor 212 retrieves an active block that has not yet been written to the EOB in step S304, and checks in step S306 whether the timestamp of the active block exceeds a critical time limit. If so, processor 212 performs a reliability check on the active block in step S308. If the reliability of the active block is lower than the critical standard, the data of the active block is moved to a spare area.

[0069] In the illustrated embodiment, if step S306 determines that the timestamp of the active block has not exceeded the critical time limit, or if step S308 is completed, processor 212 finds a data block according to a write order link List in step S310, and determines in step S312 whether the timestamp (time_stamp) of the data block has exceeded the critical time limit. If so, processor 212 pushes the data block into the scan queue SQ in step S314, and... Figure 3 The process is complete.

[0070] If step S312 shows that the currently observed data block has not yet exceeded the critical time limit, processor 212 proceeds to step S316 to determine whether the end of the write order link list has been reached. If so, Figure 3 The process ends. Otherwise, processor 212 executes step S310 again, links the LinkList according to the write order, finds the next data block, and performs a time stamp check (S312).

[0071] If step S302 shows that the scan queue SQ is not empty, the processor 212 performs a reliability check on the blocks carried by the scan queue SQ and performs necessary safe relocation in step S318.

[0072] Figure 4 The flowchart illustrates the details of reliability checking and secure transfer according to one embodiment of the present invention, corresponding to step S308 with the active block as the target block, or step S318 with the data block carried in the scanned queue SQ as the target block.

[0073] Processor 212 first initializes a page index in step S402, and then determines in step S404 whether the page index points to a designated page of special interest. If so, processor 212 reads the designated page of special interest in step S406, and determines in step S408 whether it falls below the critical criteria (e.g., whether an error has been detected by ECC technology). If it falls below the critical criteria, processor 212 performs a safe migration of the entire target block in step S410; for example, migrating the entire target block to a spare block. Next, processor 212 clears the scan queue SQ in step S412. In this way, the capacity depth of the scan queue SQ is determined to be able to load only the number of one block, and the size does not need to be too large.

[0074] If the data quality at the location indicated by the page index in step S408 meets the critical criteria (e.g., the data is confirmed to be correct via ECC technology), the processor 212 modifies the page index in step S414 and switches to check other pages until all pages of special concern in this block have been checked.

[0075] In one implementation, Figure 3The process can be triggered in the background of the overall device (when the controller 204 does not need to respond to the host 206's requests). In one embodiment, Figure 3 The process can be triggered periodically. For example, the scan queue SQ can be checked once every second (step S302). Figure 3 Figure 4 Under the process design, the safe transfer of different blocks will not occur consecutively. The controller 204 can switch back to handle the host 206's access requests to the flash memory 202 as needed.

[0076] This invention also proposes a solution for situations where the device has not been used for a long time.

[0077] In one implementation, in addition to dynamically updating the time stamps (time_stamps) of each block on the volatile memory 214, the processor 212 also stores them in the flash memory 202 as a time stamp table (TS_table), which is stored in a system block (SysBlk) of the flash memory 202. When the processor 212 is started, it performs reliability checks and secure relocation of the pages of special interest in all blocks of the flash memory 202, and then loads the time stamp table (TS_table) stored in the system block back to the volatile memory 214 for management, for use in subsequent periodically triggered time limit checks.

[0078] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A non-volatile memory controller, comprising: A communication interface coupled to a non-volatile memory having multiple blocks; as well as A processor executes program code to operate the non-volatile memory through the communication interface. in: The processor records a time tag when at least one page of each block is programmed; and For a target block whose corresponding time tag exceeds a critical time limit, the processor performs a reliability check on the target block. If the reliability of the target block is lower than a critical standard, the data of the target block is moved to a spare area.

2. The non-volatile memory controller as described in claim 1, characterized in that: The size of the critical time limit is determined by the write count of the corresponding block or the type of the corresponding block.

3. The non-volatile memory controller as described in claim 2, characterized in that: The processor performs a reliability check on the target block using error correction code (ECC) technology.

4. The non-volatile memory controller as described in claim 1, characterized in that: The processor scans through blocks whose timestamps have exceeded the critical time limit, selecting those to perform reliability checks.

5. The non-volatile memory controller as described in claim 4, characterized in that: When the scan queue is not empty, the processor uses the block recorded in the scan queue as the target block and performs a reliability check on the target block.

6. The non-volatile memory controller as described in claim 4, characterized in that: When the scan queue is empty and the timestamp of an active block exceeds the critical time limit, the processor performs a reliability check on the active block. If the reliability of the active block is lower than the critical standard, the data of the active block is moved to the spare area. Furthermore, the processor finds a data block according to a write order chain. If the timestamp of the data block exceeds the critical time limit, the data block is pushed into the scan queue.

7. The non-volatile memory controller as described in claim 4, characterized in that: When the scan queue is empty and the timestamp of the active block has not exceeded the critical time limit, the processor finds a data block according to a write order chain. When the timestamp of the data block exceeds the critical time limit, the data block is pushed into the scan queue.

8. The non-volatile memory controller as claimed in claim 1, wherein: When the processor performs a reliability check on the target block, it checks at least one page of special interest in the target block.

9. The non-volatile memory controller as described in claim 1, characterized in that: The processor dynamically updates the timestamps of each block in a volatile memory, then seals them from the volatile memory to the non-volatile memory, forming a timestamp table, which is stored in a system block of the non-volatile memory; and At startup, the processor performs a reliability check on the pages of particular interest in all blocks of the non-volatile memory and performs data migration based on the results of the reliability check, and then loads the timestamp table stored in the system blocks back into the volatile memory.

10. A method for controlling a non-volatile memory, comprising controlling a non-volatile memory including multiple blocks, including: Record a time tag when at least one page of each block is programmatically processed; and For a target block whose corresponding time tag exceeds a critical time limit, a reliability check is performed on the target block. If the reliability of the target block is lower than a critical standard, the data of the target block is moved to a spare area.

11. The non-volatile memory control method as described in claim 10, characterized in that: The size of the critical time limit is determined by the write count of the corresponding block or the type of the corresponding block.

12. The non-volatile memory control method as described in claim 11, characterized in that: This reliability check uses error correction code (ECC) technology.

13. The non-volatile memory control method as described in claim 10, characterized in that, Also includes: A scan is used to record blocks whose timestamps exceed the critical time limit, which are then selected for reliability checks.

14. The non-volatile memory control method as described in claim 13, characterized in that, Also includes: When the scan column is not empty, the block recorded in the scan column is taken as the target block, and a reliability check is performed on the target block.

15. The non-volatile memory control method as described in claim 14, characterized in that, Also includes: When the scan queue is empty and the timestamp of an active block exceeds the critical time limit, a reliability check is performed on the active block. If the reliability of the active block is lower than the critical standard, the data of the active block is moved to the spare area. Furthermore, a data block is found according to a write order link. If the timestamp of the data block exceeds the critical time limit, the data block is pushed into the scan queue.

16. The non-volatile memory control method as described in claim 13, characterized in that, Also includes: When the scan queue is empty and the timestamp of the active block has not exceeded the critical time limit, a data block is found according to a write order chain. When the timestamp of the data block exceeds the critical time limit, the data block is pushed into the scan queue.

17. The non-volatile memory control method as described in claim 10, characterized in that, Also includes: When performing a reliability check on the target block, at least one page of special interest in the target block is checked.

18. The non-volatile memory control method as described in claim 10, characterized in that, Also includes: The timestamps of each block are dynamically updated on a volatile memory, then sealed from the volatile memory to the non-volatile memory, forming a timestamp table, which is stored in a system block of the non-volatile memory; and At startup, a reliability check is performed on the pages of particular interest for all blocks of the non-volatile memory, and data migration is performed based on the results of the reliability check. Then, the timestamp table stored in the system blocks is loaded back into the volatile memory.

19. A computer program product comprising program code, executed by a processor, implementing the non-volatile memory control method as described in any one of claims 10 to 18.

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