General double-circuit mainboard high-speed signal optimization method

Abstract

The invention discloses a universal double-circuit mainboard high-speed signal optimization method, and relates to the technical field of mainboard signal optimization, and the method comprises the steps: collecting a power supply network input signal and a high-speed link differential signal error code sequence, calculating the cross spectrum density and coherence degree, and recognizing a dominant coupling peak frequency point with significant correlation between power supply noise and an error code; constructing a power supply integrity and signal integrity feasible action set and generating candidate combinations, and predicting the change effect of each combination on the influence coefficient through a multiplicative model; based on the power supply integrity suppression contribution degree, the signal integrity suppression contribution degree and the error code improvement amount, screening out an optimal parameter combination with the maximum total suppression contribution degree in combination with single-branch optimization and double-branch ratio criteria; and finally, implementing the combination and verifying the optimization effect by retesting the performance index. Accurate collaborative optimization of power supply integrity and signal integrity is realized, high-speed link signal quality and system stability are effectively improved, and the method is suitable for various mainboard configuration and topology scenes.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of mainboard signal optimization, and more particularly, to a universal dual-channel mainboard high-speed signal optimization method. BACKGROUND

[0002] Under the development trend of high-performance computing and data centers, the data rate of the mainboard high-speed interconnection link jumps from the traditional hundreds of megabits per second to tens of gigabits per second. The universal dual-channel mainboard needs to support new generation interconnection protocols such as PCIe Gen5 / Gen6, power integrity PI 2.0, and the like, and also needs to consider various combinations of boards. With the increase of interface rate and system complexity, the traditional method of analyzing signal integrity (SI) and power integrity (PI) separately gradually exposes limitations: the decoupling capacitor network noise generated by high-frequency switching current can enter the high-speed differential pair through common-mode coupling to cause inter-symbol interference; ground bounce noise and plane resonance can cause interface clock jitter, which in turn affects the effect of link training and equalization algorithm; deformation caused by heat dissipation and mechanical stress can change the differential line impedance; the length of the link and the number of connectors vary greatly in different topological combinations, making it difficult to complete full-coverage verification in the laboratory at one time.

[0003] The modern design process has emerged a co-simulation concept of signal integrity and power integrity. This method advocates considering signal quality and power noise in a unified simulation environment in order to discover coupling effects early and optimize jointly. However, the existing co-simulation still mainly relies on offline analysis, and depends on the experience of engineers to determine the decoupling capacitor network and equalization parameters. It lacks adaptive optimization capability in the face of the combinatorial explosion problem of nearly a hundred optional configurations of the universal dual-channel mainboard, and cannot dynamically perceive and compensate for environmental changes in the field. These deficiencies often cause link training failure, speed reduction, or intermittent errors in batch products in actual deployment, which seriously affects the reliability and computing performance of the whole machine. In view of the above problems, the present application provides a solution. SUMMARY

[0004] In order to overcome the above-mentioned defects of the prior art, the embodiments of the present application provide a universal dual-channel mainboard high-speed signal optimization method to solve the problems raised in the background art.

[0005] To achieve the above object, the present application provides the following technical scheme: A universal dual-channel mainboard high-speed signal optimization method, comprising the following steps: The input signal of the power supply network and the differential signal error code sequence of the high-speed link are collected, the cross-spectral density and the coherence of the input signal and the error code sequence are calculated, and based on a preset coherence threshold and an influence coefficient threshold, a dominant coupling peak frequency point with significant correlation between the power supply noise and the error code is identified; Based on the identified dominant coupling peak frequency point, a power integrity actionable set and a signal integrity actionable set are obtained, and each action in the power integrity actionable set is systematically combined with each action in the signal integrity actionable set to generate a candidate action combination set. The effect of each candidate action combination on the change of the influence coefficient is predicted by a multiplicative model, and the influence coefficient represents the degree of influence of the power supply noise on the error code. Based on the prediction result, the power integrity suppression contribution degree and the signal integrity suppression contribution degree of each candidate action combination are calculated, and then the target total suppression contribution degree is calculated based on the influence coefficient baseline and the target threshold, and the optimal parameter combination with the maximum total suppression contribution degree is selected from the candidate action combinations based on the error code improvement amount. The power integrity suppression contribution degree is based on the power supply noise spectrum amplitude change ratio, and the signal integrity suppression contribution degree is based on the cross-spectral density change ratio. The optimal parameter combination is implemented, and the performance of the high-speed mainboard is retested, and the optimization effect is determined by comparing whether the key performance indicators before and after optimization reach the preset target.

[0006] In a preferred embodiment, calculating the cross-spectral density and the coherence includes: the cross-spectral density is the Fourier transform of the cross-correlation function of the source network input signal and the differential signal error code sequence, which is used to characterize the correlation strength of the two signals at different frequencies; for the discrete sampled power supply network input signal and the differential signal error code sequence, the cross-spectral density is calculated by discrete Fourier transform, specifically, the fast Fourier transform is performed after the signal is framed, the autospectral density is obtained by averaging the square modulus of each frame frequency sequence, and the cross-spectral density is obtained by averaging the conjugate product of the corresponding frame frequency sequence; the coherence function is used to measure the linear correlation of the power supply network input signal and the differential signal error code sequence at each frequency point, and its calculation is based on the cross-spectral density and the autospectral density of the two signals.

[0007] In a preferred embodiment, identifying the dominant coupling peak frequency point specifically includes: wherein, is the frequency domain amplitude of the power supply network input signal, is the calculated cross-spectral density of the power supply network input signal and the differential signal error code sequence; The frequency point that satisfies the coherence and the path influence coefficient is selected as the dominant coupling peak frequency point, and the is the coherence threshold, is the impact coefficient threshold.

[0008] In a preferred embodiment, the power integrity actionable set includes decoupling capacitor related parameters, equivalent series resistance, decoupling capacitor location, return path optimization parameters. The signal integrity actionable set includes transmit pre-emphasis coefficients, receive continuous time linear equalization levels, decision feedback equalization coefficients.

[0009] In a preferred embodiment, the multiplicative model is expressed as and is defined as the combined impact coefficient, where is the identified dominant coupling peak frequency point, represents power integrity, SI represents signal integrity, is the impact coefficient baseline value, is the power noise spectrum amplitude change ratio, is the cross-spectral density change ratio; by implementing the power integrity action , on the basis of the power integrity action, the signal integrity action is implemented to obtain , and then the change effect of the combined action on the impact coefficient is predicted.

[0010] In a preferred embodiment, at the baseline , the local linear regression is performed using the baseline bit error rate time series data and the synchronized impact coefficient time series data to calculate the local sensitivity , and the bit error improvement amount is obtained through first-order extrapolation ; wherein is the predicted impact coefficient predicted by the multiplicative model, i represents the index of the data point, represents the impact coefficient corresponding to the i-th data point deviating from the baseline bit error rate , represents the bit error rate corresponding to the i-th data point deviating from the baseline bit error rate , is the partial differential symbol.

[0011] In a preferred embodiment, the power integrity suppression contribution degree is calculated, the signal integrity suppression contribution degree is calculated; the target total suppression contribution degree is ; wherein, is the impact coefficient baseline, is the target impact threshold.

[0012] ​​In a preferred embodiment, the screening of the optimal parameter combination comprises: calculating a total suppression contribution degree of each candidate action combination based on the power integrity suppression contribution degree and the signal integrity suppression contribution degree of the candidate action combination; performing multi-priority screening according to a preset priority rule in combination with the total suppression contribution degree and the error code improvement amount; the priority rule comprises a single-branch optimization criterion applicable to a single-branch optimization scenario, and a double-branch proportioning criterion applicable to a power integrity and signal integrity collaborative optimization scenario; and the optimal parameter combination with the largest total suppression contribution degree is selected from the candidate action combinations through the multi-priority screening.

[0013] In a preferred embodiment, the single-branch optimization criterion specifically comprises: a power integrity single-branch optimization, that is, selecting an action scheme from the power integrity actionable actions that satisfies a predicted impact coefficient after the single-branch optimization is lower than an impact coefficient threshold and has the largest power integrity suppression contribution degree; and a signal integrity single-branch optimization, that is, selecting an action scheme from the signal integrity actionable actions that satisfies a predicted impact coefficient after the single-branch optimization is lower than an impact coefficient threshold and has the largest signal integrity suppression contribution degree.

[0014] In a preferred embodiment, the double-branch proportioning criterion is that: for a collaborative action combination of the power integrity and the signal integrity, a proportioning coefficient model is established, wherein a contribution proportion of the power integrity branch is , and a contribution proportion of the signal integrity branch is ; according to a value range of the proportioning coefficient , the candidate combination is divided into different proportioning strategy intervals, including a weak power integrity strong signal integrity interval, a balanced proportioning interval, and a strong power integrity weak signal integrity interval; and based on the proportioning strategy intervals, a preliminary adjustment direction of the power integrity parameter and the signal integrity parameter is respectively specified within a feasible engineering range: when in the weak power integrity strong signal integrity interval, the power integrity parameter takes an average value of the feasible range, and the signal integrity parameter takes a maximum value of the feasible range; when in the balanced proportioning interval, an adjustable proportional weight is introduced, and values of the power integrity parameter and the signal integrity parameter are calculated by weighting between the respective extreme values of the feasible ranges according to the weight; when in the strong power integrity weak signal integrity interval, the power integrity parameter takes an upper limit value of the feasible range, and the signal integrity parameter takes an intermediate value of the feasible range; and after the preliminary adjustment direction is determined, the candidate combination is screened in the following priority order: first priority, screening a candidate action combination that satisfies and has an optimized error code rate meeting an industry standard, wherein is a total suppression contribution degree and Second priority, in the candidate action combination meeting the first priority, the optimized bit error rate of the combination meeting the industry standard is screened; in the combination meeting all priorities, the combination with the largest total suppression contribution is selected as the optimal parameter combination.

[0015] The technical effect and advantages of the universal dual-channel mainboard high-speed signal optimization method are as follows: Through cross-spectral density and coherence analysis, the power supply noise coupling frequency points with significant bit error influence can be accurately identified from the frequency domain, overcoming the limitations of PI / SI isolated analysis in traditional methods, providing a clear target for targeted optimization; by constructing a candidate action combination set and using a multiplicative model for effect prediction, joint simulation and rapid evaluation of power integrity and signal integrity parameters are realized, effectively solving the problem of low optimization efficiency caused by configuration combination explosion; the suppression contribution and bit error improvement are introduced as quantitative indicators, and single-branch optimization and double-branch matching criteria based on matching coefficients are combined for multi-level screening, so that the parameter selection process has a basis and can adaptively recommend the optimal performance and engineering feasible optimization scheme, reducing the excessive dependence on engineers' experience. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 The flowchart of the universal dual-channel mainboard high-speed signal optimization method of the present application is shown in the figure. Figure 2 The implementation logic diagram of step three in the universal dual-channel mainboard high-speed signal optimization method of the present application is shown in the figure. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0018] EMBODIMENT Please refer to Figure 1 As shown in the figure, the present application discloses a universal dual-channel mainboard high-speed signal optimization method, including the following steps: Step one: by collecting the input signal of the power network and the differential signal error code sequence of the high-speed link, the input signal and the error code sequence are analyzed in the frequency domain, the cross-spectral density between them is calculated, and the coherence degree for measuring the linear correlation degree is calculated; based on the preset coherence threshold and the influence coefficient threshold for quantifying the influence degree of power noise on error code, one or more dominant coupling peak frequencies with significant correlation between power noise and link error code are identified from the frequency domain; the identification process relies on the joint criterion of the modulus of cross-spectral density and coherence, ensuring that the located frequency points are the main threat to the system error performance; In the high-speed mainboard system, the input signal of the power network is denoted as , which is used to represent the transient voltage characteristics of the power network; the differential signal error code sequence output by the high-speed link is defined as , which is used to reflect the occurrence law of link error code; both types of signals are obtained through standardized test collection to ensure the authenticity and effectiveness of the data; Further, according to the frequency domain statistical theory, the cross-spectral density of two random signals is the Fourier transform of their cross-correlation function, which is used to represent the correlation strength of the two signals at different frequencies, and is defined as: ; Wherein, and respectively represent two random signals, which correspond to the input signal of the power network and the differential signal error code sequence of the high-speed link in this method, is the cross-spectral density of signals and , is the cross-correlation function of signals and , is the cross-correlation function of signals and , reflecting the correlation of the two signals at time delay , is the time delay variable, representing the time difference between the signals, is the frequency variable, representing the frequency component of the signal; For the cross-spectral density of discrete sampling signals, i.e. the power network and the error code sequence, it is denoted as , the cross-spectral density is calculated by discrete Fourier transform (DFT), and its modulus directly reflects the correlation strength of the two signals at the corresponding frequency point. The specific process is as follows: The input is the preprocessed discrete time sequence, the power network input signal , the differential signal error code sequence ; Wherein, , the data length and , which is suitable for efficient calculation of fast Fourier transform (FFT); The long sequence is divided into frames, each with a length of N and an inter-frame overlap rate of 50%, which reduces the fluctuation in spectral estimation caused by the randomness of single-frame data. Input signals to the power network Perform a Fast Fourier Transform (FFT) on each frame of data to obtain a complex sequence in the frequency domain. For differential signal bit error sequences Perform a Fast Fourier Transform (FFT) on each frame of data to obtain its frequency domain complex sequence. Where i is the frame number, and For frequency points, Sampling rate; For all frames Average power supply noise self-spectral density ,Right now K represents the total number of frames, ensuring quantization consistency; similarly, for all frames... The average autospectral density of the bit error sequence is obtained. ; The average of the conjugate products of the frequency domain sequences of corresponding frames of the two types of signals is obtained by... ; , For the i-th frame The Fast Fourier Transform (FFT) results of and the Fast Fourier Transform (FFT) conjugate results of e; To eliminate the interference of signal energy differences on correlation determination, a coherence function is introduced. Measuring the input signal of the power network With differential signal bit error sequence The linear correlation at each frequency point is defined as: in, The value ranges from 0 to 1. The higher the value, the stronger the linear correlation between power supply noise and link error at that frequency. To quantify the actual impact of noise in a certain frequency band on bit errors, a path influence coefficient is defined. The product of the cross-spectral density modulus and the power supply noise spectral amplitude is given by the following formula: in, Input signal to the power network frequency domain amplitude, The larger the value, the more significant the impact of power supply noise on link bit error rate at the corresponding frequency. If the system contains multiple high-speed links and multiple power supply networks, the differential signal error sequence... Defined as the error voltage of the pulse sequence of the bit error event or the clock data recovery unit (CDR), ensuring the compatibility and versatility of the method for multi-link scenarios; It should be noted that, in order to ensure the comparability of the analysis under different topologies and environmental conditions, the excitation and collection caliber are unified in this step: At the high-speed link end, a pseudo-random binary sequence PRBS31 is injected into the link to be tested through a programmable pattern generator, and a step current excitation is applied at the power supply end to excite the transient characteristics of the power supply network; the PRBS31 sequence can completely occupy the inter-symbol spectrum, effectively exposing the inter-symbol crosstalk and coupling effect; The transient voltage waveform of the power supply network node and the link error code sequence are collected; the sampling rate is set to more than 10 times the highest working rate of the system, for example, when the system rate is 32 Gb / s, the sampling rate is set to 320 GS / s; the collection time TT covers multiple power spectrum resolution units, satisfying , wherein the frequency resolution Δf is set to 1 MHz; this value is determined by analyzing the main power supply noise distribution frequency band, i.e. 1 MHz~1 GHz, taking into account the analysis accuracy and collection efficiency; the corresponding collection time ; The direct current and low frequency components are removed by a band-pass filter, and the Hanning window function is used to reduce spectral leakage, ensuring the stability and reliability of the cross-spectral density and coherence calculation results; Based on the above spectral density results, i.e. the power supply network input signal , the differential signal error code sequence , the cross-spectral density , the power supply noise self-spectral density and the error code sequence self-spectral density are calculated by using the fast Fourier transform algorithm; the coherence and the path impact coefficient at each frequency point are calculated by substituting the coherence and path impact coefficient formulas, and the multi-dimensional characteristic quantization is completed; According to engineering experience and historical data, the coherence threshold and the impact coefficient threshold are set; through frequency domain analysis, the frequency points that satisfy and are identified as the dominant coupling peak frequency points to be suppressed; if , i.e. the coherence is low, it is considered that the PDN noise and the error code sequence have insufficient correlation; it indicates that the power integrity PI has little effect on the signal integrity SI in the current board design, and the data can be directly recorded without further optimization; Specifically, after executing the above process on a certain type of high-speed mainboard system, it is detected at the 220MHz frequency point: , , so the frequency point is determined as the dominant coupling peak frequency point ; the determination process is verified by double indicators to ensure the accuracy of the positioning result; It should be noted that the coherence threshold The value is 0.65, which is determined by statistical analysis of system historical fault data, i.e. the coherence distribution of associated fault frequency points and the coupling mechanism simulation analysis. This threshold can effectively distinguish between strong and weak associated frequency points and avoid misjudgment. The influence coefficient threshold The value is 0.02V・V, which is determined by statistical analysis of multiple batches of test data of the same type of mainboard, combined with the baseline bit error rate qualified interval, i.e. the industry standard requires BER≤1×10⁻¹². This threshold ensures that only frequency points that have a significant impact on bit error are included in the dominant coupling peak frequency point range. After completing the positioning of the dominant coupling peak frequency point, the following quantitative baseline indicators are recorded as All indicators are obtained by actual measurement with standardized test equipment, including: Baseline bit error rate : The bit error rate is monitored for 24 hours by the bit error rate instrument, and the ratio of the number of bit errors to the total number of bits per unit time is calculated. The test result is ; This indicator directly reflects the initial bit error state of the link and provides a benchmark for subsequent optimization effect verification. Baseline eye height : The oscilloscope collects the differential signal of the link and generates an eye diagram. The eye opening height, i.e. the vertical margin, is extracted using eye diagram analysis software. The test result is 45mV. This indicator represents the waveform margin of the link and is a core evaluation parameter of link signal quality. Baseline influence coefficient : The path influence coefficient corresponding to the dominant coupling peak frequency point, with a value of 0.035, is used to quantify the influence strength of the dominant coupling peak frequency point.

[0019] The current system topology is also recorded simultaneously, including but not limited to link length, connector number, card type, as well as environmental temperature, load power information, as input variables for subsequent modeling and optimization.

[0020] Step two: Based on the successful identification of the dominant coupling peak frequency point, the power integrity actionable set and the signal integrity actionable set are constructed respectively. The power integrity actionable set includes adjustment options for power distribution network parameters, and the signal integrity actionable set includes adjustment options for high-speed link equalization and transmission parameters. Through the constructed multiplicative model, the candidate combination schemes formed by power integrity actions and signal integrity actions are simulated and the effect is predicted, and the change effect on the influence coefficient is evaluated, so as to pre-judge the effectiveness of different parameter adjustment strategies in suppressing noise coupling. Based on the path influence coefficient defined in step one , the power integrity PI branch changes , whose actionable parameter range is strictly defined by hardware specification and working condition constraints, including but not limited to: decoupling capacitor value , equivalent series resistance , decoupling capacitor position , return path optimization parameter ; for each power integrity PI actionable set , through the frequency domain calculation method in step one, the change ratio of power supply noise spectrum amplitude at the dominant coupling peak frequency point , denoted as power supply noise spectrum amplitude change ratio ; wherein, is the power supply noise spectrum amplitude at the dominant coupling peak frequency point re-measured by the acquisition equipment such as oscilloscope after the power integrity PI action; The signal integrity SI branch changes the transmission efficiency of power supply noise to error code by adjusting the signal end parameter, and its actionable parameter range is defined by the PCIe physical layer specification and the link characteristics in step one, including but not limited to: transmit end pre-emphasis coefficient , receive end continuous time linear equalization level , decision feedback equalization coefficient ; for each signal integrity SI actionable set , the cross-spectral density change ratio is derived through the cross-spectral density calculation method in step one , if the signal integrity SI branch is not adjusted, the conservative value can be taken due to the linear characteristics of the system; If accurate evaluation is needed, re-measurement should be made under the same collection aperture to obtain the measured ; For the combined action of power integrity PI and signal integrity SI, the comprehensive effect is predicted using a multiplicative model: Perform power integrity PI action, measure according to the method in step one, and obtain the power supply noise spectrum amplitude change ratio ; Keep the power integrity PI state, perform signal integrity SI action, re-measure according to the method in step one, and obtain the cross-spectral density change ratio ; the combined influence coefficient is ; Thus, the predicted value of the influence coefficient after the power integrity PI action is derived ; wherein, is the baseline value; For example: re-measure , after the power integrity PI action, and take the conservative value , then , which is close to the influence coefficient threshold in step one ; Systematically combine the power integrity (PI) actionable set with the signal integrity (SI) actionable set to generate a complete candidate action space; for each candidate action combination Implement the corresponding power integrity (PI) action, and measure the power noise spectrum amplitude change ratio according to the method in step one ; Implement the signal integrity (SI) action on the basis of the power integrity (PI) action, and measure the cross-spectral density change ratio according to the method in step one ; It should be noted that the specific parameter range of the power integrity (PI) branch actionable action is determined based on the system topology characteristics measured in step one; for example, based on the measured parasitic inductance , the feasible range of the decoupling capacitance value is ; the feasible range of the equivalent series resistance is ; the specific parameter range of the signal integrity (SI) branch actionable action is determined based on the link characteristics measured in step one, for example, the feasible range of the transmit end pre-emphasis coefficient is , and the feasible range of the receive end equalization level is ; these specific parameter ranges belong to the conventional technical means for determining actionable actions based on system characteristics by those skilled in the art; Based on the coherence threshold Establish a linear correlation criterion to mechanically filter the candidate action space: When , it means and are significantly linearly correlated at the dominant coupling peak frequency point , at which point the effect of the signal integrity (SI) action can be directly quantified by the cross-spectral density change ratio , that is, the cross-spectral density change ratio reflects the change in transfer efficiency, and the corresponding candidate action combination is retained; If , trigger a consistency check, and prompt to return to step one to reposition the dominant coupling peak frequency point, and eliminate the corresponding candidate action combination; For the candidate action combinations that pass the preliminary filtering, calculate the following key indicators, including calculating the impact coefficient prediction value and the bit error improvement amount ; To map the path impact coefficient corresponding to the dominant coupling peak frequency point to the bit error improvement amount , abandon the complex statistical model of the prior art, and use the 24-hour baseline bit error rate (BER) time series data and the synchronized time series data collected to do local linear regression, specifically: Extract the average 24 samples in total corresponding to baseline BER values; At baseline ±10% fluctuation ensures the linear assumption holds, local sensitivity is calculated; is the partial differential symbol, , data points deviating from baseline ±10% in step samples; based on this, the improvement of baseline BER is recorded as the error code improvement The first order extrapolation can be carried out by the following formula: ; wherein, is the predicted impact coefficient after the PI+SI combined action based on the multiplicative model, i represents the index of the data point, represents the impact coefficient corresponding to the i-th data point deviating from the baseline, represents the error rate corresponding to the i-th data point deviating from the baseline, through which the local sensitivity is calculated, and then the error code improvement is derived; and all candidate action combinations satisfying are retained to form an initial candidate action set, which contains all possible power integrity PI and signal integrity SI action combinations that can bring performance improvement.

[0021] Please refer to Figure 2 , step three: based on the prediction results of the multiplicative model, the quantitative evaluation of each candidate action combination is carried out, and its power integrity suppression contribution degree and signal integrity suppression contribution degree are calculated respectively; the power integrity suppression contribution degree reflects the suppression ability of the power supply noise amplitude by adjusting the power distribution network parameters, and the signal integrity suppression contribution degree reflects the suppression ability of the noise transfer efficiency by adjusting the signal link parameters; combining the two, the total suppression contribution degree which characterizes the overall optimization effect is obtained; at the same time, combined with the error code improvement derived from the impact coefficient prediction value, the action screening is carried out, that is, the optimal parameter combination with the maximum total suppression contribution degree and ensuring the error code performance to meet the standard is screened out from all candidate action combinations, which clearly defines the best collaborative configuration scheme of power integrity and signal integrity on both sides; Extract the power noise spectrum amplitude change ratio and cross spectrum density change ratio corresponding to each candidate action combination in the initial candidate action set, and construct the suppression contribution quantitative model; define the power integrity PI suppression contribution degree and the signal integrity SI suppression contribution degree as follows: , ; wherein, Quantifying the suppression capability of the power integrity PI branch alone, the larger the value, the more significant the power noise suppression effect; Quantifying the suppression capability of the signal integrity SI branch alone, the larger the value, the more significant the signal transmission path optimization effect; Based on the impact coefficient baseline established in step one , combined with the target impact threshold , calculate the target total suppression contribution , as the minimum standard for the total suppression effect; Further, the process of selecting the optimal parameter combination from the candidate action combination includes single branch optimization criteria and double branch ratio criteria, wherein the single branch optimization criteria are specifically as follows: for optimization schemes that only use a single branch, the following priority rules are established to directly filter: Power integrity PI single branch optimization, i.e., selecting an action scheme from the power integrity PI actionable set that satisfies and maximizes the power integrity PI suppression contribution ; Signal integrity SI single branch optimization, i.e., selecting an action scheme from the signal integrity SI actionable set that satisfies and maximizes the signal integrity SI suppression contribution ; the error code performance is verified simultaneously in the optimization process to ensure that the BER after optimization meets the industry standard requirements; The double branch ratio criteria, i.e., for scenarios that require power integrity PI and signal integrity SI collaborative optimization, multi-priority filtering is performed according to the preset priority rules, specifically as follows: for any double branch combination in the initial candidate action set Establish a ratio coefficient model , ; wherein, is the contribution ratio of the power integrity PI branch, is the contribution ratio of the signal integrity SI branch; Based on the value range of and combined with the corresponding actionable parameter ranges of each branch, such as the decoupling capacitor value range , the equivalent series resistance range , the transmit end pre-emphasis coefficient range , the receive end equalization level range , determine the preliminary parameter adjustment direction: Weak power integrity PI strong signal integrity SI interval, i.e. is in the first interval range, then the power integrity PI parameter takes the average value of the feasible range, such as , , and the signal integrity SI parameter takes the maximum value of the feasible range, such as 、 , preferentially optimizing transmission efficiency through signal integrity SI action; Balancing the proportion of the interval, that is , introduces adjustable proportion weight and , the initial value is recommended to be ; the power integrity PI parameter is biased to the upper limit between the extreme values according to the weight, that is ; wherein refers to the maximum value of the feasible range of any power integrity PI parameter in engineering application, is the minimum value of the feasible range of the corresponding power integrity PI parameter; if the power integrity PI parameter selects decoupling capacitor , its range is , when , the initial recommended value in engineering is ; Similarly , the parameter is ; wherein refers to the maximum value of the feasible range of any signal integrity SI parameter in engineering application, is the minimum value of the feasible range of the corresponding signal integrity SI parameter; if the signal integrity SI parameter selects the pre-addition of the transmitting end , its range is , when , ; realizing double-branch collaborative optimization; wherein can be adjusted according to specific performance requirements, for example, when more attention is paid to convergence speed, can be taken , and when more preference is given to the limit power integrity PI performance, can be taken ; Strong power integrity PI weak signal integrity SI interval, that is , is in the third interval range, then the power integrity PI parameter takes the upper limit value of the feasible range, such as 、 , the signal integrity SI parameter takes the middle value of the feasible range, and the power integrity PI action is preferentially suppressed by power noise; After determining the preliminary parameter adjustment direction corresponding to each branch, the double-branch combination is screened according to the priority of the following preset priority rules: the first priority is to calculate the total suppression contribution degree of the candidate action combination , which needs to meet ; wherein is the target suppression contribution degree calculated based on the influence coefficient baseline , and if it does not meet the requirement, the candidate action combination is eliminated; The second priority is to adopt local sensitivity and combination error improvement ),in, The influence coefficient of the combined action must satisfy the following conditions. ;in, The measured baseline bit error rate in step one is used; if it does not meet the requirement, it is discarded. It should be noted that all power integrity (PI) and signal integrity (SI) parameters in the above candidate action combinations must be within the range of feasible action parameters defined in step two to ensure engineering feasibility. Select from the combinations that satisfy all filtering rules. The combination with the largest overall inhibitory effect has the best overall inhibitory effect; If there are multiple For the same combination, select The combination closest to 0.5 represents the optimal balance in bi-branch optimization. If there are still multiple combinations, select the combination with the least hardware modification. For example, adjusting only the capacitor value is better than adjusting the capacitor position, and adjusting only the equalization level is better than adjusting the pre-emphasis coefficient, thereby reducing the engineering implementation cost. The optimal ratio information is obtained based on the implementation of step three: Contribution of power integrity PI branch suppression in the optimal combination Contribution of signal integrity SI branch suppression and matching coefficient in the optimal combination The matching strategy identifiers include weak power integrity (PI), strong signal integrity (SI), equalization, strong power integrity (PI), and weak signal integrity (SI). And the corresponding specific parameter scheme: Optimal power integrity PI parameters All of these parameters are within the feasible range of step one and represent the optimal signal integrity SI parameters. All of these are within the feasible range of step one.

[0022] Step 4: Implement the selected optimal parameter combination, including making necessary parameter adjustments to the hardware power distribution network according to the scheme, and configuring the signal integrity parameters of the high-speed link chip accordingly; after configuration, use the same excitation conditions and acquisition standards as the initial analysis stage to retest the performance of the optimized system, verify whether the actual influence coefficient, actual coherence and actual bit error rate of the dominant coupling peak frequency point meet the preset target threshold requirements, thereby confirming the effectiveness and stability of the optimization effect, and completing the closed-loop optimization process of the high-speed signal quality of the entire general dual-channel motherboard; Based on the optimal power integrity PI parameters determined in step three and optimal signal integrity SI parameters Configure the system according to the following specifications: Press in the motherboard power network Adding or replacing decoupling capacitors at designated locations with capacitance values ​​of [value missing] With the damping resistor having a resistance value of The return path was optimized by methods such as back drilling and fence through-holes. The requirement is that hardware modifications must strictly adhere to the feasible range of parameters defined in step one; Configure signal integrity (SI) parameters, including transmitter pre-emphasis factors, via register writing or the BMC interface. Receiver CTLE / DFE equalization coefficient / If firmware version support is required, complete the upgrade in advance; After parameter configuration, execute the link training process such as PCIe link hot reset handshake to ensure that the power integrity PI / signal integrity SI parameters take effect synchronously. The effectiveness standard refers to the link initialization verification requirements in step one. Using the same excitation method, acquisition parameters, and signal processing method as in step one, the performance of the configured system was retested. Inject the pseudo-random binary sequence specified in step one at the link end, such as PRBS31, and apply a step current excitation at the power supply end. Sampling rate maintenance The system's maximum operating speed set in step one is more than 10 times the maximum speed, and the data acquisition duration meets the requirements. ; Calculate the actual impact coefficient based on the collected data. That is, the dominant coupling peak frequency point At this point, step one: positioning, actual coherence. and actual bit error rate The calculation logic follows the frequency domain analysis method and bit error rate statistical standard of step one; Based on the threshold and target value established in the previous steps, the optimization effect is verified according to the following rules: Must meet simultaneously ;in, The target influence coefficient set for step three , ; Calculate the actual total inhibition contribution , must meet ; If any of the above conditions are not met, the actual impact coefficient of this retest will be... Actual bit error rate Actual coherence The corresponding parameter combinations are added to the training set in step two, and the candidate action set is regenerated before returning to step three for iterative solution. Include hardware modification plans, firmware version information, and test logs containing sampling rates. The multiplexing parameters and the compliance judgment result of the steps such as the collection time T are stored in the knowledge base to form a reusable optimization case, and provide a reference basis for power integrity (PI) and signal integrity (SI) collaborative optimization of similar systems.

[0023] The above formulas are dimensionless values calculated, and the formulas are obtained by software simulation of a large amount of data to obtain a formula of the most recent real situation, and the preset parameters in the formula are set by a person skilled in the art according to the actual situation.

[0024] The above embodiments can be realized wholly or partially by software, hardware, firmware or any other combination. When realized by software, the above embodiments can be realized wholly or partially in the form of a computer program product.

[0025] Those skilled in the art can realize that the modules and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application of the technical solution and the constraints of the application. A person skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0026] In addition, the functional modules in each embodiment of the present application can be integrated in one processing module, or each module can exist physically alone, or two or more modules can be integrated in one module.

[0027] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0028] Finally, the above is only the preferred embodiment of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A universal two-way mainboard high-speed signal optimization method, characterized in that, The method comprises the following steps: By collecting the input signal of the power supply network and the differential signal error code sequence of the high-speed link, the cross-spectral density and coherence of the input signal and the error code sequence are calculated, and based on the preset coherence threshold and influence coefficient threshold, the dominant coupling peak frequency point significantly associated with the power supply noise and error code is identified; Based on the identified dominant coupling peak frequency point, the power integrity actionable set and the signal integrity actionable set are obtained, and each action in the power integrity actionable set is systematically combined with each action in the signal integrity actionable set to generate a candidate action combination set; the change effect of each candidate action combination on the influence coefficient is predicted through a multiplicative model, and the influence coefficient represents the influence degree of the power supply noise on the error code; Based on the prediction change result, the power integrity suppression contribution degree and the signal integrity suppression contribution degree of each candidate action combination are calculated, and then the target total suppression contribution degree is calculated based on the influence coefficient baseline and the target threshold, and the optimal parameter combination with the maximum total suppression contribution degree is selected from the candidate action combinations in combination with the error code improvement amount; The power integrity suppression contribution degree is based on the power supply noise spectrum amplitude change ratio, and the signal integrity suppression contribution degree is based on the cross-spectral density change ratio; The optimal parameter combination is implemented, and the performance of the high-speed mainboard is retested, and the optimization effect is determined by comparing whether the key performance indicators before and after optimization reach the preset target.

2. The universal two-way mainboard high-speed signal optimization method according to claim 1, wherein, The calculation of cross-spectral density and coherence includes: the cross-spectral density is the Fourier transform of the cross-correlation function of the source network input signal and the differential signal error code sequence, which is used to represent the association strength of the two signals at different frequencies; for the discrete sampled power supply network input signal and differential signal error code sequence, the cross-spectral density is calculated by discrete Fourier transform, which is specifically to perform fast Fourier transform after framing the signal, to obtain the auto-spectral density by averaging the square modulus of each frame frequency sequence, and to obtain the cross-spectral density by averaging the conjugate product of the corresponding frame frequency sequence; the coherence function is used to measure the linear correlation of the power supply network input signal and the differential signal error code sequence at each frequency point, and its calculation is based on the cross-spectral density and the auto-spectral density of the two signals.

3. The universal two-way mainboard high-speed signal optimization method of claim 2, wherein, The dominant coupling peak frequency point is identified, specifically, a path influence coefficient is defined ; wherein, is a frequency domain amplitude of the power network input signal, is a cross-spectral density of the calculated power network input signal and the differential signal error code sequence. Filtering out frequency points satisfying the coherence degree and the path influence coefficient as the dominant coupling peak frequency point, the is the coherence degree threshold, is the influence coefficient threshold.

4. The universal two-way mainboard high-speed signal optimization method of claim 1, wherein, The power integrity actionable set includes decoupling capacitor related parameters, equivalent series resistance, decoupling capacitor position, and return path optimization parameters. The signal integrity actionable set includes transmit end pre-emphasis coefficient, receive end continuous time linear equalization level, and decision feedback equalization coefficient.

5. The universal two-way mainboard high-speed signal optimization method of claim 1, wherein, The expression of the multiplicative model is and is defined as a combined impact coefficient, wherein, is the identified dominant coupling peak frequency point, represents power integrity, SI represents signal integrity, is the impact coefficient baseline value, is the power noise spectrum amplitude change ratio, is the cross-spectrum density change ratio; by implementing a power integrity action , on the basis of the power integrity action, a signal integrity action is implemented to obtain , and then the change effect of the combined action on the impact coefficient is predicted.

6. The universal two-way mainboard high-speed signal optimization method of claim 1, wherein, Error correction is calculated as follows: at baseline Local sensitivity is calculated by performing local linear regression using baseline bit error rate time-series data and synchronization impact coefficient time-series data. The error correction amount is obtained by first-order extrapolation. ;in Here, i represents the predictive influence coefficient of the multiplicative model, and i denotes the index of the data point. Represents the bit error rate of the i-th deviation from the baseline. The influence coefficient corresponding to the data points. Represents the bit error rate of the i-th deviation from the baseline. The bit error rate corresponding to the data points. It is the symbol for partial differential.

7. The universal two-way mainboard high-speed signal optimization method of claim 1, wherein, Power integrity suppression contribution Computing, signal integrity suppression contribution Computing; target total suppression contribution is then ; wherein, is an impact factor baseline, is a target impact threshold .

8. The universal two-way mainboard high-speed signal optimization method of claim 1, wherein, The selection of the optimal parameter combination includes: calculating the total suppression contribution degree based on the power integrity suppression contribution degree and the signal integrity suppression contribution degree of each candidate action combination; combining the total suppression contribution degree and the error code improvement amount, and performing multi-priority selection according to the preset priority rule; the priority rule includes a single branch optimization criterion applicable to a single branch optimization scenario, and a double branch ratio criterion applicable to a power integrity and signal integrity collaborative optimization scenario; the optimal parameter combination with the maximum total suppression contribution degree is selected from the candidate action combinations through multi-priority selection.

9. The universal two-way mainboard high-speed signal optimization method of claim 8, wherein, The single-branch optimization criterion is specifically: a power integrity single-branch optimization, that is, from a power integrity actionable set, an action scheme is selected, which satisfies a predicted impact coefficient lower than an impact coefficient threshold and has a maximum power integrity suppression contribution after a single action; and a signal integrity single-branch optimization, that is, from a signal integrity actionable set, an action scheme is selected, which satisfies a predicted impact coefficient lower than an impact coefficient threshold and has a maximum signal integrity suppression contribution after a single action.

10. The universal two-way mainboard high-speed signal optimization method of claim 8, wherein, The double-branch proportioning criterion is: for the cooperative action combination of power integrity and signal integrity, a proportioning coefficient model is established, wherein the contribution proportion of the power integrity branch is , and the contribution proportion of the signal integrity branch is . According to the value range of the matching coefficient The candidate combinations are divided into different matching strategy intervals, including a weak power integrity strong signal integrity interval, a balanced matching interval, and a strong power integrity weak signal integrity interval. Based on the matching strategy interval, a preliminary adjustment direction of the power integrity parameter and the signal integrity parameter is respectively specified in a feasible engineering range: When in a weak power integrity strong signal integrity interval, the power integrity parameter takes an average value of a feasible range, and the signal integrity parameter takes a maximum value of a feasible range; When in the balanced proportion interval, an adjustable proportion weight is introduced The values of the power integrity parameter and the signal integrity parameter are calculated by weighting between their respective feasible range extremes according to the weight. When in the strong power integrity weak signal integrity interval, the power integrity parameter takes the upper limit value of the feasible range, and the signal integrity parameter takes the middle value of the feasible range; first, in the candidate action combination that meets the conditions, after determining the preliminary adjustment direction, the candidate combination is screened according to the following priority order: the first priority, screening the candidate action combination that meets And the candidate action combination after optimization meets the industry standard of the bit error rate, wherein The total suppression contribution degree is ; A second priority is to screen a combination whose optimized bit error rate meets an industry standard from a candidate action combination meeting the first priority; and to select a combination with a maximum total suppression contribution as an optimal parameter combination from combinations meeting all priorities.

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