A multi-modal knowledge graph generation method and system for hardware design analysis

Abstract

The application provides a multi-modal knowledge graph generation method and system for hardware design analysis, breaks the information barrier between design, verification and physics, realizes the information barrier between the three traditional EDA fields, semantically fuses and associates information from different data domains, creates a unified and queryable hardware design knowledge representation, and forms a coherent and operable unified knowledge model. By integrating the simulation results (dynamic data) and the characteristics of physical implementation (performance data) into the static structure model, a multi-modal design knowledge graph is created, which enables engineers to analyze a comprehensive design model with structure, behavior and performance characteristics in a unified framework without manually switching between different tools and data formats. Instead, engineers can access comprehensive information about the static structure, dynamic behavior and physical performance of the design through a single query interface.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and more specifically, to a method and system for generating multimodal knowledge graphs for hardware design analysis. Background Technology

[0002] In current hardware design and verification practices, engineers must rely on a fragmented and disconnected toolset to fully understand the behavior and performance of their designs. This workflow is inherently fragmented, leading to significant inefficiencies and limitations on analytical depth. Specifically:

[0003] (1) Static Analysis: Engineers use integrated development environments, static code analysis tools, and code browsers to understand the structural characteristics of HDL code. This includes tracing the connections between signals, understanding the hierarchical structure of modules, and reviewing the syntactic compliance of the code. This stage of analysis is entirely limited to the static structure designed at the code level and cannot reveal any time-related behavior during actual operation.

[0004] (2) Dynamic Analysis: To understand the behavior of the design under external stimuli, engineers use logic simulation tools (such as Synopsys VCS, Cadence Xcelium) to run test platforms and generate simulation waveform files (such as VCD or FSDB formats). These waveforms are then loaded into a standalone waveform viewer (such as Synopsys Verdi) for analysis. Engineers debug functional errors by manually examining changes in signal values ​​over time, which is an extremely time-consuming and experience-dependent process.

[0005] (3) Physical Performance Analysis: After logic synthesis, engineers turn to static timing analysis (STA) tools (such as Synopsys PrimeTime) to evaluate the physical performance metrics of the design, such as maximum clock frequency and critical path delay. The analysis process typically involves reviewing detailed text-based timing reports generated by the tool to identify performance bottlenecks.

[0006] The fundamental flaw in this workflow lies in the lack of a unified analytical framework, resulting in so-called "information silos." Static structural information, dynamic behavioral information, and physical performance information reside separately in HDL source files, simulation waveform files, and synthesis timing reports, and are analyzed by different tools. This separation forces engineers to act as manual data integrators, mentally connecting information from different data formats (code, waveforms, text reports). This manual process is not only slow but also a major source of human error, severely hindering root cause analysis of complex cross-domain problems and limiting the complexity of design problems that can be effectively debugged. Summary of the Invention

[0007] This invention addresses the technical problems existing in the prior art by providing a method and system for generating multimodal knowledge graphs for hardware design analysis.

[0008] According to a first aspect of the present invention, a method for generating a multimodal knowledge graph for hardware design analysis is provided, comprising:

[0009] Step S1: Generate a static knowledge graph representing the static structure of the static HDL source code based on the hardware design.

[0010] Step S2: Receive and parse the simulation output file corresponding to the hardware design to extract time series data representing dynamic signal behavior from the simulation output file;

[0011] Step S3: Associate the extracted time series data with the corresponding nodes or edges in the static knowledge graph, and integrate the time series data into the static knowledge graph;

[0012] Step S4: Parse the physical performance data of the hardware design from the comprehensive or static timing analysis report, and integrate the physical performance data into the static knowledge graph to generate a multimodal knowledge graph.

[0013] Based on the above technical solution, the present invention can also be improved as follows.

[0014] Optionally, step S1, generating a static knowledge graph representing the static structure based on the HDL source code of the hardware design, includes:

[0015] The HDL parser is invoked to process all static HDL source files in the project. The HDL parser extracts Module, Instance, Signal, and Statement from the static HDL source files to form nodes of the static knowledge graph, and extracts the structure and dependencies between the nodes as edges of the static knowledge graph.

[0016] Optionally, in the static knowledge graph, module nodes and instance nodes are connected by CONTAINS and INSTANTIATES edges, and statement nodes and signal nodes are connected by DRIVES or CONSUMES edges.

[0017] Optionally, step S2, receiving and parsing the simulation output file corresponding to the hardware design, to extract time-series data representing dynamic signal behavior from the simulation output file, includes:

[0018] The waveform parser parses the simulation waveform file corresponding to the hardware design, and outputs a series of timestamped signal value change events in a streaming manner.

[0019] Create an event node corresponding to each signal value change event and set its attributes, including timestamp, signal identifier, and signal value;

[0020] Connect all event nodes to each other in timestamp order using edges of type NEXT_EVENT to form a time series linked list.

[0021] Optionally, step S3, which associates the extracted time-series data with the corresponding nodes or edges in the static knowledge graph and integrates the time-series data into the static knowledge graph, includes:

[0022] Based on the signal identifiers in the simulation waveform file, the corresponding signal nodes are located in the static knowledge graph;

[0023] The signal nodes in the static knowledge graph are pointed to the first event node in the time series linked list via the HAS_EVENT edge.

[0024] Optionally, step S4, parsing the physical performance data of the hardware design from the comprehensive or static timing analysis report and integrating the physical performance data into the static knowledge graph to generate a multimodal knowledge graph, includes:

[0025] The physical performance data of the hardware design is identified and extracted from the comprehensive or static timing analysis report based on the physical report parser. The physical performance data includes timing path, signal arrival time, timing margin, and power consumption and latency of logic units.

[0026] For each timing path, the graph ensemble engine identifies the sequence of instance nodes and signal nodes contained in each timing path;

[0027] Create a TimingPath super node, which connects all instance nodes and signal nodes on each timing path through the PART_OF_PATH edge;

[0028] The extracted physical performance metrics are added as attributes to instance nodes and signal nodes.

[0029] Optionally, the method further includes:

[0030] Provide a query engine for the constructed multimodal knowledge graph;

[0031] Receive a query request containing static, dynamic, or physical domain constraints, traverse different types of nodes and edges in the multimodal knowledge graph based on the query request to respond to the query request, and return the query results.

[0032] According to a second aspect of the present invention, a multimodal knowledge graph generation system for hardware design analysis is provided, comprising:

[0033] The generation module is used to generate a static knowledge graph representing the static structure of static HDL source code based on the hardware design.

[0034] The extraction module is used to receive and parse the simulation output file corresponding to the hardware design, so as to extract time series data representing dynamic signal behavior from the simulation output file;

[0035] The first integration module is used to associate the extracted time series data with the corresponding nodes or edges in the static knowledge graph, and integrate the time series data into the static knowledge graph.

[0036] The second integration module is used to parse the physical performance data of the hardware design from the comprehensive or static timing analysis report, and integrate the physical performance data into the static knowledge graph to generate a multimodal knowledge graph.

[0037] According to a third aspect of the present invention, an electronic device is provided, including a memory and a processor, wherein the processor is configured to implement a multimodal knowledge graph generation method for hardware design analysis when executing a computer management program stored in the memory.

[0038] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, on which a computer management class program is stored, wherein when executed by a processor, the computer management class program implements the steps of a multimodal knowledge graph generation method for hardware design analysis.

[0039] This invention provides a multimodal knowledge graph generation and system for hardware design analysis. By integrating simulation results (dynamic data) and physical implementation features (performance data) into a static structural model, a multimodal design knowledge graph is created. This allows engineers to analyze a comprehensive design model with structural, behavioral, and performance characteristics within a unified framework. Engineers no longer need to manually switch between different tools and data formats, but can access comprehensive information about the static structure, dynamic behavior, and physical performance of the design through a single query interface. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a multimodal knowledge graph data model designed according to an embodiment of the present invention;

[0041] Figure 2 A flowchart of a multimodal knowledge graph generation method for hardware design analysis is provided in one embodiment of the present invention;

[0042] Figure 3 This is a hierarchical architecture diagram of a multimodal knowledge graph data model according to an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of the structure of a multimodal knowledge graph generation system for hardware design analysis, provided in one embodiment of the present invention.

[0044] Figure 5 A schematic diagram of the hardware structure of a possible electronic device provided by the present invention;

[0045] Figure 6 This is a schematic diagram of the hardware structure of a possible computer-readable storage medium provided by the present invention. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined with each other to form feasible technical solutions. Such combinations are not constrained by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0047] To address the needs of analyzing, verifying, and debugging hardware designs described using Hardware Description Languages ​​(HDLs) (such as Verilog or VHDL), the academic community has recently proposed several methods for representing HDL code using graph structures, aiming to provide richer structural information for automated analysis. However, in-depth analysis of these most relevant existing technologies reveals that they all fail to solve the aforementioned data silo problem, and their application scope is strictly limited to the field of static code analysis. Existing technologies mainly include the following:

[0048] Existing technical solution 1: Verilog LAVD.

[0049] This approach proposes a concept called "Verilog Attribute Graph" (VeriPG), which integrates Abstract Syntax Tree (AST), Control Flow Graph (CFG), and Data Dependency Graph (DDG) into a unified graph representation. Its primary goal is to leverage this graph structure to assist in the detection of security vulnerabilities in hardware design using Large Language Models (LLMs). While its graph representation method excels in handling source code structure information, according to published literature, this approach is mainly applied to static code analysis. Its data sources and modeling focus do not encompass the integration of dynamic simulation data or physical synthesis data. The essence of its methodology is deep and multi-dimensional static analysis of HDL source code. This focus on a single data domain represents a typical methodological approach in handling the complexity of hardware design.

[0050] Existing technical solution 2: HDLxGraph.

[0051] This approach also focuses on constructing graph representations from HDL code. Its implementation integrates Abstract Syntax Trees (ASTs) and Data Flow Graphs (DFGs). Its primary application is to enhance the performance of LLM in tasks such as code search, debugging, and completion when handling repository-level HDL projects through graph retrieval-enhanced generation techniques. While its graph structure design effectively utilizes the syntactic and semantic information of the code, publicly available technical solutions indicate that the framework's application focus is mainly on static code understanding and retrieval. Existing literature has not fully demonstrated its ability to integrate dynamic simulation data or physical time-series data, reflecting that current graph representation technologies still have room for exploration in multi-data-domain integration.

[0052] These related technologies represent an active exploration of applying modern data structures (graphs) and artificial intelligence (LLM) to the field of EDA. However, they primarily focus on the analysis of static code domains, leaving room for innovation in multimodal data fusion technologies.

[0053] The existing technology has the following main drawbacks:

[0054] 1. The problem of fragmentation and isolation of hardware design knowledge: Existing technologies fragment and store the static structural information (existing in HDL code), dynamic behavioral information (existing in simulation waveforms), and physical performance information (existing in timing reports) of hardware design in incompatible "information silos", lacking a unified representation and analysis framework.

[0055] 2. Limited Analytical Capabilities: Due to information silos, engineers are unable to perform high-level, cross-domain queries and root cause analyses crucial to complex systems. For example, it is impossible to directly correlate a physical timing violation path with the specific dynamic signal behavior (such as a glitch) that caused the violation through a single operation. The limitations of existing graph representation methods further exacerbate this problem, as they cannot capture or query behavioral characteristics of the design at the dynamic operation or physical implementation level.

[0056] 3. Efficiency and Reliability Issues of Manual Analysis Processes: Current analysis processes, which rely on engineers manually switching contexts between different tools and manually linking data, are inefficient, error-prone, and difficult to scale as modern chip designs become increasingly complex. The lack of automated cross-domain analysis tools forces engineers to adopt error-prone manual methods, severely impacting the efficiency of design debugging and verification.

[0057] These technical issues are interconnected and together constitute the current challenges of EDA design analysis. Among them, the information silo problem (Problem 1) is the root cause, which directly leads to the limitation of analytical capabilities (Problem 2). The combined effect of these two problems ultimately gives rise to inefficient manual analysis processes (Problem 3). The breaking point in this causal chain lies in the lack of an intermediate knowledge representation that can uniformly represent and correlate multimodal design data. This is precisely the core technical challenge that this invention aims to address.

[0058] To address the fundamental shortcomings of the prior art, the present invention aims to propose a method for generating a multimodal hardware design knowledge graph that integrates static structure, dynamic behavior, and physical performance information.

[0059] The core idea of ​​this invention is to break down the information barriers between the three traditional EDA fields of design, verification and physical implementation, and to semantically fuse and associate information from different data domains to create a single, unified and queryable unified knowledge representation of hardware design, forming a coherent and operable unified knowledge model.

[0060] By integrating simulation results (dynamic data) and physical implementation features (performance data) into a static structural model, this invention creates a multimodal design knowledge graph that provides a new capability: analyzing a comprehensive design model with structural, behavioral, and performance characteristics within a unified framework. Engineers no longer need to manually switch between different tools and data formats; instead, they can access comprehensive information about the static structure, dynamic behavior, and physical performance of the design through a single query interface.

[0061] Therefore, the purpose of this invention is to enable holistic and relational querying and analysis of hardware designs, thereby improving the analysis paradigm of hardware designs.

[0062] This invention innovatively designs a multimodal VeriPG data model, which provides a concrete and feasible framework for meaningfully associating originally unrelated static, dynamic, and physical data.

[0063] Figure 1 This illustrates how static, dynamic, and physical data are interconnected within a unified graph structure. The static graph (left) forms the basic skeleton. Dynamic data (middle) embeds time-series information into the graph by introducing TimeEvent nodes and NEXT_EVENT edges. Physical data (right) enhances the graph model by creating TimingPath supernodes or adding attributes to existing nodes.

[0064] The basic static graph pattern consists of nodes and edges representing the static structure of HDL code, such as nodes like Module, Instance, Signal, and Statement, as well as relational edges like CONTAINS, INSTANTIATES, and DRIVES.

[0065] Dynamic Data Augmentation: To efficiently represent and query massive amounts of time-series data, this invention employs a non-obvious innovative design. Instead of storing all time-value pairs of a signal as a huge list attribute on the Signal node (a method with extremely low query efficiency), it introduces TimeEvent nodes. Each TimeEvent node represents a signal value change at a specific point in time, with its core attributes being timestamp and value. All TimeEvent nodes are interconnected in timestamp order via NEXT_EVENT type edges, forming a time-series linked list embedded in the graph. Static Signal nodes point to the first TimeEvent node in their time-series linked list via HAS_EVENT edges. This approach of modeling time series as linked lists in a graph is key to solving the technical challenge of efficiently processing and querying massive amounts of time-series data in graph databases, as it allows the query engine to traverse directly along the chains without scanning all events.

[0066] Physical data augmentation: Physical performance data is integrated in two ways. First, the timing critical path is modeled as a new TimingPath supernode, which is connected to all Instance and Signal nodes that constitute it via PART_OF_PATH edges, thus materializing the path for direct querying. Second, physical performance metrics extracted from reports (such as cell_delay and dynamic_power_consumption) are directly appended as attributes to existing Instance nodes in the graph.

[0067] Table 1 defines in detail the key graph elements of the multimodal VeriPG, providing a clear basis for the specific implementation of this invention.

[0068] Table 1. Definition of Multimodal VeriPG Modes

[0069]

[0070] Having defined the target data model, the method for generating a multimodal knowledge graph from multi-source data based on hardware design is described below. The specific method for generating this multimodal knowledge graph is an ordered, phased process coordinated and executed by a graph integration engine.

[0071] Figure 2 The following is a flowchart illustrating a method for generating a multimodal knowledge graph for hardware design analysis, as provided in one embodiment of the present invention. Figure 1 As shown, the method includes the following steps:

[0072] Step S1: Generate a static knowledge graph representing the static structure of the static HDL source code based on the hardware design.

[0073] Step S2: Receive and parse the simulation output file corresponding to the hardware design to extract time series data representing dynamic signal behavior from the simulation output file;

[0074] Step S3: Associate the extracted time series data with the corresponding nodes or edges in the static knowledge graph, and integrate the time series data into the static knowledge graph;

[0075] Step S4: Parse the physical performance data of the hardware design from the comprehensive or static timing analysis report, and integrate the physical performance data into the static knowledge graph to generate a multimodal knowledge graph.

[0076] Understandably, the embodiments of the present invention first analyze the static HDL source code of the hardware design to generate a static knowledge graph representing its static structure as the basic skeleton.

[0077] Then, dynamic timing data is extracted from the simulation output file corresponding to the hardware design, and the dynamic timing data is connected to the nodes in the static knowledge graph through relational edges, thus integrating the dynamic timing data into the static knowledge graph.

[0078] Then, the physical performance data of the hardware design is parsed from the comprehensive or static timing analysis report. The physical performance data is also connected to the nodes in the static knowledge graph through relational edges, and the physical performance data is integrated into the static knowledge graph. Finally, a multimodal knowledge graph is formed by integrating static data, dynamic data and physical data into a unified graph representation.

[0079] In some embodiments of the present invention, the method for constructing the static graph in step S1 includes: calling an HDL parser to process all HDL source files in the project. The HDL parser extracts modules, instances, signals, and statements to form nodes of the static knowledge graph, and extracts the structure and dependencies between nodes as edges of the static knowledge graph to form a complete static knowledge graph. This static graph constitutes the basic skeleton or framework of the entire knowledge graph, and all subsequent dynamic and physical information will be attached to it.

[0080] In the static knowledge graph, module nodes and instance nodes are connected by CONTAINS and INSTANTIATES edges, while statement nodes and signal nodes are connected by DRIVES or CONSUMES edges.

[0081] In one embodiment of the present invention, the method for dynamic data extraction and association in step S2 includes: processing a user-specified simulation waveform file (VCD or FSDB), and the waveform parser outputting a series of timestamped signal value change events in a streaming manner. For each signal value change event, the graph integration engine performs the following operations: using the complete hierarchical name of the signal as a unique key, quickly locating the corresponding Signal node in the static knowledge graph; creating a new TimeEvent node and setting its attributes, including timestamp, signal identifier, and signal value; connecting all TimeEvent nodes to each other in time-stamp order via NEXT_EVENT type edges to form a time-series linked list. The signal nodes in the static knowledge graph are then pointed to the first event node in the time-series linked list via HAS_EVENT edges to integrate dynamic data into the static knowledge graph.

[0082] In one embodiment of the present invention, the method for physical data extraction and association in step S3 includes: final processing of the synthesis or STA report. The physical report parser identifies entities such as timing paths and unit performance from the synthesis or STA report. For each extracted information fragment, the graph integration engine performs corresponding graph operations: for example, for a timing path, the engine identifies the sequence of Instance and Signal nodes contained in the path in the graph, then creates a TimingPath super node and associates all elements on the path with it, thereby integrating hardware design-related physical performance data into a static knowledge graph, ultimately forming a multimodal knowledge graph.

[0083] Once all data sources have been processed, a multimodal knowledge graph is constructed. Finally, index optimization operations can be performed on the multimodal knowledge graph to accelerate subsequent query performance. At this point, a single, persistent multimodal knowledge graph integrating static, dynamic, and physical information is complete and ready for analysis.

[0084] See Figure 3 The diagram illustrates the logical architecture involved in generating a multimodal knowledge graph, which mainly consists of core components such as a data extraction layer, a graph integration engine, a graph database, and a query engine.

[0085] Figure 3 The overall data flow and component interactions of the system of this invention are demonstrated. Data is input from three heterogeneous sources (HDL code, simulation waveforms, and physics reports), processed by their respective parsers in the data extraction layer, and then uniformly integrated into the graph database by the graph integration engine. Finally, users or upper-layer applications interact with this multimodal knowledge graph through the query engine.

[0086] Data Extraction Layer: This layer is responsible for parsing and extracting structured information from various heterogeneous data sources. It contains a set of specialized parsers:

[0087] HDL Parser: This module is responsible for parsing HDL source code (such as Verilog) and building a high-fidelity static VeriPG as the basic skeleton.

[0088] Simulation Waveform Parser: This module is used to read and interpret standard simulation output formats, such as Value Change Dump (VCD) and Fast Signal Database (FSDB), extracting a series of event tuples containing timestamps, signal identifiers, and signal values.

[0089] Physical Report Parser: This module is specifically designed to extract key information from text-formatted synthesis and static timing analysis (STA) reports (such as the output of Synopsys PrimeTime), such as critical paths, signal arrival times, timing margins, and physical attributes like power consumption and latency of logic units.

[0090] Graph Integration Engine: This is the core logic of the invention. The engine receives multiple parsed data streams from the data extraction layer and is responsible for intelligently and consistently integrating these heterogeneous data into the graph database.

[0091] Graph database: This is a persistent storage system optimized for storing and querying graph-structured data. A preferred implementation uses a Labeled Attribute Graph (LPG) model, which flexibly represents complex relationships through nodes, edges, labels, and attributes.

[0092] Query Engine: This component provides users with an interactive interface for performing queries on the constructed multimodal knowledge graph. Users can use standard graph query language to initiate complex cross-domain query requests.

[0093] See Figure 4 This illustration shows a multimodal knowledge graph generation system for hardware design analysis according to an embodiment of the present invention. The system includes:

[0094] The generation module 401 is used to generate a static knowledge graph representing the static structure of the static HDL source code based on the hardware design.

[0095] Extraction module 402 is used to receive and parse the simulation output file corresponding to the hardware design, so as to extract time series data representing dynamic signal behavior from the simulation output file;

[0096] The first integration module 403 is used to associate the extracted time series data with the corresponding nodes or edges in the static knowledge graph, and integrate the time series data into the static knowledge graph.

[0097] The second integration module 404 is used to parse the physical performance data of the hardware design from the comprehensive or static timing analysis report, and integrate the physical performance data into the static knowledge graph to generate a multimodal knowledge graph.

[0098] It is understood that the multimodal knowledge graph generation system for hardware design analysis provided by this invention corresponds to the multimodal knowledge graph generation method for hardware design analysis provided in the foregoing embodiments. The relevant technical features of the multimodal knowledge graph generation system for hardware design analysis can be referred to the relevant technical features of the multimodal knowledge graph generation method for hardware design analysis, and will not be repeated here.

[0099] Please see Figure 5 , Figure 5 This is a schematic diagram illustrating an embodiment of the electronic device provided in this invention. For example... Figure 5As shown, an embodiment of the present invention provides an electronic device 500, including a memory 510, a processor 520, and a computer program 511 stored in the memory 510 and executable on the processor 520. When the processor 520 executes the computer program 511, it implements the steps of a multimodal knowledge graph generation method for hardware design analysis.

[0100] Please see Figure 6 , Figure 6 This is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided by the present invention. (See diagram below.) Figure 6 As shown, this embodiment provides a computer-readable storage medium 600 on which a computer program 611 is stored. When the computer program 611 is executed by a processor, it implements the steps of a multimodal knowledge graph generation method for hardware design analysis.

[0101] The present invention provides a method and system for generating multimodal knowledge graphs for hardware design analysis, which has the following beneficial effects:

[0102] (1) Overcoming fundamental defects and achieving in-depth analysis: Existing technologies are unable to perform cross-domain analysis due to their "static and one-sided" nature. This invention achieves holistic and correlational analysis of hardware design by integrating static, dynamic, and physical data. This makes it possible to debug the root causes of complex problems, such as directly locating physical timing violations to a specific signal glitch in the simulation waveform. This represents a shift from being unable to perform effective correlation analysis to having this capability.

[0103] (2) Significantly improve efficiency and accuracy: Compared with the inefficient and error-prone process of engineers manually switching between multiple tools, visually comparing, and manually linking data, the present invention provides an automated unified platform, and the results of the present invention are more reliable, avoiding errors caused by human negligence.

[0104] (3) Unlocking new query and insight capabilities: This invention enables engineers to perform in-depth analysis paths that were previously impossible due to technological limitations. This capability elevates hardware design analysis from a passive "data-viewing" mode to an active "evidence-based exploration" mode, greatly enhancing engineers' ability to gain insights into design problems.

[0105] (4) Laying the foundation for next-generation EDA tools: Existing AI-assisted EDA tools (such as Verilog LAVD and HDLxGraph) are limited in effectiveness because their input data is only static code, and they cannot understand the real dynamic behavior and physical characteristics of the design. The multimodal knowledge graph created in this invention is an extremely rich structured dataset. It can serve as an ideal input and foundational platform for training next-generation, more powerful EDA artificial intelligence / machine learning models (such as graph neural networks GNN), enabling them to understand real-world behavior and thus achieve more advanced functions, such as predicting the temporal impact based on code changes, or automatically recommending bug root causes based on abnormal behavior patterns.

[0106] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0107] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0108] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0109] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0110] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0111] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0112] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for generating a multimodal knowledge graph for hardware design analysis, characterized in that, include: Step S1: Generate a static knowledge graph representing the static structure of the static HDL source code based on the hardware design. Step S2: Receive and parse the simulation output file corresponding to the hardware design to extract time series data representing dynamic signal behavior from the simulation output file; Step S3: Associate the extracted time series data with the corresponding nodes or edges in the static knowledge graph, and integrate the time series data into the static knowledge graph; Step S4: Parse the physical performance data of the hardware design from the comprehensive or static timing analysis report, and integrate the physical performance data into the static knowledge graph to generate a multimodal knowledge graph; Step S1 involves generating a static knowledge graph representing the static structure of the HDL source code based on the hardware design, including: The HDL parser is invoked to process all static HDL source files in the project. The HDL parser extracts Module, Instance, Signal, and Statement from the static HDL source files to form nodes of the static knowledge graph, and extracts the structure and dependencies between the nodes as edges of the static knowledge graph. Step S2 involves receiving and parsing the simulation output file corresponding to the hardware design to extract time-series data representing dynamic signal behavior from the simulation output file, including: The waveform parser parses the simulation waveform file corresponding to the hardware design, and outputs a series of timestamped signal value change events in a streaming manner. Create an event node corresponding to each signal value change event and set its attributes, including timestamp, signal identifier, and signal value; Connect all event nodes to each other in timestamp order using edges of type NEXT_EVENT to form a time series linked list; Step S3, which associates the extracted time-series data with the corresponding nodes or edges in the static knowledge graph and integrates the time-series data into the static knowledge graph, includes: Based on the signal identifiers in the simulation waveform file, locate the corresponding signal nodes in the static knowledge graph; The signal node in the static knowledge graph is pointed to the first event node in the time series linked list via the HAS_EVENT edge.

2. The multimodal knowledge graph generation method according to claim 1, characterized in that, In the static knowledge graph, module nodes and instance nodes are connected by CONTAINS and INSTANTIATES edges, and statement nodes and signal nodes are connected by DRIVES or CONSUMES edges.

3. The multimodal knowledge graph generation method according to claim 1, characterized in that, Step S4 involves parsing the physical performance data of the hardware design from the comprehensive or static timing analysis report, and integrating the physical performance data into the static knowledge graph to generate a multimodal knowledge graph, including: The physical performance data of the hardware design is identified and extracted from the comprehensive or static timing analysis report based on the physical report parser. The physical performance data includes timing path, signal arrival time, timing margin, and power consumption and latency of logic units. For each timing path, the graph ensemble engine identifies the sequence of instance nodes and signal nodes contained in each timing path; Create a TimingPath super node, which connects all instance nodes and signal nodes on each timing path through the PART_OF_PATH edge; The extracted physical performance metrics are added as attributes to instance nodes and signal nodes.

4. The multimodal knowledge graph generation method according to claim 1, characterized in that, The method further includes: Provide a query engine for the constructed multimodal knowledge graph; Receive a query request containing static, dynamic, or physical domain constraints, traverse different types of nodes and edges in the multimodal knowledge graph based on the query request to respond to the query request, and return the query results.

5. A multimodal knowledge graph generation system for hardware design analysis, characterized in that, include: The generation module is used to generate a static knowledge graph representing the static structure of static HDL source code based on the hardware design. The extraction module is used to receive and parse the simulation output file corresponding to the hardware design, so as to extract time series data representing dynamic signal behavior from the simulation output file; The first integration module is used to associate the extracted time series data with the corresponding nodes or edges in the static knowledge graph, and integrate the time series data into the static knowledge graph. The second integration module is used to parse the physical performance data of the hardware design from the comprehensive or static timing analysis report, and integrate the physical performance data into the static knowledge graph to generate a multimodal knowledge graph. The generation module is used to generate a static knowledge graph representing the static structure of the static HDL source code based on the hardware design, including: The HDL parser is invoked to process all static HDL source files in the project. The HDL parser extracts Module, Instance, Signal, and Statement from the static HDL source files to form nodes of the static knowledge graph, and extracts the structure and dependencies between the nodes as edges of the static knowledge graph. The extraction module is used to receive and parse the simulation output file corresponding to the hardware design, so as to extract time series data representing dynamic signal behavior from the simulation output file, including: The waveform parser parses the simulation waveform file corresponding to the hardware design, and outputs a series of timestamped signal value change events in a streaming manner. Create an event node corresponding to each signal value change event and set its attributes, including timestamp, signal identifier, and signal value; Connect all event nodes to each other in timestamp order using edges of type NEXT_EVENT to form a time series linked list; The first integration module is used to associate the extracted time-series data with corresponding nodes or edges in the static knowledge graph, and to integrate the time-series data into the static knowledge graph, including: Based on the signal identifiers in the simulation waveform file, locate the corresponding signal nodes in the static knowledge graph; The signal node in the static knowledge graph is pointed to the first event node in the time series linked list via the HAS_EVENT edge.

6. An electronic device, characterized in that, The method includes a memory and a processor, wherein the processor is used to execute computer management programs stored in the memory to implement the steps of the multimodal knowledge graph generation method for hardware design analysis as described in any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, It stores a computer management program, which, when executed by a processor, implements the steps of the multimodal knowledge graph generation method for hardware design analysis as described in any one of claims 1-4.

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