Wafer chip defect detection method and device

Abstract

The application relates to the technical field of image processing, and discloses a wafer chip defect detection method and device; the method comprises the following steps: performing pretreatment on an original wafer image, wherein the pretreatment comprises at least one of the following: contrast enhancement, noise suppression and smoothing, sharpening enhancement and normalization processing; dividing the wafer image after the pretreatment into a plurality of chip regions, and extracting a feature vector of each chip region by using a convolutional neural network to form an initial node feature matrix; constructing a wafer spatial adjacency graph based on the spatial position relationship between the chips; inputting the initial node feature matrix and the spatial adjacency graph into a defect detection model to output a wafer-level defect detection result. The application can realize comprehensive modeling of defects in the spatial distribution and correlation feature level, and improves the accuracy and robustness of detection.

Description

Technical Field

[0001] This disclosure relates to the field of image processing technology, and more specifically, to a method and apparatus for defect detection of wafer chips. Background Technology

[0002] As the key carrier in integrated circuit manufacturing, the manufacturing precision and surface quality of wafer chips directly determine the electrical performance and long-term reliability of devices. Wafer production is complex, involving multiple stages such as photolithography, etching, chemical mechanical polishing, and thin film deposition. During these stages, factors such as airborne particulate contamination, equipment vibration, or process control errors can easily lead to defects on the wafer surface, including pattern breakage, scratches, particle adhesion, and localized residues. These defects not only reduce yield but may also cause device failure in subsequent packaging and testing stages. Therefore, establishing efficient and stable defect detection technologies is a core aspect of wafer manufacturing quality control.

[0003] Currently, wafer defect detection methods are mainly divided into two categories: algorithms based on traditional image analysis and intelligent detection based on deep learning. Traditional methods rely on image grayscale features, edge information, and geometric differences to identify abnormal regions. These methods are simple to implement, but are prone to misjudgment under conditions of changing illumination, complex textures, or unstable imaging conditions. Deep learning-based detection methods generally treat each chip unit on the wafer as an independent sample, failing to consider the spatial topological relationships between chips and the propagation characteristics of defects. In wafer manufacturing, adjacent chips are often affected by the same process factors or contamination sources, and defects exhibit obvious spatial correlations. Ignoring this spatial correlation leads to a lack of global consistency in detection results, making it difficult to accurately reflect the overall failure mode of the wafer.

[0004] It is worth noting that even existing methods employing deep learning and attention mechanisms only introduce attention at the feature extraction level of a single chip, without modeling the spatial topological relationships between chips. In other words, current technologies still treat each chip on the wafer as an independent sample, failing to capture the propagation characteristics and aggregation patterns of defects between adjacent chips. This results in a lack of global consistency in detection results and low accuracy in identifying contiguous failure regions. Therefore, there is an urgent need for a method that can explicitly model the spatial relationships between chips and achieve globally consistent detection. Summary of the Invention

[0005] In view of the above situation, this application provides a method and apparatus for defect detection of wafer chips, which aims to solve the above problems or at least partially solve the above problems.

[0006] In a first aspect, embodiments of this application provide a defect detection method for a wafer chip, the method comprising:

[0007] The original wafer image is preprocessed, and the preprocessing includes at least one of the following: contrast enhancement, noise suppression and smoothing, sharpening enhancement and normalization.

[0008] The preprocessed wafer image is divided into multiple chip regions, and a convolutional neural network is used to extract the feature vector of each chip region to form an initial node feature matrix.

[0009] Based on the spatial relationships between chips, a spatial adjacency graph of the wafer is constructed;

[0010] The initial node feature matrix and spatial adjacency graph are input into the defect detection model, and the wafer-level defect detection results are output.

[0011] The defect detection model includes at least one graph convolutional layer, at least one graph attention layer, an output mapping layer, and a classification layer. The graph convolutional layer is used to extract spatial structured features. The graph attention layer is used to perform feature aggregation using a multi-head attention mechanism. The output mapping layer is used to map features to the target dimension and output a node feature matrix. The classification layer is used to calculate the defect probability of each chip based on the node feature matrix and output wafer-level defect detection results based on defect detection rules.

[0012] Secondly, embodiments of this application also provide a defect detection device for wafer chips, the device comprising:

[0013] The preprocessing module is used to preprocess the original wafer image, and the preprocessing includes at least one of the following: contrast enhancement, noise suppression and smoothing, sharpening enhancement and normalization processing;

[0014] The feature extraction module is used to divide the preprocessed wafer image into multiple chip regions and use a convolutional neural network to extract the feature vector of each chip region to form an initial node feature matrix.

[0015] The graph construction module is used to construct a spatial adjacency graph of the wafer based on the spatial positional relationships between chips;

[0016] The defect detection module is used to input the initial node feature matrix and spatial adjacency graph into the defect detection model and output wafer-level defect detection results.

[0017] The defect detection model includes at least one graph convolutional layer, at least one graph attention layer, an output mapping layer, and a classification layer. The graph convolutional layer is used to extract spatial structured features. The graph attention layer is used to perform feature aggregation using a multi-head attention mechanism. The output mapping layer is used to map features to the target dimension and output a node feature matrix. The classification layer is used to calculate the defect probability of each chip based on the node feature matrix and output wafer-level defect detection results based on defect detection rules.

[0018] Thirdly, embodiments of this application also provide an electronic device, including: a processor; and a memory arranged to store computer-executable instructions, which, when executed, cause the processor to perform the steps described in the first aspect.

[0019] Fourthly, embodiments of this application also provide a computer-readable storage medium that stores one or more programs, which, when executed by an electronic device including multiple applications, cause the electronic device to perform the steps described in the first aspect.

[0020] The above-mentioned technical solutions adopted in the embodiments of this application can achieve the following beneficial effects: preprocessing effectively suppresses the interference of imaging noise and uneven illumination, providing stable input for feature extraction; by constructing a spatial adjacency graph of the wafer, the topological relationship between chips is incorporated into the defect detection model, overcoming the limitation of traditional methods that treat each chip as an independent sample and ignore the spatial propagation characteristics of defects, significantly improving the global consistency of detection results and the accuracy of identifying contiguous defects; using graph convolutional layers to extract regular spatial structure features, and combining graph attention layers to adaptively aggregate neighborhood information through a multi-head mechanism, enhancing the robustness to defects with complex shapes and irregular distributions; the entire process realizes end-to-end automated detection from image preprocessing, feature extraction, graph structure modeling, spatial association learning to classification decision, realizing comprehensive modeling of defects at the spatial distribution and association feature levels, improving the accuracy and robustness of detection, and reducing the dependence on manual thresholds and post-processing, improving the adaptability of the system under different process conditions and the convenience of engineering deployment. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0022] Figure 1 A flowchart illustrating the defect detection method for wafer chips provided in an embodiment of this application is shown.

[0023] Figure 2 A flowchart illustrating a method for constructing a wafer space adjacency map according to an embodiment of this application is shown;

[0024] Figure 3 A schematic diagram of the spatial adjacency graph provided in an embodiment of this application is shown;

[0025] Figure 4 A flowchart of the feature extraction method for graph convolutional layers provided in an embodiment of this application is shown;

[0026] Figure 5 A flowchart of the feature aggregation method for the graph attention layer provided in an embodiment of this application is shown;

[0027] Figure 6 This paper shows a structural diagram of a wafer chip defect detection device provided in an embodiment of this application;

[0028] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] It should be noted that the terms "first," "second," etc., in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such use can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the term "comprising" and its variations should be interpreted as open-ended terms meaning "including but not limited to."

[0031] Figure 1 This paper illustrates a flowchart of a defect detection method for wafer chips provided in an embodiment of this application. Figure 1 It can be seen that this application includes at least steps S101-S104:

[0032] Step S101: Preprocess the original wafer image.

[0033] The preprocessing includes at least one of the following: contrast enhancement, noise suppression and smoothing, sharpening enhancement and normalization.

[0034] Step S102: Divide the preprocessed wafer image into multiple chip regions, and use a convolutional neural network to extract the feature vector of each chip region to form an initial node feature matrix.

[0035] Step S103: Construct a spatial adjacency graph of the wafer based on the spatial positional relationship between chips.

[0036] Step S104: Input the initial node feature matrix and spatial adjacency graph into the defect detection model, and output the wafer-level defect detection results.

[0037] The defect detection model includes at least one graph convolutional layer, at least one graph attention layer, an output mapping layer, and a classification layer. The graph convolutional layer is used to extract spatial structured features, the graph attention layer is used to aggregate features using a multi-head attention mechanism, the output mapping layer is used to map features to the target dimension and output the node feature matrix, and the classification layer is used to calculate the defect probability of each chip based on the node feature matrix and output the wafer-level defect detection results based on the defect detection rules.

[0038] from Figure 1 As can be seen from the method shown, this application achieves end-to-end automated detection through image preprocessing, feature extraction, graph structure modeling, spatial correlation learning to classification decision, realizing comprehensive modeling of defects at the spatial distribution and correlation feature level, improving the accuracy and robustness of detection, reducing the dependence on manual thresholds and post-processing, and improving the system's adaptability under different process conditions and the convenience of engineering deployment.

[0039] In some embodiments of this application, in the above method, since wafer inspection images are usually acquired by optical microscopy equipment or online inspection devices, there are problems such as brightness differences, background noise, and reflection artifacts. If directly input into the model, it is easy to cause unstable feature extraction. Therefore, in step S101, a series of preprocessing operations are performed to make the defect area visually distinct from the background. Image preprocessing mainly includes four sub-steps: contrast enhancement, noise smoothing, sharpening enhancement, and normalization.

[0040] 1. Enhanced contrast

[0041] Improve detail visibility by adjusting the image brightness distribution. Specifically, this is a linear enhancement method that adjusts the original pixel matrix. Transform based on average brightness:

[0042]

[0043] in, This represents the image after contrast enhancement. The contrast adjustment factor is set to 1.2 in this embodiment.

[0044] By increasing the grayscale difference between the defect area and the background area, local anomalies such as cracks and particle contamination are made more prominent in the image, thereby improving the stability of subsequent feature extraction.

[0045] 2. Noise suppression and smoothing

[0046] Enhanced images often contain high-frequency noise. To prevent misjudgment, the image is smoothed using a two-dimensional Gaussian filter. The Gaussian kernel used is:

[0047]

[0048] in, The standard deviation is set to 1.0 in this embodiment. The filtered image. It retains the macroscopic structural features, removes subtle noise interference, and makes the background area transition smoothly.

[0049] 3. Sharpening Enhancement

[0050] To highlight defect edges and texture details, high-frequency components are superimposed on the smoothed image. An unsharp masking algorithm is employed.

[0051]

[0052] in, This represents the image after sharpening and enhancement. This represents the image after noise smoothing. The sharpening factor is set to 1.0 in this embodiment.

[0053] Sharpening can enhance the boundary features of defects such as cracks and broken lines.

[0054] 4. Normalization processing

[0055] To eliminate the effects of differences in lighting conditions and inconsistent imaging gain, local zero-mean normalization is employed:

[0056]

[0057] in, This represents the normalized image. and These are the local mean and standard deviation, respectively. Set as This prevents the denominator from being zero. Normalization ensures the consistency of the numerical distribution of the input data, improving the convergence speed and generalization ability of the network model.

[0058] In this embodiment, the preprocessed image exhibits a more balanced brightness distribution, highlights defect details, and significantly reduces background noise through the aforementioned steps. This stage provides clear and stable input features for the feature extraction module, which helps improve the discriminative performance of the subsequent graph neural network.

[0059] In some embodiments of this application, after image preprocessing is completed in step S101, chip-level segmentation and feature vector extraction are performed on the overall wafer image in step S102 to achieve structured input and region-level analysis. Chips on a wafer are typically arranged in a regular array, and their geometric distribution parameters are determined during the design phase. By utilizing layout coordinate information, the entire wafer image can be segmented into multiple independent chip regions, providing a foundation for subsequent spatial topology modeling.

[0060] Specifically, the chip area is divided based on the following method:

[0061] Based on wafer mask information or equipment calibration data, obtain the width of each chip. ,high Number of rows and columns and the starting coordinates of the top left corner If there is a gap between adjacent chips, then the step size will be used. Alternative chip size parameters. Based on this data, calculate the... Line number Chip center coordinates:

[0062]

[0063] Using this center as a reference, the corresponding chip area is extracted. :

[0064]

[0065] Through the above calculations, the entire wafer image is precisely divided into... There are three non-overlapping chip regions, each corresponding to a node in the subsequent graph neural network.

[0066] The chip partitioning process can be automated using scripts. To prevent interference from incomplete chips at the wafer edges, embodiments of this application may optionally use region masks to exclude partially obscured or incomplete chip areas. If there is slight rotation or offset in the image, geometric correction can be performed using template matching or Hough transform before partitioning to ensure partitioning accuracy.

[0067] Furthermore, each chip area The input is fed into a convolutional neural network model to extract local texture and morphological features.

[0068] In some embodiments, the convolutional neural network uses ResNet-18 as the backbone network and introduces a feature pyramid network into ResNet-18. That is, features of the chip region are extracted based on ResNet-18 to obtain feature maps of multiple stages, and then the feature pyramid network is used to fuse the feature maps of multiple stages to obtain the feature vector of each chip.

[0069] Specifically, ResNet-18 is used as the feature extraction backbone network, the final classification layer is removed, and only the convolutional feature extraction part is retained. The input image size is uniformly adjusted to... After processing by a convolutional network, a 256-dimensional feature vector is output:

[0070]

[0071] in, Indicates the first i Line number j The feature vector of the chip region centered on the column. Indicates the first i Line number j The chip area is centered around the column.

[0072] To fully describe the multi-scale structural features of defects, a Feature Pyramid Network (FPN) structure is introduced into the convolutional network to fuse the feature maps of layers 2 (conv2_x), 3 (conv3_x), and 4 (conv4_x) of ResNet-18. Specifically, the fusion method involves first upsampling the deep features by a factor of 2, then adding them element-wise with the shallow features, and finally... The number of channels in the convolution is unified to 256. The fused features are represented as follows:

[0073]

[0074] This structure enables the model to maintain sensitivity to details while possessing a stronger ability to express defect patterns.

[0075] The extracted feature vectors are then normalized using L2 to generate the initial node feature matrix. ,in This represents the total number of chips.

[0076] In this embodiment, by precisely dividing the wafer image according to the chip array, the transformation from a holistic image to structured region data is achieved, providing node-based input for subsequent graph structure modeling. Using a convolutional neural network to extract feature vectors for each chip region effectively captures the local visual patterns of texture, morphology, and potential defects within the chip. The generated feature vectors, after normalization, form a unified node feature representation, which not only provides high-quality initial feature input for the graph neural network but also enhances the comparability of features between different chips and the stability of spatial correlation modeling. Simultaneously, this step, through a multi-scale feature fusion mechanism, takes into account both detailed features and semantic information, improving the model's ability to identify defects at different scales. Overall, this process achieves automated conversion from the original image to a structured feature representation, laying a reliable foundation for subsequent global spatial correlation analysis based on graph neural networks, and contributing to improved overall defect detection accuracy and system robustness.

[0077] In some embodiments of this application, after chip region partitioning and feature extraction are completed in step S102, the entire wafer is modeled as graph structure data to describe the spatial adjacency relationships between chips and the characteristics of potential defect propagation. Chips on the wafer are arranged in a regular grid in geometric space, and there are often process correlations between adjacent chips, such as being jointly affected by errors from the same lithography step or the diffusion of contaminant particles. To fully utilize this spatial correlation, this application establishes a graph model to achieve a structured representation of global spatial information. Figure 2 As shown, this application provides a method for constructing a wafer space adjacency graph, including the following steps:

[0078] Step S201: Using chips as nodes and spatial associations between chips as edges, establish node connection relationships using an eight-adjacency model.

[0079] The entire wafer is represented as a figure. ,in, A set of nodes, representing chips on a wafer. This is a set of edges, representing the spatial connections between chips. Number of nodes. Equal to the total number of chips . No. Line number Column chip corresponding node Its initial features are the feature vectors output by the aforementioned convolutional network. express.

[0080] The embodiments of this application adopt an eight-adjacency model, that is, each chip Establish connections with its eight neighboring chips (top, bottom, left, right, top-left, top-right, bottom-left, bottom-right). For boundary chips, only establish connections with their actual neighbors. Edge set. Defined as:

[0081]

[0082] This adjacency pattern can capture multi-directional spatial dependencies, making it suitable for the anisotropic propagation characteristics of wafer defects.

[0083] Step S202: Construct an adjacency matrix based on the edge set and normalize it to obtain a normalized adjacency matrix.

[0084] Based on the edge set Constructing an adjacency matrix ,in:

[0085]

[0086] To enhance model stability and training convergence, the adjacency matrix is ​​symmetrically normalized. First, self-loops are added, resulting in... ,in, Let the identity matrix be denoted by ... The diagonal element is Then the normalized adjacency matrix is ​​defined as:

[0087]

[0088] This normalization method ensures that the features of each node remain consistent on a numerical scale during message propagation, avoiding interference from nodes with large degree differences in model learning.

[0089] Step S203: Design hybrid edge weights based on feature cosine similarity and Euclidean distance, and generate a weighted adjacency matrix through the normalized adjacency matrix and the hybrid edge weights.

[0090] To more accurately reflect the strength of association between different neighbors, this application introduces learnable weights on the edges. This application employs a hybrid weighting strategy that combines feature similarity and spatial distance:

[0091]

[0092] in, The cosine similarity of the feature vectors. The Euclidean distance between the centers of the two chips is... As the distance attenuation coefficient, this application sets (in chip width units). This hybrid weighting strategy considers both spatial proximity and feature consistency, enabling the model to adaptively identify defect clusters.

[0093] The weighted adjacency matrix is ​​defined as ,in .

[0094] Step S204: Generate a spatial adjacency graph based on the weighted adjacency matrix and the node connection relationships.

[0095] Based on the adjacency relationships and weight definitions described above, a weighted graph is constructed. ,like Figure 3 The diagram illustrates a spatial adjacency graph. A corresponding sparse matrix representation is generated for input into the graph neural network. (Node feature matrix) with normalized weighted adjacency matrix Together, they serve as input for subsequent message propagation stages, enabling unified modeling of the overall spatial relationships of the wafer.

[0096] In this embodiment, the wafer defect detection problem is transformed from the traditional independent sample classification problem into a graph structure data analysis problem, laying the foundation for information transmission and spatial correlation feature capture of graph convolutional neural networks.

[0097] In some embodiments of this application, after constructing the wafer spatial adjacency graph in step S103, this application utilizes a fusion architecture of Graph Convolutional Network (GCN) and Graph Attention Network (GAT) to achieve multi-layer propagation of node features and adaptive aggregation of spatial correlation features. This process achieves interaction of different node features through message passing of the weighted adjacency matrix, enabling the model to capture the spatial diffusion pattern and structured distribution features of defects.

[0098] The graph neural network constructed in this application has a total depth of 5 layers, and the specific structure configuration is as follows:

[0099] Layer 1 (First Graph Convolutional Layer): Input dimension 256, Output dimension 512;

[0100] Layer 2 (Second Graph Convolutional Layer): Input dimension 512, Output dimension 512;

[0101] Layer 3 (Attention Layer of the First Graph): Input dimension 512, Output dimension 512;

[0102] Layer 4 (Second Graph Attention Layer): Input dimension 512, Output dimension 512;

[0103] Layer 5 (Output Mapping Layer): Input dimension 512, output dimension 128.

[0104] The input to the graph neural network input layer is the initial node feature matrix output in step S102. Layers 1-2 use standard graph convolution operations to extract regularized spatial relationship features; layers 3-4 introduce a graph attention mechanism to assign adaptive weights to different neighboring nodes; layer 5 uses a fully connected transformation to map high-dimensional features to the low-dimensional space required for classification.

[0105] like Figure 4 As shown, this application provides a feature extraction method for graph convolutional layers, including the following steps:

[0106] Step S301: Based on the normalized adjacency matrix and the features of neighboring nodes, obtain the aggregated neighborhood feature matrix.

[0107] For nodes According to the normalized adjacency matrix Weighted summation of the features of its neighboring nodes:

[0108]

[0109] in, This represents the aggregated neighborhood feature matrix. W The normalized adjacency matrix constructed in step S103, l Indicates the number of floors. Indicates the first l-1 Features of neighboring nodes in a layer.

[0110] Step S302: Perform a linear transformation on the aggregated neighborhood feature matrix and activate it based on the activation function.

[0111] Aggregated feature matrix Learnable weight matrix A linear transformation is applied, followed by the application of a nonlinear activation function:

[0112]

[0113] Among them, the first layer weight matrix Bias vector ; Second layer weight matrix Bias vector .

[0114] The activation function used is Leaky ReLU:

[0115]

[0116] With the negative slope coefficient set to 0.01, this activation function retains a small gradient in the negative region compared to the standard ReLU, which can effectively alleviate the gradient vanishing problem.

[0117] Step S303: Apply batch normalization to the activated features to obtain normalized features.

[0118] To accelerate training convergence and stabilize the feature distribution, a batch normalization operation is applied after activation:

[0119]

[0120] in, and These are the within-batch mean and variance, respectively. and For learnable scaling and translation parameters, Set as .

[0121] Step S304: Apply random deactivation operation to randomly discard features with a preset probability and output spatial structured features.

[0122] Apply Dropout to randomly discard a portion of the neuron's output:

[0123]

[0124] The dropout rate p is set to 0.3, meaning that during each forward propagation, 30% of the neuron outputs are randomly reset to zero, and the remaining outputs are processed according to... Scale by a factor of 1 to keep the expected value unchanged.

[0125] Through the propagation of the two-layer GCN mentioned above, the model achieves the aggregation of spatial information within the 2-hop neighborhood of the chip node.

[0126] like Figure 5 As shown, this application provides a feature aggregation method for a graph attention layer, including the following steps:

[0127] Step S401: Perform a linear feature transformation on the node features output by the graph convolutional layer to map the dimension to 128 dimensions.

[0128] Linear transformations are applied to node features to extract high-level semantic information:

[0129]

[0130] in, To share the weight matrix, the transformed feature dimension is 128.

[0131] Step S402: For each node and its neighboring nodes, concatenate the transformed node feature vectors and calculate the original attention score.

[0132] The transformed node feature pairs are concatenated, and a score is calculated using an attention mechanism:

[0133]

[0134] in, This indicates a vector concatenation operation, resulting in a vector with a dimension of 256. This is a learnable attention vector. The negative slope coefficient of the LeakyReLU activation function is set to 0.2. For nodes i For nodes j The original attention score.

[0135] Step S403: Normalize the original attention scores of each node and its neighboring nodes to obtain normalized attention weights.

[0136] For nodes i The attention scores of all neighboring nodes (including itself) are normalized using softmax:

[0137]

[0138] This normalization operation ensures that the sum of the attention weights of all neighboring nodes is 1.

[0139] Step S404: Based on the attention weights, perform a weighted summation of the neighborhood features to generate the output features of the attention head.

[0140] Based on attention weights, the neighborhood features are summed using a weighted average:

[0141]

[0142] Step S405: Employ a multi-head attention mechanism to fuse the 128-dimensional features output by multiple attention heads to generate fused features.

[0143] To enhance the robustness and expressiveness of feature learning, this application employs a multi-head attention mechanism in both layers 3 and 4. (Number of attention heads) Set to 4. Each attention head independently calculates attention weights and generates a 128-dimensional feature vector.

[0144] The third layer uses a concatenation method to merge the outputs from each header:

[0145]

[0146] The feature dimension after concatenation is This splicing operation integrates the different subspace features extracted from each head into a complete high-dimensional representation.

[0147] The fourth layer uses an averaging method to fuse the outputs from each head:

[0148]

[0149] The average fusion dimension is 512. The average fusion method reduces dimensionality fluctuations while preserving common features of each head, making the output features more stable.

[0150] The weight matrix of each attention head is initialized independently, and the first... The parameters of the head include: feature transformation matrix and attention vector .

[0151] After multi-head attention fusion at layer 4, layer normalization is applied:

[0152]

[0153] in, and Let the mean and variance of this feature matrix be... and These are learnable parameters. Layer normalization stabilizes the feature distribution and accelerates training convergence.

[0154] Furthermore, based on the residual connection mechanism, the output features of the second graph convolutional layer, the residual projection matrix, and the output features of the second graph attention layer are fused together and used as the input to the output mapping layer.

[0155] Specifically, the fifth layer is the output mapping layer, which maps the 512-dimensional features of the fourth layer to 128 dimensions:

[0156]

[0157] in, ， .

[0158] Perform L2 normalization on the output features:

[0159]

[0160] This normalization operation projects all feature vectors onto a unit hypersphere, making the features of different samples comparable in geometric space.

[0161] After multi-layer propagation and feature aggregation in a 5-layer graph neural network, the output node feature matrix is ​​obtained. Each node has a 128-dimensional feature vector. It also includes the chip's local texture features, neighborhood spatial structure information, and global defect distribution context. This feature matrix As input to the classification layer in step S105, it is used for final defect judgment and wafer-level quality analysis.

[0162] In this embodiment, during the feature extraction stage, a multi-scale convolutional neural network is used to fuse shallow texture and deep semantic features, ensuring that different types of defects can be stably identified under changes in morphology and scale. By introducing a graph convolutional structure with an attention mechanism, the model can adaptively adjust the weights of neighborhood information during feature propagation, highlighting the feature contribution of abnormal regions, thereby improving the recognition accuracy of complex defect clusters.

[0163] In some embodiments of this application, after information propagation through multi-layer graph convolution and attention mechanisms, a node-level high-dimensional feature representation matrix is ​​obtained. To achieve defect identification and classification, this application sets a classification layer after the graph convolutional layer to determine the defects of the chip corresponding to each node.

[0164] Features of each node After transformation by a fully connected layer and processing by the Sigmoid activation function, the output is the probability value of it being a defective chip:

[0165]

[0166] in, This is the classification weight matrix. For bias terms, Indicates the first The probability that a chip is a defective sample (NG). The Sigmoid function is defined as:

[0167]

[0168] Based on probability threshold Perform binary classification: when If the chip is found to be defective (labeled 1), it is considered normal (labeled 0). In some embodiments, the threshold is... Set to 0.5, which can be adjusted according to actual testing needs.

[0169] In this embodiment, the loss function of the classification layer includes classification loss and spatial consistency constraint. The classification loss uses the Focal Loss function; to ensure that the detection results of adjacent chips remain spatially smooth and consistent, the spatial consistency constraint uses a graph Laplacian-based regularization term to encourage consistency in the prediction results of adjacent nodes.

[0170] Specifically, the loss function for the classification layer is: .

[0171] in, Represents classification loss. Represents spatial consistency constraints. This is the regularization coefficient, used to balance classification accuracy and spatial consistency. This application sets... .

[0172] The classification loss function is expressed as follows:

[0173]

[0174] in, For the true labels of the samples, As a balance factor, This application sets the focusing parameters. (Give higher weight to a few defective classes). This function is passed through The loss weight for difficult-to-classify samples is increased, making the model pay more attention to defective samples that are prone to misclassification, thereby improving detection sensitivity.

[0175] The expression for spatial consistency loss is:

[0176]

[0177] in, Let the size of the edge set be . This term represents the edge weight. It causes spatially adjacent chips with similar features to tend to receive similar prediction probabilities, which aligns with the physical characteristic of spatial clustering of wafer defects.

[0178] In this embodiment, through joint optimization, the model can improve the recognition stability of spatially continuous regions while maintaining detection accuracy. Furthermore, by adding a spatial smoothing regularization term to the loss function, the continuity of prediction results for adjacent nodes is constrained, effectively avoiding the occurrence of isolated false detections and ensuring that the detection results have spatial consistency and physical rationality.

[0179] Furthermore, node-level classification results can be further aggregated to wafer-level judgment. Defect detection rules include at least one of the following:

[0180] (1) Defect density determination: The proportion of defective nodes exceeds the threshold. Time (set in this application embodiment) (i.e., 5%), marked as NG; this rule is used to detect scattered defect patterns and reflects the overall process stability.

[0181] (2) Spatial clustering determination: The continuous area of ​​the defect region is greater than the threshold. When the contiguous area is (as defined in this embodiment) (Each chip), marked as NG. This rule is used to detect clustered failures caused by localized process anomalies.

[0182] If any of the above conditions are met, the wafer is deemed non-compliant (NG) and requires process traceability or scrapping.

[0183] Furthermore, by performing graph global average pooling on all node features, a wafer-level global feature representation can be obtained:

[0184]

[0185] This wafer-level feature It can be used for probabilistic assessment of overall wafer quality or batch-to-batch consistency analysis.

[0186] The classification output and loss optimization process enables the model to maintain stable recognition performance under imbalanced sample conditions, and improves the physical rationality and global consistency of detection results under spatial topological constraints.

[0187] The training process of the defect detection model is described below. The training phase includes steps such as data preparation, optimization algorithm selection, learning rate scheduling strategy, model early stopping mechanism, and parameter saving.

[0188] 1. Training data preparation

[0189] The input samples are preprocessed wafer image data and their corresponding defect annotations. The annotation data comes from the results of automated inspection equipment or expert review information. To balance the sample ratio of different defect categories, stratified sampling is used in the dataset. All images undergo normalization and size unification operations before input to ensure consistency between the numerical range and the input dimensions. Node labels are generated based on chip-level inspection results; normal samples are labeled 0, and defective samples are labeled 1.

[0190] The training set, validation set, and test set are divided in a ratio of 7:1.5:1.5. The batch size is set to 8 (i.e., each batch contains 8 wafer images and their corresponding graph structures).

[0191] 2. Optimization Algorithm Selection

[0192] The model parameters are updated using the Adam optimization algorithm. Its parameters are set as follows: initial learning rate... First-order momentum coefficient Second momentum coefficient Weight decay coefficient The optimization objective is to minimize the total loss function. The model calculates the gradient and updates the weights using the backpropagation algorithm.

[0193] 3. Weight Initialization

[0194] The network weights are initialized using the He method, i.e., the weight matrix... Each element has a mean of 0 and a standard deviation of Sampling is performed from a normal distribution, where Input dimension. Bias vector. Initialize to 0. Attention vector. Xavier initialization is used, starting with a mean of 0 and a standard deviation of 0. Sampling is performed from a normal distribution, where The dimension is vector. This initialization scheme ensures stable gradient propagation between layers during the initial training phase.

[0195] 4. Learning rate scheduling strategy

[0196] To prevent oscillations or premature convergence during training, a cosine annealing learning rate scheduling strategy is employed. Its variation pattern is as follows:

[0197]

[0198] in, For the first Learning rate for each iteration The initial learning rate, Minimum learning rate, T The annealing period is measured in epochs. This strategy maintains a large learning rate in the early stages of training to accelerate convergence, and gradually reduces the learning rate in the later stages to improve accuracy and stability.

[0199] 5. Early stopping mechanism and model saving

[0200] During training, the loss and accuracy on the validation set are monitored. The total number of training epochs is set to 200. If the validation set loss does not decrease for 10 consecutive epochs, an early stopping mechanism is triggered to terminate training and avoid overfitting. After training, the model parameters that best perform on the validation set are saved as the final detection model to ensure the model's generalization performance in real-world applications. The model parameters are saved as a .pth format file, containing the weight matrices, bias vectors, batch normalization parameters, and optimizer states for all network layers.

[0201] 6. Model Reasoning and Output

[0202] During the inference phase, a new wafer image is input to obtain the defect probability of each chip. According to the set threshold A binary classification decision is made to obtain node-level detection results.

[0203] Spatial aggregation calculations can be used to further generate a wafer-level defect distribution heatmap. This heatmap presents the defect probability distribution using a color mapping method: probability value... Mapped to a chromatogram [blue → green → yellow → red], where blue indicates normal ( (Close to 0), red indicates defects ( (Approximately 1). This visualization can help process engineers quickly locate areas of concentrated defects and trace the causes of potential process anomalies.

[0204] The trained graph neural network model of this application can be deployed in factory inspection terminals or edge computing devices. To improve real-time performance, this application can also adopt the following optimization strategies:

[0205] (1) Graph sparsification: Remove edges with attention weights below the threshold (set to 0.01) to reduce computation;

[0206] (2) INT8 quantization: Quantizes floating-point weights into 8-bit integers, compresses the model size to 1 / 4 of the original, and improves inference speed by 2–3 times;

[0207] (3) Batch inference: For large-size wafers, they can be processed in parallel by region, and the detection results of each region can be spliced ​​together in space to restore the original results.

[0208] In this embodiment, on an NVIDIA RTX 3090 GPU, the complete inference time for a single wafer (containing approximately 1000 chips) is about 45 ms, meeting the industrial-grade real-time inspection requirements (<100 ms). This training and inference process ensures the model's stable performance under multiple batches and process conditions, enabling the present invention to achieve high-precision, low-latency wafer defect detection in a production line environment.

[0209] In some embodiments of this application, a defect detection device for a wafer chip is provided, which corresponds one-to-one with the defect detection methods for wafer chips described in the above embodiments. For example... Figure 6 As shown, the defect detection device for the wafer chip includes a preprocessing module 101, a feature extraction module 102, a graph construction module 103, and a defect detection module 104.

[0210] Preprocessing module 101 is used to preprocess the original wafer image, and the preprocessing includes at least one of the following: contrast enhancement, noise suppression and smoothing, sharpening enhancement and normalization processing;

[0211] The feature extraction module 102 is used to divide the preprocessed wafer image into multiple chip regions and use a convolutional neural network to extract the feature vector of each chip region to form an initial node feature matrix.

[0212] Graph construction module 103 is used to construct a spatial adjacency graph of the wafer based on the spatial positional relationship between chips;

[0213] Defect detection module 104 is used to input the initial node feature matrix and spatial adjacency graph into the defect detection model and output wafer-level defect detection results;

[0214] The defect detection model includes at least one graph convolutional layer, at least one graph attention layer, an output mapping layer, and a classification layer. The graph convolutional layer is used to extract spatial structured features. The graph attention layer is used to perform feature aggregation using a multi-head attention mechanism. The output mapping layer is used to map features to the target dimension and output a node feature matrix. The classification layer is used to calculate the defect probability of each chip based on the node feature matrix and output wafer-level defect detection results based on defect detection rules.

[0215] In some embodiments of this application, in the above-described apparatus, the convolutional neural network uses ResNet-18 as the backbone network and introduces a feature pyramid network into ResNet-18;

[0216] Feature extraction module 102 is specifically used to extract features of the chip region based on ResNet-18 and obtain feature maps of multiple stages;

[0217] The feature pyramid network is used to fuse feature maps from multiple stages to obtain the feature vector of each chip.

[0218] In some embodiments of this application, in the above-described apparatus, the graph construction module 103 is specifically used to establish node connection relationships using an eight-adjacency model with chips as nodes and inter-chip spatial associations as edges.

[0219] An adjacency matrix is ​​constructed based on the edge set and then normalized to obtain a normalized adjacency matrix.

[0220] Hybrid edge weights are designed based on feature cosine similarity and Euclidean distance, and a weighted adjacency matrix is ​​generated through the normalized adjacency matrix and the hybrid edge weights.

[0221] A spatial adjacency graph is generated based on the weighted adjacency matrix and the node connection relationships.

[0222] In some embodiments of this application, in the above-described apparatus, the graph convolutional layer is used to extract spatially structured features, including:

[0223] Based on the normalized adjacency matrix and the features of neighboring nodes, the aggregated neighborhood feature matrix is ​​obtained;

[0224] The aggregated neighborhood feature matrix is ​​linearly transformed and then activated based on an activation function.

[0225] Batch normalization is applied to the activated features to obtain normalized features;

[0226] By applying a random deactivation operation, features with a preset probability are randomly discarded, and spatially structured features are output.

[0227] In some embodiments of this application, in the above-described apparatus, the graph attention layer is used to perform feature aggregation using a multi-head attention mechanism, including:

[0228] The node features output by the graph convolutional layer are subjected to a linear feature transformation, which maps the dimension to 128.

[0229] For each node and its neighboring nodes, the transformed node feature vectors are concatenated, and the original attention score is calculated.

[0230] The original attention scores of each node and its neighboring nodes are normalized to obtain normalized attention weights;

[0231] Based on the attention weights, the neighborhood features are weighted and summed to generate the output features of the attention head;

[0232] A multi-head attention mechanism is adopted to fuse the 128-dimensional features output by multiple attention heads to generate fused features.

[0233] In some embodiments of this application, the defect detection model in the above-described apparatus includes a first graph convolutional layer, a second graph convolutional layer, a first graph attention layer, and a second graph attention layer;

[0234] The second graph convolutional layer and the second graph attention layer are connected by a residual connection mechanism. The features fused from the output features of the second graph convolutional layer, the residual projection matrix, and the output features of the second graph attention layer are used as the input to the output mapping layer.

[0235] In some embodiments of this application, in the above-described apparatus, the loss function of the classification layer includes a classification loss and a spatial consistency constraint. The classification loss employs a Focal Loss function, and the spatial consistency constraint employs a regularization term based on graph Laplacian.

[0236] In some embodiments of this application, the defect detection rules in the above-described apparatus include at least one of the following:

[0237] When the percentage of defective nodes exceeds a certain threshold, the wafer is considered defective.

[0238] When a defective region forms a continuous area larger than the area threshold, the wafer is judged as defective.

[0239] In some embodiments of this application, in the above-described apparatus, the defect detection model uses the Adam optimization algorithm to update network parameters, the He initialization method to initialize network weights, and the cosine annealing strategy to schedule the learning rate during training.

[0240] An early stopping mechanism is set up during training; if the validation set loss does not decrease for several consecutive rounds, training is stopped.

[0241] It should be noted that any of the aforementioned wafer chip defect detection devices can implement the aforementioned wafer chip defect detection methods one by one, which will not be elaborated here.

[0242] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Figure 7 As shown, at the hardware level, this electronic device includes a processor, and optionally also includes an internal bus, a network interface, and memory. The memory may include main memory, such as high-speed random-access memory (RAM), or it may include non-volatile memory, such as at least one disk drive. Of course, this electronic device may also include other hardware required for other business operations.

[0243] The processor, network interface, and memory can be interconnected via an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 7 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0244] Memory is used to store programs. Specifically, programs may include program code, which includes computer operation instructions. Memory may include main memory and non-volatile memory, and provides instructions and data to the processor.

[0245] The processor reads the corresponding computer program from non-volatile memory into main memory and then runs it, forming a defect detection device for the wafer chip at the logical level. The processor executes the program stored in memory and specifically performs the aforementioned methods.

[0246] The processor may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0247] This electronic device can execute the wafer chip defect detection method provided in several embodiments of this application, and realize the wafer chip defect detection device in Figure 6 The functions of the embodiments shown are not described in detail here.

[0248] This application also proposes a computer-readable storage medium that stores one or more programs, the programs including instructions that, when executed by an electronic device including multiple applications, enable the electronic device to perform the wafer chip defect detection method provided in several embodiments of this application.

[0249] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0250] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0251] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0252] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0253] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0254] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0255] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0256] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0257] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0258] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for defect detection of a wafer chip, characterized in that, The method includes: The original wafer image is preprocessed, and the preprocessing includes at least one of the following: contrast enhancement, noise suppression and smoothing, sharpening enhancement and normalization. The preprocessed wafer image is divided into multiple chip regions, and a convolutional neural network is used to extract the feature vector of each chip region to form an initial node feature matrix. Based on the spatial relationships between chips, a spatial adjacency graph of the wafer is constructed; The initial node feature matrix and spatial adjacency graph are input into the defect detection model, and the wafer-level defect detection results are output. The defect detection model includes a first graph convolutional layer, a second graph convolutional layer, a first graph attention layer, a second graph attention layer, an output mapping layer, and a classification layer. The graph convolutional layer is used to extract spatial structured features, the graph attention layer is used to perform feature aggregation using a multi-head attention mechanism, the output mapping layer is used to map features to the target dimension output node feature matrix, and the classification layer is used to calculate the defect probability of each chip based on the node feature matrix and output wafer-level defect detection results based on defect detection rules. The second graph convolutional layer and the second graph attention layer are connected by a residual connection mechanism, and the output features of the second graph convolutional layer, the residual projection matrix, and the fused features output by the second graph attention layer are used as the input to the output mapping layer. The construction of a spatial adjacency graph for the wafer based on the spatial positional relationships between chips includes: Using chips as nodes and spatial relationships between chips as edges, an eight-adjacency model is used to establish node connection relationships. An adjacency matrix is ​​constructed based on the edge set and then normalized to obtain a normalized adjacency matrix. Hybrid edge weights are designed based on feature cosine similarity and Euclidean distance, and a weighted adjacency matrix is ​​generated through the normalized adjacency matrix and the hybrid edge weights. A spatial adjacency graph is generated based on the weighted adjacency matrix and the node connection relationships.

2. The method according to claim 1, characterized in that, The convolutional neural network uses ResNet-18 as the backbone network and introduces a feature pyramid network into ResNet-18; The extraction of feature vectors for each chip region using a convolutional neural network includes: Based on ResNet-18, features of the chip region are extracted to obtain feature maps at multiple stages; The feature pyramid network is used to fuse feature maps from multiple stages to obtain the feature vector of each chip.

3. The method according to claim 1, characterized in that, The graph convolutional layer is used to extract spatially structured features, including: Based on the normalized adjacency matrix and the features of neighboring nodes, the aggregated neighborhood feature matrix is ​​obtained; The aggregated neighborhood feature matrix is ​​linearly transformed and then activated based on an activation function. Batch normalization is applied to the activated features to obtain normalized features; By applying a random deactivation operation, features with a preset probability are randomly discarded, and spatially structured features are output.

4. The method according to claim 1, characterized in that, The graph attention layer is used for feature aggregation using a multi-head attention mechanism, including: The node features output by the graph convolutional layer are subjected to a linear feature transformation, which maps the dimension to 128. For each node and its neighboring nodes, the transformed node feature vectors are concatenated, and the original attention score is calculated. The original attention scores of each node and its neighboring nodes are normalized to obtain normalized attention weights; Based on the attention weights, the neighborhood features are weighted and summed to generate the output features of the attention head; A multi-head attention mechanism is adopted to fuse the 128-dimensional features output by multiple attention heads to generate fused features.

5. The method according to claim 1, characterized in that, The loss function of the classification layer includes classification loss and spatial consistency constraint. The classification loss adopts the Focal Loss function, and the spatial consistency constraint adopts a regularization term based on graph Laplacian.

6. The method according to claim 1, characterized in that, The defect detection rule includes at least one of the following: When the percentage of defective nodes exceeds a certain threshold, the wafer is considered defective. When a defective region forms a continuous area larger than the area threshold, the wafer is judged as defective.

7. The method according to any one of claims 1 to 6, characterized in that, The defect detection model uses the Adam optimization algorithm to update network parameters, the He initialization method to initialize network weights, and the cosine annealing strategy to schedule the learning rate during training. An early stopping mechanism is set up during training; if the validation set loss does not decrease for several consecutive rounds, training is stopped.

8. A defect detection device for wafer chips, characterized in that, The device includes: The preprocessing module is used to preprocess the original wafer image, and the preprocessing includes at least one of the following: contrast enhancement, noise suppression and smoothing, sharpening enhancement and normalization processing; The feature extraction module is used to divide the preprocessed wafer image into multiple chip regions and use a convolutional neural network to extract the feature vector of each chip region to form an initial node feature matrix. The graph construction module is used to construct a spatial adjacency graph of the wafer based on the spatial positional relationships between chips; The defect detection module is used to input the initial node feature matrix and spatial adjacency graph into the defect detection model and output wafer-level defect detection results. The defect detection model includes a first graph convolutional layer, a second graph convolutional layer, a first graph attention layer, a second graph attention layer, an output mapping layer, and a classification layer. The graph convolutional layer is used to extract spatial structured features, the graph attention layer is used to perform feature aggregation using a multi-head attention mechanism, the output mapping layer is used to map features to the target dimension output node feature matrix, and the classification layer is used to calculate the defect probability of each chip based on the node feature matrix and output wafer-level defect detection results based on defect detection rules. The second graph convolutional layer and the second graph attention layer are connected by a residual connection mechanism, and the output features of the second graph convolutional layer, the residual projection matrix, and the fused features output by the second graph attention layer are used as the input to the output mapping layer. The graph construction module is specifically used to establish node connection relationships using chips as nodes and spatial associations between chips as edges, employing an eight-adjacency model; constructing an adjacency matrix based on the edge set and normalizing it to obtain a normalized adjacency matrix; designing hybrid edge weights based on feature cosine similarity and Euclidean distance; generating a weighted adjacency matrix through the normalized adjacency matrix and the hybrid edge weights; and generating a spatial adjacency graph based on the weighted adjacency matrix and the node connection relationships.

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