Oscillation circuit and electronic device

Abstract

The application belongs to the field of electronic circuits and provides an oscillation circuit and an electronic device. The oscillation circuit comprises a trimmable resistance array module, a charge pump module and an oscillator core module; the oscillator core module is connected with the trimmable resistance array module and the charge pump module respectively. The trimmable resistance array module outputs a first current according to a first frequency trimming signal. The charge pump module outputs a second current according to a first oscillation signal. The oscillator core module outputs the first oscillation signal and a clock signal according to the first current and the second current; if the oscillation frequency of the clock signal does not reach a preset frequency, the first frequency trimming signal is changed to change the first current, so that the oscillation frequency reaches the preset frequency. The application combines the frequency trimming mode and the closed-loop control of the feedback loop, which can not only make the oscillation frequency reach the preset frequency, but also ensure that it remains stable under various working conditions, finally meeting the requirement of ±2% accuracy in the scene of UART communication.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to an oscillation circuit and electronic device. Background Technology

[0002] UART (Universal Asynchronous Receiver / Transmitter) communication protocol is an asynchronous serial communication protocol, therefore the two communicating parties do not share a clock signal. Data transmission and reception rely entirely on each party's independent local reference oscillator (clock source) to generate the baud rate clock. Therefore, UART communication has specific requirements for the accuracy (frequency stability) of the reference oscillator to ensure that the receiving end can sample data bits at the correct time.

[0003] To ensure that the sampling point at the receiving end does not deviate from the effective window of the data bits (usually required to be kept near the middle of the data bits) during the entire data frame transmission, the accuracy requirement for the oscillator is typically ±2% in practical engineering. Furthermore, frequency offsets caused by operating temperature, power supply voltage, and process fluctuations must not exceed the allowable error range.

[0004] Traditional relaxor oscillators generate oscillation signals by utilizing the periodic charging and discharging characteristics of capacitors. Although they have the advantage of simple circuit structure, their accuracy is limited and they cannot meet the requirements of UART communication. Summary of the Invention

[0005] This application provides an oscillation circuit and electronic device that can solve the problem that traditional relaxation oscillators are difficult to meet the requirements of UART communication due to their limited accuracy.

[0006] In a first aspect, embodiments of this application provide an oscillation circuit, including an adjustable resistor array module, a charge pump module, and an oscillator core module; the oscillator core module is connected to the adjustable resistor array module and the charge pump module respectively.

[0007] The adjustable resistor array module is used to output a first current according to a first frequency adjustment signal; the charge pump module is used to output a second current according to a first oscillation signal; the oscillator core module is used to output a first oscillation signal and a clock signal according to the first current and the second current; if the oscillation frequency of the clock signal does not reach the preset frequency, the first frequency adjustment signal is changed to change the first current, thereby making the oscillation frequency reach the preset frequency.

[0008] In one possible implementation of the first aspect, the adjustable resistor array module includes n+1 resistors R 01 ,R 11 ,……,R n1n-1 resistors R 02 ,R 12 ,……,R (n-2)2 and n switches, where n is a natural number greater than 2; n-1 resistors R 02 ,R 12 ,……,R (n-2)2 series in series, resistor R (n-2)2 The first terminal and resistor R n1 The first terminal receives the power supply voltage, and the i-th resistor R i1 The first end is connected to resistor R (i-1)2 With resistance R (i-2)2 The common terminal, 2≤i≤n-1, resistor R 02 The second terminal is connected to resistor R respectively 11 The first terminal and resistor R 01 The first terminal is connected to resistor R. 11 ,R 21 ,……,R n1 The second terminal is connected to the first terminal of each of the n switches, and the resistor R 01 The second terminal is connected to the second terminal of the charge pump module, the oscillator core module, and the n switches respectively. The third terminal of the n switches is grounded, and the control terminal of the n switches receives the first frequency adjustment signal.

[0009] In one possible implementation of the first aspect, the oscillator core module includes an integration unit, a voltage-to-current conversion unit, an oscillation unit, and a logic control unit; the integration unit is connected to the adjustable resistor array module, the charge pump module, and the voltage-to-current conversion unit, respectively, and the oscillation unit is connected to the voltage-to-current conversion unit, the logic control unit, and the charge pump module, respectively.

[0010] The integration unit is used to output a first voltage based on the first current and the second current; the voltage-to-current conversion unit is used to convert the first voltage and output a third current; the oscillation unit is used to output a first oscillation signal and a second oscillation signal based on the third current, the first oscillation signal and the second oscillation signal; the logic control unit is used to output a clock signal and an indication signal based on the first oscillation signal, wherein the indication signal is used to characterize the validity of the clock signal.

[0011] In one possible implementation of the first aspect, the integration unit includes a first operational amplifier and a first capacitor, a first input terminal of the first operational amplifier is connected to a first terminal of the first capacitor, the adjustable resistor array module and the charge pump module, a second input terminal of the first operational amplifier is grounded, and an output terminal of the first operational amplifier is connected to a second terminal of the first capacitor and the voltage-to-current conversion unit.

[0012] In one possible implementation of the first aspect, the voltage-to-current conversion unit includes a second operational amplifier, a trimming resistor, a first transistor, and a first current source. The first input terminal of the second operational amplifier is connected to the source of the first transistor and the first terminal of the trimming resistor, respectively. The second input terminal of the second operational amplifier is connected to the integration unit. The output terminal of the second operational amplifier is connected to the gate of the first transistor. The drain of the first transistor is connected to the first terminal of the first current source and the oscillation unit, respectively. The second terminal of the first current source receives a power supply voltage. The second terminal of the trimming resistor is grounded. The control terminal of the trimming resistor receives a second frequency trimming signal.

[0013] In one possible implementation of the first aspect, the voltage-to-current conversion unit includes a second operational amplifier, a trimming resistor, and a first transistor. The first input terminal of the second operational amplifier is connected to the first terminal of the trimming resistor and the source of the first transistor, respectively. The second input terminal of the second operational amplifier is connected to the integration unit. The output terminal of the second operational amplifier is connected to the gate of the first transistor. The second terminal of the trimming resistor receives a power supply voltage. The control terminal of the trimming resistor receives a second frequency trimming signal. The drain of the first transistor is connected to the oscillation unit.

[0014] In one possible implementation of the first aspect, the oscillation unit includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a second capacitor, a third capacitor, a second current source, a third current source, a first inverter, a second inverter, and an RS flip-flop; the source of the second transistor is connected to the voltage-to-current conversion unit, the gate of the second transistor receives a bias voltage, the drain of the second transistor is connected to the source of the third transistor and the source of the fifth transistor, the gate of the third transistor is connected to the gate of the fourth transistor, the original code output terminal of the RS flip-flop, the logic control unit, and the charge pump module, the drain of the third transistor is connected to the drain of the fourth transistor, the first terminal of the third capacitor, and the gate of the seventh transistor, and the gate of the fifth transistor is connected to the... The gate of the sixth transistor and the inverted code output of the RS flip-flop are connected. The drain of the fifth transistor is connected to the drain of the sixth transistor, the first terminal of the second capacitor, and the gate of the eighth transistor. The first terminal of the second current source and the second terminal of the third current source receive the power supply voltage. The second terminal of the second current source is connected to the drain of the seventh transistor and the input of the first inverter. The second terminal of the third current source is connected to the drain of the eighth transistor and the input of the second inverter. The output of the first inverter is connected to the set terminal of the RS flip-flop. The output of the second inverter is connected to the reset terminal of the RS flip-flop. The source of the fourth transistor, the second terminal of the third capacitor, the second terminal of the second capacitor, the source of the sixth transistor, the source of the seventh transistor, and the source of the eighth transistor are grounded.

[0015] In one possible implementation of the first aspect, the charge pump module includes a first switch, a second switch, a third switch, a fourth switch, and a charge pump capacitor. The first terminal of the first switch is connected to the adjustable resistor array module and the oscillator core module, respectively. The second terminal of the first switch is connected to the first terminal of the second switch and the negative terminal of the charge pump capacitor, respectively. The second terminal of the second switch is grounded. The positive terminal of the charge pump capacitor is connected to the first terminal of the third switch and the first terminal of the fourth switch, respectively. The second terminal of the third switch is grounded. The second terminal of the fourth switch receives a power supply voltage. The control terminals of the second switch and the fourth switch receive a first signal. The control terminals of the first switch and the third switch receive a second signal.

[0016] In one possible implementation of the first aspect, the charge pump module further includes a logic unit, which is connected to the control terminals of the first switch, the second switch, the third switch, the fourth switch, and the oscillator core module, respectively; the logic unit is used to output a first signal and a second signal according to the first oscillation signal.

[0017] Secondly, embodiments of this application provide an electronic device including the oscillation circuit described in any one of the first aspects.

[0018] The beneficial effects of the embodiments in this application compared with the prior art are:

[0019] This application provides an oscillation circuit, including an adjustable resistor array module, a charge pump module, and an oscillator core module; the oscillator core module is connected to the adjustable resistor array module and the charge pump module respectively.

[0020] The adjustable resistor array module is used to output a first current based on a first frequency adjustment signal. The charge pump module is used to output a second current based on a first oscillation signal. The oscillator core module is used to output a first oscillation signal and a clock signal based on the first current and the second current; if the oscillation frequency of the clock signal does not reach the preset frequency, the first frequency adjustment signal is changed to change the first current, thereby making the oscillation frequency reach the preset frequency.

[0021] This application dynamically adjusts the oscillation frequency of the clock signal through a feedback loop (the signal path between the charge pump module and the oscillator core module). Frequency deviation can be dynamically eliminated in the feedback loop, thereby improving the accuracy of the oscillation frequency and ultimately making the oscillation frequency of the clock signal reach a stable state. At the same time, when the oscillation frequency of the clock signal does not reach the preset frequency, the oscillation frequency can also be adjusted through the first frequency adjustment signal to make the oscillation frequency reach the preset frequency.

[0022] In summary, this application combines frequency tuning and closed-loop control of the feedback loop to ensure that the oscillation frequency reaches the preset frequency and remains stable under various operating conditions, ultimately meeting the ±2% accuracy requirements of scenarios such as UART communication.

[0023] It is understandable that the beneficial effects of the second aspect mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of an oscillation circuit provided in an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of an oscillation circuit provided in another embodiment of this application;

[0027] Figure 3 This is the circuit structure diagram of the adjustable resistor array module;

[0028] Figure 4 This is a circuit diagram of a charge pump module;

[0029] Figure 5 This is another circuit diagram of the charge pump module;

[0030] Figure 6 This is the circuit diagram of the integrating unit;

[0031] Figure 7 This is the circuit diagram of the first operational amplifier;

[0032] Figure 8 This is a circuit diagram of a voltage-to-current conversion unit;

[0033] Figure 9 This is another circuit structure diagram of the voltage-to-current conversion unit;

[0034] Figure 10 This is the circuit diagram of the oscillation unit.

[0035] In the diagram: 10. Oscillating circuit; 11. Adjustable resistor array module; 12. Charge pump module; 121. Logic unit; 13. Oscillator core module; 131. Integrating unit; 132. Voltage-to-current conversion unit; 133. Oscillating unit; 134. Logic control unit. Detailed Implementation

[0036] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0037] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0038] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0039] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0040] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0041] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0042] To address the problem that traditional relaxation oscillators, due to their limited accuracy, cannot meet the requirements of UART communication, embodiments of this application provide an oscillation circuit, such as... Figure 1 As shown, the oscillation circuit 10 includes an adjustable resistor array module 11, a charge pump module 12, and an oscillator core module 13; the oscillator core module 13 is connected to the adjustable resistor array module 11 and the charge pump module 12, respectively.

[0043] Specifically, the adjustable resistor array module 11 is used to output a first current I according to the first frequency trimming signal freq_trim(n:1).OUT,rdac The charge pump module 12 is used to output a second current I based on the first oscillation signal OUT. OUT,cp The oscillator core module 13 is used to determine the first current I. OUT,rdac Second current I OUT,cp Output the first oscillation signal OUT and the clock signal CLK_OUT. If the oscillation frequency of the clock signal CLK_OUT is f... osc The preset frequency f was not reached. osc,exp Then, the first frequency trimming signal freq_trim(n:1) is changed to change the first current I. OUT,rdac This leads to an oscillation frequency f osc Reaching the preset frequency f osc,exp In this embodiment, the first frequency trimming signal freq_trim(n:1) is an n-bit trimming signal. By changing the code value corresponding to the n-bit trimming signal, the first frequency trimming signal freq_trim(n:1) can be changed.

[0044] This application uses a feedback loop (the signal path between the charge pump module 12 and the oscillator core module 13) to control the oscillation frequency f of the clock signal CLK_OUT. osc Dynamic adjustments can be made to dynamically eliminate frequency deviations in the feedback loop, thereby increasing the oscillation frequency f. osc The precision ultimately affects the oscillation frequency f of the clock signal CLK_OUT. osc Reaching a stable state; simultaneously, when the oscillation frequency f of the clock signal CLK_OUT... osc The preset frequency f was not reached. osc,exp At the same time, the oscillation frequency f can also be adjusted using the first frequency trimming signal freq_trim(n:1). osc Adjustments are made to make the oscillation frequency f osc Reaching the preset frequency f osc,exp .

[0045] In summary, this application combines frequency tuning with closed-loop control of the feedback loop to achieve the desired oscillation frequency f. osc Reaching the preset frequency f osc,exp It can also ensure that it remains stable under various working conditions, ultimately meeting the ±2% accuracy requirements of scenarios such as UART communication.

[0046] like Figure 2As shown, the core module 13 of the oscillator includes an integration unit 131, a voltage-to-current conversion unit 132, an oscillation unit 133, and a logic control unit 134. The integration unit 131 is connected to the adjustable resistor array module 11, the charge pump module 12, and the voltage-to-current conversion unit 132, respectively. The common terminal of the integration unit 131, the adjustable resistor array module 11, and the charge pump module 12 is called node A. The oscillation unit 133 is connected to the voltage-to-current conversion unit 132, the logic control unit 134, and the charge pump module 12, respectively.

[0047] Specifically, the integrator 131 is used to determine the first current I. OUT,rdac Second current I OUT,cp Output first voltage V ctrl .from Figure 2 As can be seen from this, the first current I OUT,rdac Second current I OUT,cp The two forces act together at node A, and the current I at node A is... SUM =I OUT,rdac -I OUT,cp Integrator 131 based on current I SUM Output first voltage V ctrl The voltage-to-current conversion unit 132 is used to convert the first voltage V ctrl Perform the conversion and output the third current I. VCO The oscillation unit 133 is used to adjust the third current I. VCO The system outputs a first oscillation signal OUT and a second oscillation signal OUTB. The logic control unit 134 outputs a clock signal CLK_OUT and an indication signal CLK_OK based on the first oscillation signal OUT. The indication signal CLK_OK is used to characterize the validity of the clock signal CLK_OUT. It should be noted that immediately after the oscillation circuit 10 is powered on, its oscillation frequency f... osc With preset frequency f osc,exp Due to a significant error, the output clock signal CLK_OUT is unstable. Therefore, an indicator signal CLK_OK is needed to characterize the validity of the clock signal CLK_OUT. In this embodiment, the clock signal CLK_OUT reaches a stable state when the indicator signal CLK_OK goes high.

[0048] like Figure 3 As shown, the adjustable resistor array module 11 includes n+1 resistors R 01 ,R 11 ,……,R n1 n-1 resistors R 02 ,R 12 ,……,R (n-2)2There are n switches, where n is a natural number greater than 2, and n-1 resistors R. 02 ,R 12 ,……,R (n-2)2 series in series, resistor R (n-2)2 The first terminal and resistor R n1 The first terminal receives the power supply voltage VDD, and the i-th resistor R i1 The first end is connected to resistor R (i-1)2 With resistance R (i-2)2 The common terminal, 2≤i≤n-1, resistor R 02 The second terminal is connected to resistor R respectively 11 The first terminal and resistor R 01 The first terminal is connected to resistor R. 11 ,R 21 ,……,R n1 The second terminal is connected to the first terminal of each of the n switches, and the resistor R 01 The second terminal is connected to the second terminals of the charge pump module 12, the oscillator core module 13 and n switches respectively. The third terminal of the n switches is grounded. The control terminal of the n switches receives the first frequency trimming signal freq_trim(n:1).

[0049] Specifically, n+1 resistors R 01 ,R 11 ,……,R n1 The resistance is 2R, and there are n-1 resistors R. 02 ,R 12 ,……,R (n-2)2 The resistance is R. The first frequency trimming signal freq_trim(n:1) controls n switches to be grounded or connected to the output first current I. OUT,rdac On the wire. When the i-th trimming signal in the first frequency trimming signal freq_trim(n:1) is high, the i-th switch in the adjustable resistor array module 11 is connected to the output first current I. OUT,rdac On the wire, the i-th switch is connected to the ground, and vice versa. In this way, the output resistance R of the adjustable resistor array module 11 can be changed. OUT,dac resistance r OUT,dac This changes the first current I. OUT,rdac .

[0050] For example, when the first trimming signal in the first frequency trimming signal freq_trim(n:1) is high and the remaining n-1 trimming signals are low, the first switch in the adjustable resistor array module 11 is connected to the output first current I. OUT,rdac On the conductor, the remaining n-1 switches are grounded.

[0051] Output resistance R OUT,dac resistance rOUT,dac =R 11 / / R 01 +R*(n-1)=R*n;

[0052] When all n bits of the first frequency trimming signal freq_trim(n:1) are high, the output resistor R OUT,dac resistance r OUT,dac =R, at this time the output resistance R OUT,dac resistance r OUT,dac Minimum.

[0053] When all n bits of the first frequency trimming signal freq_trim(n:1) are low, the output resistor R OUT,dac resistance r OUT,dac =R(n+1), at this time the output resistance R OUT,dac resistance r OUT,dac maximum.

[0054] like Figure 4 As shown, the charge pump module 12 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and a charge pump capacitor C. cp The first terminal of the first switch S1 is connected to the adjustable resistor array module 11 and the oscillator core module 13 respectively, and the second terminal of the first switch S1 is connected to the first terminal of the second switch S2 and the charge pump capacitor C respectively. cp The negative terminal of the first switch is connected, the second terminal of the second switch S2 is grounded, and the charge pump capacitor C... cp The positive terminals are connected to the first terminals of the third switch S3 and the fourth switch S4, respectively. The second terminal of the third switch S3 is grounded. The second terminal of the fourth switch S4 receives the power supply voltage VDD. The control terminals of the first switch S1 and the third switch S3 receive the second signal P2. The control terminals of the second switch S2 and the fourth switch S4 receive the first signal P1.

[0055] Specifically, the charge pump module 12 has two operating modes: when the first signal P1 is high and the second signal P2 is low, the second switch S2 and the fourth switch S4 are turned on, the first switch S1 and the third switch S3 are turned off, and the charge pump capacitor C... cp The positive terminal receives the power supply voltage VDD, the negative terminal is grounded, and the charge pump capacitor C... cp It is charged and gains a charge Q during this stage, Q = c cp *VDD; where c cp For charge pump capacitor C cp The capacitance value.

[0056] When the first signal P1 is low and the second signal P2 is high, the second switch S2 and the fourth switch S4 are open, and the first switch S1 and the third switch S3 are closed. The charge pump capacitor C... cp The positive terminal is grounded, and the charge pump capacitor C cp The negative terminals are connected to the adjustable resistor array module 11 and the oscillator core module 13, respectively, and the charge pump capacitor C cp The charge is discharged, releasing a charge Q during this phase. During this phase, the charge pump capacitor C... cp When the positive terminal voltage changes abruptly from VDD to 0, its negative terminal voltage changes abruptly from 0 to -VDD.

[0057] Current I at node A SUM =I OUT,rdac -I OUT,cp The voltage at node A is affected by the opposing forces of the adjustable resistor array module 11 and the charge pump module 12. The adjustable resistor array module 11 attempts to pull the voltage at node A to VDD, while the charge pump module 12 attempts to pull the voltage at node A to -VDD.

[0058] First current I OUT,rdac Second current I OUT,cp The expressions for are shown in equations (1) and (2) respectively:

[0059] I OUT,rdac =VDD / r OUT,dac (1);

[0060] I OUT,cp =f osc *c cp *VDD (2);

[0061] Due to the first current I OUT,rdac Second current I OUT,cp All are proportional to VDD, therefore the oscillation circuit 10 is not sensitive to fluctuations in the power supply voltage VDD.

[0062] The oscillation circuit 10 maintains the oscillation frequency f of the clock signal CLK_OUT through a feedback loop (the signal path between the charge pump module 12 and the oscillator core module 13). osc It is in a stable state. If the oscillation frequency f osc The feedback loop will reduce the oscillation frequency f. osc Rise until I OUT,cp =I OUT,rdac Make the oscillation frequency f osc It is in a stable state. At the oscillation frequency f osc When in a steady state, I OUT,cp =I OUT,rdac Based on equations (1) and (2), we can conclude that:

[0063] f osc =1 / (r OUT,dac *c cp (3);

[0064] From equation (3), we can see that the oscillation frequency f osc With output resistance R OUT,dac resistance r OUT,dac and charge pump capacitor C cp The capacitance value c cp Related. If the oscillation frequency f osc The expected frequency f was not reached. osc，exp This can be achieved by changing the output resistance R. OUT,dac resistance r OUT,dac (that is, change the first frequency trimming signal freq_trim(n:1)) to make the oscillation frequency f osc Reaching the expected frequency f osc，exp This ensures that the accuracy of the oscillation circuit 10 meets the ±2% accuracy requirement for scenarios such as UART communication.

[0065] like Figure 5 As shown, the charge pump module 12 also includes a logic unit 121, which is connected to the control terminals of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, and the oscillator core module 13.

[0066] Specifically, the operating mode of the charge pump module 12 is controlled by the first oscillation signal OUT output by the oscillator core module 13. More specifically, the logic unit 121 in the charge pump module 12 is used to output a first signal P1 and a second signal P2 based on the first oscillation signal OUT. Depending on the states of the first signal P1 and the second signal P2, the charge pump module 12 can operate in either of the aforementioned operating modes.

[0067] like Figure 6 As shown, the voltage-to-current conversion unit 132 includes a first operational amplifier AMP1 and a first capacitor C1. The first input terminal of the first operational amplifier AMP1 is connected to the first terminal of the first capacitor C1, the adjustable resistor array module 11, and the charge pump module 12, respectively. The second input terminal of the first operational amplifier AMP1 is grounded, and the output terminal of the first operational amplifier AMP1 is connected to the second terminal of the first capacitor C1 and the voltage-to-current conversion unit 132, respectively. In this embodiment, the first input terminal of the first operational amplifier AMP1 is a negative input terminal, and the second input terminal is a positive input terminal.

[0068] Specifically, the integration unit 131 is essentially an integrator, used to convert the current I at node A into an integrator. SUM Converted to the first voltage V ctrlFor an ideal integrator, the following transfer function exists, as shown in equation (4):

[0069] I SUM =1 / (Sc1)*V ctrl (4);

[0070] Where c1 is the capacitance of the first capacitor C1, and S is the Laplace operator.

[0071] The oscillator circuit 10 maintains the oscillation frequency f of the clock signal CLK_OUT through a feedback loop (the signal path between the charge pump module 12 and the oscillator core module 13). osc It is in a stable state. According to formula (2), the second current I... OUT,cp With oscillation frequency f osc Proportional. If the oscillation frequency f osc Decrease, second current I OUT,cp This will decrease accordingly, leading to I OUT,rdac >I OUT,cp At this point, node A will draw current from the integrator, causing current I to... SUM This reduces the first voltage V. ctrl Reduce. It should be noted that, in the design of the voltage-to-current conversion unit 132 and the oscillation unit 133, the first voltage V should be guaranteed. ctrl With oscillation frequency f osc Inversely proportional. Thus, at the first voltage V... ctrl When the frequency decreases, the oscillation frequency f osc The frequency will increase accordingly, and the change in frequency will be fed back to the second current I. OUT,cp , causing the second current I OUT,cp Rise until I OUT,cp =I OUT,rdac Eventually, a stable state is reached.

[0072] Figure 7The circuit diagram of the first operational amplifier AMP1 is shown. AMP1 is a class AB operational amplifier, including a fourth current source IS4, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, and a twentieth transistor M20. The ninth transistor M9 and the tenth transistor M10 form a differential input pair, serving as the two input terminals of the first operational amplifier AMP1. The fourth current source IS4 provides bias current to the differential pair, and this current source is composed of a cascode current mirror. The eleventh transistor, M11, acts as the active load for the ninth transistor, M9. Together with the twelfth and thirteenth transistors, M12 and M13, it effectively converts the current changes of the differential input pair into voltage changes, providing a suitable input signal for the subsequent intermediate stage (i.e., the common-source amplifier stage where the twentieth transistor, M20, is located). This ensures that the entire circuit can effectively amplify the input differential signal. The fourteenth and fifteenth transistors, M14 and M15, form a current mirror, providing bias current for the output stage. The sixteenth, seventeenth, eighteenth, and nineteenth transistors, M16, M17, M18, and M19, form a push-pull output structure, which has advantages such as high driving capability and high efficiency.

[0073] like Figure 8 As shown, the voltage-to-current conversion unit 132 includes a second operational amplifier AMP2 and a trimming resistor R. VCO The first transistor M1 and the first current source IS1, and the first input terminal of the second operational amplifier AMP2 are respectively connected to the source of the first transistor M1 and the adjustment resistor R. VCO The first terminal is connected to the first terminal of the second operational amplifier AMP2, the second input terminal of the second operational amplifier AMP2 is connected to the integration unit 131, the output terminal of the second operational amplifier AMP2 is connected to the gate of the first transistor M1, the drain of the first transistor M1 is connected to the first terminal of the first current source IS1 and the oscillation unit 133, the second terminal of the first current source IS1 receives the power supply voltage VDD, and the adjustment resistor R... VCO The second terminal is grounded, and the adjusting resistor R is adjusted. VCO The control terminal receives the second frequency trimming signal VCO_trim. The circuit structure of the second operational amplifier AMP2 is similar to that of the first operational amplifier AMP1, except that its output structure adopts a CLASSA structure. It should be noted that in this structure, the first transistor M1 is an NMOS transistor. In this embodiment, the first input terminal of the second operational amplifier AMP2 is a negative input terminal, and the second input terminal is a positive input terminal.

[0074] Specifically, the second operational amplifier AMP2 and the first transistor M1 form a negative feedback loop. Due to the virtual short circuit of the operational amplifier, the first voltage V... ctrl With the source voltage V of the first transistor M1 ctrl,vco If they are approximately equal, then the third current I can be obtained. VCO The expression:

[0075] I VCO =i1-V ctrl,vco / r VCO =i1-V ctrl / r VCO (5);

[0076] Where i1 is the current output by the first current source IS1, and r VCO To adjust resistor R VCO The resistance value. From equation (5), it can be seen that the third current I... VCO With the first voltage V ctrl Inversely proportional.

[0077] Since the first current source IS1 is composed of a common-source cascode current mirror, its power supply suppression is relatively good, and it is typically used in practical applications. Figure 8 The structure shown.

[0078] The voltage-to-current conversion unit 132 also has another circuit structure, such as Figure 9 As shown, the voltage-to-current conversion unit 132 includes a second operational amplifier AMP2 and a trimming resistor R. VCO The first input terminal of the first transistor M1 and the second operational amplifier AMP2 are respectively connected to the adjustment resistor R. VCO The first terminal is connected to the source of the first transistor M1, the second input terminal of the second operational amplifier AMP2 is connected to the integration unit 131, the output terminal of the second operational amplifier AMP2 is connected to the gate of the first transistor M1, and the adjustment resistor R... VCO The second terminal receives the power supply voltage VDD, and the adjustment resistor R VCO The control terminal receives the second frequency tuning signal VCO_trim, and the drain of the first transistor M1 is connected to the oscillation unit 133. It should be noted that in this structure, the first transistor M1 is a PMOS transistor.

[0079] Specifically, the second operational amplifier AMP2 and the first transistor M1 form a negative feedback loop. Due to the virtual short circuit of the operational amplifier, the first voltage V... ctrl With the source voltage V of the first transistor M1 ctrl,vco If they are approximately equal, then the third current I can be obtained. VCO The expression:

[0080] I VCO =(VDD-Vctrl,vco ) / r VCO =(VDD-V ctrl ) / r VCO (6);

[0081] From equation (6), it can be concluded that when the power supply voltage VDD fluctuates, I VCO It will also change, and the power supply suppression of this structure is relatively poor. Meanwhile, as can be seen from equation (6), the third current I... VCO With the first voltage V ctrl Inversely proportional.

[0082] like Figure 10 As shown, the oscillation unit 133 includes a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a second capacitor C2, a third capacitor C3, a second current source IS2, a third current source IS3, a first inverter INV1, a second inverter INV2, and an RS flip-flop. The source of the second transistor M2 is connected to the voltage-to-current conversion unit 132, and the gate of the second transistor M2 receives the bias voltage VCAS. The drain of the second transistor M2 is connected to the source of the third transistor M3 and the source of the fifth transistor M5. The gate of the third transistor M3 is connected to the gate of the fourth transistor M4, the original code output terminal Q of the RS flip-flop, the logic control unit 134, and the charge pump module 12. The drain of the third transistor M3 is connected to the drain of the fourth transistor M4, the first terminal of the third capacitor C3, and the gate of the seventh transistor M7. The gate of the fifth transistor M5 is connected to the gate of the sixth transistor M6 and the inverted code output terminal of the RS flip-flop. The fifth transistor M5 is connected to the drain of the sixth transistor M6, the first terminal of the second capacitor C2, and the gate of the eighth transistor M8. The first terminal of the second current source IS2 and the second terminal of the third current source IS3 receive the power supply voltage VDD. The second terminal of the second current source IS2 is connected to the drain of the seventh transistor M7 and the input terminal of the first inverter INV1. The second terminal of the third current source IS3 is connected to the drain of the eighth transistor M8 and the input terminal of the second inverter INV2. The output terminal of the first inverter INV1 is connected to the set terminal S of the RS flip-flop, and the output terminal of the second inverter INV2 is connected to the reset terminal R of the RS flip-flop. The source of the fourth transistor M4, the second terminal of the third capacitor C3, the second terminal of the second capacitor C2, the source of the sixth transistor M6, the source of the seventh transistor M7, and the source of the eighth transistor M8 are grounded. The third transistor M3 and the fourth transistor M4 constitute an inverter, which is controlled by the first oscillation signal OUT. The fifth transistor M5 and the sixth transistor M6 form an inverter, which is controlled by the second oscillation signal OUTB. The second current source IS2 and the third current source IS3 are both composed of common-source cascode current mirrors.

[0083] Specifically, assuming that in the first stage, initially, the first oscillation signal OUT is high, the second oscillation signal OUTB is low, the first inverter INV1 outputs a low level, the second inverter INV2 outputs a high level, and the fifth transistor M5 is turned on. After the fifth transistor M5 is turned on, the third current I... VCO The second capacitor C2 is charged, while the third capacitor C3 is discharged. The seventh transistor M7 is turned off, causing the first inverter INV1 to output a low level. When the voltage on the second capacitor C2 rises to the threshold voltage Vth of the eighth transistor M8, the eighth transistor M8 turns on, its drain voltage decreases, causing the second inverter INV2 to output a high level. The RS flip-flop is reset, causing the first oscillation signal OUT to go low and the second oscillation signal OUTB to go high. The first stage ends, and the second stage begins. The above process is reversed: the output of the first inverter INV1 goes high, the output of the second inverter INV2 goes low, and the third transistor M3 turns on. After the third transistor M3 turns on, the third capacitor C3 is charged by the third current I. VCO While the capacitor C2 is charging, the second capacitor C2 is discharging, and the eighth transistor M8 is turned off, causing the output of the second inverter INV2 to go low. When the voltage on the third capacitor C3 rises to the threshold voltage Vth of the seventh transistor M7, the seventh transistor M7 turns on, its drain voltage decreases, causing the output of the first inverter INV1 to go high, the RS flip-flop to be set, making the first oscillation signal OUT go high and the second oscillation signal OUTB go low. This cycle repeats, generating a fixed period T on the first oscillation signal OUT and the second oscillation signal OUTB.osc A square wave signal with a fixed period T osc The oscillation frequency f osc The reciprocal of the value. To ensure that the duty cycle of the clock signal CLK_OUT is 50%, the capacitance of the second capacitor C2 should be equal to the capacitance of the third capacitor C3.

[0084] Assuming that the capacitance of the second capacitor C2 and the third capacitor C3 are both c, based on the above principle, we can deduce that:

[0085] Vth = I VCO *0.5*T osc / c=I VCO *0.5 / (f osc *c) (7);

[0086] Since the threshold voltage Vth is fixed, therefore I VCO with f osc It is directly proportional. According to equation (6), V ctrl with I VCO Inversely proportional; and because I VCO with f osc Positive correlation, therefore V ctrl with f osc They are inversely proportional. This relationship ensures that the frequency-voltage coefficient of the oscillator core module 13 is negative, thus enabling the oscillation frequency f to be achieved through the feedback loop. osc The goal is stability.

[0087] This application combines frequency tuning with closed-loop control of the feedback loop (the signal path between the charge pump module 12 and the oscillator core module 13) to achieve the desired oscillation frequency f. osc Reaching the preset frequency f osc,exp This ensures stability under various operating conditions, ultimately meeting the ±2% accuracy requirements of scenarios such as UART communication. It should be noted that, in addition to frequency tuning via the first frequency tuning signal freq_trim(n:1), this application also employs another frequency tuning method: after the oscillation circuit 10 is powered on, the first input terminal (i.e., the negative input terminal) of the first operational amplifier AMP1 in the integration unit 131 is disconnected from node A and connected to the output terminal of the first operational amplifier AMP1. The second input terminal (i.e., the positive input terminal) of the first operational amplifier AMP1 receives the expected operating voltage V. exp This forms a unity negative feedback. The output of the first operational amplifier AMP1 remains connected to the second input (i.e., the positive input) of the second operational amplifier AMP2. At this time, the voltage-to-current conversion unit 132 (here, AMP2) is adjusted using the second frequency tuning signal VCO_trim. Figure 8 The adjustment resistor R (using the structure shown as an example) VCOAdjust the frequency f to achieve the desired oscillation frequency. osc Approximately the preset frequency f osc,exp When the oscillation frequency f osc Approximately the preset frequency f osc,exp At this time, the second operational amplifier AMP2 will be in a suitable operating state, in which:

[0088] V ctrl,vco =V exp (8);

[0089] I VCO =i1-V ctrl,vco / r VCO =i1-V exp / r VCO (9);

[0090] Vth = I VCO *0.5 / (f osc,exp *c) (10);

[0091] This frequency tuning method can prevent V ctrl and V ctrl,vco Deviation from V exp This avoids problems with the closed-loop operation of the oscillation circuit 10. After this adjustment step is completed, the first input terminal of the first operational amplifier AMP1 is connected to node A, and the second input terminal of the first operational amplifier AMP1 is grounded; according to equation (3), the output resistor R is adjusted by the first frequency adjustment signal freq_trim(n:1). OUT,dac resistance r OUT,dac Adjustments are made to the oscillation frequency f. osc After adjustment, the oscillation frequency f was finally made... osc Reaching the expected frequency f osc,exp When the oscillation frequency f osc Reaching the expected frequency f osc,exp Afterwards, the operating state of the second operational amplifier AMP2 remains close to its state after the first adjustment. This ensures that the oscillation frequency f of the oscillation circuit 10 is maintained. osc When the expected frequency f is reached osc,exp Each module can then be in a suitable working state, thereby ensuring the stable operation of the circuit.

[0092] As can be seen from the above, the oscillation circuit 10 proposed in this application uses a dual-tuning method to tune the oscillation frequency f. osc And ensure the oscillation frequency f osc Change the normal operating state of the oscillation circuit 10 before and after. When the oscillation frequency f needs adjustment... oscFirst, the oscillator circuit 10 is switched to open-loop mode (that is, the first input terminal of the first operational amplifier AMP1 is disconnected from node A and connected to the output terminal of the first operational amplifier AMP1, and the second input terminal of the first operational amplifier AMP1 receives the expected operating voltage V). exp The second frequency trimming signal VCO_trim is used to adjust the trimming resistor R. VCO Adjustments were made to make the oscillation frequency f in this mode. osc Approximately the preset frequency f osc,exp At this time, the "input voltage" of the voltage-to-current conversion unit 132 remains within the appropriate range (i.e., it will not deviate from the expected operating voltage V). exp This ensures that the oscillation frequency f is adjusted in closed-loop mode. osc The oscillator circuit 10 operates normally. Then, in closed-loop mode (connecting the first input terminal of the first operational amplifier AMP1 to node A and grounding the second input terminal of the first operational amplifier AMP1), the resistance value of the adjustable resistor array module 11 is adjusted using the first frequency adjustment signal freq_trim(n:1), thereby affecting the first current I. OUT,rdac The oscillation frequency f is then affected by the actions of the integrator 131, the voltage-to-current conversion unit 132, and the oscillation unit 133. osc The second current I is then adjusted through the feedback loop (the signal path between the charge pump module 12 and the oscillator core module 13). OUT,cp The magnitude of the oscillation frequency f after the oscillation circuit 10 has stabilized. osc Ultimately determined by the output resistor R OUT,dac resistance r OUT,dac and charge pump capacitor C cp The capacitance value c cp The decision is made. Therefore, the oscillation frequency f osc It can be adjusted to the preset frequency f osc,exp Meanwhile, the oscillation circuit 10 provided in this application embodiment employs resistors and capacitors with low temperature drift and low process fluctuation, thereby ensuring that temperature and process deviations do not significantly affect the oscillation frequency f. osc The impact is limited.

[0093] In summary, this application uses a dual-frequency tuning method to adjust the oscillation frequency f. osc The error is controlled within ±2%; simultaneously, the oscillation frequency f is ensured through closed-loop control of the feedback loop. osc It can remain stable under various operating conditions.

[0094] This application also provides an electronic device including the oscillation circuit described above. Since the electronic device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here. The electronic device provided in this application can be any electronic device including the oscillation circuit described above.

[0095] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0096] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An oscillation circuit, characterized in that, It includes an adjustable resistor array module, a charge pump module, and an oscillator core module; the oscillator core module is connected to the adjustable resistor array module and the charge pump module, respectively. The adjustable resistor array module is used to output a first current according to a first frequency adjustment signal; The charge pump module is used to output a second current according to the first oscillation signal; the oscillator core module is used to output a first oscillation signal and a clock signal according to the first current and the second current; the second current is adjusted through the feedback loop between the charge pump module and the oscillator core module, thereby adjusting the oscillation frequency of the clock signal so that the oscillation frequency of the clock signal reaches a preset frequency; If the oscillation frequency of the clock signal does not reach the preset frequency, the first frequency adjustment signal is changed to change the first current, thereby making the oscillation frequency reach the preset frequency. The first frequency adjustment signal is an n-bit adjustment signal. The first frequency adjustment signal is changed by changing the code value corresponding to the n-bit adjustment signal. The core module of the oscillator includes an integration unit, a voltage-to-current conversion unit, an oscillation unit, and a logic control unit; the integration unit is connected to the adjustable resistor array module, the charge pump module, and the voltage-to-current conversion unit, respectively, and the oscillation unit is connected to the voltage-to-current conversion unit, the logic control unit, and the charge pump module, respectively. The integration unit is used to output a first voltage based on the first current and the second current; the voltage-to-current conversion unit is used to convert the first voltage and output a third current; the oscillation unit is used to output a first oscillation signal and a second oscillation signal based on the third current, a first oscillation signal, and a second oscillation signal; the logic control unit is used to output a clock signal and an indication signal based on the first oscillation signal, wherein the indication signal is used to characterize the validity of the clock signal; The oscillation frequency of the clock signal is related to the resistance value of the output resistor of the adjustable resistor array module. The first current is determined by the resistance value of the output resistor of the adjustable resistor array module. Changing the first frequency adjustment signal changes the resistance value of the output resistor of the adjustable resistor array module, thereby changing the first current and ultimately changing the oscillation frequency.

2. The oscillation circuit according to claim 1, characterized in that, The adjustable resistor array module includes n+1 resistors R 01 ,R 11 ,……,R n1 n-1 resistors R 02 ,R 12 ,……,R （n-2）2 and n switches, where n is a natural number greater than 2; n-1 resistors R 02 ,R 12 ,……,R （n-2）2 series in series, resistor R （n-2）2 The first terminal and resistor R n1 The first terminal receives the power supply voltage, and the i-th resistor R i1 The first end is connected to resistor R （i-1）2 With resistance R （i-2）2 The common terminal, 2≤i≤n-1, resistor R 02 The second terminal is connected to resistor R respectively 11 The first terminal and resistor R 01 The first terminal is connected to resistor R. 11 ,R 21 ,……,R n1 The second terminal is connected to the first terminal of each of the n switches, and the resistor R 01 The second terminal is connected to the second terminal of the charge pump module, the oscillator core module, and the n switches respectively. The third terminal of the n switches is grounded, and the control terminal of the n switches receives the first frequency adjustment signal.

3. The oscillation circuit according to claim 1, characterized in that, The integration unit includes a first operational amplifier and a first capacitor. The first input terminal of the first operational amplifier is connected to the first terminal of the first capacitor, the adjustable resistor array module, and the charge pump module, respectively. The second input terminal of the first operational amplifier is grounded, and the output terminal of the first operational amplifier is connected to the second terminal of the first capacitor and the voltage-to-current conversion unit, respectively.

4. The oscillation circuit according to claim 1, characterized in that, The voltage-to-current conversion unit includes a second operational amplifier, a trimming resistor, a first transistor, and a first current source. The first input terminal of the second operational amplifier is connected to the source of the first transistor and the first terminal of the trimming resistor. The second input terminal of the second operational amplifier is connected to the integration unit. The output terminal of the second operational amplifier is connected to the gate of the first transistor. The drain of the first transistor is connected to the first terminal of the first current source and the oscillation unit. The second terminal of the first current source receives the power supply voltage. The second terminal of the trimming resistor is grounded. The control terminal of the trimming resistor receives a second frequency trimming signal.

5. The oscillation circuit according to claim 1, characterized in that, The voltage-to-current conversion unit includes a second operational amplifier, a trimming resistor, and a first transistor. The first input terminal of the second operational amplifier is connected to the first terminal of the trimming resistor and the source of the first transistor, respectively. The second input terminal of the second operational amplifier is connected to the integration unit. The output terminal of the second operational amplifier is connected to the gate of the first transistor. The second terminal of the trimming resistor receives the power supply voltage. The control terminal of the trimming resistor receives a second frequency trimming signal. The drain of the first transistor is connected to the oscillation unit.

6. The oscillation circuit according to claim 1, characterized in that, The oscillation unit includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a second capacitor, a third capacitor, a second current source, a third current source, a first inverter, a second inverter, and an RS flip-flop. The source of the second transistor is connected to the voltage-to-current conversion unit, the gate of the second transistor receives a bias voltage, the drain of the second transistor is connected to the source of the third transistor and the source of the fifth transistor, the gate of the third transistor is connected to the gate of the fourth transistor, the original code output terminal of the RS flip-flop, the logic control unit, and the charge pump module, the drain of the third transistor is connected to the drain of the fourth transistor, the first terminal of the third capacitor, and the gate of the seventh transistor, and the gate of the fifth transistor is connected to the gate of the sixth transistor. The gate of the transistor is connected to the inverted code output of the RS flip-flop. The drain of the fifth transistor is connected to the drain of the sixth transistor, the first terminal of the second capacitor, and the gate of the eighth transistor. The first terminal of the second current source and the second terminal of the third current source receive the power supply voltage. The second terminal of the second current source is connected to the drain of the seventh transistor and the input of the first inverter. The second terminal of the third current source is connected to the drain of the eighth transistor and the input of the second inverter. The output of the first inverter is connected to the set terminal of the RS flip-flop. The output of the second inverter is connected to the reset terminal of the RS flip-flop. The source of the fourth transistor, the second terminal of the third capacitor, the second terminal of the second capacitor, the source of the sixth transistor, the source of the seventh transistor, and the source of the eighth transistor are grounded.

7. The oscillation circuit according to claim 1 or 2, characterized in that, The charge pump module includes a first switch, a second switch, a third switch, a fourth switch, and a charge pump capacitor. The first terminal of the first switch is connected to the adjustable resistor array module and the oscillator core module, respectively. The second terminal of the first switch is connected to the first terminal of the second switch and the negative terminal of the charge pump capacitor, respectively. The second terminal of the second switch is grounded. The positive terminal of the charge pump capacitor is connected to the first terminal of the third switch and the first terminal of the fourth switch, respectively. The second terminal of the third switch is grounded. The second terminal of the fourth switch receives a power supply voltage. The control terminals of the second switch and the fourth switch receive a first signal. The control terminals of the first switch and the third switch receive a second signal.

8. The oscillation circuit according to claim 7, characterized in that, The charge pump module further includes a logic unit, which is connected to the control terminals of the first switch, the second switch, the third switch, the fourth switch, and the oscillator core module, respectively; the logic unit is used to output a first signal and a second signal according to the first oscillation signal.

9. An electronic device, characterized in that, Includes the oscillation circuit described in any one of claims 1-8.

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