Silicon-based perception-storage integrated chip and preparation method thereof

Abstract

The invention discloses a silicon-based sensing-storage integrated chip which is formed by integrating a silicon-based sensor array and a memory array from top to bottom in the vertical direction. The silicon-based sensor array is positioned at the upper part, and the input end of the silicon-based sensor array is used as the input end of the chip to receive an incident light signal; the memory array is located at the lower part, the input end of the memory array is connected with the output end of the sensor array through a process integration mode, and the output end serves as the output end of the chip. The invention also discloses a preparation method of the integrated chip. The preparation method comprises the following steps of: performing a front process: injecting a protection ring, injecting a photosensitive surface, and preparing an antireflection film structure and a front electrode; and back process: preparing the output end of the sensor, preparing a dielectric material-electrode on the output end of the sensor, and forming a memory array layer through photoetching. The sensor array layer and the memory array layer are integrated in the vertical direction, the whole technological process is compatible with the silicon technology, and the sensor array layer and the memory array layer have important scientific significance and wide application prospects for promoting the development of sensing, memory and computing integrated chips.

Description

Technical Field

[0001] This invention relates to a silicon-based integrated sensing-storage chip and its fabrication method, belonging to the field of visual sensing chip technology. Background Technology

[0002] Industry research data shows that the global artificial intelligence (AI) chip market exceeded $57 billion in 2024 and is projected to grow to $400 billion by 2027. Despite the surging demand for AI chips year after year, the current market size of AI vision processing chips accounts for only about 1.4% of the AI ​​chip market, significantly lagging behind the overall industry development. The main reason for the slow development of the AI ​​vision processing chip industry is that its core vision perception chips still use a traditional chip architecture that separates the sensor, memory, and processor, gradually revealing drawbacks such as high latency and high power consumption, failing to meet the high-efficiency processing requirements of massive visual data in advanced visual intelligence applications. Developing low-power, polymorphic, and scalably integrate silicon-based sensing-in-memory computing chips to shorten data transmission distances and reduce data transfer is an inevitable way to solve this problem.

[0003] Currently, integrated sensing-memory-computing chips mainly fall into two categories: one is integrated sensing-memory devices, which are still in their early stages. Although small-scale recognition tasks have been achieved, issues such as complex material systems, unclear mechanisms, and incompatible processes remain to be resolved. The other is integrated sensing-memory systems, which, compared to integrated sensing-memory devices, have the significant advantages of clear design paths, simple working mechanisms, and a structure that is closer to the human visual perception system. However, integrated sensing-memory-computing chips still face key challenges such as incompatibility between device processes and silicon-based process platforms, and the difficulty in integrating the chips with existing silicon-based functional layers. Summary of the Invention

[0004] The purpose of this invention is to overcome the aforementioned shortcomings and provide a silicon-based integrated sensing-memory chip and its fabrication method. This invention solves the technical problems of small effective light-receiving area (i.e., large dead zone), low integration density, small array size, and incompatibility between material systems and silicon processes. This invention achieves vertical integration of the sensor layer and memory layer, with the entire process compatible with silicon processes. It has significant scientific importance and broad application prospects for promoting the development of integrated sensing-memory-computing chips.

[0005] To achieve the above-mentioned objectives, the present invention provides the following technical solution:

[0006] This invention provides a positive illumination silicon-based integrated sensing and storage chip. The integrated chip is fabricated by integrating a silicon-based sensor array layer and a memory array layer through a process integration method. The chip has a vertical structure as a whole, and the entire chip fabrication process is compatible with silicon-based processes.

[0007] A silicon-based sensing-storage integrated chip is constructed by integrating a silicon-based sensor array and a memory array vertically from top to bottom. The silicon-based sensor array is located at the top of the integrated chip, and its input terminal serves as the chip's input terminal for receiving incident light signals. The memory array is located at the bottom of the integrated chip, and its input terminal is connected to the output terminal of the sensor array via a process integration method. Its output terminal serves as the chip's output terminal.

[0008] The working principle of a silicon-based sensing-storage integrated chip is that a silicon-based sensor array receives incident light signals and converts them into electrical signals. The electrical signals then drive a memory array to achieve signal storage.

[0009] Furthermore, silicon-based sensor arrays contain hundreds of thousands to tens of thousands of unit sensing devices;

[0010] Each unit sensing device has a traditional PN two-terminal device structure, including an input terminal, an absorption layer, and an output terminal.

[0011] Furthermore, the input terminal of the sensing device is used to receive the incident light signal, and its structure includes a doping concentration of 1E19cm⁻¹. -3 ~1E21 cm -3 The ohmic contact electrode can be p-type or n-type doped; including doping concentrations of 1E12 cm⁻¹. -3 ~1E19 cm -3 The photosensitive surface has a contact electrode located within the photosensitive surface region; it includes an antireflection coating layer, which can reduce the reflectivity of the sensor to light wavelengths in the range of 200nm to 1800nm, thereby improving the absorption characteristics of the sensing device for incident light.

[0012] Furthermore, the resistivity of the absorber layer material is 100 Ω·cm to 10000 Ω·cm on a silicon substrate.

[0013] Antireflective coatings can be single-layer films composed of one of the following: silicon oxide, silicon nitride, aluminum oxide, zinc sulfide, hafnium oxide, magnesium oxide, and zinc sulfide; or they can be multi-layer films composed of several of these materials.

[0014] Furthermore, the output of the sensing device is doped with a concentration of 1E19 cm⁻¹. -3 ~1E21 cm -3 The ohmic contact electrode can be N-type or P-type, with the doping polarity opposite to that of the input terminal.

[0015] Furthermore, the memory array layer contains hundreds of thousands to tens of thousands of memory devices, each corresponding to a sensor unit.

[0016] The memory has a traditional vertical structure with "electrode-dielectric material-electrode" at both ends; when the sensor output terminal acts as an electrode, its structure can also be a vertical structure with "dielectric material-electrode".

[0017] The dielectric material includes one or more of oxide materials, phase change materials, or ferromagnetic materials;

[0018] Oxide materials include aluminum oxide, titanium oxide, nitric oxide, zinc oxide, tantalum oxide, or their doped or modified oxide materials;

[0019] Phase change materials include GeSbTe, SbTe, GeTe, and GeSb phase change materials or their doped and modified forms, which are mainly composed of germanium, antimony, and tellurium.

[0020] Ferromagnetic materials include barium lead oxide, lithium niobate, zirconium titanate, lead calcium titanium zirconate titanate, hafnium oxide, zirconium hafnium oxide, yttrium hafnium oxide, zinc oxide, iron, cobalt, nickel, ferrite or doped ferromagnetic materials;

[0021] The dielectric material structure can be a single-layer thin film made of one material or a multi-layer thin film made of multiple materials.

[0022] The above-mentioned method for fabricating a silicon-based sensing-storage integrated chip includes:

[0023] S1 performs cleaning and initial oxidation on the silicon substrate.

[0024] S2 front-side process: Protective ring fabrication, the protective ring area is photolithographically etched on the surface of the silicon substrate and then etched;

[0025] S3 ion implantation, implantation energy 50–100 keV, implantation dose 5E14–5E16 cm⁻¹ -2 Complete the fabrication of the protective ring;

[0026] S4 front-side process: Photosensitive surface fabrication, photolithography of the photosensitive surface area on the silicon substrate surface, followed by etching;

[0027] S5 ion implantation, implantation energy 20–50 keV, implantation dose 5E12–1E14 cm⁻¹ -2 S6 front-side process: Depositing an antireflection coating structure on the surface of a silicon substrate;

[0028] S7 Backside Process: Fabricating the sensor output terminal, photolithographically lithographically depicting the output terminal area on the back side of the substrate, ensuring alignment with the frontside process;

[0029] S8 ion implantation, implantation energy 50–100 keV, implantation dose 5E14–5E16 cm⁻¹ -2 The output end is then fabricated, thus completing the sensor array fabrication; next, high-temperature propulsion is performed at 800℃~1000℃ for 30 minutes to form the photosensitive surface;

[0030] S9 back-side process: memory fabrication, further depositing an "electrode-dielectric material-electrode" memory structure on the back side;

[0031] S10 back-side process: memory fabrication, photolithography, etching of the memory structure, paying attention to alignment with the front-side process, to complete the fabrication of the memory array layer, that is, to complete the fabrication of the output end of the integrated sensing-storage chip;

[0032] S11 back panel process: Blue film is applied to protect the memory array;

[0033] S12 front-side process: fabricating the input terminal of the integrated sensing-storage chip, photolithography and etching the antireflection film structure of the sensor to form the electrode area; then completing the front-side metallization and patterning to complete the front-side electrode fabrication.

[0034] S13 removes the blue film on the back, completing the fabrication of the integrated sensing-storage chip.

[0035] Furthermore, in step S8, the high-temperature advancement aims to complete the diffusion of the protective ring, photosensitive surface, and sensor output terminal in one step, forming the PIN. This one-step advancement saves fabrication steps and avoids damage to the silicon substrate material caused by multiple annealing processes.

[0036] Compared with the prior art, the present invention has at least one of the following advantages:

[0037] (1) This invention creatively proposes a silicon-based sensing-storage integrated chip, which adopts a vertical integration method to maximize the light-receiving area and has significant advantages in terms of integration degree;

[0038] (2) The full-process fabrication technology proposed in this invention is fully compatible with silicon-based processes and can solve the problem of large-scale chip applications;

[0039] (3) The sensor output terminal and memory input terminal of the present invention are integrated through process integration, achieving a new breakthrough in chip integration. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the cross-sectional structure of a silicon-based integrated sensing-storage chip according to the present invention.

[0041] Figure 2This is a schematic diagram of a 32×32 positive illumination silicon-based integrated sensing-storage chip package design based on the present invention;

[0042] In the diagram, 1-electrode, 2-Si3N4 layer, 3-silicon oxide layer, 4-P-type photosensitive surface, 5-protective ring, 6-pure silicon, 7-N + 8-memory structure. Detailed Implementation

[0043] The features and advantages of the present invention will become clearer and more apparent from the following detailed description.

[0044] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments. Although various aspects of embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0045] This invention discloses a low-power, multi-modal, silicon-process compatible, positive-illumination silicon-based integrated sensing and storage chip. Its complete technical route and process integration scheme are silicon-based compatible, which has important scientific significance and broad application prospects for promoting the development of integrated sensing, storage, and computing chips.

[0046] There are two main technical approaches currently available. The first is the integrated sensing-storage technology, where the core chip material needs to possess both sensing and storage functions. This approach currently faces serious challenges, including complex material systems, unclear mechanisms, incompatibility with silicon processes, and difficulties in large-scale fabrication. The second approach is integrated sensing-storage technology. Existing integration methods combine NiCr fixed resistors, HfO2 non-volatile resistive random access memory (RRAM), and pin photodetectors to create an integrated neuromorphic array. However, this approach uses planar integration, resulting in a small effective light-receiving area (i.e., a large dead zone), low integration density, and a small array size. Furthermore, NiCr resistor integration also suffers from incompatibility with silicon processes.

[0047] The present invention proposes a forward-illuminated silicon-based sensing and storage integrated chip, which adopts a vertical integration method. On the one hand, it maximizes the light-receiving area and has a significant advantage in terms of integration degree. On the other hand, the full-process fabrication technology proposed in this invention is fully compatible with silicon-based processes and can solve the problem of large-scale chip applications.

[0048] This invention relates to a silicon-based integrated sensing and storage chip.

[0049] Its structure consists of a silicon-based sensor array and a memory array integrated vertically from top to bottom. The silicon-based sensor array is located above the silicon-based sensing-memory integrated chip, and its input terminal serves as the input terminal of the silicon-based sensing-memory integrated chip, used to receive incident light signals. The memory array is located below the silicon-based sensing-memory integrated chip, and its input terminal is connected to the output terminal of the sensor array through a process integration method. Its output terminal serves as the output terminal of the silicon-based sensing-memory integrated chip.

[0050] The working principle of the silicon-based sensing-storage integrated chip is that the silicon-based sensor array receives the incident light signal and converts the incident light signal into an electrical signal, which then drives the memory array to realize the signal storage function.

[0051] In one specific implementation, the memory layer structure is directly fabricated on the back electrode of the sensor layer, and the entire process is compatible with silicon-based processes.

[0052] In one specific implementation, the sensor adopts a vertical device structure at both ends, and the device type can be a silicon PN junction photodetector or a silicon PIN photodetector.

[0053] In one specific embodiment, the memory can adopt a vertical structure with "electrode-dielectric material-electrode" at both ends, or it can adopt a "dielectric material-electrode" structure when the sensor output terminal acts as the memory electrode. The memory of the present invention has multi-level resistive switching characteristics of conductance or resistance and non-volatility characteristics. That is, under electrical excitation conditions, the device can realize mutual conversion between high conductance state and low conductance state, which can be two-level conductance states (high and low) or multi-level conductance states that change with voltage; after the electrical excitation conditions are removed, the conductance or resistance value of the memory can continue to be maintained.

[0054] In one specific implementation, depending on the storage mechanism, the memory can be a resistive switching memory, a phase-change memory, a ferroelectric memory, or a magnetic memory.

[0055] In one specific embodiment, the dielectric material of the memory may be, but is not limited to, aluminum oxide, titanium oxide, halide, zinc oxide, tantalum oxide and their doped and modified oxide materials; GeSbTe, SbTe, GeTe, GeSb phase change materials and their doped and modified phase change materials, mainly composed of germanium (Ge), antimony (Sb), and tellurium (Te); barium lead oxide, lithium niobate, zirconium titanate, lead zirconium titanate perovskite type materials, and ferroelectric hafnium oxide, zirconium hafnium oxide, yttrium hafnium oxide, zinc oxide; iron, cobalt, nickel, ferrite and their doped ferromagnetic materials; characterized in that the functional material structure may be a single-layer thin film or a double-layer or multi-layer thin film structure composed of any two or more materials.

[0056] like Figure 1 As shown, the present invention discloses a method for fabricating a silicon-based integrated sensing and storage chip using a positive illumination method. The specific steps are as follows:

[0057] S1. Perform standardized cleaning on the silicon 6 to complete the initial field oxidation;

[0058] S2, First photolithography, etching the front protective ring area, boron implantation, forming protective ring 5;

[0059] S3, Second photolithography, etching the front photosensitive area;

[0060] S4, boron is injected into the photosensitive surface, followed by field oxidation and high-temperature propulsion to form a P-type photosensitive surface 4;

[0061] S5. Deposit Si3N4 layer 2 and silicon oxide layer 3 on the front and back sides of the silicon 6 to complete the antireflection film structure;

[0062] S6. The third photolithography step involves etching the back-side Si3N4 / SiO2 layer and performing phosphorus implantation to prepare N2O. + Zone 7;

[0063] S7, on the back N + TiN / HfO2 / TiNiAg film structure was sequentially prepared on region 7 and then coated with adhesive for protection.

[0064] S8. Fourth photolithography step: dry etching of the TiN / HfO2 / TiNiAg device region to form memory structure 8;

[0065] S9. Deposit SiO2 on the outside of memory structure 8 for filling and protection;

[0066] S10. Perform the fifth photolithography on the memory structure 8 to lithographically pattern the back metal electrode area; perform the sixth photolithography to complete the back metal patterning and form the back electrode 1;

[0067] S11, back side blue film protection; the front side Si3N4 / SiO2 layer is subjected to the 7th photolithography to etch the front side metal electrode holes;

[0068] S12, the 8th photolithography step, completes the front metal patterning, forms the front electrode 1, removes the back blue film, and completes the fabrication of the silicon-based integrated neuromorphic chip.

[0069] S13, inverted welding.

[0070] S14, bonding, completing the packaging, such as Figure 2 .

[0071] This invention provides a positive illumination silicon-based integrated sensing and storage chip and its fabrication method. The sensor layer and memory layer are vertically integrated through process integration, and the entire process is compatible with silicon processes.

[0072] The present invention has been described in detail above with reference to specific embodiments and exemplary examples; however, these descriptions should not be construed as limiting the present invention. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and embodiments of the present invention without departing from the spirit and scope of the invention, and all such modifications and improvements fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims.

[0073] As the standard.

[0074] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A silicon-based sensing-storage integrated chip, characterized in that, This includes top-down integrated silicon-based sensor arrays and memory arrays; The silicon-based sensor array is located on the top of the chip, and the input terminal of the silicon-based sensor array serves as the input terminal of the chip, used to receive incident light signals. The memory array is located at the bottom of the chip. The input of the memory array is integrated with the output of the silicon-based sensor array, and the output of the memory array serves as the output of the chip.

2. The silicon-based sensing-storage integrated chip according to claim 1, characterized in that, Silicon-based sensor arrays contain hundreds of thousands to tens of thousands of sensing units; Each unit sensing device has a PN two-terminal device structure, including an input terminal, an absorption layer, and an output terminal.

3. The silicon-based sensing-storage integrated chip according to claim 2, characterized in that, The input terminal of the unit sensing device includes an ohmic contact electrode, a photosensitive surface, and an antireflection coating layer; The doping concentration of the ohmic contact electrode is 1E19 cm⁻¹ -3 ~1E21 cm -3 The doping polarity is either P-type or N-type; The doping concentration of the photosensitive surface is 1E12 cm⁻¹ -3 ~1E19 cm -3 The ohmic contact electrode is located within the photosensitive surface area; Antireflective coatings are used to reduce the reflectivity of unit sensing devices for light wavelengths in the range of 200 nm to 1800 nm.

4. The silicon-based sensing-storage integrated chip according to claim 2, characterized in that, The absorber layer material of the unit sensing device is a silicon substrate with a resistivity of 100 Ω·cm to 10000 Ω·cm.

5. A silicon-based sensing-storage integrated chip according to claim 3, characterized in that, The antireflection coating of the unit sensing device is a single-layer or multi-layer film composed of one or more of silicon oxide, silicon nitride, aluminum oxide, zinc sulfide, hafnium oxide, magnesium oxide or zinc sulfide.

6. The silicon-based sensing-storage integrated chip according to claim 2, characterized in that, The output of the unit sensing device is doped at a concentration of 1E19 cm⁻¹. -3 ~1E21 cm -3 The ohmic contact electrode has a doping polarity opposite to that of the input terminal.

7. The silicon-based sensing-storage integrated chip according to claim 1, characterized in that, The memory array contains hundreds of thousands to tens of thousands of memory devices, each of which corresponds one-to-one with a unit sensing device; When the output terminal of the unit sensing device acts as the electrode of the memory device, the structure of the memory device is a dielectric material-electrode vertical structure. When the output of the unit sensing device does not act as an electrode of the storage device, the structure of the storage device is an electrode-dielectric material-electrode vertical structure.

8. A silicon-based sensing-storage integrated chip according to claim 7, characterized in that, The dielectric material of the storage device is a single-layer thin film or a multi-layer thin film composed of one or more of oxide materials, phase change materials or ferromagnetic materials; Oxide materials include aluminum oxide, titanium oxide, nitric oxide, zinc oxide, tantalum oxide, or their doped or modified oxide materials; Phase change materials include GeSbTe, SbTe, GeTe, and GeSb phase change materials or their doped and modified forms, which are mainly composed of germanium, antimony, and tellurium. Ferromagnetic materials include barium lead oxide, lithium niobate, zirconium titanate, lead zirconium titanate calcium titanium, hafnium oxide, zirconium hafnium oxide, yttrium hafnium oxide, zinc oxide, iron, cobalt, nickel, ferrite or doped ferromagnetic materials.

9. A method for fabricating a silicon-based sensing-storage integrated chip according to any one of claims 1-8, characterized in that, include: S1 performs cleaning and initial oxidation on the silicon substrate. S2 is used to photolithographically etch a protective ring area on the front side of the silicon substrate and then etch it. S3 injects ions into the protective ring region to complete the fabrication of the protective ring; S4 photolithography is used to etch the photosensitive area on the front side of the silicon substrate, followed by etching. S5 injects ions into the photosensitive surface region; S6 deposits an antireflection coating structure on the front side of a silicon substrate; S7 is a photolithographically etched region on the back side of a silicon substrate to represent the output area of ​​a silicon-based sensor array. S8 injects ions into the output region of the silicon-based sensor array to complete the fabrication of the output of the silicon-based sensor array; Then, high-temperature propulsion is performed to form a photosensitive surface; S9 deposits a memory film on the back side of a silicon substrate; S10 photolithography and etching of the memory film layer completes the fabrication of the memory array, that is, the fabrication of the chip's output terminal; S11 applies a blue film to protect the memory array; S12 photolithography and etching are used to form the antireflection film structure on the front side of the silicon substrate to form the electrode area; then the electrode area is metallized and patterned on the front side to complete the fabrication of the front electrode, that is, to complete the fabrication of the chip's input end. S13 removes the blue film, completing the fabrication of a silicon-based integrated sensing-storage chip.

10. The method for fabricating a silicon-based sensing-storage integrated chip according to claim 9, characterized in that, In step S3, the implanted ion energy is 50–100 keV, and the implantation dose is 5E14–5E16 cm⁻¹. -2 ; In step S5, the injected ion energy is 20–50 keV, and the injection dose is 5E12–1E14 cm⁻¹. -2 ; In step S8, the implanted ion energy is 50–100 keV, and the implantation dose is 5E14–5E16 cm⁻¹. -2 ; In step S8, the temperature for high-temperature propulsion is 800℃~1000℃, and the time is 20~40min.

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