Light emitting diode chip

Abstract

The invention provides a light emitting diode chip. The light-emitting diode chip comprises a light-emitting diode unit and a hard mask covering the side wall of the light-emitting diode unit, the side wall of the hard mask is covered with an insulating layer, and the side wall of the insulating layer extends in a continuous downward extending trend. The insulating layer is arranged on the electrode layer, so that the outer wall of the insulating layer does not form a step at the connecting position of the electrode layer and the light-emitting main body, and the step is limited as a wall surface of which the main extension direction is horizontal. As the step is not formed, the size of the light-emitting main body of the light-emitting diode unit can be allowed to be larger under the condition that the pixel size is fixed, so that a light-emitting area with a larger area is obtained, and the light extraction rate is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a light emitting diode chip. BACKGROUND

[0002] The existing micro-LED chip is a large size pixel unit, usually the pixel unit is 10 μm or above. Since the size of the pixel unit itself is large enough, the maximum horizontal width of the light emitting diode body is smaller than the horizontal width of the bottom electrode layer, which can also ensure the area of the light emitting region. Because the maximum horizontal width of the light emitting diode body of the existing micro-LED chip is smaller than the horizontal width of the bottom electrode layer, and the light emitting diode usually includes an insulating layer, the sidewall of the insulating layer (i.e. the part of the insulating layer on the sidewall of the light emitting diode) will usually form a stepped structure in some sections, that is, the existing micro-LED chip has a stepped structure. Generally, the width of the above-mentioned stepped structure is 1 μm or above.

[0003] With the continuous reduction of the size of micro-LED, the influence of the above-mentioned stepped structure becomes more and more prominent. For example, for a single LED with a diameter of 4 μm, a stepped space of 1 μm is equivalent to occupying a considerable part of the volume of the light emitting body. That is, for a small size pixel unit, due to the existence of the stepped structure, the width of the light emitting body of the light emitting diode is small under the condition of a certain pixel unit size, so the area of the light emitting region is small, which seriously reduces the luminous efficiency.

[0004] Therefore, it is necessary to provide a light emitting diode chip to at least partially solve the above-mentioned problems. SUMMARY

[0005] According to one aspect of the present application, a light emitting diode chip is provided. According to one aspect of the present application, the sidewall of the insulating layer of the light emitting diode unit of the light emitting diode chip extends in a continuous downward extending trend, so that the outer wall of the insulating layer does not form a step at the connection position of the electrode layer and the light emitting body. Since the insulating layer sidewall does not form a step, the size of the light emitting body of the light emitting diode unit can be made larger under the condition of a certain pixel size, so as to obtain a larger light emitting region to improve the light output rate.

[0006] According to one aspect of the present application, a light emitting diode chip is provided, comprising a substrate and a plurality of light emitting diode units arranged in an array on the substrate, wherein each of the light emitting diode units comprises:

[0007] a light emitting body, the light emitting body comprising a first type semiconductor, a light emitting layer and a second type semiconductor stacked in turn from bottom to top,

[0008] an electrode layer, a radial dimension of the electrode layer being larger than a radial dimension of the light emitting body and positioned at a bottom of the light emitting body, thereby conductively connecting the light emitting body and electrodes of the light emitting diode chip,

[0009] a hard mask covering a sidewall of the light emitting layer and the first type semiconductor; and

[0010] an insulating layer covering a sidewall of the electrode layer and a sidewall of the hard mask,

[0011] wherein the insulating layer extends in a continuous downward extending tendency at a connecting position of the light emitting body and the electrode layer, so that an outer wall of the insulating layer does not form a step at the connecting position of the electrode layer and the light emitting body, the step being defined as a wall surface mainly extending horizontally.

[0012] In an embodiment, each of the light emitting diode units forms a columnar structure with a radial dimension gradually decreasing from bottom to top as a whole, and the insulating layer comprises an insulating layer top section covering an outer side of the light emitting body and an insulating layer bottom section covering an outer side of the electrode layer, wherein:

[0013] an inclination angle of an outer wall of the insulating layer top section is larger than an inclination angle of an outer wall of the insulating layer bottom section; or

[0014] an inclination angle of an outer wall of the insulating layer top section is equal to an inclination angle of an outer wall of the insulating layer bottom section; or

[0015] an inclination angle of an outer wall of the insulating layer top section is smaller than an inclination angle of an outer wall of the insulating layer bottom section.

[0016] In an embodiment, the outer wall of the insulating layer top section has an unchanging inclination angle from a top end to a bottom end thereof, and / or

[0017] the outer wall of the insulating layer bottom section has an unchanging inclination angle from a top end to a bottom end thereof.

[0018] In an embodiment, a connecting position of the outer wall of the insulating layer bottom section and the outer wall of the insulating layer top section forms only one edge around the light emitting diode unit; or

[0019] the outer wall of the insulating layer top section smoothly transitions to the outer wall of the insulating layer bottom section.

[0020] In an embodiment, the outer wall of the insulating layer bottom section forms at least one edge around the light emitting diode unit; and / or the insulating layer top section forms at least one edge around the light emitting diode unit,

[0021] wherein a vertical component of the wall surface between any pair of adjacent edges on the outer wall of the insulating layer is greater than a horizontal component.

[0022] In one embodiment, the hard mask extends from a top end of the light emitting body down to a bottom end of the light emitting body, and the insulating layer extends from the top end of the light emitting body to a bottom end of the electrode layer.

[0023] In one embodiment, the hard mask comprises a plurality of sub-layers arranged in a radial direction from inner to outer.

[0024] In one embodiment, the light emitting diode chip further comprises:

[0025] a top conductive layer, the conductive layer covering a top surface and a sidewall of the light emitting body.

[0026] In one embodiment, the top conductive layer comprises a first top conductive layer covering only the top surface of the light emitting body, and a second top conductive layer covering a top surface of the first top conductive layer and covering an outer sidewall of the insulating layer, wherein:

[0027] a top end of the insulating layer is lower than a top surface of the first top conductive layer, or the top end of the insulating layer is flush with the top surface of the first top conductive layer.

[0028] In one embodiment, the light emitting diode chip further comprises:

[0029] a first electrode disposed at the substrate and positioned at a bottom of the light emitting diode unit, the first electrode conductively connected with the first type semiconductor via the electrode layer; and

[0030] a second electrode, a portion of the second electrode disposed at the substrate and positioned between a pair of the light emitting diode units having a first adjacent relationship, the portion of the second electrode conductively connected with the second type semiconductor,

[0031] wherein the portion of the second electrode is embedded in the substrate.

[0032] In one embodiment, the second electrode is disposed around each of the light emitting diode units to form between the light emitting diode units having the first adjacent relationship, and / or

[0033] In a predetermined cross-section taken by a plane in which an axis of the light emitting diode unit lies, the second electrode is formed as a trapezoidal cross-section with a radial dimension gradually increasing or decreasing from bottom to top.

[0034] In one embodiment, the light emitting diode chip further comprises a top conductive layer coated outside the insulating layer,

[0035] The top opening of the insulating layer allows the top conductive layer to conductively contact the second type semiconductor, and the dielectric material opening between adjacent light emitting diode units allows the top conductive layer to conductively contact the second electrode.

[0036] In one embodiment, the electrode layer comprises:

[0037] A bottom conductive layer located at the bottom side of the first type semiconductor;

[0038] A bonding layer located at the bottom side of the bottom conductive layer.

[0039] In one embodiment, the ratio of the thickness of the bonding layer to the thickness of the hard mask is 10:1-1:1.

[0040] In one embodiment, the ratio of the thickness of the bonding layer to the thickness of the hard mask is 2:1; and / or the thickness of the bonding layer is 400nm and the thickness of the hard mask is 200nm.

[0041] In one embodiment, the first electrode comprises a top segment and a bottom segment, at least one of the top segment and the bottom segment is formed as a columnar structure perpendicular to the substrate, the radial dimension of the top segment is smaller than the radial dimension of the bottom segment, and the second electrode is located between the top segments of adjacent first electrodes.

[0042] In one embodiment, the bottom surface of the top segment of the first electrode and the bottom surface of the second electrode are flush; and / or

[0043] At least one of the top segment and the bottom segment gradually increases its respective radial dimension in a direction from bottom to top.

[0044] In one embodiment, there is a gap between the pair of light emitting diode units having the first adjacent relationship, the portion of the second electrode is positioned directly below the gap,

[0045] and the bottom ends of the pair of light emitting diode units having the second adjacent relationship are in close proximity.

[0046] In one embodiment, the electrode layer of the pair of light emitting diode units having the second adjacent relationship at least partially blocks the second electrode between the pair of light emitting diode units in a vertical direction.

[0047] In one embodiment, the light emitting diode chip is a micro light emitting diode chip using micro-scale LEDs as light emitting diodes.

[0048] In one embodiment, the insulating layer extends from the top end of the sidewall of the light emitting body to the bottom end of the sidewall of the electrode layer in a continuous downward extending trend, so that the outer wall of the insulating layer does not form a step on the complete sidewall of the light emitting diode unit.

[0049] In one embodiment, the angle between the main extension direction of any segment of the insulating layer and the vertical plane is less than 30°.

[0050] In one embodiment, the outer sidewall of the insulating layer comprises a segment whose main extension direction is horizontal but whose radial extension size in the horizontal direction is no more than 100 nm.

[0051] In one embodiment, the maximum horizontal width of the light emitting diode unit is less than or equal to 4 μm. BRIEF DESCRIPTION OF DRAWINGS

[0052] For a better understanding of the above objects, features and advantages of the present application, reference should be made to the preferred embodiments thereof which are shown in the accompanying drawings. The same reference numerals in different drawings denote the same or similar components. It is to be understood that the drawings are schematically illustrating the preferred embodiments of the present application and have no limiting effect on the scope of the present application, and the components in the drawings are not drawn to scale.

[0053] Figure 1A A plan view of a light emitting diode chip according to one aspect of the present application is shown, in which structures such as microlenses are omitted to show the light emitting diode units;

[0054] Figure 1B A plan view of a second electrode of the light emitting diode chip;

[0055] Figure 2 A partial enlarged view of part E in Figure 1A A cross-sectional view taken along the A-B-D line in Figure 1A A view of the A-B-D cross-section of the light emitting diode chip shown;

[0056] Figure 3A A partial enlarged view of part E in Figure 2

[0057] A modification of Figures 3B-3E Figure 3A

[0058] Figure 4A A modification of Figure 4B Figure 2 ​​​​

[0059] Figures 5A-5D Flowchart of a manufacturing process for a light emitting diode unit

[0060] Figures 6A-6D Flowchart of a manufacturing process for a light emitting diode unit according to a preferred embodiment of the invention

[0061] Legend of reference signs:

[0062] 100 micro light emitting diode chip

[0063] 1 substrate

[0064] 11 opening

[0065] 12 top substrate layer

[0066] 13 bottom substrate layer

[0067] 14 dielectric material

[0068] 21 light emitting diode unit

[0069] 211 light emitting body

[0070] 2111 second type semiconductor

[0071] 2112 light emitting layer

[0072] 2113 first type semiconductor

[0073] 212 electrode layer

[0074] 2121 bottom conductive layer

[0075] 2122 bonding layer

[0076] 2123 electrode layer blank

[0077] 214 hard mask

[0078] 2141 horizontal portion

[0079] 216 top conductive layer

[0080] 2161 first top conductive layer

[0081] 2162 sunken contact section

[0082] 2163 third top conductive layer

[0083] 217 insulating layer

[0084] 2171 insulating layer top section

[0085] 2172 insulating layer bottom section

[0086] 2173 ridge

[0087] 2174a first edge

[0088] 2174b second edge

[0089] 2175 step surface

[0090] 2176 wall surface between adjacent edges

[0091] 22 light-transmissive spacer

[0092] 23 microlens

[0093] 3 first electrode

[0094] 31 top section

[0095] 32 bottom section

[0096] 4 second electrode

[0097] 43 hollow portion

[0098] 5 photoresist

[0099] 6 dashed line frame

[0100] 7 top mask DETAILED DESCRIPTION

[0101] Reference will now be made in detail to the preferred embodiments of the present application, examples of which are illustrated in the accompanying drawings. The preferred embodiments described herein are merely exemplary and not limiting, as one skilled in the art can make other ways and / or modifications of the present application after having the benefit of this disclosure without departing from the spirit and scope of the present application.

[0102] Figures 1A-6D A micro light emitting diode chip according to the present application is shown. First of all, it should be noted that the directional terms and positional terms in the present application should be understood as relative directional terms and positional terms, rather than absolute directional terms and positional terms. The directional terms and positional terms in the present application can be explained with reference to the exemplary structure shown. Figures 1A-6D

[0103] In particular, the "axial direction" can be understood as the axial direction of the substantially cylindrical structure formed by the light emitting diode units 21 of the micro light emitting diode chip 100, which is shown by X in the figure. It should be noted that the light emitting diode units 21 can be formed in various structures such as a cylinder, a truncated cone, a prism, or other shapes having a height extending in the X direction, and for the convenience of description, these structures are all regarded as having an axial direction X. The "radial direction" is the radial direction with respect to the axial direction X, which is shown by R in the figure; and the "circumferential direction" is the circumferential direction around the axial direction X, which is shown by C in the figure. Figure 1A Figure 1A Figure 1A ​​​indicated by C; the "height direction" and the "thickness direction" are directions parallel to or coinciding with the axial direction X.

[0104] The positional terms should also be understood in conjunction with Figures 2-6D understanding. For example, the expressions "above", "below", "bottom side", "top side", etc. can be understood with reference to the relative positions of the components shown in Figures 2-6D .

[0105] In addition, "gradually from top to bottom" merely indicates the relative positional characteristics between two components at a certain state, and does not represent the final relative positional characteristics between the two components. In certain cases, such as before the product is inverted, the relative positional characteristics between the two components can be that the radial dimension gradually decreases from bottom to top, and after the product is inverted, the relative positional characteristics become that the radial dimension gradually decreases from top to bottom.

[0106] Referring first to Figures 1A-2 , some preferred embodiments of the present application provide a light emitting diode chip, particularly a micro light emitting diode chip 100, i.e. a high pixel density LED formed in a micron order period. The micro light emitting diode chip 100 includes a substrate 1 and a plurality of light emitting diode units 21 arranged in an array on the substrate 1, as well as micro lenses 23 and light-transmitting spacers 22. The substrate 1 may, for example, be an IC driving backplane, which includes a dielectric layer, such as a SiO2 layer, and a driving circuit (not shown) contained in the dielectric layer. Each light emitting diode unit 21 is generally formed in a truncated conical shape around an axis X, and in a direction from bottom to top, its radial dimension gradually decreases (but not necessarily uniformly). In a predetermined cross section taken by the plane in which the axis X of the light emitting diode unit 21 lies (for example, as shown in the cross section), the cross section of the light emitting diode unit 21 is formed in a trapezoidal shape with a radial dimension gradually decreasing from bottom to top. In other embodiments, the cross section of the light emitting diode unit can be formed in a trapezoidal shape with a radial dimension gradually decreasing from top to bottom. The embodiments of the present application can be applied to light emitting diode chips with light emitting diode units having a radial dimension gradually decreasing from bottom to top, and can also be applied to light emitting diode chips with light emitting diode units having a radial dimension gradually increasing from top to bottom. Figure 2 Figures 1A-6D

[0107] It should be noted that the shapes of the components described in the present application do not mean that the components have strictly geometric shape characteristics, but only visually conform to the specific shape characteristics. In some embodiments, the substrate can also contain other circuits in addition to the IC driving circuit. In other embodiments, the light emitting diode chip can be a large particle LED light emitting diode chip.

[0108] Referring to Figure 2 ​​Each light emitting diode unit 21 includes a light emitting body 211, which includes a light emitting layer 2112, a first type semiconductor 2113 on a bottom side of the light emitting layer 2112, and a second type semiconductor 2111 on a top side of the light emitting layer 2112. The light emitting body 211 is also referred to as an epitaxial layer, and the light emitting layer 2112 is also referred to as an active layer. The first type semiconductor 2113 can be one of an N-type semiconductor and a P-type semiconductor, and the second type semiconductor 2111 can be the other of the N-type semiconductor and the P-type semiconductor.

[0109] With continued reference to Figure 2 Each light emitting diode unit 21 further includes an electrode layer 212, which has a radial dimension greater than that of the light emitting body 211 and is positioned at the bottom of the light emitting body to conductively connect the light emitting body and an electrode (e.g., the first electrode 3 to be discussed later) of the light emitting diode chip. The electrode layer 212 includes a bottom conductive layer 2121 on the bottom side of the first type semiconductor 2113 and a bonding layer 2122 on the bottom side of the bottom conductive layer 2121.

[0110] The micro light emitting diode chip 100 further includes a first electrode 3 and a second electrode 4. The first electrode 3 is disposed at the substrate 1 and positioned at the bottom of each light emitting diode unit 21, and is conductively connected via the bottom conductive layer 2121, the bonding layer 2122, and the first type semiconductor 2113. The second electrode 4 is disposed at the substrate 1 and positioned between adjacent light emitting diode units 21, and is conductively connected with the second type semiconductor 2111. The first electrode 3 is an electrode of the same polarity as the first type semiconductor 2113, and the second electrode 4 is an electrode of the same polarity as the second type semiconductor 2111. In some embodiments, the first type semiconductor 2113 is a P-type semiconductor, the second type semiconductor 2111 is an N-type semiconductor, the first electrode 3 is a P-type electrode, and the second electrode 4 is an N-type electrode.

[0111] In the present embodiment, the light emitting diode unit 21 does not include the first electrode 3 and the second electrode 4, and the light emitting diode unit 21 can also be referred to as a light emitting mesa.

[0112] The light emitting diode unit 21 further comprises a hard mask 214 covering the outside of the light emitting layer 2112 and the first type semiconductor 2113. The light emitting diode unit 21 further comprises an insulating layer 217 covering the sidewall of the electrode layer 212 and the sidewall of the hard mask 214. In some embodiments, the insulating layer 217 extends from the top end of the side of the light emitting diode unit 21 to the bottom end of the side of the light emitting diode unit 21. In some embodiments, the hard mask 214 extends downward from the top end of the light emitting body 211 and stops at the bottom end of the light emitting body 211, while the insulating layer 217 extends from the top end of the light emitting body 211 to the bottom end of the electrode layer 212.

[0113] In some embodiments, the hard mask 214 is a transparent insulating material, and the electrode layer 212 and the hard mask 214 have a high selectivity ratio, which in this embodiment is greater than or equal to 2. The following will be described with reference to Figure 2 and Figure 3A It can be seen that the insulating layer 217 extends along the sidewall of the light emitting body 211 (there is a hard mask 214 between the insulating layer 217 and the light emitting body 211) in a continuous downward extending trend, so that the outer wall of the insulating layer 217 does not form a step at the connection position of the electrode layer 212 and the light emitting body 211, and further, the outer wall of the insulating layer 217 does not form a step at any position from the top to the bottom of the light emitting diode unit 21.

[0114] It should be noted that in some embodiments, the "downward extending trend" refers to the main extension direction of the component being downward, that is, the vertical component is greater than the horizontal component, that is, the angle between the vertical plane is smaller than the angle between the horizontal plane; "continuous" refers to any section of the sidewall of the insulating layer meeting the above "downward extending trend"; if a part can form a "step", it means that the main extension direction of this part is horizontal, "the main extension direction is horizontal" means that the horizontal component is greater than the vertical component, that is, the angle between the horizontal plane is smaller than the angle between the vertical plane. More preferably, for any section of the sidewall of the insulating layer, the angle between the main extension direction and the vertical plane is less than 30°. That is, in the present application, the "step" is defined as the wall surface with the main extension direction being horizontal. It can be understood that errors are inevitable in production, and if only a small section of the outer sidewall of the insulating layer exists due to process errors, but the horizontal extension radial dimension of the small section is less than 100 nm, then such a section still does not constitute a "step". In other words, the wall surface with the main extension section being horizontal (which is only the result of errors) but the horizontal extension radial dimension being very small (less than 100 nm) does not meet the definition of "step" due to process errors.

[0115] That is, for any wall, the whole of which extends roughly in the vertical direction, it can be understood that the width of the light emitting body 211 can be further increased under the condition of a certain pixel size (try to imagine that if the angle between the outer wall of the insulating layer 217 and the horizontal plane is small under the condition of a certain pixel size, the width of the upper half of the roughly trapezoidal structure of the light emitting diode unit 21 constituted by the light emitting body 211 can only be made small).

[0116] In some embodiments, the insulating layer 217 can only extend in a continuous downward extending trend at the connection position of the electrode layer 212 and the light emitting body 211, so that the outer wall of the insulating layer 217 does not form a step at the connection position of the electrode layer 212 and the light emitting body 211. More specifically, and the insulating layer 217 includes an insulating layer top section 2171 covering the outer side of the light emitting body 211 and an insulating layer bottom section 2172 covering the outer side of the electrode layer 212. It should be noted that "covering" does not necessarily mean that the two components are in direct contact, for example, there is also a hard mask 214 between the insulating layer 217 and the light emitting body 211, but the insulating layer 217 can still be referred to as covering the outer side of the light emitting body 211.

[0117] From Figure 2 and Figure 3A , it can be seen that the insulating layer bottom section 2172 only includes a part of the insulating layer 217, while the insulating layer top section 2171 includes both the hard mask 214 and a part of the insulating layer 217. It should be noted that the "outer wall of the insulating layer" refers to the outermost wall of the whole insulating layer.

[0118] Referring to Figure 3A , the inclination angle (the angle between the wall and the vertical direction) of the outer wall of the insulating layer top section 2171 is smaller than the inclination angle (the angle between the wall and the vertical direction) of the outer wall of the insulating layer bottom section 2172. Because the outer wall of the insulating layer top section 2171 and the outer wall of the insulating layer bottom section 2172 have different inclination angles, a ridge 2173 around the light emitting diode unit 21 is formed at the connection of the outer wall of the insulating layer bottom section 2172 and the outer wall of the insulating layer top section 2171. Although there is a ridge 2173, a ridge obviously cannot constitute a step structure.

[0119] Further, in Figure 2 and Figure 3AIn the structure shown, the outer wall of the top section 2171 of the insulation layer has a constant inclination angle from its top end to its bottom end, and the outer wall of the bottom section 2172 of the insulation layer has a constant inclination angle from its top end to its bottom end. That is, the outer wall of the top section 2171 of the insulation layer itself is smooth without having a ridge or step structure, and the outer wall of the bottom section 2172 of the insulation layer itself is smooth without having a ridge or step structure. It should be noted that in some other embodiments, the outer wall of the top section 2171 of the insulation layer can have a varying inclination angle, in which case the “inclination angle of the outer wall of the top section 2171 of the insulation layer and the bottom section 2172 of the insulation layer” refers to the overall extending angle of the outer wall or the overall extending angle of the main section thereof. It should also be noted that even if the outer wall of the top section 2171 of the insulation layer and the outer wall of the bottom section 2172 of the insulation layer are each a non-smooth outer wall, there will still be no step on the outer wall of the insulation layer 217 in this case.

[0120] For example, the outer wall of the bottom section 2172 of the insulation layer can have at least one ridge surrounding the light-emitting diode unit 21, and the outer wall of the top section 2171 of the insulation layer can also have at least one ridge surrounding the light-emitting diode unit 21. That is, there are multiple ridges on the outer wall of the entire insulation layer 217. However, for the wall surface between any pair of adjacent ridges, the vertical inclination component of the wall surface is greater than the horizontal inclination component, that is, the included angle between the wall surface and the vertical plane is less than 45°, and the included angle between the wall surface and the horizontal plane is greater than 45°, so that the wall surface formed between any pair of adjacent ridges does not constitute a step. In some more preferred embodiments, the included angle between the wall surface and the vertical plane for the wall surface between any pair of adjacent ridges on the outer wall of the insulation layer 217 is less than 30°, that is, the wall surface extends more relatively along the vertical direction, and it can be understood that under the condition of a certain pixel size, the width of the light-emitting body 211 can be further increased (for example, under the condition of a certain pixel size, if the included angle between the outer wall of the insulation layer 217 and the horizontal plane is smaller, then the width of the light-emitting body 211 as the upper half of the substantially trapezoidal structure constituted by the light-emitting diode unit 21 can only be made smaller).

[0121] Figures 3B-3E Some deformations are shown Figure 3A .

[0122] Referring to Figure 3B , the inclination angle (and the included angle with the vertical direction) of the outer wall of the top section 2171 of the insulation layer is greater than the inclination angle (and the included angle with the vertical direction) of the outer wall of the bottom section 2172 of the insulation layer, and a ridge 2173 is formed between the outer wall of the top section 2171 of the insulation layer and the outer wall of the bottom section 2172 of the insulation layer without forming a step.

[0123] Referring to Figure 3CThe inclination angle of the outer wall of the top section 2171 of the insulation layer is equal to the inclination angle of the outer wall of the bottom section 2172 of the insulation layer. The outer wall of the top section 2171 of the insulation layer smoothly transitions to the outer wall of the bottom section 2172 of the insulation layer. Therefore, there is no edge 2173 between the outer wall of the top section 2171 of the insulation layer and the outer wall of the bottom section 2172 of the insulation layer, and there is no step.

[0124] Referring to 3D, the outer wall of the bottom section 2172 of the insulating layer may have at least one edge surrounding the light-emitting diode unit 21 (in other cases, the top section 2171 of the insulating layer may also have at least one edge surrounding the light-emitting diode unit 21). That is, the entire outer wall of the insulating layer 217 has multiple edges, such as the first edge 2174a and the second edge 2174b. However, for the wall surface 2176 between any pair of adjacent edges, the vertical tilt component of the wall surface is greater than the horizontal tilt component, that is, the angle between the wall surface and the vertical plane is less than 45°, while the angle with the horizontal plane is greater than 45°, so the wall surface 2176 formed between any pair of adjacent edges does not constitute a step. In some more preferred embodiments, the angle between the wall surface 2176 between any pair of adjacent edges on the outer wall of the insulating layer 217 and the vertical plane is less than 30°. That is, the wall surface extends more vertically. Therefore, it can be understood that with a fixed pixel size, the width of the light-emitting body 211 can be further increased (imagine, with a fixed pixel size, if the angle between the outer wall of the insulating layer 217 and the horizontal plane is small, then the width of the light-emitting body 211, as the upper half of the roughly trapezoidal structure formed by the light-emitting diode unit 21, can only be made smaller).

[0125] refer to Figure 3E The insulating layer 217 has two edges on its sidewall, a first edge 2174a and a second edge 2174b. Due to manufacturing tolerances, the wall 2176 between the first edge 2174a and the second edge 2174b extends approximately horizontally, but the radial dimension of this horizontal extension is less than 100 nm. This structure still conforms to the definition of "stepless".

[0126] In other words, "stepless" has different meanings in different implementations, such as... Figures 2-3D In the illustrated embodiment, for any segment of the insulating layer 217, the main extension direction of the segment is downward (it may have a certain horizontal component, but the overall extension direction is downward) and it does not have any horizontally extending segments. Such a structure is called "stepless"; while in... Figure 3E In the embodiment shown, a section of the insulating layer 217 extends horizontally, but this is merely due to error; its radial dimension is very small, less than 100 nm. Figure 3EThe implementation shown is also referred to as "stepless".

[0127] Since no steps are formed at the connection between the sidewalls of the top section 2171 and the bottom section 2172 of the insulating layer, or on the sidewalls of the top section 2171 and the bottom section 2172 of the insulating layer, the size of the light-emitting body of the LED unit can be made larger and the area of ​​the light-emitting region can be larger when the pixel size is fixed, thereby improving the light extraction efficiency. (Imagine, if there are steps on the sidewalls of the insulating layer when the pixel size is fixed, the width of the light-emitting body itself must be reduced in order to make room for the steps, and the area of ​​the light-emitting region will be reduced, thus affecting the light extraction efficiency.)

[0128] Whether the implementation has a single edge or multiple edges, the presence of edges is a result of process optimization. That is, allowing the presence of edges can reduce the precision requirements in the process, improve production efficiency, and will not adversely affect product performance. As mentioned above, the edges do not form steps, and the overall diode chip still has good light extraction efficiency.

[0129] In some embodiments, the hard mask 214 itself may comprise a plurality of sublayers arranged radially from the inside to the outside. The oxide forming the outermost layer of the hard mask 214 enables the absence of steps during the overall molding process of the insulating layer 217 (as will be described in detail later). It should be noted that the hard mask 214 and at least its outermost layer may also be made of other materials, and obtaining a stepless structure from other materials also falls within the scope of this invention.

[0130] In each of the above embodiments, the maximum horizontal width of the light-emitting diode unit 21 is less than or equal to 4 μm.

[0131] The following is about Figure 2 Some other preferred configurations are described below. The light-emitting diode chip 100 includes a top conductive layer 216 integrally coated on a plurality of light-emitting diode cells 21. The top conductive layer 216 contacts a second type semiconductor 2111 on the top of each light-emitting diode cell 21, and contacts a second electrode 4 embedded in the substrate 1 between light-emitting diode cells 21 having a first adjacent relationship. That is, the second electrode 4 is electrically connected via the top conductive layer 216 and the second type semiconductor 2111.

[0132] As mentioned above, the second electrode 4 is embedded in the substrate 1, so that the bottom end of the second electrode 4 is lower than the bottom end of the plurality of light-emitting diode units 21. The connection relationship between the second electrode 4 and the top conductive layer 216 also has certain preferred settings.

[0133] refer to Figure 2 ,Will Figure 2The pair of adjacent light emitting diode units 21 in the middle on the right is referred to as a pair of light emitting diodes with a first adjacent relationship, and Figure 2 The pair of adjacent light emitting diode units 21 in the middle on the left is referred to as a pair of light emitting diodes with a second adjacent relationship, and Figure 2 The light emitting diode unit 21 in the middle is both one of the light emitting diodes with the first adjacent relationship and one of the light emitting diodes with the second adjacent relationship. There is a gap between the pair of light emitting diode units 21 with the first adjacent relationship, and the second electrode 4 is partially positioned directly below the gap, while the bottom end (the portion above the substrate 1) of the pair of light emitting diode units 21 with the second adjacent relationship is adjacent to or has a small or no gap.

[0134] Further, the top conductive layer 216 extends from the top of the second-type semiconductor 2111 to the top of the second electrode 4. Since the second electrode 4 is partially embedded in the substrate 1, the second electrode 4 is below the top conductive layer 216. In order to enable the second electrode 4 to contact the top conductive layer 216 and avoid a short circuit problem, the insulating layer 217 extends downward from the top of the light emitting diode unit 21 and stops above the second electrode 4 between the light emitting diode units 21 with the first adjacent relationship without reaching the top of the second electrode 4 (the portion of the insulating layer 217 extending horizontally above the substrate 1), that is, the insulating layer 217 forms an opening at the top of the second electrode 4, and the dielectric layer of the substrate 1 also forms an opening at the same position, so as to allow the sunken contact section 2162 of the top conductive layer 216 and the second electrode 4 to contact each other at the opening. The insulating layer 217 and the dielectric layer of the substrate 1 can be collectively referred to as a dielectric material.

[0135] Continuing to refer to Figure 2 , the portion of the top conductive layer 216 between the second electrode 4 and any pair of light emitting diode units 21 with the second adjacent relationship is spaced apart by the dielectric material 14 of the substrate. The bonding layer 2122 or the bottom conductive layer 2121 of the pair of light emitting diode units 21 with the second adjacent relationship at least partially blocks the second electrode 4 between the pair of light emitting diode units 21 in the vertical direction, that is, the pair of light emitting diode units 21 with the second adjacent relationship overlaps the second electrode 4 in the vertical direction. Partially embedding the second electrode 4 in the substrate 1 can reduce the area occupied by the second electrode 4 in the array of light emitting diode units, and even when the second electrode 4 is completely embedded in the substrate, the second electrode 4 can not occupy any area in the array of light emitting diode units. Such an arrangement can ensure that the light emitting diode units 21 can be made larger under the premise of a certain overall size of the chip, so that the optical effect of the chip is better.

[0136] In fact, referring to Figure 1B and Figure 2The second electrode 4 is disposed around almost every light-emitting diode unit 21, thus forming between any adjacent light-emitting diode units 21. Specifically, in a micro light-emitting diode chip 100, the second electrode 4 is integrally connected and formed in a grid shape, with each light-emitting diode unit 21 positioned within the grid. This part can be referred to... Figure 1B The top view of the second electrode 4 shown. Figure 1B As shown, the mesh-like structure formed by the second electrode 4 includes an array of hollow portions 43. Each light-emitting diode unit 21 is positioned correspondingly in one of the hollow portions 43. However, each light-emitting diode unit 21 is not directly placed within its corresponding hollow portion 43, but may be located directly above it. For the integrated second electrode 4, a portion of its structure contacts the top conductive layer 216 (e.g., located in...). Figure 2 (As shown, there are light-emitting diodes with a first adjacent relationship), while a portion of the section is spaced apart from the top conductive layer 216. For example... Figure 1A As shown, an opening 11 is formed at a specific location on the substrate 1 to expose the second electrode 4 or the top conductive layer 216 on top of the second electrode 4, etc. Figure 2 As can be seen, on a predetermined cross section taken from the plane containing the axis X of the light-emitting diode unit, the second electrode is formed as a trapezoidal cross section with radial dimensions gradually increasing or decreasing from bottom to top.

[0137] The second electrode 4 is at least partially embedded in the dielectric layer of the substrate 1, which reduces the space occupied by the second electrode 4 between adjacent light-emitting diode units 21 and allows the gap between adjacent light-emitting diode units 21 to be adaptively reduced, thereby reducing the overall size of the chip 100, so that it can be matched with thinner and more portable electronic devices and adapt to more application scenarios.

[0138] In some embodiments, both the bottom conductive layer 2121 and the top conductive layer 216 can be transparent conductive layers made of, for example, ITO. The bonding layer 2122 is used to bond the light-emitting body 211 to the substrate 1, and the material of the bonding layer 2122 can be selected from at least one of Ag, Pt, Au, Sn, Cr, and Ti. Specifically, the bonding layer 2122 includes a mirror layer (e.g., P-mirror) on top of it, and the mirror layer is made of pure silver, pure gold, a gold-chromium alloy, or a silver-copper alloy. Alternatively, the mirror layer may contain gold and trace elements, with gold as the main component and the trace elements including at least one of chromium, titanium, and nickel. Specifically, different metals have different reflectivities for red, green, and blue wavelengths, and specific materials can be selected for different colors. Pure silver and silver-copper alloys are particularly suitable for yellow-green LEDs. Pure silver, pure gold, and gold-chromium alloys are particularly suitable for red LEDs.

[0139] In some embodiments, the thickness ratio of the bonding layer 2122 and the hard mask 214 can have a certain special relationship, for example, the ratio of the thickness of the bonding layer 2122 and the thickness of the hard mask 214 is 10:1-1:1. The ratio of the thickness of the bonding layer 2122 and the thickness of the hard mask 214 is 2:1. For example, the thickness of the bonding layer 2122 can be 400 nm, and the thickness of the hard mask 214 can be 200 nm. Such a size structure is particularly suitable for small-size light-emitting diode chips, for example, it is particularly suitable for light-emitting diode chips with a pixel size (usually, one pixel contains a light-emitting diode unit and a microlens on the top thereof) of 3 μm or less.

[0140] The correlation between the thickness of the bonding layer 2122 and the thickness of the hard mask 214 is very important in terms of process and product performance. Setting it to 10:1-1:1, preferably 2:1, can ensure that the thickness of each layer is within the process window range, avoiding manufacturing failures caused by mismatched thickness.

[0141] As shown in Figure 2 , Figure 4A and Figure 4B , the top conductive layer 216 includes a first top conductive layer 2161 covering only the top surface of the light-emitting body 211, and a second top conductive layer 2163 covering the top surface of the first top conductive layer 2161 and covering the outer sidewall of the insulating layer 217. Figure 2 In the structure shown in Figure 4A , the top of the insulating layer 217 and the hard mask 214 is higher than the top surface of the first top conductive layer 2161; while in the structure shown in Figure 4B , the top surface of the insulating layer 217 and the hard mask is lower than the top surface of the first top conductive layer 2161.

[0142] Figure 4A and Figure 4B The structure shown in can improve the performance of the light-emitting diode unit 21, for example: it can increase the area of the ohmic contact on the top of the light-emitting body, and can produce better conductive and current spreading effects; on the other hand, as the pixel size decreases, the top size of the light-emitting diode unit 21 will also be smaller, and the insulating layer 217 does not extend to the top, thereby exposing the top layer, which can reduce the requirement for the line width of photolithography; on the other hand, such a setting will make the top layer have no corner of the insulating layer protrusion, so that the coverage and continuity of the top conductive layer 216 will be better, and the electrical connection will be more reliable and stable.

[0143] The first electrode 3 can also have some preferred configurations. The first electrode 3 includes a top section 31 and a bottom section 32, at least one of the top section 31 and the bottom section 32 is formed as a columnar structure perpendicular to the substrate 1, the radial dimension of the top section 31 is smaller than that of the bottom section 32, and the second electrode 4 is located between the top sections 31 of adjacent first electrodes 3. The bottom surface of the top section 31 of the first electrode 3 and the bottom surface of the second electrode 4 are flush, and at least one of the top section 31 and the bottom section 32 gradually increases in its respective radial dimension in a direction from bottom to top.

[0144] Corresponding to the top section 31 and the bottom section 32 of the first electrode 3, the substrate 1 also includes a top substrate layer 12 accommodating the top section 31 of the first electrode 3 and a bottom substrate layer 13 accommodating the bottom section 32 of the first electrode 3, and the top substrate layer 12 and the bottom substrate layer 13 can be integrally formed without a clear boundary.

[0145] Among them, the bottom section 32 is located at the bottom surface layer of the substrate 1, and the bottom surface layer of the substrate 1 will not be subjected to special process manufacturing in the process, and the top substrate layer 12 can serve as a rewiring layer, which is higher than the bottom substrate layer 13, facilitating processing of the top surface of the top substrate layer 12 during the production process. Preferably, the junction cross section of the first type semiconductor 2113 and the bottom conductive layer 2121 is flat, and the junction cross section of the bottom conductive layer 2121 and the bonding layer 2122 is flat, which can increase the light reflection on the bottom side of the light-emitting layer 2112 and increase the light emission.

[0146] Figures 5A-6D A method for manufacturing a light-emitting diode chip is shown. Figures 5A-5D One of the methods is shown, Figures 6A-6D Another method is shown, Figures 6A-6D The method shown is superior to Figures 5A-5D The method shown, therefore Figures 6A-6D The performance of the manufactured light-emitting diode chip is superior to Figures 5A-5D The light-emitting diode chip produced by the process.

[0147] First, the process of Figures 5A-5D will be described. Part of the process flow includes:

[0148] STEP1: Provide a substrate 1, an electrode layer blank 2123 and a light-emitting body blank stacked in order from bottom to top, wherein the light-emitting body blank includes a first type semiconductor blank, a light-emitting layer blank and a second type semiconductor blank stacked in order from bottom to top (i.e., the precursor of the light-emitting body 211 containing the first type semiconductor 2113, the second type semiconductor 2111 and the light-emitting layer 2112); STEP2: Etch the light-emitting body blank to form a plurality of light-emitting bodies 211, and expose the top surface of the electrode layer blank 2123 between adjacent light-emitting bodies, which can be obtained after the step is completedFigure 5A The structure shown.

[0149] The process also includes STEP 3: covering the light-emitting body 211 and the electrode layer blank 2123 with a hard mask 214; and STEP 4: etching downward between adjacent light-emitting bodies 211 to form an electrode layer 212, exposing the top surface of the substrate 1 between adjacent electrode layers 212.

[0150] The STEP4 process is in Figure 5B and Figure 5C The text shows ( ) Figure 5B and Figure 5C (These are two phases that appear sequentially in the etching step). In this step, photoresist 5 needs to be applied to each light-emitting element. Due to the special nature of the hard mask 214 material (e.g., silicon oxide), the portion covering the sidewalls of the light-emitting element (referred to as the sidewall portion) has the same etching rate as the portion covering the electrode layer 2123 blank (referred to as the horizontal portion 2141). It can be understood that during the etching process, although the target is only to etch the horizontal portion 2141, the sidewall portion inevitably gets etched due to its equally high etching rate, resulting in damage to the light-emitting element structure. To avoid this, the photoresist 5, in addition to covering the sidewalls of the light-emitting element, also needs to partially cover a portion of the horizontal portion 2141 of the hard mask 214. In this step, the hard mask 214 that is etched away is shown by the dashed box 6.

[0151] from Figure 5C As can be seen, after the etching process, the hard mask 214 itself forms a stepped structure consisting of a horizontal portion 2141 on the sidewall of the light-emitting diode.

[0152] Then proceed to STEP 5: remove the photoresist 5, and completely cover the substrate 1 and the light-emitting diode including the electrode layer 212 and the light-emitting body 211 with the insulating layer 217. The morphology after this process is as follows: Figure 5D As shown, since the hard mask 214 has a stepped structure, the insulating layer 217 covering it also forms a stepped surface 2175. The two ends of this stepped surface 2175 are referred to as the first edge 2174a and the second edge 2174b. It can be seen that the wall defined between the first edge 2174a and the second edge 2174b is set to extend horizontally, thus forming a stepped surface. The first edge 2174a is formed between the stepped surface 2175 of the insulating layer 217 and the top section 2171 of the insulating layer, and the second edge 2174b is formed between the stepped surface 2175 of the insulating layer 217 and the bottom section 2172 of the insulating layer. The first edge 2174a and the second edge 2174b respectively constitute corner structures.

[0153] Figures 6A-6DAn improvement to the process of Figures 5A-5D is shown. Part of the process flow includes:

[0154] STEP1: providing a substrate 1, an electrode layer blank 2123 and a light emitting body blank stacked from bottom to top, wherein the light emitting body blank comprises a first type semiconductor blank, a light emitting layer blank and a second type semiconductor blank stacked from bottom to top (i.e. a precursor of the light emitting body 211 comprising the first type semiconductor 2113, the second type semiconductor 2111 and the light emitting layer 2112), and a first top conductive layer blank (corresponding to a precursor of the first top conductive layer 2161) is further stacked on the light emitting body blank.

[0155] STEP2: applying a top mask 7 on the top of the first top conductive layer blank at predetermined positions, and then etching the light emitting body blank to form a plurality of light emitting bodies 211, each of which has a first top conductive layer 2161 on the top, and the top surface of the electrode layer blank 2123 is exposed between adjacent light emitting bodies 211. The structure shown in Figure 6A can be obtained after this step.

[0156] STEP3: covering the light emitting bodies 211 and the electrode layer blank 2123 with a hard mask 214. The structure shown in Figure 6B can be obtained after this step.

[0157] In some embodiments, the hard mask 214 is a transparent insulating material, and the electrode layer blank 2123 and the hard mask 214 have a high selectivity ratio. In this embodiment, the selectivity ratio between the electrode layer blank 2123 and the hard mask 214 is greater than or equal to 2.

[0158] STEP4: applying photoresist 5 on each light emitting body, and etching downward between adjacent light emitting bodies 211 to form electrode layers 212, and the top surface of the substrate 1 is exposed between adjacent electrode layers 212.

[0159] The appearance after STEP4 is shown in Figure 6C . In this embodiment, the photoresist 5 only covers the side wall and the top surface of the hard mask 214, and does not extend to the top surface of the electrode layer blank 2123. Since the surface of the light emitting body 211 is covered with photoresist 5, the hard mask 214 on the top and the side wall of the light emitting body is protected, while the part of the hard mask (shown by the dashed box 6) covering the electrode layer blank 2123 is not protected. Finally, the hard mask 214 on the top and the side wall of the light emitting body is retained, while the part of the hard mask (shown by the dashed box 6) covering the electrode layer blank 2123 is etched away.

[0160] Further, since the electrode layer blank 2123 has a high selectivity ratio with the hard mask 214, when the photoresist 5 is partially consumed during the etching process, the electrode layer blank 2123 is etched away first due to the high selectivity ratio, and thus the hard mask 214 on the sidewall of the light emitting body 211 will not be etched away when the electrode layer 212 is formed.

[0161] As can be seen from Figure 6C , after the etching step and removal of the photoresist, the sidewall of the light emitting diode (without the insulating layer) is a smooth structure without steps.

[0162] Subsequently, STEP 5 is entered: the insulating layer 217 is formed on the substrate 1 and the light emitting diode including the electrode layer 212 and the light emitting body 211. The structure after this process is shown in Figure 6D , since the sidewall of the light emitting diode does not have a step structure before the insulating layer 217 is formed, the insulating layer 217 formed thereon will also not have a step structure.

[0163] According to the manufacturing method shown in Figures 6A-6D , due to the unique application of the hard mask 214 and the photoresist 5, the etching step and the step of applying the insulating layer 217 after etching will not produce steps on the sidewall of the light emitting diode. Since the sidewall of the insulating layer does not form steps, the size of the light emitting body of the light emitting diode unit can be made larger and the light emitting area can be made larger under the condition of a certain pixel size, so that the light emission rate can be improved.

[0164] Figures 6A-6D The light emitting diode chip manufactured according to the manufacturing method and its variants can have the same or similar structure as in Figures 1A-4B , and the description of the embodiments of Figures 1A-4B should be understood as a description of the products manufactured according to Figures 6A-6D .

[0165] From the above, those skilled in the art will readily recognize that alternative structures of the disclosed structures can be used as alternative embodiments, and the disclosed embodiments can be combined to produce new embodiments, which are also within the scope of the appended claims.

Claims

1. A light emitting diode chip (100), characterized in that The light emitting diode chip comprises a substrate (1) and a plurality of light emitting diode units (21) arranged in an array on the substrate, wherein each of the light emitting diode units comprises: a light emitting body (211) comprising a first type semiconductor (2113), a light emitting layer (2112) and a second type semiconductor (2111) stacked in sequence from bottom to top, an electrode layer (212) having a radial dimension greater than that of the light emitting body (211) and positioned at the bottom of the light emitting body to conductively connect the light emitting body and the electrode of the light emitting diode chip, a hard mask (214) covering the sidewalls of the light emitting layer and the first type semiconductor; and an insulating layer (217) covering the sidewalls of the electrode layer (212) and the sidewalls of the hard mask (214), wherein the insulating layer extends in a continuous downward extending trend at the connecting position of the light emitting body and the electrode layer, so that the outer wall of the insulating layer does not form a step at the connecting position of the electrode layer and the light emitting body, the step being defined as a wall surface mainly extending horizontally.

2. The light emitting diode chip of claim 1, wherein, Each of the light emitting diode units forms a columnar structure with a radial dimension gradually decreasing from bottom to top, and the insulating layer (217) comprises an insulating layer top section (2171) covering the outer side of the light emitting body and an insulating layer bottom section (2172) covering the outer side of the electrode layer (212), wherein: the inclination angle of the outer wall of the insulating layer top section (2171) is greater than that of the insulating layer bottom section (2172); or the inclination angle of the outer wall of the insulating layer top section (2171) is equal to that of the insulating layer bottom section (2172); or the inclination angle of the outer wall of the insulating layer top section (2171) is less than that of the insulating layer bottom section (2172).

3. The light emitting diode chip of claim 2, wherein, the outer wall of the insulating layer top section (2171) has an unchanging inclination angle from its top end to its bottom end, and / or the outer wall of the insulating layer bottom section (2172) has an unchanging inclination angle from its top end to its bottom end.

4. The light emitting diode chip of claim 2, wherein, the connecting position of the outer wall of the insulating layer bottom section (2172) and the outer wall of the insulating layer top section (2171) forms only one edge (2173) around the light emitting diode unit; or the outer wall of the insulating layer top section smoothly transitions to the outer wall of the insulating layer bottom section.

5. The light emitting diode chip of claim 4, wherein, the outer wall of the insulating layer bottom section (2172) forms at least one edge around the light emitting diode unit; and / or the insulating layer top section forms at least one edge around the light emitting diode unit, wherein the vertical inclination component of the wall surface (2176) between any pair of adjacent edges on the outer wall of the insulating layer is greater than the horizontal inclination component.

6. The light emitting diode chip of claim 1, wherein, The hard mask extends downward from a top end of the light emitting body and stops at a bottom end of the light emitting body, and the insulating layer extends from the top end of the light emitting body to a bottom end of the electrode layer (212).

7. The light emitting diode chip of claim 6, wherein, The hard mask comprises a plurality of sub-layers arranged radially from inside to outside.

8. The light emitting diode chip of claim 1, wherein, The light emitting diode unit further comprises: a top conductive layer (216) covering a top surface and a sidewall of the light emitting body.

9. The light emitting diode chip of claim 8, wherein, The top conductive layer (216) comprises a first top conductive layer (2161) covering only the top surface of the light emitting body (211) and a second top conductive layer (2163) covering a top surface of the first top conductive layer (2161) and covering an outer sidewall of the insulating layer (217), wherein: a top end of the insulating layer (217) is lower than a top surface of the first top conductive layer (2161), or the top end of the insulating layer and the top surface of the first top conductive layer are flush.

10. The light emitting diode chip of any of claims 1-7, wherein, The light emitting diode chip further comprises: a first electrode (3) disposed at the substrate and positioned at a bottom of the light emitting diode unit, the first electrode being conductively connected via the electrode layer and the first type semiconductor (2113); and a second electrode (4), a portion of the second electrode being disposed at the substrate and positioned between a pair of the light emitting diode units having a first adjacent relationship, the portion of the second electrode being conductively connected with the second type semiconductor (2111), wherein the portion of the second electrode is embedded in the substrate (1).

11. The light emitting diode chip of claim 10, wherein, The second electrode (4) is disposed around each of the light emitting diode units to form between the light emitting diode units having the first adjacent relationship, and / or In a predetermined cross section taken by a plane in which an axis of the light emitting diode unit lies, the second electrode is formed as a trapezoidal cross section whose radial dimension gradually increases or decreases from bottom to top.

12. The light emitting diode chip of claim 10, wherein, The light emitting diode chip further comprises a top conductive layer coated outside the insulating layer, a top opening of the insulating layer to allow the top conductive layer to conductively contact the second type semiconductor, and a dielectric material opening between adjacent light emitting diode units to allow the top conductive layer to conductively contact the second electrode.

13. The light emitting diode chip of any of claims 1-7, wherein, The electrode layer comprises: a bottom conductive layer (2121) located at a bottom side of the first type semiconductor (2113); a bonding layer (2122) located at a bottom side of the bottom conductive layer.

14. The light emitting diode chip of claim 13, wherein, A ratio of a thickness of the bonding layer to a thickness of the hard mask is 10:1-1:

1.

15. The light emitting diode chip of claim 14, wherein, A ratio of a thickness of the bonding layer to a thickness of the hard mask is 2:1; and / or the thickness of the bonding layer is 400 nm and the thickness of the hard mask is 200 nm.

16. The light emitting diode chip of claim 10, wherein, The first electrode (3) comprises a top segment (31) and a bottom segment (32), at least one of the top segment and the bottom segment is formed as a columnar structure perpendicular to the substrate, a radial dimension of the top segment is smaller than a radial dimension of the bottom segment, and the second electrode (4) is located between the top segments (31) of adjacent first electrodes.

17. The light emitting diode chip of claim 16, wherein, a bottom surface of the top section of the first electrode and a bottom surface of the second electrode are flush; and / or at least one of the top section and the bottom section gradually increases its respective radial dimension in a direction from bottom to top.

18. The light emitting diode chip of claim 10, wherein, a gap exists between the pair of light emitting diode units having the first adjacent relationship, the portion of the second electrode (4) is positioned directly below the gap, and a bottom end of a pair of light emitting diode units having a second adjacent relationship is immediately adjacent.

19. The light emitting diode chip of claim 18, wherein, the electrode layer of the pair of light emitting diode units having the second adjacent relationship at least partially obstructs a second electrode between the pair of light emitting diode units in a vertical direction.

20. The light emitting diode chip of any of claims 1-7, wherein, the light emitting diode chip is a micro light emitting diode chip using a micron-scale LED as a light emitting diode.

21. The light emitting diode chip of claim 1, wherein, the insulating layer extends from a sidewall top end of the light emitting body to a sidewall bottom end of the electrode layer in a continuous downward extending trend, so that an outer wall of the insulating layer does not form a step on a complete sidewall of the light emitting diode unit.

22. The light emitting diode chip of claim 1, wherein, an included angle between a main extension direction of any one section of the insulating layer and a vertical plane is less than 30°.

23. The light emitting diode chip of claim 1, wherein, an outer sidewall of the insulating layer includes a section whose main extension direction is a horizontal direction but whose radial extension dimension in the horizontal direction is no more than 100 nm.

24. The light emitting diode chip of claim 1, wherein, characterized in that a maximum horizontal width of the light emitting diode unit is less than or equal to 4 μm.

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