Artificial synaptic transistor based on thermal field regulation and control and manufacturing method thereof

Abstract

The invention relates to the field of research, development and application of semiconductor devices, in particular to an artificial synaptic transistor based on thermal field regulation and control and a manufacturing method of the artificial synaptic transistor. The artificial synapse transistor comprises a substrate, a carbon nanotube channel, a gate dielectric layer, a gate electrode and a source and drain electrode in contact with the carbon nanotube channel, the substrate is of a silicon dioxide / heavily-doped P-type silicon wafer / silicon dioxide laminated structure from bottom to top, and the transistor channel is an irregular single-walled carbon nanotube layer obtained through water bath heating deposition. The gate dielectric layer is a hafnium oxide layer obtained by atomic layer deposition, and the gate electrode and the source and drain electrodes are of a titanium / gold laminated composite structure from bottom to top. According to the invention, the charge trap state at the dielectric interface between the channel and the top of the carbon nano tube is regulated and controlled by using the temperature, so that the conductance polymorphic and progressive control of the device is realized, and the synaptic weight is effectively regulated.

Description

TECHNICAL FIELD

[0001] The present application relates to the research and application field of semiconductor devices, in particular to an artificial synapse transistor based on thermal field regulation and a manufacturing method thereof, which is suitable for brain-like chips, biological sensing, programmable logic devices, etc. BACKGROUND

[0002] The explosive data growth in the information age is posing a serious challenge to the traditional von Neumann computing architecture, especially when dealing with massive unstructured data, the energy efficiency and speed bottleneck is increasingly prominent. Inspired by the efficient information processing mechanism of the biological brain, neuromorphic computing builds artificial networks that simulate biological neurons and synapses, showing strong parallel processing, adaptive learning ability and high fault tolerance, providing a promising way to break through the computing bottleneck. In this system, the plasticity of artificial synapses, i.e. the ability to adjust the connection strength, such as long-term potentiation (LTP) and long-term depression (LTD), is the cornerstone of learning and memory function. Therefore, it is crucial to develop high-performance artificial synapse devices.

[0003] The artificial synapse scheme based on reconfigurable transistors has the ability to dynamically regulate the polarity, threshold and other electrical properties of the device, providing an effective way to achieve synaptic plasticity, and is expected to improve system energy efficiency and integration through single-device multifunctionalization. To achieve this goal, researchers have explored a variety of physical mechanisms to dynamically regulate device conductance. Electric field regulation is one of the most commonly used strategies, floating gate transistors change the floating gate charge through tunneling effect or hot electron injection to simulate weights, but usually face high programming voltage, slow speed and reliability challenges; ferroelectric field effect transistors use the remanent polarization of ferroelectric materials to regulate the channel, limited by the speed of ferroelectric domain switching and the fatigue effect, limiting its durability; electrolyte gate-controlled transistors use the double-layer effect to achieve strong static doping at low voltage, but the response speed is limited by the slower ion migration, and long-term stability and electrolyte compatibility are still potential problems. In addition to the electric field, other mechanisms have also been widely explored, chemical doping schemes introduce / remove dopants through electrochemical reactions to regulate conductance, although non-volatile can be achieved, but the speed is slow and it is difficult to accurately control the doping distribution; devices based on phase change materials use the significant resistance difference between crystalline and amorphous states of the material to store weights, however, the phase change process usually requires higher energy to trigger, resulting in higher power consumption, and may have material fatigue and phase separation problems, affecting cycle stability. Although these diverse schemes have made significant progress in simulating synaptic functions, they generally have inherent limitations in power consumption, speed, accuracy, stability, or a combination of these factors. More importantly, these studies often pay less attention to the compatibility of devices with biological systems, such as high operating voltage, potential chemical toxicity or material itself biological safety risk, which greatly limits their practical potential in neuromorphic applications that require direct interaction with biological environments.

[0004] The patent with publication number CN113659078A proposes a new type of synaptic transistor device based on polyimide gate insulating layer and its preparation method, which relies on electric field to regulate the interface action of gate insulating layer and semiconductor layer, lacks thermal field regulation means, and cannot simulate the temperature-dependent synaptic plasticity in biological nervous system. The temperature adaptability is limited to room temperature environment. The semiconductor layer uses organic polymers such as poly-3-hexylthiophene, and the carrier mobility is much lower than that of carbon nanotubes, resulting in limited device response speed and on-off ratio; and the organic polymer material does not have biological compatibility, which cannot meet the application of neural interface and other interactions with biological environment. The patent with publication number CN119584756A proposes a thermoelectric-driven fiber-based organic electrochemical synaptic transistor and its preparation method and application. Since the electric field is not used to regulate the conductance characteristics or synaptic function of the device, it is essentially still dependent on single electric field regulation; the material system uses composite fibers and ionic gel electrolyte, and the stability of ionic gel is poor, which is easy to fail in long-term use; in addition, there is no temperature-sensitive charge trap layer formed by HfO2, which cannot realize the temperature-driven charge trapping / de-trapping regulation and reversible conversion of device polarity.

[0005] In order to overcome the above limitations, it is necessary to explore new materials and regulation mechanisms. Single-walled carbon nanotubes (CNT) have become an ideal choice for building artificial synapses due to their unique one-dimensional structure, high carrier mobility, excellent electrostatic regulation ability, high sensitivity to environment and potential biological compatibility. At the same time, temperature regulation as a new and biologically inspired means is attracting attention. Temperature not only deeply affects the performance of semiconductors, but also regulates key processes such as neurotransmitter release and receptor binding in biological nervous systems. Therefore, using temperature regulation for artificial synapses is expected to achieve more biologically adaptive neural morphological hardware that is closer to the biological thermodynamic response mechanism, and may form a multi-physical field cooperative regulation with electricity, light and other fields to expand the device function. SUMMARY

[0006] The purpose of the present application is to propose an artificial synaptic transistor based on thermal field regulation and its manufacturing method, which uses temperature regulation to regulate the charge trap state at the interface between carbon nanotube channel and top dielectric, realizes the gradual control of device conductance polymorphism, and further realizes the effective regulation of synaptic weight.

[0007] The technical solution of the present application is: An artificial synapse transistor based on thermal field regulation, comprising a substrate, a carbon nanotube channel, a gate dielectric layer, a gate electrode and a source-drain electrode in contact with the carbon nanotube channel, the overall structure being: silicon dioxide / heavily doped P-type silicon slice / silicon dioxide / titanium / gold / semiconductor carbon nanotube / hafnium oxide / titanium / gold, a self-bottom-up laminated composite structure; wherein the substrate is a self-bottom-up laminated structure of silicon dioxide / heavily doped P-type silicon slice / silicon dioxide, the transistor channel is an irregular single-walled carbon nanotube layer obtained by water bath heating deposition, the gate dielectric layer is a hafnium oxide layer obtained by atomic layer deposition, and the gate electrode and the source-drain electrode are a self-bottom-up titanium / gold laminated composite structure; a layer of non-metered oxide HfO x , x = 2 ~ 10.

[0008] The artificial synapse transistor based on thermal field regulation, the hafnium oxide layer obtained by atomic layer deposition dopes the carbon nanotube channel, thereby obtaining a thermal field-adjustable charge trap state at the interface between the channel and the top dielectric layer; a thermoelectric device is carried by a phase change heat-conducting material below the substrate, so that the thermoelectric device and the carbon nanotube field effect transistor are connected through the phase change heat-conducting material; the thermoelectric device is connected to an external direct current power supply, the temperature of the carbon nanotube field effect transistor is regulated based on the Peltier effect, the rate and equilibrium state of the interface trap capturing and releasing charges are significantly affected by the temperature change, and in combination with the electric field activation of the gate voltage, the number of trapped charges can be non-volatilely changed, thereby effectively regulating the carrier concentration and conductivity of the carbon nanotube channel, realizing multi-state and progressive control of the device conductance, and simulating an artificial synapse based thereon.

[0009] A manufacturing method of an artificial synapse transistor based on thermal field regulation, comprising the following steps: (1) The substrate is ultrasonically cleaned by acetone and isopropyl alcohol in sequence to remove surface impurities, and then the surface residues are further removed by an oxygen plasma cleaning machine; (2) A photoresist mask layer is accurately formed on the substrate by using a photolithography technology, the maximum effective range of the mask layer is a 2*2 cm exposure area, the source-drain electrode area required is exposed on the substrate, and a titanium / gold laminated metal electrode is prepared in the specified area by a vacuum electron beam evaporation technology, so as to construct the source-drain electrode of the transistor; (3) The surface residues of the silicon slice and the source-drain electrode are removed by using an oxygen plasma cleaning technology; (4) After the primer base glue is uniformly spin-coated on the substrate, the substrate is immersed in a carbon nanotube solution treated by ultrasonic dispersion, and the carbon nanotube channel layer of the transistor is deposited on the substrate by a water bath heating method; (5) First, by lithography technology, the photoresist mask layer is precisely constructed on the substrate on which the carbon nanotube channel has been deposited, and the carbon nanotube channel region is patterned; then, by using oxygen plasma cleaning technology, the carbon nanotubes outside the channel are etched, and the excess carbon nanotube film is effectively removed; (6) By using atomic layer deposition technology, hafnium oxide dielectric layer is uniformly deposited on the carbon nanotube channel, and doping of the carbon nanotube channel is realized by hafnium oxide, forming an interface doping layer that can be controlled by thermal field; (7) By using lithography technology, the required gate electrode evaporation area is exposed on the hafnium oxide dielectric layer, and by using vacuum electron beam evaporation technology, a titanium / gold gate electrode in close contact with the hafnium oxide dielectric layer is prepared; (8) By using lithography technology, a photoresist mask layer is made, and the required hafnium oxide etching area is exposed, exposing the titanium / gold source and drain metal electrodes in contact with the carbon nanotube channel and the substrate. Previously, by using reactive ion etching technology, carbon tetrafluoride is used as the reaction gas to accurately etch the hafnium oxide, and finally a complete carbon nanotube field effect transistor array is obtained; (9) A thermoelectric device compatible with the carbon nanotube field effect transistor is constructed, and the surface of the thermoelectric device is sprayed with acetone and isopropyl alcohol to remove surface impurities; then, the surface of the thermoelectric device is attached to a phase change heat conducting material, and the substrate of the transistor is tightly attached to the surface of the phase change heat conducting material. By applying a direct current power supply, the surface temperature of the thermoelectric device is accurately controlled, and the working temperature of the transistor is flexibly adjusted.

[0010] In steps (2) and (7) of the method for manufacturing the artificial synapse transistor based on thermal field regulation, the two end source and drain electrodes and the top gate electrode are deposited using an electron beam evaporator, the titanium layer has a thickness in the range of 5-6 nm, and the gold layer has a thickness in the range of 50-51 nm.

[0011] In step (3) of the method for manufacturing the artificial synapse transistor based on thermal field regulation, the oxygen plasma cleaning time is 20 min, the oxygen flow rate is 180 sccm, and the power is 200 W.

[0012] In step (4) of the method for manufacturing the artificial synapse transistor based on thermal field regulation, the carbon nanotubes are mixed with toluene at a mass ratio of 1:8, and the mixture is ultrasonically dispersed and centrifugally purified to remove carbon nanotube bundles and insoluble substances, obtaining a semiconductor carbon nanotube solution. The supernatant is collected as the channel material. The carbon nanotube solution is ultrasonically treated at a frequency of 40 Hz, a power of 100 W, and a time of 5 min. The ultrasonically dispersed carbon nanotube solution is transferred to a culture dish; In the process of depositing the carbon nanotube film, the cleaned substrate is first heated to 180 DEG C on a hot plate for 30 min to remove moisture on the substrate. To enable the carbon nanotubes to be better adsorbed on the substrate and uniformly dispersed, a Primer primer is spin-coated on the top surface of the substrate by a spin coater, and then the substrate is baked at 105 DEG C on a hot plate for 2 min. The baked substrate is immersed in the carbon nanotube solution in a culture dish under ultrasonic oscillation, and the culture dish is placed in a 60 DEG C water bath, wherein the height of the deionized water surface just exceeds the height of the carbon nanotube solution in the culture dish. After 2-3 hours, the deposition of the carbon nanotube film is completed.

[0013] The method for manufacturing the artificial synapse transistor based on thermal field regulation, in step (5), LOR3A and S-1813 double-layer photoresist are spin-coated on the surface of the carbon nanotube film in sequence, and the exposed pattern is a square region with a side length of 180-182 μm; the exposed sample is placed in an oxygen plasma cleaning machine, the oxygen flow rate is 180 sccm, the power is 200 W, and the cleaning time is 2 min to remove the excess carbon nanotube film outside the channel.

[0014] The method for manufacturing the artificial synapse transistor based on thermal field regulation, in step (6), a 40 nm hafnium oxide dielectric layer is prepared above the carbon nanotube film at a temperature of 200 DEG C using an atomic layer deposition device; the hafnium precursor is selected as tetra(dimethylamino)hafnium, and the oxygen source precursor is water; the deposition process parameters include temperature setting, gas flow rate setting, and pulse time setting; in terms of temperature, the temperature of the hafnium precursor and the substrate is a key parameter, and the deposition temperature is 200 DEG C; the gas flow rate needs to be accurately controlled, and the pulse time refers to the residence time of the precursor gas in the reaction chamber; the deposition cycle process starts with the introduction of the hafnium precursor gas, followed by adsorption and carrier gas purging; then the oxygen source precursor gas is introduced, and after the reaction, carrier gas purging is performed again; the above steps are repeated to form one atomic layer deposition cycle, and 0.05-0.2 nm of hafnium oxide film is deposited in each cycle, and the film thickness is accurately controlled by controlling the number of cycles; wherein the reaction temperature is set to 200 DEG C, the flow rate of the hafnium precursor is 30 sccm, the flow rate of water vapor is 150 sccm, and the flow rate of nitrogen as the carrier gas is 100 sccm; in each cycle, the pulse time of the hafnium precursor is 0.5 seconds, the pulse time of the water vapor is 1 second, and the carrier gas purging time is 5 s; after 200-500 atomic layer deposition cycles, a 10-50 nm thick hafnium oxide dielectric layer is prepared.

[0015] The step (8) in the manufacturing method of the artificial synapse transistor based on thermal field regulation is etching by using a reactive ion etching machine, and the etching conditions are as follows: carbon tetrafluoride with a flow rate of 50 sccm is used as etching gas, the pressure is 5.0-5.5 Pa, the power is 100 W, and the etching time is 5-10 min.

[0016] The step (9) in the manufacturing method of the artificial synapse transistor based on thermal field regulation is that the surface of the thermoelectric device is sequentially sprayed with acetone and isopropyl alcohol for cleaning, and after standing for 1 min, the surface impurities are removed by wiping with a dust-free cloth, and the phase change heat conduction material is attached to the surface of the thermoelectric device and attached to the bottom of the carbon nanotube field effect transistor substrate; the surface temperature of the thermoelectric device is regulated by an external direct current power supply, the temperature range is-25 ℃-120 ℃, the temperature change step is accurate to 0.1 ℃, and the temperature change rate reaches 3.84 ℃ / s.

[0017] The design idea of the present application is: The rapid data growth in the information age exposes the serious limitations of the traditional von Neumann computing architecture, which is low in speed and energy efficiency when processing unstructured data such as video or biological signals. In contrast, the human brain exhibits excellent parallel processing, adaptive learning and fault tolerance. Inspired by this biological efficiency, neuromorphic computing aims to simulate neurons and synapses, with plastic artificial synapses such as long-term potentiation (LTP) and long-term depression (LTD) enabling learning and memory functions, so its development is crucial for the next generation of computing.

[0018] Reconfigurable transistors, which can dynamically adjust electrical properties such as polarity and threshold voltage, are ideal platforms for artificial synapses. Unlike traditional fixed-function devices, these transistors provide multi-functionality within a single cell, improving energy efficiency and integration density. This adaptability supports in-memory computing and allows conductance adjustment to simulate synaptic weight changes, directly replicating biological excitatory and inhibitory behavior. This multi-functionality makes reconfigurable transistors a cornerstone for building efficient, brain-like systems. Despite their potential, existing reconfigurable transistor methods face significant obstacles. For example, floating gate transistors require high programming voltages, are slow, and have poor reliability. Ferroelectric field effect transistors reduce voltage requirements but are limited by slow domain switching speed and material fatigue. Electrolyte-gated transistors use ion migration for low-voltage operation but lack sufficient response time and stability. Other methods, such as chemical doping or phase change materials, also suffer from slow speed, high power consumption, or precision issues. Furthermore, these designs often overlook biological compatibility, with high voltages and toxic materials hindering their application in biological sensors or neural interfaces.

[0019] In view of this, exploring new materials and regulatory mechanisms becomes inevitable. Temperature control provides a biologically inspired solution to these challenges, affecting semiconductor properties such as carrier mobility and conductance, while also being associated with biological processes such as neurotransmitter regulation. Unlike electrical or chemical methods, thermal regulation can achieve fast, accurate, and non-volatile adjustments over a wide range, avoiding high voltages or toxic substances. This approach is consistent with biological thermodynamics, enhancing the compatibility of neuromorphic systems interacting with living organisms. Single-walled carbon nanotubes (CNTs) are ideal for artificial synapses due to their one-dimensional structure, excellent carrier mobility, and low interface defect density. Their flexibility (bendable to 3mm radius) is suitable for wearable electronic devices, while their carbon-based properties ensure biocompatibility. The sensitivity of CNTs to temperature further enhances their suitability for thermal regulation, enabling precise control over electrical properties.

[0020] The present application prepares single-walled carbon nanotube channels by using a water bath heated solution deposition method, and combines technologies such as photolithography, gold evaporation, and atomic layer deposition to manufacture hafnium oxide doped carbon nanotube field effect transistors (CNTFET). To enhance the temperature sensitivity of CNTFET, atomic layer deposition (ALD) technology is used to deposit hafnium oxide (HfO2) on the CNT channel to achieve doping of the CNT, and a temperature-sensitive charge trap layer is constructed above the channel. The present application selects TEC to apply precise and dynamic temperature control to the device, covering a wide range of -25 ℃ to 120 ℃, and temperature changes significantly affect the rate and equilibrium state of interface trap capture and release of charges. Combined with the electrical activation of the gate voltage, temperature can non-volatilely change the number of trapped charges, effectively regulating the carrier concentration and conductivity of the CNT channel. At 25 ℃, the channel polarity is bipolar; while when the temperature rises to 120 ℃, the channel polarity changes to N-type. Under temperature regulation, the T-RFET can realize reversible conversion of bipolar and N-type, exhibiting the advantages of multi-physical coupling regulation. During the test, we comprehensively characterized key artificial synapse performance parameters including excitatory postsynaptic current, paired pulse facilitation, spike duration-dependent plasticity, and artificial synapse weight regulation under different voltage stimulation, providing theoretical support and technical path for breaking the boundaries of traditional computing and building truly brain-like intelligent systems.

[0021] The application realizes the dynamic characteristics of reconfigurable transistors (T-RFET) by thermoelectric devices (TEC), and successfully simulates the excitatory / inhibitory conversion of biological synapses. We designed a temperature-driven trap capture / decapture T-RFET, built a charge storage interface above the CNT channel, and used the defect states at the interface of HfO2 layer as the top gate dielectric layer as temperature-sensitive charge trap / de-trap centers. By integrating TEC, we realized precise (temperature control accuracy 0.1℃) and dynamic (temperature change rate 3.84℃ / s) temperature control, covering a wide range of-25℃ to 120℃. Temperature change significantly affects the charge capture and release rate and equilibrium state of the interface trap, combined with the field activation of the gate voltage, non-volatilely regulates the number of trap charges, thereby effectively changing the carrier concentration and conductivity of the CNT channel. Experiments show that temperature regulation reversibly switches the polarity of T-RFET (converts between N-type and bipolar type), and through precise and stepwise temperature regulation, realizes the multi-state and gradual control of the device conductance, successfully simulates the long-term potentiation and long-term depression behavior of synapses. This study takes temperature as the core regulation parameter, shows the advantages of thermal field regulation in control accuracy and wide temperature range, uses temperature as a unique and potentially biocompatible physical field, and constructs a thermal-electric coupling regulation mechanism, providing a new paradigm for synaptic plasticity simulation, and opening up a new way for developing biologically reasonable multi-physical field regulation neural morphological devices and constructing flexible and environmentally adaptable neural morphological computing systems.

[0022] The application has the advantages and beneficial effects that: 1、The artificial synapse transistor based on thermal field regulation disclosed by the application takes carbon nanotube field effect transistor (CNTFET) as the core device carrier, integrates thermoelectric devices and constructs a temperature-sensitive charge trap layer, so that the CNTFET has the function of simulating the synaptic plasticity of biological synapses, and finally forms an artificial synapse transistor based on thermal field regulation. The application utilizes the characteristics of high carrier mobility, significant on-off ratio and obvious polarity transition of the thermally reconfigurable carbon nanotube field effect transistor, realizes the regulation of temperature on the performance of the artificial synapse, reversibly changes the polarity of the carbon nanotube field effect transistor through temperature regulation of the transistor by the thermoelectric device, efficiently and conveniently realizes the reversible change of the polarity of the carbon nanotube field effect transistor, realizes the control of temperature on the synaptic EPSC (excitatory postsynaptic current), PPF (paired pulse facilitation), SDDP (spike duration-dependent plasticity), SADP (spike amplitude-dependent plasticity) and synaptic weight adjustment at different temperatures, ensures the stability of the device testing process, and provides theoretical support and technical path for breaking the traditional computing boundary and constructing a truly brain-like intelligent system.

[0023] 2. The artificial synapse transistor based on thermal field regulation utilizes the method of water bath heating and deposition of carbon nanotube solution to deposit and prepare a carbon nanotube channel, and the preparation process is simple, effective, clean and lossless, and the uniformity of the device performance is ensured.

[0024] 3. The artificial synapse transistor based on thermal field regulation utilizes atomic layer deposition technology to grow a 40 nm hafnium oxide dielectric layer to realize thermal doping of oxygen vacancies of the carbon nanotube channel, and a temperature-sensitive charge trap layer is constructed, so that the polarity conversion of the carbon nanotube field effect transistor under temperature control is realized, the process is simple and effective, and the device has high carrier mobility and polarity conversion performance.

[0025] 4. The artificial synapse transistor based on thermal field regulation innovatively uses a miniaturized thermoelectric device to realize dynamic temperature control, and the evolution law of the electrical characteristics of the CNTFET in a wide temperature range (-20 ℃~120 ℃) is systematically studied. The device exhibits a bipolar / N-type polarity switchable phenomenon in the temperature variation interval of 20 ℃~70 ℃ for the first time, and a temperature-electric parameter mapping model is constructed. Through the synergistic effect of in-situ thermoelectric refrigeration / heating dual modes, the temperature control of the artificial synapse EPSC, PPF, SDDP, SADP and synaptic weight adjustment at different temperatures is realized efficiently, conveniently and quickly, which provides a physical basis for the time-varying characteristic regulation of the CNTFET. The invention breaks through not only the progress of the adaptability of the neuromorphic device in the dynamic environment, but also opens up a new path for the development of intelligent transistors with temperature self-sensing function, and shows important application value in the thermal management of brain-like chips, programmable logic devices and biological sensing fields. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 : a is a three-dimensional structure schematic diagram of the artificial synapse transistor based on thermal field regulation; b is a thermal field regulation mechanism schematic diagram. The artificial synapse device is composed of a carbon nanotube transistor with a top gate structure, and the dielectric layer is a 30 nm thick hafnium oxide layer.

[0027] Figure 2 is a front structure schematic diagram of the artificial synapse transistor based on thermal field regulation. In the figure, the bottommost part is a silicon dioxide (SiO2) layer, and the upper part is a heavily doped silicon (P + Si) substrate. Above the substrate is a carbon nanotube (Carbon Nanotube) connected to a source (S) and a drain (D) as a channel material of the transistor. The source and the drain are made of a metal material for injecting and collecting charge carriers to the carbon nanotube channel. The carbon nanotube is covered with a non-metering oxide (NDO, i.e. a hafnium oxide layer HfO x(x=2~10), which plays the role of interface regulation. Above the NDO layer is the gate (G), which regulates the conductivity of the carbon nanotube channel by controlling the gate voltage. The whole structure shows the temperature-sensitive charge trap layer constructed above the carbon nanotube channel, as well as the layout of the gate and the source and the drain.

[0028] Figure 3 For the present application, the optical microscope schematic diagram of the artificial synapse transistor device based on thermal field regulation. In the figure, the transistor source (Source) and drain (Drain) are Ti / Au, the gate electrode (Gate) is Ti / Au, the channel (Channel) is carbon nanotube (CNT), the gate oxide (Insulator) is HfO2, and a layer of non-metering oxide HfO x (x=2~10).

[0029] Figure 4 For the present application, the principle energy band diagram of hafnium oxide doped carbon nanotube of the artificial synapse transistor based on thermal field regulation. In the figure, the energy band structure schematic diagram of the N-type doped carbon nanotube field effect transistor (CNTFET) at room temperature and high temperature is shown. The figure contains two main parts: the left side is the HfO x layer and the carbon nanotube (CNT) interface, and the right side is the energy band diagram. The left side shows the oxygen vacancies in the HfO x layer and the electrons released by the oxygen vacancies. The HfO x layer is connected with the carbon nanotube, and the Au electrode below the right side of the energy band diagram shows the energy band structure of the carbon nanotube (CNT) and the Au electrode. The conduction band (E c ), valence band (E v ), Fermi level (E F ), and barrier height (φSB) are marked in the figure. At high temperature, the position of the valence band of the carbon nanotube changes relative to room temperature. The dashed line represents the defect energy level after doping. The overall structure is used to show the energy band changes of the N-type doped CNTFET at different temperatures, and the electrons released by the oxygen vacancies affect the Fermi level and the barrier height of the carbon nanotube, thereby affecting the performance of the transistor.

[0030] Figure 5 For the present application, the Raman spectrum of the carbon nanotube channel region covered by hafnium oxide in the transistor. In the figure, the curve represents the Raman spectrum change trend of the carbon nanotube field effect transistor during the temperature regulation process from-25 ℃ to 120 ℃. Among them, the horizontal coordinate Raman Shift represents the Raman shift (cm -1 ), and the vertical coordinate Intensity represents the relative intensity of scattered light (a.u.). The D peak, G peak and 2D peak correspond to the characteristic peaks of the carbon nanotube.

[0031] Figure 6 EPSC (excitatory postsynaptic current) current-time graph of the artificial synapse transistor device based on thermal field regulation involved in the present application. In the figure, the vertical coordinate Current represents the current between the source and the drain of the transistor I DS (A), the horizontal coordinate Time (s) represents the pulse time.

[0032] Figure 7 PPF (paired pulse facilitation) current-time graph of the artificial synapse transistor device based on thermal field regulation involved in the present application. In the figure, the vertical coordinate Current represents the current between the source and the drain of the transistor I DS (A), the horizontal coordinate Time (s) represents the pulse time.

[0033] Figure 8 PPF (paired pulse facilitation) / electric pulse amplitude-temperature curve of the artificial synapse transistor device based on thermal field regulation involved in the present application. In the figure, the vertical coordinate PPF index (%) represents the paired pulse facilitation index, and the horizontal coordinate Temperature represents the temperature state (℃).

[0034] Figure 9 SDDP (spike duration-dependent plasticity) / electric pulse cycle-temperature curve of the artificial synapse transistor device based on thermal field regulation involved in the present application. In the figure, the vertical coordinate SDDP index (%) represents the spike duration-dependent plasticity index, and the horizontal coordinate Temperature (℃) represents the temperature state.

[0035] Figure 10 PPF (paired pulse facilitation) / electric pulse amplitude-temperature curve of the artificial synapse transistor device based on thermal field regulation involved in the present application. In the figure, the vertical coordinate PPF index (%) represents the paired pulse facilitation index, and the horizontal coordinate Temperature (℃) represents the temperature state.

[0036] Figure 11 SADP (spike amplitude-dependent plasticity) / electric pulse amplitude-temperature curve of the artificial synapse transistor device based on thermal field regulation involved in the present application. In the figure, the vertical coordinate SADP index (%) represents the spike amplitude-dependent plasticity index, and the horizontal coordinate Temperature (℃) represents the temperature state.

[0037] Figure 12The strong dependence of the weight change of the artificial synapse device on the polarity of the stimulation pulse under the electrical pulse stimulation of different working temperatures and different pulse amplitudes proves the feasibility of the back propagation of the artificial synapse device. I DS (A), the abscissa is Time (s) representing the pulse period applied to the transistor. DETAILED DESCRIPTION

[0038] In the implementation process, the present application first proposes an artificial synapse transistor device based on thermal field regulation, and a carbon nanotube field effect transistor is prepared under room temperature conditions. A 40 nm hafnium oxide dielectric layer is deposited by using an atomic layer deposition technology to dope the carbon nanotube channel material, and a temperature-sensitive CNT / HfO x charge layer trap layer is constructed. The high-performance and high-efficiency field effect gate voltage regulation and the temperature regulation of the oxygen vacancy doped carbon nanotube channel are realized. The reversible polarity transition in different temperature ranges is observed. The weight adjustment of the oxygen vacancy doped CNTFET artificial synapse device is systematically studied, and the performance parameters such as EPSC, PPF, SDDP and SADP of the artificial synapse device under different temperature conditions are obtained. The performance regulation method of the artificial synapse device based on the thermal reconfigurable carbon nanotube field effect transistor can effectively characterize the influence of the environmental temperature change on the performance of the artificial synapse device, can simulate the response of the biological body to the environmental temperature change, and thus can improve the stability and reliability of the specific performance of the device. The realization of the artificial synapse device based on the thermal reconfigurable carbon nanotube field effect transistor not only promotes the progress of the neuromorphic device in the dynamic environmental adaptability, but also opens up a new path for the development of intelligent transistors with temperature self-sensing function, and shows important application value in the thermal management of brain-like chips, programmable logic devices and biological sensing fields.

[0039] In the following, the present application is further described in detail through examples and drawings. EMBODIMENT

[0040] In this embodiment, the artificial synapse transistor device based on thermal field regulation and the manufacturing method thereof are as follows: As shown in Figure 1 , Figure 2 , the CNTFET adopts a vertical stacked heterostructure, which specifically comprises, from bottom to top: 300 nm silicon dioxide layer / 300 μm heavily doped boron (P + type, doping concentration 10 19 ~10 21A sandwich structure of silicon substrate / 300 nm silicon dioxide layer. This design effectively isolates the charge interference between the silicon substrate and the functional layer by using the double passivation characteristics of silicon dioxide, and the heavily doped silicon can be used as the back gate electrode. The source and drain electrodes are composite metal electrodes composed of a 5 nm titanium (Ti) adhesion layer / 50 nm gold (Au) conductive layer. The titanium layer reduces the contact resistance by enhancing the metal-semiconductor interface bonding force, and the gold layer provides high conductivity. The channel layer is a single-walled carbon nanotube (SWCNT) network film (thickness 3-6 nm) deposited by solution method. High-quality arc discharge carbon nanotubes (diameter 1.55±0.1 nm) from Carbon Solution Inc. have a band gap of about 1 eV. The gate dielectric layer is a 40 nm hafnium oxide (HfO2) thin film grown by atomic layer deposition, and the top gate electrode is a 5 nm Ti / 50 nm Au stacked electrode.

[0041] The manufacturing process is as follows: First step, substrate pretreatment cleaning process, acetone (40 kHz ultrasonic, 100 W, 5 min), isopropanol (40 kHz ultrasonic, 100 W, 5 min), oxygen plasma (O2 flow rate 180 sccm, 200 W, 10 min) three-step method to remove organic residues and surface oxide layer.

[0042] Second step, make source / drain metal electrodes to the target substrate, photoresist patterning uses S1813 positive photoresist (spin coating thickness 1.5 μm) with ultraviolet lithography exposure, forming a 2×2 cm 2 effective exposure area. Ti / Au is evaporated by electron beam evaporation (substrate temperature 50°C) to deposit titanium / gold electrodes at the source and drain.

[0043] Third step, carbon nanotube channel deposition, single-walled carbon nanotubes are high-quality arc discharge carbon nanotubes from Carbon Solution Inc., with a diameter distribution concentrated at a peak diameter of 1.55±0.1 nm and a bundle length of 1-5 μm. First, mix the block-shaped carbon nanotubes with toluene at a mass ratio of 1:8, disperse by ultrasonic (30 min) and centrifuge (45000 g, 1 h) to remove carbon nanotube bundles and insoluble substances, obtain a semiconductor single-walled carbon nanotube solution with a purity of more than 99.9 wt%, collect the supernatant as the channel material. Then, ultrasonic treat the carbon nanotube solution, the ultrasonic frequency is 40 Hz, the power is 100 W, the ultrasonic dispersed carbon nanotube solution is transferred to a petri dish.

[0044] In the process of depositing the carbon nanotube film, the cleaned silicon substrate is first heated to 180°C on a hot plate for 30 min to remove moisture on the substrate. To enable the single-walled carbon nanotubes to be better adsorbed on the substrate and uniformly dispersed, a precursor primer (MCC-Primer, Micro Chem Corporation Primer, as the primer) is spin-coated on the surface of the substrate by a spin coater, and then baked at 105°C on a hot plate for 2 min. The baked substrate is immersed in the carbon nanotube solution culture dish after ultrasonic dispersion, and the culture dish is placed in a 60°C water bath. The deionized water level in the water bath is just above the carbon nanotube solution level in the culture dish. After two and a half hours, the deposition of single-walled carbon nanotubes is completed, and a carbon nanotube film is formed.

[0045] Fourth step, patterned etching, spin-coating LOR3A and S-1813 double-layer photoresist on the surface of the carbon nanotube film in turn, the exposed pattern is a square area with a side length of 180-182 μm; the exposed sample is placed in an oxygen plasma cleaning machine, the flow rate of oxygen is 180 sccm, the power is 200 W, and the cleaning time is 2 min, to remove the excess carbon nanotube film exposed outside the source-drain metal electrode.

[0046] Fifth step, gate dielectric layer and top gate integration, ALD growth of HfO2, using C8H 24 HfN4 precursor and H2O as the reaction source, 500 cycles at 200°C (single cycle thickness 0.08 nm), obtain 40 nm dense film. Then prepare the top gate electrode, the same source-drain process.

[0047] Sixth step, reactive ion etching, using photolithography technology to produce a photoresist mask layer, the maximum effective range of the mask is 2×2 cm 2 exposed area, exposing the required hafnium oxide etching area, exposing the titanium / gold source-drain metal electrode in contact with the carbon nanotube channel and the substrate, using carbon tetrafluoride to etch the patterned hafnium oxide, so that the source-drain electrode is exposed to the air, and a carbon nanotube field effect transistor array is obtained. The etching conditions are as follows: using a reactive ion etching machine (RIE) for etching, using carbon tetrafluoride with a flow rate of 50 sccm as the etching gas, the pressure is 5.0-5.5 Pa, the power is 100 W, and the etching time is 5 min 30 s.

[0048] In the carbon nanotube field effect transistor, the substrate is composed of silicon dioxide / heavily doped silicon slice / silicon dioxide from bottom to top, the source electrode and the drain electrode and the gate electrode are composed of a laminated composite structure of titanium / gold from bottom to top, the channel is composed of single-walled carbon nanotubes deposited by solution, the dielectric layer between the gate electrode and the channel is hafnium oxide, and the overall structure is: silicon dioxide / silicon / silicon dioxide / titanium / gold / semiconductor carbon nanotube / hafnium oxide / titanium / gold, a laminated composite structure from bottom to top. The thicknesses are: 300 nm / 300 μm / 300 nm / 5 nm / 50 nm / 3-6 nm / 30 nm / 5 nm / 50 nm, and the growth temperature of the hafnium oxide dielectric layer is 200 ℃.

[0049] The above is the manufacturing process of the carbon nanotube field effect transistor, which further constitutes the device structure as shown in Figure 1 The bottom substrate is composed of silicon dioxide (SiO2) / P-type doped silicon (Si) / silicon dioxide (SiO2) from bottom to top, titanium (Ti) / gold (Au) electrodes are first evaporated on the silicon substrate as the source electrode and the drain electrode by electron beam evaporation technology. The carbon nanotube (CNT) in contact with the electrode and the silicon substrate serves as the device channel, hafnium oxide (HfO2) is grown on the carbon nanotube channel as a dielectric layer, and titanium (Ti) / gold (Au) electrodes are evaporated on the dielectric layer as the gate electrode of the device.

[0050] As shown in Figure 2 , the two-dimensional structure schematic diagram of the carbon nanotube field effect transistor prepared by the method of doping the carbon nanotube channel by atomic layer deposition of hafnium oxide dielectric layer. The carbon nanotube field effect transistor (mainly adopting a vertical stacked structure, mainly including the following functional layers: carbon nanotube channel: single-walled carbon nanotube as a conductive channel, with a diameter of about 1-2 nm. HfO x dielectric layer: a high dielectric constant oxide with a thickness of about 5-10 nm uniformly covers the surface of CNT to form a gate dielectric layer by atomic layer deposition (ALD). Au electrode system: symmetric gold electrodes are used as the source electrode (S) and the drain electrode (D), which form ohmic contact with CNT through van der Waals force to ensure efficient injection of carriers. Oxygen vacancy distribution: oxygen vacancies are enriched at the HfO x / CNT interface as active sites for charge transfer.

[0051] In the specific experiment, the HfO x / CNT layer mainly realizes the following functions: hafnium oxide dielectric regulation: the high dielectric property enables HfO x to realize a stronger gate electric field under the same physical thickness, effectively shielding interface scattering and improving transconductance (g m ). CNT band engineering: undoped CNT is a typical P-type semiconductor (hole-dominated), but through oxygen vacancy doping, the Fermi level (EF ) to the conduction band (E c ) and move, realizing N-type conversion. Defect-carrier coupling: oxygen vacancies act as localized state traps, releasing electrons to the CNT conduction band through thermal excitation or electric field, forming a non-equilibrium carrier concentration gradient. The artificial synapse transistor device based on thermal field regulation and its manufacturing method in this embodiment includes the following steps: (1)-(8) are the specific manufacturing process of hafnium oxide doped carbon nanotube field effect transistor. (9) is the specific temperature control scheme details of the carbon nanotube field effect transistor through the thermal electric device.

[0052] (1) In this embodiment, during the entire ultrasonic cleaning process, acetone and isopropyl alcohol are used to clean the device, and the ultrasonic frequency is set to 40 Hz and the power is set to 100 W for each cleaning. The cleaning time of each solvent is 10 min. The oxygen plasma cleaning step is set to 10 min, the oxygen flow rate is controlled at 180 sccm, and the power is maintained at 200 W; (2) In this embodiment, when preparing the source and drain electrodes, a photoetching technology is used to accurately form a photoresist mask layer on the substrate, and the maximum effective range of the mask layer is an exposure area of 2*2 cm. The desired source and drain electrode evaporation area is exposed on the substrate, and a titanium / gold layered metal electrode is prepared in the specified area by vacuum electron beam evaporation technology, and the source and drain electrodes of the transistor are constructed. The evaporation thickness of the Ti layer is set to 5-6 nm, and the evaporation thickness of the Au layer is controlled to be between 50-51 nm; (3) In this embodiment, an oxygen plasma etching technology is used, the oxygen plasma cleaning time is 20 min, the oxygen flow rate is 180 sccm, and the power is 200 W, to remove the residues on the surface of the Si wafer and the source and drain electrodes; (4) In this embodiment, the carbon nanotubes and toluene are mixed in a mass ratio of 1:8, then ultrasonic dispersion and centrifugal purification are performed to remove carbon nanotube bundles and insoluble impurities, and a semiconducting carbon nanotube solution is obtained. The supernatant is taken as the channel material. Then, the carbon nanotube solution is subjected to ultrasonic treatment at a frequency of 40 Hz and a power of 100 W for 5 min, and then the ultrasonically dispersed solution is transferred to a culture dish for standby.

[0053] In the carbon nanotube film deposition link, the cleaned silicon substrate is first placed on a hot plate, and baked at 180 ℃ for 30 min to remove moisture. To enhance the adsorption and dispersion uniformity of carbon nanotubes on the substrate, the primer primer is spin-coated on the upper surface of the substrate using a spin coater, and baked on a 105 ℃ hot plate for 2 min. Then, the baked silicon substrate is immersed in a culture dish containing an ultrasonic dispersion carbon nanotube solution, and the culture dish is placed in a 60 ℃ water bath, with the liquid level of deionized water slightly higher than that of the solution in the culture dish. After two and a half hours, the carbon nanotubes are deposited to form a thin film; (5) In this embodiment, the oxygen plasma cleaning technology and photolithography technology are used, and the LOR3A and S-1813 double-layer photoresist are spin-coated on the surface of the carbon nanotube film in turn using a spin coater, and the pattern is exposed to form a square region with a side length of 180~182 μm. This step aims to pattern the carbon nanotube channel region that needs to be protected; then, the exposed sample is placed in an oxygen plasma cleaning machine using oxygen plasma cleaning technology, with an oxygen flow rate of 180 sccm and a power of 200 W, and cleaned for 2 min to etch the parts outside the source and drain metal electrodes, effectively removing the excess and possibly interfering carbon nanotube film; (6) In this embodiment, an atomic layer deposition technology is used to prepare a 40 nm hafnium oxide dielectric layer covering the carbon nanotube film at a temperature of 200 ℃. As for the selection of the precursor, the hafnium precursor is tetra(dimethylamino)hafnium (C8H 24 HfN4), and the oxygen source precursor can be water (H2O). The deposition process parameters include temperature setting, gas flow rate and pulse time setting. In terms of temperature, the temperature of the hafnium precursor and the substrate is a key parameter, and the deposition temperature range is generally 200 ℃. The gas flow rate needs to be accurately controlled, and the pulse time refers to the residence time of the precursor gas in the reaction chamber. The deposition cycle process starts with the introduction of the hafnium precursor gas, followed by adsorption and carrier gas purging. Then the oxygen source precursor gas is introduced, and after the reaction, carrier gas purging is performed again. Repeat the above steps to form an ALD cycle, which can deposit about 0.1~0.2 nm of hafnium oxide film per cycle, and the film thickness can be accurately controlled by controlling the number of cycles. In the experiment, tetra(dimethylamino)hafnium (C8H 24 HfN4) is used as the hafnium precursor, and water vapor is used as the oxygen source precursor. The reaction temperature is set to 200 ℃, the flow rate of tetra(dimethylamino)hafnium (C8H 24 HfN4) is 30 sccm, the flow rate of water vapor is 150 sccm, and the flow rate of carrier gas (nitrogen) is 100 sccm. In each cycle, tetra(dimethylamino)hafnium (C8H 24The pulse time of HfN4 is 0.5 s, the pulse time of water vapor is 1 s, and the carrier gas purge time is 5 s. After 200 ALD cycles, a 40 nm thick hafnium oxide dielectric layer is successfully prepared.

[0054] A layer of hafnium oxide dielectric layer is uniformly covered on the carbon nanotube channel, and the carbon nanotube channel is doped by hafnium oxide to form an interface doping layer that can be controlled by thermal field, providing a basis for subsequent thermal field-OC and forming an insulating basis for subsequent gate electrode production; (7) In this embodiment, photolithography technology is used to expose the required gate electrode evaporation area on the hafnium oxide dielectric layer, and vacuum electron beam evaporation technology is used, in which the evaporation thickness of the Ti layer is set to be in the range of 5-6 nm, and the evaporation thickness of the Au layer is controlled to be between 50-51 nm; a titanium / gold gate electrode in close contact with the hafnium oxide dielectric layer is prepared; (8) In this embodiment, photolithography technology is used to make a photoresist mask layer, and the required hafnium oxide etching area is exposed to the titanium / gold source and drain metal electrodes in contact with the carbon nanotube channel and the substrate, and a reactive ion etching machine is used for etching, with the etching conditions being: using carbon tetrafluoride with a flow rate of 50 sccm as the etching gas, a pressure of 5.0-5.5 Pa, a power of 100 W, and an etching time of 7 minutes and 30 seconds, to accurately etch the hafnium oxide, and finally obtain a carbon nanotube field effect transistor array with complete structure; as shown in Figure 3 the device optical microscope diagram of a single hafnium oxide doped carbon nanotube field effect transistor, including a source, a drain, a gate electrode, a channel, and a gate oxide, in which a layer of non-metered oxide HfO is sandwiched between the top of the channel CNT and the gate oxide HfO2 x .

[0055] (9) In this embodiment, a thermoelectric device compatible with the carbon nanotube field effect transistor is constructed, and the surface of the thermoelectric device is sprayed with acetone and then isopropanol, and after each spraying, it is left to stand for 1 min, then wiped dry with a dust-free cloth to remove surface impurities. Subsequently, the phase change heat conducting material is attached to the surface of the thermoelectric device and is attached to the substrate of the carbon nanotube field effect transistor. The surface temperature of the thermoelectric device is adjusted by an external DC power supply, with a temperature range of -25 ℃ to 120 ℃, a temperature control accuracy of 0.1 ℃, and a heating or cooling rate of 3.84 ℃ / s.

[0056] To reveal the internal mechanism of the above-mentioned temperature-induced polarity conversion from a physical level, we constructed a CNT / HfO x interface energy band diagram, as shown in Figure 4 (i) In the initial low temperature or without heat treatment state, the Au electrode (work function 5.1 eV) is in contact with the intrinsic CNT (E V ~ -4.8 eV, EC ~ -3.0 eV) contact to form a Schottky barrier (Φ SB At this point, due to the physical adsorption of oxygen molecules from the air and their removal of electrons from the CNT surface, the hole concentration in the channel increases, endowing the device with certain P-type conductivity characteristics or bipolar behavior. Simultaneously, HfO in the device... x The dielectric layer (grown via atomic layer deposition) is rich in oxygen vacancy defects, which are present in CNT / HfO x (ii) Temperature-sensitive localized defect states are formed at the interface. When the temperature rises, multiple physical processes work together: First, oxygen molecules adsorbed on the CNT surface undergo thermal desorption, releasing the captured electrons back into the channel; more importantly, the high temperature activates HfO x Oxygen vacancy defects in the dielectric layer enable the trapping of oxygen molecules desorbed from the CNT surface, simultaneously injecting electrons into the CNT channel. This defect-induced electron injection process causes the CNT's conduction band to shift towards the Fermi level (E). F The electrons are significantly brought closer together, thus greatly improving electron injection efficiency and effectively suppressing hole conduction, ultimately causing the device to switch from bipolar to N-type dominance. As the temperature decreases, HfO... x Oxygen molecules trapped by defect states are re-released and physically adsorbed again onto the CNT surface, allowing the device's polarity to be reversibly restored. Furthermore, the dynamic changes in oxygen content within the dielectric layer also affect the interface state density. These interface states, by trapping charge carriers, modulate the device's threshold voltage, manifesting as a positive shift. The entire process is theoretically similar to that of a charge-trapping floating-gate transistor, but its core driving force originates from the unique modulation of interfacial chemical-physical processes (oxygen adsorption / desorption) and defect state activity by temperature.

[0057] Temperature-controlled Raman spectroscopy can effectively explain the oxygen desorption process. When oxygen molecules adsorb onto the surface of carbon nanotubes, they extract electrons from the π-electron system of the carbon nanotubes, exhibiting a p-type doping effect. Under thermal field control, the heating conditions provide the energy required for desorption of the adsorbed oxygen molecules, and the electrons return to the π-electron system of the carbon nanotubes, thereby weakening or even eliminating this p-type doping effect. This charge transfer significantly alters the position of the Fermi level, thus affecting the states of electrons and phonons participating in Raman scattering, ultimately leading to spectral changes. Figure 5 As shown, during the temperature control process from -25 ℃ to 120 ℃, as electrons flow back into the carbon nanotubes in the channel region, the Fermi level rises, causing the G peak to redshift and return to a lower position. Similarly, due to the restoration of resonance conditions and changes in phonon energy, the 2D peak redshifts and returns to its intrinsic position. As for the D peak, the heating process removes a small number of oxygen-containing functional groups, repairing the sp... 2The carbon network reduced defects, thus weakening the D peak intensity. However, during the cooling process from 120 °C to room temperature (25 °C), we observed a reversible peak position change: the G and 2D peaks underwent a blue shift, and the D peak intensity increased again. This indicates that the temperature-induced polarity reversal is reversible.

[0058] like Figure 6 The figure shows the current-time plot of EPSC (excitatory postsynaptic current) of an artificial synaptic transistor based on thermal field modulation. The EPSC of an artificial synapse simulates the current response generated by a postsynaptic neuron in a biological nervous system when it receives an excitatory signal. Its core mechanism is similar to that of the EPSC in a biological synapse, but it is implemented in an artificial device in an electrical form. The existence and dynamic characteristics of the EPSC reveal the functional performance of the artificial synapse and its potential in neuromorphic computing.

[0059] The thermally modulated artificial synaptic transistor involved in this invention, when stimulated by the same positive gate voltage pulse, causes oxygen vacancies in the hafnium oxide dielectric layer-doped carbon nanotube field-effect transistor to migrate into the semiconducting carbon nanotube channel, thereby enhancing the channel conductivity and manifesting as an instantaneous increase in postsynaptic current. Because the device operates at different ambient temperatures of 20°C and 120°C, the different device polarities lead to different amplitudes of the instantaneous EPSC current. At 20°C, the current rapidly reaches its peak after the pulse is applied, then decays exponentially, eventually stabilizing near the baseline. This dynamic process closely matches the typical waveform of biological synaptic EPSC (rapid depolarization followed by slow repolarization). The 5V, 2s input pulse corresponds to the duration of biological action potentials (milliseconds to seconds), indicating that the device can effectively simulate the time-domain response characteristics of biological synapses.

[0060] The rapid decay (Q reduction) of EPSC at high temperatures inhibits the conversion from STM to LTM, making it suitable for temporary information storage scenarios requiring dynamic erasure and rewriting (such as buffers); while the high Q value at low temperatures (20℃) is beneficial for long-term weight solidification. The EPSC maintains stable output (no current oscillation or baseline drift) at 120℃, indicating that the device has high-temperature reliability, making it suitable for high-temperature resistant neuromorphic chips in automotive electronics or industrial automation.

[0061] like Figure 7PPF (paired-pulse facilitation) current-time diagram of the artificial synapse transistor based on thermal field regulation. The paired-pulse facilitation of the artificial synapse is one of the core characteristics of simulating the short-term plasticity (STP) of biological synapses. Its essence is to reveal the dynamic response mechanism and temporary memory capacity of the synapse through the dynamic change of the post-synaptic current under two consecutive pulse stimuli. In the biological nervous system, when the presynaptic neuron receives two consecutive and very short interval pulse stimuli, the post-synaptic current induced by the second stimulus is significantly stronger than the first one, which is called double-pulse facilitation. Its core mechanism is related to the dynamic change of the calcium ion concentration of presynaptic neurotransmitter release, which shows the "temporary memory" effect of the synapse to the previous stimulus. In artificial synapse devices (such as double-layer transistors, ferroelectric synapses, etc.), PPF is achieved by regulating the relaxation time of carrier or ion migration in the material. PPF value is defined as the ratio of the second pulse response peak (A2) to the first pulse response peak (A1) (A2 / A1 x 100%).

[0062] The device involved in the application receives an electrical pulse stimulus parameter: double-pulse voltage 5 V, pulse width 4 s, interval ΔT=2 s. The pulse interval time (4 s) is in the typical PPF response sensitive region (1~10 s), which can effectively trigger the non-equilibrium state superposition of carriers / ions. Response amplitude: at 20 ℃, the absolute value of the first peak (A1) is 3.24 x 10 -8 A, the second peak (A2) is 4.43 x 10 -8 A, the PPF index (A2 / A1) reaches 127%; at 120 ℃, A1=1.09 x 10 -6 A, A2=1.15 x 10 -6 A, the PPF index decreases to 110%. High temperature causes the PPF efficiency to decrease by 17.3%. The main reason is that oxygen vacancies release more electrons at high temperature, enhancing the initial conductance (A1 increases), but high temperature also accelerates electron-hole recombination, limiting the increase of A2.

[0063] As shown in Figure 8 , it embodies the non-monotonic temperature dependence of the PPF index. When the device works in the low temperature region (20~80℃), the PPF index under all voltage periods (1s, 2s, 3s) decreases linearly with temperature, for example: V=1s: at 0℃, PPF≈28%, at 80℃, it decreases to the lowest point≈8%, the decrease is 71.4%. V=3s: at 0℃, PPF≈25%, at 80℃, it is≈5%, the decrease is 80%. The main mechanism in this stage is the thermal enhancement effect of carrier mobility: the increase of lattice vibration (phonon scattering) caused by temperature rise reduces the carrier mobility, shortens the residence time of carriers in the channel, and reduces the double-pulse superposition effect.

[0064] When the device works in the high temperature zone (80-120 ℃), the PPF index rises significantly with the increase of temperature, for example: V=1 s: PPF≈18 % at 120 ℃, which is 125 % higher than that at 80 ℃. V=3 s: PPF≈10 % at 120 ℃, which is doubled compared with that at 80 ℃. The dominant mechanism switches to trap-assisted charge release: high temperature activates deep level defect states (oxygen vacancies), releases trapped charges, enhances carrier concentration gradient, and restores pulse superposition efficiency.

[0065] In addition, Figure 8 The regulation law of voltage cycle on PPF index is also reflected: short cycle advantage (V=1 s): at all temperatures, the PPF index of 1 s cycle is higher than that of 2 s and 3 s. For example, at 120 ℃, the PPF (18 %) of V=1 s is 80 % higher than that of V=3 s (10 %). The main mechanism is that short cycle pulse maintains non-equilibrium state concentration through high frequency carrier injection, reduces the loss of recombination, and enhances the synergistic effect of double pulse. Long cycle sensitivity (V=3 s): long cycle (3 s) is more sensitive to temperature change, and the decrease (80 %) from 0 ℃ to 80 ℃ is significantly greater than that of 1 s cycle (71.4 %). The main mechanism is that long cycle allows carriers to diffuse to trap states, and at low temperature, recombination is dominant, and at high temperature, trap release effect is delayed, and response lag is delayed.

[0066] As Figure 9 shown, the present application relates to the SDDP (Spike Duration-Dependent Plasticity) / electric pulse cycle-temperature curve of the artificial synapse transistor based on thermal field regulation. SDDP (Spike Duration-Dependent Plasticity) is a key mechanism in artificial synapses to simulate the plasticity of biological synapses, which is used to describe the dynamic adjustment of synaptic weight (such as conductance, current response) with the change of input pulse duration. SDDP imitates the time dependence of signal transmission in biological synapses: when the pulse signal duration released by presynaptic neurons is different, the response intensity of postsynaptic neurons will show difference. When the device works in the low temperature zone (20-60 ℃), the SDDP index of the device increases from 2000 % to the peak value of 8000 %, and the increase in temperature promotes the carrier mobility and ion migration rate, the double-layer capacitor (EDLC) is quickly formed, and the pulse superposition effect is enhanced. When the device works in the high temperature zone (60-120 ℃), the SDDP index of the device decreases from 8000 % to 4000 %, due to the enhancement of phonon scattering and the aggravation of trap state recombination, which leads to the decline of carrier storage capacity.

[0067] In addition, Figure 9The carrier three-stage competition of the device is also shown: stage I (T < 60 DEG C): thermal excitation dominates, the carrier concentration and mobility increase synchronously, and the SDDP index is positively correlated with the product. Stage II (60 DEG C < T < 100 DEG C): trap-assisted recombination becomes the main factor, and the mobility gain is offset. Stage III (T > 100 DEG C): lattice vibration (phonon) scattering and ion disordering intensify, the average free path of the carrier approaches the quantum confinement scale, and the transport efficiency collapses.

[0068] As shown in Figure 10 The PPF / electric pulse amplitude-temperature curve characterization of the artificial synapse transistor based on thermal field regulation is related to the present application. The temperature-voltage synergistic effect of the device is mainly reflected, and for the temperature-dominant carrier scattering at low temperature (0-80 DEG C): the PPF index at all voltages (3 V / 4 V / 5 V) continuously decreases in the range of 0-80 DEG C, for example: 5V pulse: PPF at 0 DEG C is about 28 %, and at 80 DEG C, it decreases to the lowest point of about 8 %, and the decrease is 71.4 %; 3V pulse: PPF at 0 DEG C is about 25 %, and at 80 DEG C, it is about 5 %, and the decrease is 80 %. The main mechanism is that the increase of temperature leads to the enhancement of lattice vibration (phonon scattering), the decrease of carrier mobility, the shortening of carrier residence time, and the weakening of double-pulse superposition effect. And the PPF of the device at high voltage (5V) in the low temperature zone (0-40 DEG C) decreases more slowly, because the strong electric field accelerates the carrier injection, and partly offsets the decrease of mobility.

[0069] When the artificial synapse device works at a temperature greater than 80 DEG C, the deep level defects (such as oxygen vacancies in HfO2) are activated (Ea≈0.35 eV) by heat, the trapped charges are released, and the carrier concentration gradient is restored, for example: 5V pulse: PPF at 120 DEG C rises to about 12 %, and the increase is 50 %; 3V pulse: PPF at 120 DEG C rises to about 8 %, and the increase is 60 %. The main mechanism is that the trap-assisted charge release rate exceeds the recombination loss. The PPF rise amplitude (4 %) of 5V pulse is significantly higher than that (3 %) of 3V, because the high voltage enhances the delocalization of the carrier under the driving of the electric field, and inhibits the high-temperature recombination.

[0070] As shown in Figure 11As shown, the present application relates to the SADP (Spike Amplitude-Dependent Plasticity) / electric pulse amplitude-temperature curve of the artificial synapse transistor based on thermal field regulation. SADP is a key mechanism that simulates the plasticity of biological synapses, and its core feature is the dynamic adjustment of synaptic weight (such as conductance, current response) with the amplitude (intensity) of the input pulse signal. SADP simulates the intensity-dependent mechanism of signal transmission in biological synapses: when the intensity (amplitude) of the pulse signal released by the presynaptic neuron is different, the response intensity of the postsynaptic neuron will show differences. In Figure 11 In the low temperature region (0~60 ℃), the SADP index increases from 0 % to a peak of 9000 %, and the carrier injection efficiency under high electric field is promoted by the increase in temperature, and the ion migration rate is also improved synchronously. In the high temperature region (60~120 ℃), the index decreases from 9000 % to 2000 %, and due to the dominance of phonon scattering and trap state recombination, the carrier storage capacity collapses. In the medium temperature optimum (40~100 ℃), the SADP reaches a peak of 8000 % at 80 ℃, and the moderate electric field balances the decrease in mobility and trap activation. In the high temperature recession (>100 ℃), the index decreases rapidly to 4000 %, and the lattice disorder intensifies the localization of carriers.

[0071] As shown in Figure 12 , the artificial synapse transistor based on thermal field regulation has a strong dependence of the change of the synaptic weight on the polarity of the stimulation pulse under the electric pulse stimulation of different working temperatures and different polarities of the pulse amplitude. When the device works at 20 ℃, the response characteristics are: +5 V pulse: the output current is positive (red line), and the amplitude is about 10 -7 A. -5 V pulse: the output current is still positive (green line), and the amplitude is similar to that of +5 V. The key feature is that both positive and negative pulses drive unidirectional carrier (such as hole) injection, and does not reflect the polarity dependence, which can realize the regulation of the artificial synapse weight by positive and negative voltage pulses. When the device works at 120 ℃, the response characteristics are: +5 V pulse: the positive current is maintained, and the amplitude rises to 10 -6 A (an increase of 1 order of magnitude). -5 V pulse: the output current becomes negative (green line negative), and the amplitude is about -10 -9 A. The key feature is the strong correlation between polarity dependence and temperature sensitivity, and the negative pulse triggers the injection of reverse carriers (such as electrons), which can realize the regulation of the artificial synapse weight by unidirectional voltage pulse.

[0072] Since the device works at low temperature mainly dominated by hole injection, the HfO2 dielectric layer doped carbon nanotube device behaves as a bipolar semiconductor at low temperature, and oxygen vacancies act as acceptor defects, capturing electrons to form hole-dominant conduction. The device occurs oxygen vacancy thermal activation at high temperature, and the activated oxygen vacancies release electrons to become additional carriers at high temperature (120 DEG C), and the material changes from bipolar to N-type. Oxygen vacancies introduce shallow donor levels in the forbidden band, and electrons can transition to the conduction band (E c ).

[0073] By the above method, the artificial synapse transistor based on thermal field regulation proposed in the application is successfully realized.

[0074] The results of the embodiment show that the artificial synapse transistor based on thermal field regulation realizes reversible polarity conversion of the carbon nanotube field effect transistor under variable temperature by the method of doping carbon nanotubes with a hafnium oxide dielectric layer grown by atomic layer deposition. The reconfigurability of the artificial synapse under temperature regulation is systematically studied, and the performance of the artificial synapse under different temperature ranges is observed. The results of the artificial synapse under different temperature conditions show that the electrical performance parameters such as EPSC, PPF, SDDP and SADP change to different degrees with the change of temperature. And the key performance parameters of the artificial synapse are comprehensively characterized, including excitatory postsynaptic current, paired pulse facilitation, spike duration-dependent plasticity and weight adjustment of the artificial synapse under different voltage stimulation. The theoretical support and technical path are provided for breaking the traditional computing boundary and constructing a truly brain-like intelligent system.

Claims

1. A thermofield-based artificial synapse transistor, characterized by, The artificial synapse transistor comprises a substrate, a carbon nanotube channel, a gate dielectric layer, a gate electrode and source-drain electrodes in contact with the carbon nanotube channel, and the overall structure is: silicon dioxide / heavily doped P-type silicon wafer / silicon dioxide / titanium / gold / semiconductor carbon nanotube / hafnium oxide / titanium / gold, a self-bottom-up laminated composite structure; wherein the substrate is a self-bottom-up laminated structure of silicon dioxide / heavily doped P-type silicon wafer / silicon dioxide, the transistor channel is an irregular single-walled carbon nanotube layer obtained by water bath heating deposition, the gate dielectric layer is a hafnium oxide layer obtained by atomic layer deposition, and the gate electrode and the source-drain electrodes are a self-bottom-up titanium / gold laminated composite structure; a layer of non-metered oxide HfO x , x=2~10.

2. The artificial synapse transistor based on thermal field regulation according to claim 1, characterized in that, The hafnium oxide layer obtained by atomic layer deposition dopes the carbon nanotube channel, and then obtains the charge trap state of the channel and the top dielectric layer doping interface which can be adjusted by thermal field; the heat-electricity device is connected to the carbon nanotube field effect transistor through the phase change heat-conducting material; the heat-electricity device is connected to the external direct current power supply, the temperature of the carbon nanotube field effect transistor is adjusted based on the Peltier effect, the rate and equilibrium state of the interface trap capturing and releasing charges are significantly affected by the temperature change, and the number of trapped charges can be non-volatilely changed by combining the electric field activation of the gate voltage, so as to effectively adjust the carrier concentration and conductivity of the carbon nanotube channel, realize the multi-state and gradual control of the device conductivity, and simulate the artificial synapse based on the same.

3. The method of claim 1 or 2, wherein the method is implemented by a computer system. The method comprises the following steps: (1) the substrate is sequentially subjected to ultrasonic cleaning by acetone and isopropyl alcohol to remove surface impurities, and then is further subjected to surface residue removal by an oxygen plasma cleaning machine; (2) a photoetching technology is used to accurately form a photoresist mask layer on the substrate, the maximum effective range of the mask layer is 2*2 cm of an exposed area, the source and drain electrode area required is exposed on the substrate, a titanium / gold layered metal electrode is prepared in the specified area by a vacuum electron beam evaporation technology, and the source and drain electrode of the transistor is constructed; (3) an oxygen plasma cleaning technology is used to remove the residues on the surface of the silicon wafer and the source and drain electrode; (4) after the primer base glue is uniformly spin-coated on the substrate, the substrate is immersed in a carbon nanotube solution subjected to ultrasonic dispersion treatment, and the carbon nanotube is deposited on the substrate by a water bath heating method to form a transistor channel layer; (5) first, a photoetching technology is used to accurately construct a photoresist mask layer on the substrate on which the carbon nanotube channel has been deposited, and the carbon nanotube channel area is patterned; then, an oxygen plasma cleaning technology is used to etch the carbon nanotube outside the channel, and the excess carbon nanotube film is effectively removed; (6) an atomic layer deposition technology is used to uniformly deposit a hafnium oxide dielectric layer on the carbon nanotube channel, the carbon nanotube channel is doped by the hafnium oxide, and an interface doping layer which can be adjusted by thermal field is formed; (7) a photoetching technology is used to expose the gate electrode evaporation area required on the hafnium oxide dielectric layer, and a titanium / gold gate electrode which is in close contact with the hafnium oxide dielectric layer is prepared by a vacuum electron beam evaporation technology; (8) a photoetching technology is used to make a photoresist mask layer, and the hafnium oxide etching area required is exposed, the titanium / gold source and drain metal electrode which is in contact with the carbon nanotube channel and the substrate is exposed, a reactive ion etching technology is used to accurately etch the hafnium oxide by taking carbon tetrafluoride as a reaction gas, and finally a carbon nanotube field effect transistor array with complete structure is obtained; (9) a heat-electricity device compatible with the carbon nanotube field effect transistor is constructed, and the surface of the heat-electricity device is sprayed with acetone and isopropyl alcohol to remove surface impurities; then, the phase change heat-conducting material is attached to the surface of the heat-electricity device, and the substrate of the transistor is closely attached to the surface of the phase change heat-conducting material, the surface temperature of the heat-electricity device is accurately adjusted by an external direct current power supply, and then the working temperature of the transistor is flexibly adjusted.

4. The fabrication method of artificial synapse transistor based on thermal field control according to claim 3, characterized in that, In step (2) and step (7), the two end source-drain electrodes and the top gate electrode are deposited by using an electron beam evaporator, the thickness of the titanium layer is 5-6 nm, and the thickness of the gold layer is 50-51 nm.

5. The fabrication method of artificial synapse transistor based on thermal field control according to claim 3, wherein, In step (3), the oxygen plasma cleaning time is 20 min, the oxygen flow rate is 180 sccm, and the power is 200 W.

6. The fabrication method of artificial synapse transistor based on thermal field control according to claim 3, wherein, In step (4), the carbon nanotubes are mixed with toluene at a mass ratio of 1:8, ultrasonic dispersion and centrifugal purification are performed, carbon nanotube bundles and insoluble substances are removed, a semiconductor carbon nanotube solution is obtained, the supernatant is collected as a channel material, the carbon nanotube solution is ultrasonically treated, the ultrasonic frequency is 40 Hz, the power is 100 W, and the time is 5 min, and the ultrasonically dispersed carbon nanotube solution is transferred to a culture dish; In the process of depositing the carbon nanotube film, the cleaned substrate is first heated to 180℃ on a hot plate for 30 min to remove water on the substrate, in order to make the carbon nanotubes better adsorb on the substrate and uniformly disperse, the Primer primer is spin-coated on the surface of the substrate by a spin coater, and then placed on a hot plate at 105℃ for 2 min; the baked substrate is immersed in the ultrasonically dispersed carbon nanotube solution culture dish, and the culture dish is placed in a 60℃ water bath, wherein the deionized water liquid level is just above the carbon nanotube solution liquid level in the culture dish, and the deposition of the carbon nanotube film is completed after 2-3 hours.

7. The fabrication method of artificial synapse transistor based on thermal field control according to claim 3, characterized in that, In step (5), LOR3A and S-1813 double-layer photoresist are spin-coated on the surface of the carbon nanotube film in sequence by a spin coater, the exposed pattern is a square region with a side length of 180-182 μm; The exposed sample is placed in an oxygen plasma cleaning machine, the oxygen flow rate is 180 sccm, the power is 200 W, and the cleaning time is 2 min, so as to remove the excess carbon nanotube film outside the channel.

8. The fabrication method of artificial synapse transistor based on thermal field control according to claim 3, characterized in that, In step (6), a 40 nm hafnium oxide dielectric layer is prepared above the carbon nanotube film using an atomic layer deposition device at a temperature of 200℃; the precursor is selected, the hafnium precursor is selected as tetra(dimethylamino)hafnium, the oxygen source precursor is water, and the deposition process parameters include temperature setting, gas flow rate and pulse time setting; in terms of temperature, the temperature of the hafnium precursor and the substrate is a key parameter, the deposition temperature is 200℃; the gas flow rate needs to be accurately controlled, and the pulse time refers to the residence time of the precursor gas in the reaction chamber; The deposition cycle process starts from the input of hafnium precursor gas, adsorption and carrier gas purge; then the oxygen source precursor gas is input, and after reaction, carrier gas purge is performed again; the above steps are repeated to form an atomic layer deposition cycle, each cycle deposits 0.05-0.2 nm of hafnium oxide film, and the film thickness is accurately controlled by controlling the cycle number; wherein the reaction temperature is set to 200℃, the flow rate of hafnium precursor is 30sccm, the flow rate of water vapor is 150sccm, and the flow rate of nitrogen as carrier gas is 100sccm; in each cycle, the pulse time of hafnium precursor is 0.5 seconds, the pulse time of water vapor is 1 second, and the carrier gas purge time is 5s; After 200-500 atomic layer deposition cycles, a 10-50 nm thick hafnium oxide dielectric layer is prepared.

9. The fabrication method of artificial synapse transistor based on thermal field control according to claim 3, characterized in that, In step (8), a reactive ion etching machine is used for etching, and the etching conditions are: using carbon tetrafluoride with a flow rate of 50sccm as etching gas, pressure 5.0-5.5 Pa, power 100 W, etching time 5-10 min.

10. The fabrication method of artificial synapse transistor based on thermal field control according to claim 3, wherein, In step (9), the surface of the thermoelectric device is sequentially sprayed with acetone and isopropyl alcohol for cleaning, and after standing for 1 min, it is wiped dry with a dust-free cloth to remove surface impurities, and the phase change heat conduction material is attached to the surface of the thermoelectric device, and the carbon nanotube field effect transistor substrate is attached to the bottom. The surface temperature of the thermoelectric device is controlled by an external DC power supply, with a temperature range of -25℃ to 120℃, a temperature step accuracy of 0.1℃, and a temperature change rate of 3.84℃ / s.

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