Three-dimensional semiconductor memory device

Abstract

Disclosed is a three-dimensional semiconductor memory device including: gate-to-gate dielectric layers and electrode layers alternately stacked on a substrate; vertical semiconductor patterns penetrating the gate-to-gate dielectric layers and the electrode layers and extending into the substrate; barrier dielectric patterns between the vertical semiconductor patterns and the electrode layers; tunnel dielectric layers between the barrier dielectric patterns and the vertical semiconductor patterns and in contact with the gate-to-gate dielectric layers; and first charge storage patterns between the barrier dielectric patterns and the tunnel dielectric layers. One of the first charge storage patterns is in contact with a top surface and a bottom surface of one of the barrier dielectric patterns.

Description

Technical Field

[0001] The present invention relates to three-dimensional semiconductor memory devices. Background Technology

[0002] Semiconductor devices have become highly integrated to meet customers' potential demands for higher performance and / or lower manufacturing costs. Since the integration of semiconductor devices is a factor in determining product price, there is an increasing need for higher levels of integration. The integration level of a typical two-dimensional or planar semiconductor device is primarily determined by the area occupied by a single memory cell, and therefore it is influenced by the level of technology used to form intricate patterns. However, the expensive processing equipment required to increase the patterning fineness may set a practical limit on increasing the integration level of two-dimensional or planar semiconductor devices. Therefore, three-dimensional semiconductor memory devices with three-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0003] Some exemplary embodiments of the present invention provide three-dimensional semiconductor memory devices with increased reliability.

[0004] The purpose of this invention is not limited to the purposes mentioned above, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0005] According to some exemplary embodiments conceived in this invention, a three-dimensional semiconductor memory device may include: a plurality of inter-gate dielectric layers and a plurality of electrode layers alternately stacked on a substrate; a vertical semiconductor pattern penetrating the inter-gate dielectric layers and electrode layers, the vertical semiconductor pattern extending into the substrate; a plurality of barrier dielectric patterns, spaced apart from each other, respectively between the vertical semiconductor pattern and the electrode layers; a tunnel dielectric layer, contacting the inter-gate dielectric layer, between the barrier dielectric pattern and the vertical semiconductor pattern; and a plurality of first charge storage patterns, spaced apart from each other, respectively between the barrier dielectric pattern and the tunnel dielectric layer. One of the first charge storage patterns may contact the top and bottom surfaces of one of the barrier dielectric patterns.

[0006] According to some exemplary embodiments of the present invention, a three-dimensional semiconductor memory device may include: a substrate on a peripheral logic structure; a source pattern on the substrate; a plurality of inter-gate dielectric layers and a plurality of electrode layers alternately stacked on the source pattern; a vertical semiconductor pattern penetrating the inter-gate dielectric layers, electrode layers, and source pattern, the vertical semiconductor pattern extending into the substrate; a plurality of barrier dielectric patterns spaced apart from each other, respectively between the vertical semiconductor pattern and the electrode layers; a tunnel dielectric layer in contact with the inter-gate dielectric layer, the tunnel dielectric layer being in contact with each other; and a plurality of first charge storage patterns spaced apart from each other, respectively between the barrier dielectric pattern and the tunnel dielectric layer. One of the first charge storage patterns may contact a sidewall of one of the barrier dielectric patterns and simultaneously contact a sidewall of the inter-gate dielectric layer adjacent to said first charge storage pattern.

[0007] According to some exemplary embodiments conceived in this invention, a three-dimensional semiconductor memory device may include: a plurality of inter-gate dielectric layers and a plurality of electrode layers alternately stacked on a substrate; a vertical semiconductor pattern penetrating the inter-gate dielectric layers and the electrode layers, the vertical semiconductor pattern extending into the substrate; a plurality of blocking dielectric patterns spaced apart from each other, respectively between the vertical semiconductor pattern and the electrode layers; a tunnel dielectric layer in contact with the inter-gate dielectric layer, the tunnel dielectric layer being in contact with the inter-gate dielectric layer; and a plurality of first charge storage patterns spaced apart from each other, respectively between the blocking dielectric pattern and the tunnel dielectric layer. The vertical length of one of the first charge storage patterns may be greater than the vertical length of one of the blocking dielectric patterns. The blocking dielectric pattern may be in contact with the first charge storage pattern. Attached Figure Description

[0008] Figure 1 A block diagram illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to a concept of the present invention is shown.

[0009] Figure 2 A circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some exemplary embodiments of the concept of the present invention is shown.

[0010] Figure 3 A top view is shown illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to a concept of the present invention.

[0011] Figure 4 It shows along Figure 3 A sectional view taken by line A-A'.

[0012] Figure 5It shows Figure 4 Enlarged view of section P1.

[0013] Figure 6 The display shows Figure 5 A perspective view of the charge storage pattern.

[0014] Figure 7 It shows along Figure 3 The sectional view taken by line B-B'.

[0015] Figure 8 , Figure 9A , Figure 10A , Figure 11 , Figure 12 , Figure 13 , Figure 14A and Figure 15 Display manufacturing is shown Figure 4 A cross-sectional view of a method for constructing a three-dimensional semiconductor memory device.

[0016] Figure 9B The display shows Figure 9A Enlarged view of section P1.

[0017] Figure 10B The display shows Figure 10A Enlarged view of section P1.

[0018] Figure 14B The display shows Figure 14A Enlarged view of section P1.

[0019] Figure 16 , Figure 17 and Figure 18 The display shows the relationship with Figure 4 Enlarged view of segment P1 corresponding to segment P1.

[0020] Figure 19 It shows along Figure 3 A sectional view taken by line A-A'.

[0021] Figure 20A The display shows Figure 19 Enlarged view of section P1.

[0022] Figure 20B The display shows Figure 19 An enlarged view of a deformation example of section P1.

[0023] Figure 21 and Figure 22 Display manufacturing is shown Figure 19 A cross-sectional view of a method for constructing a three-dimensional semiconductor memory device.

[0024] Figure 23 It shows along Figure 3A sectional view taken by line A-A'.

[0025] Figure 24 The display shows Figure 23 Enlarged view of section P1.

[0026] Figure 25 and Figure 26 Display manufacturing is shown Figure 23 A cross-sectional view of a method for constructing a three-dimensional semiconductor memory device.

[0027] Figure 27 The display shows Figure 23 An enlarged view of a deformation example of section P1. Detailed Implementation

[0028] Some exemplary embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings to help to clearly explain the inventive concept.

[0029] Figure 1 A block diagram illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to a concept of the present invention is shown.

[0030] Reference Figure 1 A three-dimensional semiconductor memory device according to some exemplary embodiments of the present invention may include a peripheral logic structure PS, a cell array structure CS on the peripheral logic structure PS, and / or a connection line structure connecting the cell array structure CS to the peripheral logic structure PS.

[0031] The peripheral logic structure PS may include row decoders and column decoders, page buffers and / or control circuitry.

[0032] When viewed from above, the cell array structure CS can overlap with the peripheral logic structure PS. The cell array structure CS can include multiple memory blocks BLK0 to BLKn, each memory block being a data erasure unit. Each of the memory blocks BLK0 to BLKn can include a memory cell array with a three-dimensional structure (or a vertical structure).

[0033] Figure 2 A circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some exemplary embodiments of the concept of the present invention is shown.

[0034] Reference Figure 2 On each of the memory blocks BLK0 to BLKn, cell strings CSTRs can be arranged two-dimensionally along a first direction D1 and a second direction D2, and can extend along a third direction D3. Multiple cell strings CSTRs can be connected in parallel to each of the bit lines BL0 to BL2. Multiple cell strings CSTRs can be connected together to a common source line CSL.

[0035] One of the cell strings (CSTRs) may include series-connected string select transistors SST21 and SST11, series-connected memory cell transistors (MCTs), ground select transistors (GSTs), and erase control transistors (ECTs). Each memory cell transistor (MCT) may include a data storage element. The CSTR may also include a dummy cell (DMC) between the string select transistor SST11 and the memory cell transistors (MCTs) and between the ground select transistor GST and the memory cell transistors (MCTs). Other cell strings (CSTRs) may have the same or similar structures as discussed above.

[0036] The serial select transistor SST11 can be controlled by the serial select line SSL11, and the serial select transistor SST21 can be controlled by the serial select line SSL21. The memory cell transistor MCT can be controlled by the corresponding word lines WL0 to WLn, and the dummy cell transistor DMC can be controlled by the corresponding dummy word line DWL. The ground select transistor GST can be controlled by the ground select lines GSL0, GSL1, or GSL2, and the erase control transistor ECT can be controlled by the erase control line ECL.

[0037] A memory cell transistor (MCT) may include a gate electrode that is spaced at the same or substantially the same distance from the common source line (CSL) and connected to one of the word lines WL0 to WLn, thus having an equipotential state. Conversely, although the gate electrode of the memory cell MCT is spaced at the same or substantially the same distance from the common source line (CSL), the gate electrodes of different rows or columns can be controlled independently of each other.

[0038] Figure 3 A top view is shown illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to a concept of the present invention. Figure 4 It shows along Figure 3 A sectional view taken by line A-A'. Figure 5 It shows Figure 4 Enlarged view of section P1. Figure 6 The display shows Figure 5 A perspective view of the charge storage pattern. Figure 7 It shows along Figure 3 The sectional view taken by line B-B'.

[0039] Reference Figures 3 to 7 The cell array structure CS can be disposed on the peripheral logic structure PS. The peripheral logic structure PS may include a first substrate 100, a peripheral transistor PTR, a peripheral interlayer dielectric layer 102, and peripheral connection lines 104 in the peripheral interlayer dielectric layer 102 and electrically connected to the peripheral transistor PTR. Figure 4 The diagram illustrating the internal structure of the external logic structure PS is omitted, but this internal structure can be compared with... Figure 7The external logic structure PS shown has the same or similar internal structure.

[0040] The cell array structure CS may include a second substrate 10. The second substrate 10 may be one of a semiconductor material (e.g., a silicon wafer), a dielectric material (e.g., glass), or a semiconductor or conductor covered by a dielectric material. The second substrate 10 may be a semiconductor layer. The second substrate 10 may include a cell array region CAR and a connection region CNR. The connection region CNR may be located at the edge of the cell array region CAR.

[0041] Figure 3 It shows the BLK structure with a single block (which is Figure 1 The cell array structure CS corresponds to one of the memory blocks BLK0 to BLKn shown. A first source contact plug CSPLG1 can be disposed between adjacent block structures BLK. Additionally, a second source contact plug CSPLG2 can be disposed on the central portion of the block structure BLK, and can divide the block structure BLK into two parts in the second direction D2. When in... Figure 3 When viewed in the top view shown, the first source contact plug CSPLG1 may have a linear shape that extends continuously in the first direction D1. On the other hand, the second source contact plug CSPLG2 may have discontinuous segments (or cut-off areas) in the connection region CNR. The block structure BLK and the first source contact plug CSPLG1 and the second source contact plug CSPLG2 may have dielectric spacers SS made of dielectric material therebetween. The first source contact plug CSPLG1 and the second source contact plug CSPLG2 may include at least one selected from, for example, doped semiconductors (e.g., doped silicon), metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and transition metals (e.g., titanium or tantalum).

[0042] The block structure BLK may include a first stack ST1 on the second substrate 10 and a second stack ST2 on the first stack ST1. The first stack ST1 may include a source structure SC adjacent to the second substrate 10. The source structure SC may include a first source pattern SCP1 spaced apart from the second substrate 10 and a second source pattern SCP2 between the first source pattern SCP1 and the second substrate 10. The first source pattern SCP1 may include a semiconductor pattern doped with impurities, such as doped polysilicon. The second source pattern SCP2 may include a semiconductor pattern doped with impurities, such as doped polysilicon. The second source pattern SCP2 may also include a semiconductor material different from the semiconductor material of the first source pattern SCP1. The impurities doped in the second source pattern SCP2 may have the same conductivity type as the impurities doped in the first source pattern SCP1. The impurities doped in the second source pattern SCP2 may have the same or different concentrations as the impurities doped in the first source pattern SCP1.

[0043] The second stack ST2 may be covered by an upper dielectric layer 22. The first stack ST1 and the second stack ST2 may include alternately stacked electrode layers EL1, EL2, EL, ELm, and ELn, and an inter-gate dielectric layer 12. The electrode layers EL1, EL2, EL, ELm, and ELn may include, from bottom to top, a first electrode layer EL1, a second electrode layer EL2, an intermediate electrode layer EL, an m-th electrode layer ELm, and an n-th electrode layer ELn. The first stack ST1 may have a first electrode layer EL1, a second electrode layer EL2, and one or more intermediate electrode layers EL, and the second stack ST2 may have the remaining intermediate electrode layers EL, the m-th electrode layer ELm, and the n-th electrode layer ELn.

[0044] The first electrode layer EL1 can correspond to, for example, Figure 2 The erase control line ECL. The second electrode layer EL2 can correspond to, for example, one of the ground selection lines GSL0, GSL1, and GSL2. The intermediate electrode layer EL can correspond to Figure 2 The word lines WL0 to WLn. The separation dielectric pattern 9 and the second source contact plug CSPLG2 can divide the m-th electrode layer ELm into multiple lines, corresponding to the string select lines SSL11, SSL12, and SSL13 extending in the first direction D1 and spaced apart from each other in the second direction D2, as shown below. Figure 2 As shown. The separation dielectric pattern 9 and the second source contact plug CSPLG2 can divide the nth electrode layer ELn into multiple lines, which correspond to the series select lines SSL21, SSL22 and SSL23 extending in the first direction D1 and spaced apart from each other in the second direction D2, as shown. Figure 2As shown. Electrode layers EL1, EL2, EL, ELm and ELn may include at least one selected from, for example, doped semiconductors (e.g., doped silicon), metals (e.g., tungsten, copper, aluminum, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.) and transition metals (e.g., titanium, tantalum, etc.).

[0045] On the cell array region CAR, the first source contact plug CSPLG1 can penetrate the inter-gate dielectric layer 12 and the electrode layers EL1, EL2, EL, ELm, and ELn, and can be electrically connected to the source structure SC. The first source contact plug CSPLG1 can contact the first source pattern SCP1 of the source structure SC, but can be spaced apart from the second source pattern SCP2 of the source structure SC. The first source pattern SCP1 can contact the sidewall of the second source pattern SCP2. A buffer dielectric layer 11 can be inserted between the second substrate 10 and the first source pattern SCP1 adjacent to the first source contact plug CSPLG1. On the cell array region CAR, the second source contact plug CSPLG2 can penetrate the inter-gate dielectric layer 12 and the electrode layers EL1, EL2, EL, ELm, and ELn, and can have an electrical connection to the source structure SC. The second source contact plug CSPLG2 can be spaced apart from the first source pattern SCP1 by a dielectric spacer SS, but can contact the second source pattern SCP2. The dielectric spacer SS can be inserted between the electrode layers EL1, EL2, EL, ELm, and ELn and the first source contact plug CSPLG1 and the second source contact plug CSPLG2. Figure 3 , Figure 4 and Figure 7 Although seven electrode layers EL1, EL2, EL, ELm and ELn are shown for ease of description, the number of electrode layers EL1, EL2, EL, ELm and ELn is not limited to this, but can be greater than 7.

[0046] like Figure 3 As shown, multiple vertical semiconductor patterns VS and multiple first dummy vertical semiconductor patterns DVS1 can be disposed on the cell array region CAR. The first dummy vertical semiconductor patterns DVS1 can be linearly disposed along a first direction D1 in the central portion of a segment of the block structure BLK. Separate dielectric patterns 9 can be disposed between the upper portions of the first dummy vertical semiconductor patterns DVS1.

[0047] Reference Figure 3 and Figure 7The block structure BLK can have a stepped structure on the connection region CNR. For example, the electrode layers EL1, EL2, EL, ELm, and ELn can have their length in the first direction D1 decrease with increasing distance from the second substrate 10. Each of the electrode layers EL1, EL2, EL, ELm, and ELn can have a pad portion (not shown) on the connection region CNR. The first stack ST1 can also include a first interlayer dielectric layer 24 covering the ends of the electrode layers EL1, EL2, and EL. The first interlayer dielectric layer 24 can have a top surface coplanar with the top surface of the first stack ST1. The second stack ST2 can include a second interlayer dielectric layer 26 covering the ends of the electrode layers EL, ELm, and ELn, and also covering the first interlayer dielectric layer 24. The second interlayer dielectric layer 26 can have a top surface coplanar with the top surface of the second stack ST2.

[0048] On the connection region CNR, multiple second dummy vertical semiconductor patterns DVS2 can be configured to penetrate the first stack ST1 and the second stack ST2 and extend into the second substrate 10. The second dummy vertical semiconductor patterns DVS2 can have a width greater than the width of the vertical semiconductor pattern VS and the width of the first dummy vertical semiconductor pattern DVS1. The vertical semiconductor pattern VS, as well as the first dummy vertical semiconductor pattern DVS1 and the second dummy vertical semiconductor pattern DVS2, can all include a doped or undoped monocrystalline silicon layer or a polycrystalline silicon layer. Each of the vertical semiconductor pattern VS, the first dummy vertical semiconductor pattern DVS1, and the second dummy vertical semiconductor pattern DVS2 can have a hollow shell shape. Each of the vertical semiconductor pattern VS, the first dummy vertical semiconductor pattern DVS1, and the second dummy vertical semiconductor pattern DVS2 can have an interior, each filled with a buried dielectric pattern 29.

[0049] Conductive pads 34 may be provided on the corresponding upper portions of the vertical semiconductor pattern VS and the first dummy vertical semiconductor pattern DVS1 and the second dummy vertical semiconductor pattern DVS2. The conductive pads 34 may be doped regions or may be made of a conductive material. The conductive pads 34 on each vertical semiconductor pattern VS may be connected to the bit line BL via bit line contacts BPLG penetrating the upper dielectric layer 22. Conversely, the conductive pads 34 on each of the first dummy vertical semiconductor pattern DVS1 and the second dummy vertical semiconductor pattern DVS2 may not be connected to the bit line BL. The vertical semiconductor pattern VS and the first dummy vertical semiconductor pattern DVS1 and the second dummy vertical semiconductor pattern DVS2 may have sidewalls, each sidewall having an inflection point between the first stack ST1 and the second stack ST2 where the slope changes.

[0050] Multiple through-path TVS can be disposed on the edge of the connection region CNR. The upper dielectric layer 22 can be provided with connection lines 28 connected to the through-path TVS. Connection lines 28 can be electrically connected to at least one of the bit line BL, electrode layers EL1, EL2, EL, ELm, and ELn, at least one of the vertical semiconductor patterns VS, and / or the first source contact plug CSPLG1 and the second source contact plug CSPLG2. The through-path TVS can penetrate the upper dielectric layer 22, the second interlayer dielectric layer 26, the first interlayer dielectric layer 24, and the peripheral interlayer dielectric layer 102, and can electrically connect the connection lines 28 to the peripheral connection lines 104.

[0051] Reference Figures 4 to 6 A tunnel dielectric layer TL can be interposed between the vertical semiconductor pattern VS and the electrode layers EL1, EL2, EL, ELm, and ELn. A charge storage pattern CTL can be interposed between the tunnel dielectric layer TL and the electrode layers EL1, EL2, EL, ELm, and ELn. A barrier dielectric pattern BCL can be interposed between the charge storage pattern CTL and the electrode layers EL1, EL2, EL, ELm, and ELn. A high-k dielectric layer HL can be interposed between the barrier dielectric pattern BCL and the electrode layers EL1, EL2, EL, ELm, and ELn. The high-k dielectric layer HL can extend to be located between the inter-gate dielectric layer 12 and the electrode layers EL1, EL2, EL, ELm, and ELn.

[0052] The tunnel dielectric layer TL and the blocking dielectric pattern BCL may include, for example, a silicon oxide layer. The charge storage pattern CTL may include, for example, a silicon nitride layer, a silicon oxide nitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, a stacked trap layer, a polycrystalline silicon layer, a variable resistance layer, or a phase change layer. The high-k dielectric layer HL may include a metal oxide layer material such as an aluminum oxide layer, whose dielectric constant is greater than that of the silicon oxide layer. The high-k dielectric layer HL may have sidewalls aligned with the sidewalls 12s of the adjacent high-k dielectric layer HL of the inter-gate dielectric layer 12.

[0053] Reference Figure 5 and Figure 6The tunnel dielectric layer TL can extend continuously along the vertical semiconductor pattern VS. The barrier dielectric patterns BCLs adjacent to the corresponding electrode layers EL1, EL2, EL, ELm, and ELn can be spaced apart from each other and not connected. Each barrier dielectric pattern BCL can have sidewalls BCLs, a top surface BCL1, and a bottom surface BCLb. Compared to the sidewalls 12s of the inter-gate dielectric layer 12 adjacent to the barrier dielectric pattern BCL, the barrier dielectric pattern BCL can protrude towards the vertical semiconductor pattern VS. The charge storage patterns CTLs adjacent to the corresponding barrier dielectric pattern BCLs can be spaced apart from each other and not connected. The charge storage pattern CTL can have a vertical length L1 greater than the vertical length L2 of the barrier dielectric pattern BCL. The charge storage pattern CTL can contact the sidewalls BCLs of the barrier dielectric pattern BCL and simultaneously contact a portion of the sidewalls 12s of the inter-gate dielectric layer 12.

[0054] A charge storage pattern CTL may contact the sidewall BCLs, top surface BCLu, and bottom surface BCLb of a corresponding barrier dielectric pattern in a barrier dielectric pattern BCL. The charge storage pattern CTL may have a C-shaped profile. The charge storage pattern CTL may protrude toward the vertical semiconductor pattern VS compared to the sidewall 12s adjacent to the charge storage pattern CTL of the inter-gate dielectric layer 12. The charge storage pattern CTL may include: sidewall portions CTLs that contact the sidewall BCLs of the barrier dielectric pattern BCL; an upper protrusion CTLu that contacts the top surface BCLu of the barrier dielectric pattern BCL; and a lower protrusion CTLb that contacts the bottom surface BCLb of the barrier dielectric pattern BCL. The upper protrusion CTLu and the lower protrusion CTLb may protrude laterally more than the sidewall portions CTLs. The sidewall portions CTLs may have a cylindrical shape. Each of the upper protrusion CTLu and the lower protrusion CTLb may have an annular shape.

[0055] In this invention, because the charge storage patterns (CTLs) are spaced apart from each other and not connected, when operating a three-dimensional semiconductor memory device, it is possible to prevent charges stored in one charge storage pattern (CTL) from moving to an adjacent charge storage pattern (CTL), thereby avoiding data loss. As a result, multi-level cell (MLC) operations can be advantageous.

[0056] Furthermore, in this invention, because the charge storage pattern CTL contacts the sidewalls BCLs, top surface BCLu, and bottom surface BCLb of the barrier dielectric pattern BCL, the charge storage area can be increased compared to the case where the charge storage pattern CTL only contacts the sidewalls BCLs of the barrier dielectric pattern BCL. For example, because the charge storage pattern CTL has a C-shaped cross-section or a vertical length L1 greater than the vertical length L2 of the barrier dielectric pattern BCL, the charge storage area can be increased to facilitate the operation of the multilevel cell (MLC).

[0057] Figure 7 Segment P1 can be with Figure 5 The same segment P1. For example, Figure 5 The shape of the interlayer dielectric layer 24 can correspond to the shape of the barrier dielectric pattern BCL, charge storage pattern CTL, tunnel dielectric layer TL, and high-k dielectric layer HL interposed between the electrode layers EL1, EL2, EL, ELm, and ELn and the first dummy vertical semiconductor pattern DVS1 and the second dummy vertical semiconductor pattern DVS2. Uneven structures can be formed on the sidewalls of the vertical semiconductor pattern VS and the sidewalls of the first dummy vertical semiconductor pattern DVS1 and the second dummy vertical semiconductor pattern DVS2. Therefore, the channel length can be increased to reduce or prevent short-channel effects. The tunnel dielectric layer TL can have an uneven structure in its cross-section. One of the first interlayer dielectric layer 24 and the second interlayer dielectric layer 26 may have neither a charge storage pattern CTL nor a barrier dielectric pattern BCL between it and the second dummy vertical semiconductor pattern DVS2, but may only have the tunnel dielectric layer TL.

[0058] The second source pattern SCP2 can contact the sidewalls of the vertical semiconductor pattern VS. For example... Figure 4 As shown, the remaining tunnel dielectric layer TLr can be interposed between the second substrate 10 and the bottom surface of the vertical semiconductor pattern VS. The second source pattern SCP2 can separate the remaining tunnel dielectric layer TLr from the tunnel dielectric layer TL. A portion of the second source pattern SCP2 can extend along the sidewall of the vertical semiconductor pattern VS in a third direction D3. The remaining dummy charge storage pattern CTLr can remain between the tunnel dielectric layer TL and the upper part of the first source pattern SCP1.

[0059] Figure 8 , Figure 9A , Figure 10A , Figure 11 , Figure 12 , Figure 13 , Figure 14A and Figure 15 Display manufacturing is shown Figure 4 A cross-sectional view of a method for constructing a three-dimensional semiconductor memory device. Figure 9B The display shows Figure 9A Enlarged view of section P1. Figure 10B The display shows Figure 10A Enlarged view of section P1. Figure 14B The display shows Figure 14A Enlarged view of section P1.

[0060] Reference Figure 8 The second substrate 10 can be positioned on the peripheral logic structure PS. The second substrate 10 can be adhered to the peripheral logic structure PS. Alternatively, a deposition process can be performed to form the second substrate 10 on the peripheral logic structure PS. A buffer dielectric layer 11 can be formed on the second substrate 10. The buffer dielectric layer 11 may include, for example, a silicon oxide layer. Deposition and etching processes can be performed to form a lower sacrificial layer 13 on the buffer dielectric layer 11. An auxiliary buffer dielectric layer 15 can be formed on the top surface and sidewalls of the lower sacrificial layer 13. The auxiliary buffer dielectric layer 15 may include, for example, a silicon oxide layer. A first source pattern SCP1 can be formed on the auxiliary buffer dielectric layer 15. The first source pattern SCP1 may include, for example, a semiconductor layer doped with impurities. A first initial stack PST1 can be formed by alternately stacking an inter-gate dielectric layer 12 and a sacrificial layer 19 on the first source pattern SCP1. The first initial stack PST1 can be patterned to form a plurality of first channel vias CH1 spaced apart from each other. The first channel via CH1 can be filled with a buried dielectric layer 5, and then a second initial stack PST2 can be formed by alternately stacking an inter-gate dielectric layer 12 and a sacrificial layer 19 on the first initial stack PST1. The second initial stack PST2 can be etched to form a second channel via CH2 that overlaps with the first channel via CH1. The second channel via CH2 can expose the buried dielectric layer 5. The sacrificial layer 19 and the lower sacrificial layer 13 can be formed of a material that is etch-selective relative to the inter-gate dielectric layer 12. For example, the inter-gate dielectric layer 12 can be formed of a silicon oxide layer, and the sacrificial layer 19 and the lower sacrificial layer 13 can be formed of a silicon nitride layer. The second channel via CH2 can have a lower width smaller than the upper width of the first channel via CH1. Furthermore, a discrete dielectric pattern 9 can be formed in the second initial stack PST2.

[0061] Reference Figure 9A and Figure 9BAfter the buried dielectric layer 5 is removed, a first selective deposition process can be performed to form an initial barrier pattern PBCL on the corresponding sidewalls of the sacrificial layer 19 exposed to the first channel via CH1 and the second channel via CH2. When the sacrificial layer 19 is formed of a silicon nitride layer, the initial barrier pattern PBCL can be formed of a silicon layer or a polysilicon layer. A silane gas (such as silane (SiH4) or silane (Si2H6)) can be supplied to perform the first selective deposition process. In the first selective deposition process, since the affinity between the silane gas and the silicon nitride layer constituting the sacrificial layer 19 is greater than the affinity between the silane gas and the silicon oxide layer constituting the inter-gate dielectric layer 12, the initial barrier pattern PBCL can be deposited only on the surface of the sacrificial layer 19. Each initial barrier pattern PBCL can have sidewall PBCLs, a top surface PBBCLu, and a bottom surface PBCLb. When the lower sacrificial layer 13 is formed from a silicon oxide layer, a dummy initial barrier pattern DPBCL can also be formed on the sidewall of the lower sacrificial layer 13 during the formation of the initial barrier pattern PBCL. The dummy initial barrier pattern DPBCL can be formed from a silicon layer or a polysilicon layer.

[0062] A second selective deposition process can be performed to form a charge storage pattern (CTL) on the surface of the corresponding initial barrier pattern PBCL. The charge storage pattern CTL can be formed from a silicon nitride layer. In the second selective deposition process, the initial barrier pattern PBCL and the dummy initial barrier pattern DPBCL can be provided with one or more silicon source gases (e.g., silane, dichlorosilane, and tetrachlorosilane) only on their surfaces to alternately and repeatedly perform the first and second steps, the first step forming a single-atom-thick silicon layer, and the second step supplying a nitrogen source gas (e.g., ammonia) to bond the silicon layer with nitrogen to form a single-atom-thick silicon nitride layer. When the second selective deposition process is performed, because the affinity between the silicon source gas and the silicon layer constituting the initial barrier pattern PBCL is greater than the affinity between the silicon source gas and the silicon oxide layer constituting the inter-gate dielectric layer 12, the charge storage pattern CTL can be formed only on the surface of the initial barrier pattern PBCL. Each charge storage pattern CTL can be formed to contact the sidewall PBCLs, top surface PBCLu, and bottom surface PBCLb of the initial barrier pattern PBCL. When forming the charge storage pattern CTL, a dummy charge storage pattern DCTL can also be formed on the dummy initial blocking pattern DPBCL and the sidewalls of the first source pattern SCP1. The dummy charge storage pattern DCTL can be formed from a silicon nitride layer.

[0063] An atomic layer deposition (ALD) process can be performed to conformally form a tunnel dielectric layer TL, which conformally covers the inner sidewalls and bottom surface of the first channel hole CH1 and the second channel hole CH2.

[0064] Reference Figure 10A and Figure 10B A semiconductor layer can be conformally deposited on the tunnel dielectric layer TL to form a buried dielectric layer 5 to fill the first channel via CH1 and the second channel via CH2. A polishing process can then be performed to form a vertical semiconductor pattern VS in the first channel via CH1 and the second channel via CH2. The upper part of the buried dielectric layer 5 can be recessed, and the recessed area can then be filled with a semiconductor layer or conductive layer doped with impurities to form a conductive pad 34. The aforementioned process can also form... Figure 3 and Figure 7 The first dummy vertical semiconductor pattern DVS1 and the second dummy vertical semiconductor pattern DVS2 are shown.

[0065] Reference Figure 10A and Figure 11 At locations spaced apart from the vertical semiconductor pattern VS, the second initial stack PST2 and the first initial stack PST1 can be sequentially etched to form the first source contact groove CSG1 and the second source contact groove CSG2. The second source contact groove CSG2 can expose the sidewalls of the lower sacrificial layer 13 and the sidewalls of the auxiliary buffer dielectric layer 15.

[0066] Reference Figure 11 and Figure 12 An isotropic etching process can be performed to remove the lower sacrificial layer 13, auxiliary buffer dielectric layer 15, and buffer dielectric layer 11 exposed in the second source contact groove CSG2, thus forming a first empty space 13S. This first empty space 13S exposes the bottom surface and lower sidewall of the first source pattern SCP1 and also exposes the top surface of the second substrate 10. During this stage, a portion of the dummy initial blocking pattern DPBCL, the dummy charge storage pattern DCTL, and a portion of the tunnel dielectric layer TL can be removed to expose the lower sidewall of the vertical semiconductor pattern VS, leaving a remaining tunnel dielectric layer TLr on the bottom surface of the first channel hole CH1. Additionally, the remaining dummy charge storage pattern CTLr can be retained between the tunnel dielectric layer TL and the upper part of the first source pattern SCP1.

[0067] Reference Figure 12 and Figure 13A conductive layer can be conformally stacked on the second initial stack PST2 to fill the first empty space 13S, where the sacrificial layer 13 is removed through the second source contact groove CSG2. The conductive layer can also be formed on the sidewalls of the first source contact groove CSG1 and the second source contact groove CSG2. An etching process can be performed to remove the conductive layer from the sidewalls of the first source contact groove CSG1 and the second source contact groove CSG2, and then the first empty space 13S can be filled with a second source pattern SCP2 formed by the conductive layer. The first source contact groove CSG1 and the second source contact groove CSG2 can be exposed at their sidewalls.

[0068] Reference Figure 13 , Figure 14A and Figure 14B An isotropic etching process can be performed to remove the sacrificial layer 19 through the first source contact groove CSG1 and the second source contact groove CSG2, and a second empty space 19S can be formed between the gate inter-dielectric layers 12. The second empty space 19S can expose the initial blocking pattern PBCL. In addition, the second empty space 19S can also expose the sidewalls of the separation dielectric pattern 9.

[0069] Reference Figure 14A , Figure 14B and Figure 15 An oxidation process can be performed to oxidize the initial barrier pattern PBCL exposed in the second empty space 19S, thereby forming a barrier dielectric pattern BCL. Since the initial barrier pattern PBCL is formed from a silicon layer or a polysilicon layer, the barrier dielectric pattern BCL can be formed from a silicon oxide layer formed in the oxidation process described above. A high-k dielectric layer HL can be conformally formed to cover the sidewalls of the barrier dielectric pattern BCL and the top and bottom surfaces of the inter-gate dielectric layer 12, which are exposed in the second empty space 19S. A conductive layer can be formed to fill the second empty space 19S. The conductive layer can also be formed on the sidewalls of the first source contact groove CSG1 and the second source contact groove CSG2. The conductive layer can be removed from the sidewalls of the first source contact groove CSG1 and the second source contact groove CSG2, thereby exposing the sidewalls of the first source contact groove CSG1 and the second source contact groove CSG2. The second empty space 19S can be filled with electrode layers EL1, EL2, EL, ELm, and ELn formed from the conductive layer. Figure 15 Segment P1 can be with Figure 5 The same applies to section P1. Dielectric spacers SS can be formed on the sidewalls of the first source contact groove CSG1 and the second source contact groove CSG2. Subsequently, refer to... Figure 4The first source contact plug CSPLG1 and the second source contact plug CSPLG2 can be formed in the first source contact groove CSPLG1 and the second source contact groove CSPLG2, respectively.

[0070] Figure 16 and Figure 18 The display shows the relationship with Figure 4 Enlarged view of segment P1 corresponding to segment P1.

[0071] Reference Figure 16 In this embodiment, a three-layer charge storage pattern can be provided. For example, a first charge storage pattern CTL1 may be in contact with the sidewalls BCLs, top surface BCLu, and bottom surface BCLb of a barrier dielectric pattern BCL. A second charge storage pattern CTL2 may cover the sidewalls, top surface, and bottom surface of the first charge storage pattern CTL1. A third charge storage pattern CTL3 may cover the sidewalls, top surface, and bottom surface of the second charge storage pattern CTL2. The second charge storage pattern CTL2 may include a material different from the materials of the first charge storage pattern CTL1 and the third charge storage pattern CTL3. For example, the second charge storage pattern CTL2 may include a silicon layer or a polysilicon layer. The first charge storage pattern CTL1 and the third charge storage pattern CTL3 may include silicon nitride layers.

[0072] Or, refer to Figure 17 A double-layer charge storage pattern can be provided. For example, a first charge storage pattern CTL1 can contact the sidewalls BCLs, top surface BCU, and bottom surface BCLb of a barrier dielectric pattern BCL. A second charge storage pattern CTL2 can cover the sidewalls, top surface, and bottom surface of the first charge storage pattern CTL1. The second charge storage pattern CTL2 can include a silicon layer or a polysilicon layer. The first charge storage pattern CTL1 can include a silicon nitride layer.

[0073] Reference Figure 18 In this embodiment, five charge storage patterns can be provided. For example, the first to fifth charge storage patterns CTL1 to CTL5 can be interposed between the barrier dielectric pattern BCL and the tunnel dielectric layer TL. The second charge storage pattern CTL2 and the fourth charge storage pattern CTL4 can include materials different from those of the first charge storage pattern CTL1, the third charge storage pattern CTL3, and the fifth charge storage pattern CTL5. For example, the second charge storage pattern CTL2 and the fourth charge storage pattern CTL4 can include silicon layers or polysilicon layers, and the first charge storage pattern CTL1, the third charge storage pattern CTL3, and the fifth charge storage pattern CTL5 can include silicon nitride layers.

[0074] Figures 16 to 18Semiconductor memory devices can be advantageous for performing multi-level cell (MLC) operations.

[0075] Figures 16 to 18 Semiconductor memory devices can be used in Figure 9A and Figure 9B The first selective deposition process and the second selective deposition process are performed alternately and repeatedly in the steps to form the structure.

[0076] Figure 19 It shows along Figure 3 A sectional view taken by line A-A'. Figure 20A The display shows Figure 19 Enlarged view of section P1.

[0077] Reference Figure 19 and Figure 20A The charge storage pattern CTL can have sidewalls aligned with the sidewalls 12s of the inter-gate dielectric layer 12. The charge storage pattern CTL can have the same vertical length as the barrier dielectric pattern BCL. Compared to the barrier dielectric pattern BCL and the high-k dielectric layer HL adjacent to the inter-gate dielectric layer 12, the inter-gate dielectric layer 12 between adjacent electrode layers EL1, EL2, EL, ELm, and ELn can protrude towards the vertical semiconductor pattern VS. Therefore, in Figure 19 and Figure 20A During operation of the semiconductor memory device, the inter-gate dielectric layer 12 can act as an electric field barrier to block or mitigate edge field effects caused by voltages applied to the electrode layers EL1, EL2, EL, ELm, and ELn adjacent to the inter-gate dielectric layer 12. Therefore, faults can be reduced or prevented, and the reliability of the semiconductor memory device can be increased. The tunnel dielectric layer TL and the vertical semiconductor pattern VS can have a roughness less than [a certain value]. Figure 4 The unevenness is shown in its cross-sectional view. The charge storage pattern CTL can contact the sidewalls BCLs of the blocking dielectric pattern BCL, but not the top surface BCU or bottom surface BCLb of the blocking dielectric pattern BCL. Other configurations can be referenced. Figures 3 to 7 The structures discussed are the same or similar.

[0078] Figure 20B The display shows Figure 19 An enlarged view of a deformation example of section P1.

[0079] Reference Figure 20BThe barrier dielectric pattern BCL may have sidewalls aligned with the sidewalls 12s of the inter-gate dielectric layer 12. The charge storage pattern CTL may contact the sidewalls BCLs of the barrier dielectric pattern BCL and simultaneously contact a portion of the sidewalls 12s of the inter-gate dielectric layer 12. The charge storage pattern CTL may contact the sidewalls BCLs of the barrier dielectric pattern BCL, but not the top surface BCLu and bottom surface BCLb of the barrier dielectric pattern BCL. The charge storage pattern CTL may have a vertical length L1 greater than the vertical length L2 of the barrier dielectric pattern BCL. Other configurations may be referenced. Figure 20A The structures discussed are the same or similar.

[0080] Figure 21 and Figure 22 Display manufacturing is shown Figure 20A A cross-sectional view of a method for constructing a three-dimensional semiconductor memory device.

[0081] Reference Figure 21 The buried dielectric layer 5 can be obtained from Figure 8 The first initial stack PST1 is removed, thereby exposing the sidewalls of the first channel via CH1 and the second channel via CH2. For example, an isotropic etching process can be performed to partially remove the sacrificial layer 19 and the lower sacrificial layer 13 to partially expose the top and bottom surfaces of the inter-gate dielectric layer 12 adjacent to the first channel via CH1 and the second channel via CH2. Additionally, the top surface of the buffer dielectric layer 11 can be exposed, and the bottom surface of the auxiliary buffer dielectric layer 15 can be exposed.

[0082] Reference Figure 21 and Figure 22 , refer to Figure 9A and Figure 9B The first selective deposition process discussed can be performed to form an initial barrier pattern PBCL on the sidewalls of the sacrificial layer 19 and the lower sacrificial layer 13. In this stage, the initial barrier pattern PBCL can be formed such that its thickness does not protrude beyond the sidewalls of the inter-gate dielectric layer 12. Furthermore, a second selective deposition process can be performed to form a charge storage pattern CTL. The charge storage pattern CTL can be formed such that its thickness does not protrude beyond the sidewalls of the inter-gate dielectric layer 12. Subsequently, a reference process can be performed. Figures 9A to 15 The process discussed is for manufacturing Figure 20A Semiconductor memory devices.

[0083] Figure 23 It shows along Figure 3 A sectional view taken by line A-A'. Figure 24 The display shows Figure 23 Enlarged view of section P1.

[0084] Reference Figure 23and Figure 24 Compared to the high-k dielectric layer HL, the sidewalls 12s of the inter-gate dielectric layer 12 can protrude laterally, but compared to the charge storage pattern CTL, the sidewalls 12s of the inter-gate dielectric layer 12 can not protrude laterally. The sidewalls 12s of the inter-gate dielectric layer 12 can have an uneven structure. The middle portion of the sidewalls 12s of the inter-gate dielectric layer 12 can protrude more than the top and bottom of the sidewalls 12s of the inter-gate dielectric layer 12. The charge storage pattern CTL can contact the sidewalls BCLs, top surface BCLu, and bottom surface BCLb of the blocking dielectric pattern BCL, and can have a C-shaped profile. Figure 23 and Figure 24 During operation of the semiconductor memory device, the inter-gate dielectric layer 12 can be used to block or mitigate edge field effects caused by voltages applied to the electrode layers EL1, EL2, EL, ELm, and ELn adjacent to the inter-gate dielectric layer 12. Therefore, faults can be reduced or prevented, and the reliability of the semiconductor memory device can be increased. Other configurations can be referenced above. Figure 19 The structures discussed are the same or similar.

[0085] Figure 25 and Figure 26 Display manufacturing is shown Figure 23 A cross-sectional view of a method for constructing a three-dimensional semiconductor memory device.

[0086] Reference Figure 24 and Figure 25 , Figure 21 The protruding inter-gate dielectric layer 12 shown can be subjected to an isotropic etching process at high temperature using one or more etchants including hydrofluoric acid and phosphoric acid to partially remove the protruding portion of the inter-gate dielectric layer 12, while simultaneously giving the sidewalls 12s of the inter-gate dielectric layer 12 a non-uniform or rounded profile.

[0087] Reference Figure 24 and Figure 26 , can execute reference Figure 9A and Figure 9B The first selective deposition process discussed is used to form the initial barrier dielectric pattern PBCL. Then, a second selective deposition process can be performed to form the charge storage pattern CTL. Subsequent processes can be performed as described in the reference. Figures 9A to 15 The execution discussed.

[0088] Figure 27 The display shows Figure 23 An enlarged view of a deformation example of section P1. Figure 27 The implementation method can correspond to Figure 24 Examples and Figure 16 Example combinations of cases.

[0089] Reference Figure 27 The first charge storage pattern CTL1 may contact the sidewalls BCLs, top surface BCLu, and bottom surface BCLb of the barrier dielectric pattern BCL. The second charge storage pattern CTL2 may cover the sidewalls, top surface, and bottom surface of the first charge storage pattern CTL1. The third charge storage pattern CTL3 may cover the sidewalls, top surface, and bottom surface of the second charge storage pattern CTL2. The second charge storage pattern CTL2 may include a material different from the materials of the first charge storage pattern CTL1 and the third charge storage pattern CTL3. For example, the second charge storage pattern CTL2 may include a silicon layer or a polysilicon layer. The first charge storage pattern CTL1 and the third charge storage pattern CTL3 may include silicon nitride layers. The middle portion of the sidewalls 12s of the inter-gate dielectric layer 12 may protrude further than the top and bottom of the sidewalls 12s of the inter-gate dielectric layer 12.

[0090] In the three-dimensional semiconductor memory device conceived according to the present invention, because the charge storage patterns are spaced apart from each other and not connected to each other, when operating the three-dimensional semiconductor memory device, it is possible to prevent the charge stored in the charge storage pattern from moving to the adjacent charge storage pattern, thereby avoiding data loss. As a result, the three-dimensional semiconductor memory device can improve reliability.

[0091] Furthermore, in the three-dimensional semiconductor memory device conceived according to the present invention, since the charge storage pattern has a C-shaped cross-section or a vertical length greater than the vertical length of the blocking dielectric pattern, the charge storage area can be increased to facilitate the operation of the multilevel cell (MLC).

[0092] Furthermore, in the three-dimensional semiconductor memory device conceived according to the present invention, the inter-gate dielectric layer between adjacent electrode layers can protrude toward the vertical semiconductor pattern compared to the blocking dielectric pattern or high-k dielectric layer adjacent to the inter-gate dielectric layer. Therefore, the inter-gate dielectric layer can serve as an electric field barrier to reduce or block edge field effects caused by voltages applied to adjacent electrode layers, thereby reducing or preventing faults and improving the reliability of the semiconductor memory device.

[0093] Although the invention has been described in conjunction with some exemplary embodiments of the inventive concept shown in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and essential characteristics of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made therein without departing from the scope and spirit of the inventive concept.

[0094] This application claims priority to Korean Patent Application No. 10-2019-0112099, filed on September 10, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A three-dimensional semiconductor memory device, comprising: a plurality of inter-gate dielectric layers and a plurality of electrode layers stacked alternately on a substrate; a vertical semiconductor pattern penetrating the inter-gate dielectric layers and the electrode layers, the vertical semiconductor pattern extending into the substrate; a plurality of blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, respectively, the plurality of blocking dielectric patterns being spaced apart from each other; a tunnel dielectric layer between the plurality of blocking dielectric patterns and the vertical semiconductor pattern, the tunnel dielectric layer being in contact with the inter-gate dielectric layers; and a plurality of first charge storage patterns between the plurality of blocking dielectric patterns and the tunnel dielectric layer, respectively, the first charge storage patterns being spaced apart from each other, wherein one of the first charge storage patterns is in contact with a top surface and a bottom surface of one of the plurality of blocking dielectric patterns, wherein a first blocking dielectric pattern of the plurality of blocking dielectric patterns is separated from a sidewall of the inter-gate dielectric layer adjacent to the first blocking dielectric pattern in a vertical direction.

2. The three-dimensional semiconductor memory device of claim 1, wherein each of the first charge storage patterns has a C-shaped cross-section.

3. The three-dimensional semiconductor memory device of claim 1, wherein the one of the first charge storage patterns is in contact with a sidewall of the inter-gate dielectric layer adjacent to the one of the plurality of blocking dielectric patterns.

4. The three-dimensional semiconductor memory device of claim 1, wherein a vertical length of the one of the first charge storage patterns is greater than a vertical length of the one of the plurality of blocking dielectric patterns.

5. The three-dimensional semiconductor memory device of claim 1, further comprising: a source pattern between the substrate and a lowermost one of the inter-gate dielectric layers; and a dummy charge storage pattern partially in contact with a sidewall of the source pattern.

6. The three-dimensional semiconductor memory device of claim 1, further comprising a remaining tunnel dielectric layer between and in contact with the vertical semiconductor pattern and the substrate, the remaining tunnel dielectric layer being spaced apart from the tunnel dielectric layer.

7. The three-dimensional semiconductor memory device of claim 1, wherein the plurality of blocking dielectric patterns and the first charge storage patterns protrude toward the vertical semiconductor pattern compared to a sidewall of the inter-gate dielectric layers.

8. The three-dimensional semiconductor memory device of claim 1, further comprising a second charge storage pattern between the tunnel dielectric layer and the one of the first charge storage patterns, the second charge storage pattern being in contact with a top surface and a bottom surface of the one of the first charge storage patterns, wherein the second charge storage pattern comprises a material different from a material of the first charge storage pattern. ​ 9. The three-dimensional semiconductor memory device of claim 8, further comprising a third charge storage pattern between the second charge storage pattern and the tunnel dielectric layer, the third charge storage pattern in contact with top and bottom surfaces of the second charge storage pattern, wherein the third charge storage pattern comprises a same material as a material of the first charge storage pattern.

10. The three-dimensional semiconductor memory device of claim 1, further comprising a plurality of high-k dielectric layers between the electrode layers and the plurality of blocking dielectric patterns, respectively, wherein sidewalls of the gate-to-gate dielectric layer protrude more than sidewalls of the high-k dielectric layers.

11. The three-dimensional semiconductor memory device of claim 1, further comprising a peripheral logic structure under the substrate, the peripheral logic structure electrically connected to at least one of the electrode layers or to the vertical semiconductor pattern.

12. A three-dimensional semiconductor memory device, comprising: a substrate over a peripheral logic structure; a source pattern on the substrate; a plurality of gate-to-gate dielectric layers and a plurality of electrode layers alternately stacked on the source pattern; a vertical semiconductor pattern penetrating the gate-to-gate dielectric layers, the electrode layers, and the source pattern, the vertical semiconductor pattern extending into the substrate; a plurality of blocking dielectric patterns between the vertical semiconductor pattern and corresponding electrode layers, respectively, the plurality of blocking dielectric patterns spaced apart from each other; a tunnel dielectric layer between the plurality of blocking dielectric patterns and the vertical semiconductor pattern, the tunnel dielectric layer in contact with the gate-to-gate dielectric layer; and a plurality of first charge storage patterns between the plurality of blocking dielectric patterns and the tunnel dielectric layer, respectively, the first charge storage patterns spaced apart from each other, wherein one of the first charge storage patterns is in contact with a sidewall of one of the plurality of blocking dielectric patterns and simultaneously in contact with a sidewall of the gate-to-gate dielectric layer adjacent to the one of the first charge storage patterns, wherein a first blocking dielectric pattern of the plurality of blocking dielectric patterns is separated from a sidewall of the gate-to-gate dielectric layer vertically adjacent to the first blocking dielectric pattern.

13. The three-dimensional semiconductor memory device of claim 12, wherein a vertical length of the one of the first charge storage patterns is greater than a vertical length of the one of the plurality of blocking dielectric patterns.

14. The three-dimensional semiconductor memory device of claim 12, wherein each of the first charge storage patterns has a C-shaped cross-section.

15. The three-dimensional semiconductor memory device of claim 12, further comprising a dummy charge storage pattern partially in contact with a sidewall of the source pattern and spaced apart from the first charge storage patterns.

16. The three-dimensional semiconductor memory device of claim 12, further comprising a remaining tunnel dielectric layer between and simultaneously in contact with the vertical semiconductor pattern and the substrate, the remaining tunnel dielectric layer spaced apart from the tunnel dielectric layer. ​ 17. The three-dimensional semiconductor memory device of claim 12, wherein the plurality of blocking dielectric patterns and the first charge storage pattern protrude toward the vertical semiconductor pattern more than sidewalls of the intergate dielectric layer.

18. The three-dimensional semiconductor memory device of claim 12, further comprising a second charge storage pattern between the tunnel dielectric layer and the one of the first charge storage patterns, the second charge storage pattern in contact with a top surface and a bottom surface of the one of the first charge storage patterns, wherein the second charge storage pattern comprises a material different from a material of the one of the first charge storage patterns.

19. The three-dimensional semiconductor memory device of claim 12, further comprising a plurality of high-k dielectric layers between the electrode layers and the plurality of blocking dielectric patterns, respectively, wherein sidewalls of the intergate dielectric layer protrude more than sidewalls of the high-k dielectric layers.

20. A three-dimensional semiconductor memory device, comprising: a plurality of intergate dielectric layers and a plurality of electrode layers alternately stacked on a substrate; a vertical semiconductor pattern penetrating the intergate dielectric layers and the electrode layers, the vertical semiconductor pattern extending into the substrate; a plurality of blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, respectively, the plurality of blocking dielectric patterns spaced apart from each other; a tunnel dielectric layer between the plurality of blocking dielectric patterns and the vertical semiconductor pattern, the tunnel dielectric layer in contact with the intergate dielectric layers; and a plurality of first charge storage patterns between the plurality of blocking dielectric patterns and the tunnel dielectric layer, respectively, the first charge storage patterns spaced apart from each other, wherein a vertical length of one of the first charge storage patterns is greater than a vertical length of one of the plurality of blocking dielectric patterns, the one of the plurality of blocking dielectric patterns in contact with the one of the first charge storage patterns, wherein a first blocking dielectric pattern of the plurality of blocking dielectric patterns is separated from a sidewall of the intergate dielectric layer adjacent to the first blocking dielectric pattern in a vertical direction.

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