Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes an anode electrode disposed on a substrate; an emission layer disposed on the anode electrode; a cathode electrode disposed on the emission layer; an insulating partition wall provided between the substrate and the anode electrode, the insulating partition wall overlapping the anode electrode in a plan view; and a connection electrode connected to the cathode electrode, generally surrounding the emission layer, the cathode electrode, and the insulating partition wall, and extending on the substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0096055, filed on July 22, 2024, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, a method of manufacturing the display device, and an electronic device including the display device. Background Technology

[0004] With the development of information technology, display devices, which serve as the connection medium between users and information, are becoming increasingly important. In response, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) is increasing. Summary of the Invention

[0005] The objective of this disclosure is to provide a display device with improved reliability.

[0006] Another objective of this disclosure is to provide a method for manufacturing a display device.

[0007] The objectives of this disclosure are not limited to those described above, and other technical objectives not described will be clearly understood by those skilled in the art from the following description.

[0008] According to embodiments of the present disclosure, a display device may include: an anode electrode disposed on a substrate; an emitting layer disposed on the anode electrode; a cathode electrode disposed on the emitting layer; an insulating partition wall disposed between the substrate and the anode electrode, overlapping the anode electrode in a plan view; and a connecting electrode connected to the cathode electrode, generally surrounding the emitting layer, the cathode electrode and the insulating partition wall, and extending on the substrate.

[0009] In an embodiment, the display device may further include an insulating layer disposed between the substrate and the insulating partition wall.

[0010] In one embodiment, the insulating partition wall may protrude from the insulating layer, and the anode electrode may be spaced apart from the insulating layer by the insulating partition wall.

[0011] In an embodiment, the connecting electrode may include: an auxiliary electrode disposed on the cathode electrode and in direct contact with the cathode electrode; a partition wall pattern surrounding an insulating partition wall and connected to the auxiliary electrode; and a connecting line disposed between the insulating layer and the partition wall pattern, extending on the insulating layer and connected to the partition wall pattern.

[0012] In one embodiment, the auxiliary electrode may include a transparent conductive oxide (TCO).

[0013] In an embodiment, the display device can further include an insulating film disposed between the insulating partition wall and the anode electrode, and disposed between the partition wall pattern and the anode electrode.

[0014] In an embodiment, the display device can further include a sub-electrode disposed between the anode electrode and the insulating film.

[0015] In an embodiment, the display device can further include a circuit element disposed between the substrate and the insulating layer, and connected to at least one of the anode electrode and the sub-electrode.

[0016] In an embodiment, a contact hole for connection between at least one of the anode electrode and the sub-electrode and the circuit element can be defined in the insulating film, the insulating partition wall, and the insulating layer.

[0017] In an embodiment, the display device can further include a pixel definition film surrounding edges of the anode electrode and contacting the insulating film.

[0018] In an embodiment, the display device can further include an insulating pattern disposed between the anode electrode and the emission layer, and overlapping the contact hole in a plan view.

[0019] In an embodiment, the insulating pattern and the pixel definition film can include the same material.

[0020] According to an embodiment of the disclosure, a display device can include anode electrodes disposed on a substrate, respectively overlapping sub-pixel regions in a plan view, and spaced apart from each other; emission layers respectively disposed on the anode electrodes; cathode electrodes respectively disposed on the emission layers and spaced apart from each other; insulating partition walls disposed between the substrate and the anode electrodes, respectively overlapping the anode electrodes in a plan view, and spaced apart from each other; and connection electrodes connecting the cathode electrodes to each other.

[0021] In an embodiment, the connection electrodes can include auxiliary electrodes respectively disposed on the cathode electrodes and respectively directly contacting the cathode electrodes; partition wall patterns respectively surrounding the insulating partition walls, each of the partition wall patterns overlapping and connected to a corresponding one of the auxiliary electrodes in the plan view; and connection lines disposed between the substrate and the partition wall patterns, and connecting the partition wall patterns to each other.

[0022] In an embodiment, the connection lines can be disposed between the substrate and the insulating partition walls, and extend entirely on the substrate except for portions overlapping the insulating partition walls in the plan view.

[0023] According to an embodiment of the disclosure, a method of manufacturing a display device can include forming an insulating partition wall on a substrate; forming an anode electrode overlapping the insulating partition wall on the insulating partition wall; forming an emission layer on the anode electrode; forming a cathode electrode on the emission layer; and forming a connection electrode connected to the cathode electrode, generally surrounding the cathode electrode and the insulating partition wall, and extending on the substrate.

[0024] In an embodiment, the forming of the connection electrode can include forming a connection line including a first opening on the substrate before the forming of the insulating partition wall.

[0025] In an embodiment, the forming of the connection electrode can further include forming a preliminary insulating layer on the connection line, the preliminary insulating layer including a second opening overlapping the first opening in a plan view; forming a preliminary partition wall pattern on an entire area of the connection line and the preliminary insulating layer; and forming a partition wall pattern including a third opening overlapping the second opening in the plan view by patterning the preliminary partition wall pattern.

[0026] In an embodiment, the insulating partition wall can be formed inside the partition wall pattern.

[0027] In an embodiment, the forming of the connection electrode can further include forming an auxiliary electrode surrounding the emission layer and the cathode electrode on the cathode electrode after the forming of the cathode electrode. The auxiliary electrode can directly contact the partition wall pattern.

[0028] According to an embodiment of the disclosure, an electronic device can include a processor to provide input image data, and a display device to display an image based on the input image data. The display device can include an anode electrode disposed on a substrate, an emission layer disposed on the anode electrode, a cathode electrode disposed on the emission layer, an insulating partition wall disposed between the substrate and the anode electrode, overlapping the anode electrode in a plan view, and having an area smaller than an area of the anode electrode in the plan view, and a connection electrode connected to the cathode electrode, generally surrounding the emission layer, the cathode electrode, and the insulating partition wall, and extending on the substrate.

[0029] In an embodiment, the electronic device can be at least one of a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer (PC), a watch phone, a car display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra-mobile personal computer (UMPC), a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0030] Specific details are included in the detailed description and the accompanying drawings.

[0031] According to the above-described embodiment, since the anode electrodes are separated from the insulating layer by the insulating partition walls and protrude, it is possible to prevent a shadow effect from occurring in a case where the emission layer is completely deposited on the anode electrodes. Accordingly, it is possible to form the emission layer of a more uniform thickness in the sub-pixel region.

[0032] Further, when the cathode electrodes are connected to each other, the connection electrodes can stably connect the cathode electrodes to each other by using the auxiliary electrodes, the partition wall pattern, and the connection lines which are in contact with and connected to each other, instead of connecting the cathode electrodes as a single extended structure. Accordingly, it is possible to improve the reliability of the display device.

[0033] Effects according to embodiments are not limited to what has been exemplified above, and include more various effects in the specification. BRIEF DESCRIPTION OF DRAWINGS

[0034] The above and other features of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the attached drawings, in which:

[0035] Figure 1 is a schematic block diagram illustrating an embodiment of a display device;

[0036] Figure 2 is a schematic block diagram illustrating an embodiment of one of sub-pixels of Figure 1

[0037] Figure 3 is a plan view illustrating an embodiment of a display panel of Figure 1

[0038] Figure 4 is a schematic cross-sectional view illustrating an embodiment of a display panel of Figure 3

[0039] Figure 5 is a schematic cross-sectional view illustrating another embodiment of a display panel of Figure 3

[0040] Figure 6 is a schematic cross-sectional view illustrating an embodiment of one of pixels of Figure 3

[0041] Figure 7 is a schematic cross-sectional view illustrating an embodiment of a contact portion between an anode electrode and a circuit element in an embodiment of Figure 6

[0042] Figures 8 to 35 is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present disclosure;

[0043] Figure 36 ​​​​​​is a schematic block diagram illustrating an embodiment of a display system; and

[0044] Figures 37 to 40 is a perspective view illustrating an application example of the display system of Figure 36 DETAILED DESCRIPTION

[0045] The present disclosure can be modified in various ways and has various forms. Therefore, specific embodiments will be illustrated in the drawings and will be described in detail in the specification. It should be understood, however, that the present disclosure is not intended to be limited to the disclosed specific forms and includes all modifications, equivalents, and alternatives within the spirit and technical scope of the present disclosure.

[0046] In describing each drawing, like reference numerals are used to refer to like parts. In the drawings, the sizes of structures are shown exaggerated for clarity of the present disclosure. The terms of "first" and "second" and the like can be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another component. For example, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component without departing from the scope of the present disclosure.

[0047] The terms used in this document are for the purpose of describing particular embodiments and are not intended to be limiting. As used in this document, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Also, the term "comprises," "comprising," "includes," "including," and / or "contains," and / or variants thereof, as used in this document, specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0048] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. To this end, the term "connected" can refer to physical, electrical, and / or fluidic connection with or without intervening elements. Also, when an element is referred to as being "in contact with" or "in contact" with another element, the element can be "in electrical contact" or "in physical contact" with the other element; or "indirectly in contact" or "directly in contact" with the other element.

[0049] ​Spatially relative terms, such as "under", "below", "lower", "above", "upper", "on", "directly on", "over", and "side" (e.g., as in "side wall"), can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0050] In the description and claims, for purposes of comprehension of the language of this document, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group". For example, "at least one of A and B" can be understood to mean "A, B, or A and B". In the description and claims, for purposes of comprehension of the language of this document, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunctive or disjunctive sense and can be understood to be equivalent to "and / or"

[0051] In the description, when a portion of a layer, region, or plate, etc. is formed on another portion, the formation direction is not limited to the upper direction, but includes formation of the portion in a side surface or lower direction. Conversely, when a portion of a layer, region, or plate, etc. is formed "under" another portion, this includes not only the case where the portion is "directly" under the other portion, but also the case where there is yet another portion between the portion and the other portion.

[0052] Unless otherwise defined or implied in this document, all terms used, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in the specification.

[0053] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, singular forms include plural forms unless the context clearly indicates otherwise.

[0054] Figure 1is a schematic block diagram illustrating an embodiment of a display device.

[0055] Referring to Figure 1 , the display device DD can include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0056] The display panel DP can include sub-pixels SP. The sub-pixels SP can be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The sub-pixels SP can be connected to the data driver 130 through first to n-th data lines DL1 to DLn.

[0057] The sub-pixels SP can generate light of two or more colors. For example, each of the sub-pixels SP can generate light such as red light, green light, blue light, cyan light, magenta light, or yellow light.

[0058] Two or more of the sub-pixels SP can configure one pixel PXL. For example, as shown in Figure 1 , the pixel PXL can include three sub-pixels SP. As described above, the pixel PXL can emit light of various colors and various brightnesses according to a combination of light emitted from the sub-pixels SP included in the pixel PXL.

[0059] The gate driver 120 can be connected to the sub-pixels SP arranged in a row direction through the first to m-th gate lines GL1 to GLm. The gate driver 120 can output gate signals to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS can include a start signal indicating a start of each frame, a horizontal synchronization signal, and the like.

[0060] The gate driver 120 can be disposed at one side of the display panel DP. However, the present disclosure is not limited thereto. For example, the gate driver 120 can be divided into two or more physically and / or logically divided drivers, and the drivers can be disposed at one side of the display panel DP and another side of the display panel DP opposite to the one side. As described above, according to an embodiment, the gate driver 120 can be disposed adjacent to the display panel DP in various shapes.

[0061] The data driver 130 can be connected to the sub-pixels SP arranged in a column direction through the first to n-th data lines DL1 to DLn. The data driver 130 can receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. In an embodiment, the data control signal DCS can include a source start signal, a source shift clock signal, and a source output enable signal, and the like.

[0062] The data driver 130 can receive a voltage from the voltage generator 140. The data driver 130 can apply a data signal having a gray voltage corresponding to the image data DATA to the first to nth data lines DL1 to DLn using the received voltage. The data signal corresponding to the image data DATA can be applied to the first to nth data lines DL1 to DLn in a case where a gate signal is applied to each of the first to mth gate lines GL1 to GLm. Accordingly, the sub-pixel SP can generate light corresponding to the data signal, and the display panel DP can display an image.

[0063] In an embodiment, the gate driver 120 and the data driver 130 can include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0064] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 can be configured to generate a plurality of voltages, and provide the generated voltages to components such as the gate driver 120, the data driver 130, and the controller 150 of the display apparatus DD. The voltage generator 140 can generate a voltage by receiving an input voltage from the outside of the display apparatus DD and adjusting the received voltage.

[0065] The voltage generator 140 can generate a first power voltage and a second power voltage. The first power voltage and the second power voltage can be provided to the sub-pixel SP through the power line PL. In another embodiment, at least one of the first power voltage and the second power voltage can be provided from the outside of the display apparatus DD.

[0066] The voltage generator 140 can provide various voltages and / or signals. For example, the voltage generator 140 can provide one or more initialization voltages applied to the sub-pixel SP. For example, during a sensing operation for sensing an electrical characteristic of a transistor and / or a light emitting element of the sub-pixel SP, a reference voltage can be applied to the first to nth data lines DL1 to DLn, and the voltage generator 140 can generate and transmit the reference voltage to the data driver 130. For example, during a display operation for displaying an image on the display panel DP, a pixel control signal can be applied to the sub-pixel SP, and the voltage generator 140 can generate the pixel control signal. In an embodiment, the voltage generator 140 can provide the pixel control signal to the sub-pixel SP through the pixel control line PXCL. In an embodiment, the pixel control line PXCL can be connected between the voltage generator 140 and the display panel DP, but the present disclosure is not limited thereto. For example, the pixel control line PXCL can be connected between the gate driver 120 and the display panel DP, and the pixel control signal can be transmitted from the voltage generator 140 to the pixel control line PXCL through the gate driver 120. Figure 1 In an embodiment, the pixel control line PXCL can be connected between the gate driver 120 and the display panel DP, but the present disclosure is not limited thereto. For example, the pixel control line PXCL can be connected between the voltage generator 140 and the display panel DP, but the present disclosure is not limited thereto. For example, the pixel control line PXCL can be connected between the gate driver 120 and the display panel DP, and the pixel control signal can be transmitted from the voltage generator 140 to the pixel control line PXCL through the gate driver 120.

[0067] The controller 150 can control the overall operation of the display device DD. The controller 150 can receive input image data IMG and a corresponding control signal CTRL from an external source. In response to the control signal CTRL, the controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS.

[0068] The controller 150 can convert input image data IMG suitable for a display device DD or a display panel DP, and output image data DATA. In an embodiment, the controller 150 can output image data DATA by aligning input image data IMG with sub-pixels SP suitable for row units.

[0069] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 can be included in a driver integrated circuit (DIC), and the data driver 130, voltage generator 140, and controller 150 can be functionally separated components within a single driver integrated circuit (DIC). In another embodiment, at least one of the data driver 130, voltage generator 140, and controller 150 can be provided as a component different from the driver integrated circuit (DIC).

[0070] Figure 2 It is a diagram. Figure 1 A schematic block diagram illustrating an embodiment of a subpixel within a subpixel. Figure 2 In Figure 1 In the sub-pixels SP, the sub-pixels SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) are shown as an example.

[0071] refer to Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0072] The light-emitting element (LD) can be connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. The first power supply voltage node VDDN can be connected to... Figure 1 One of the power lines PL, and receives the first power supply voltage. The second power supply voltage node VSSN can be connected to Figure 1 The first power supply line is another one of the power supply lines PL, and receives a second power supply voltage. The first power supply voltage may have a higher voltage level than the second power supply voltage.

[0073] The light emitting element LD can be connected between the anode electrode AE and the cathode electrode CE. The anode electrode AE can be connected to the first power supply voltage node VDDN through the sub-pixel circuit SPC. For example, the anode electrode AE can be connected to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC. The cathode electrode CE can be connected to the second power supply voltage node VSSN. The light emitting element LD can be configured to emit light according to a current flowing from the anode electrode AE to the cathode electrode CE.

[0074] The sub-pixel circuit SPC can be connected to Figure 1 an i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm of the display panel DP, and Figure 1 a j-th data line DLj among the first data line DL1 to the n-th data line DLn of the display panel DP. In response to a gate signal received through the i-th gate line GLi, the sub-pixel circuit SPC can control the light emitting element LD to emit light according to a data signal received through the j-th data line DLj. In an embodiment, the sub-pixel circuit SPC can be further connected to Figure 1 a pixel control line PXCL of the display panel DP, and the sub-pixel circuit SPC can further control the light emitting element LD in response to a pixel control signal received through the pixel control line PXCL.

[0075] For such an operation, the sub-pixel circuit SPC can include circuit elements, such as transistors and one or more capacitors.

[0076] The transistors of the sub-pixel circuit SPC can include P-type transistors and / or N-type transistors. In an embodiment, the transistors of the sub-pixel circuit SPC can include metal oxide semiconductor field effect transistors (MOSFETs). In an embodiment, the transistors of the sub-pixel circuit SPC can include amorphous silicon semiconductors, single-crystal silicon, polycrystalline silicon semiconductors, or oxide semiconductors, etc.

[0077] Figure 3 is a plan view illustrating an embodiment of the display panel DP. Figure 1

[0078] Referring to Figure 3 , the display panel DP can include a display area DA and a non-display area NDA. The display panel DP can display an image through the display area DA. The non-display area NDA can be disposed adjacent to the display area DA.

[0079] ​The display panel DP can include sub-pixels SP in the display area DA. The sub-pixels SP can be arranged in a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the sub-pixels SP can be arranged in a matrix form in the first direction DR1 and the second direction DR2. For example, the sub-pixels SP can be arranged in a zigzag form along the first direction DR1 and the second direction DR2. The arrangement of the sub-pixels SP can vary according to embodiments. The first direction DR1 can be a row direction, and the second direction DR2 can be a column direction.

[0080] Two or more of the sub-pixels SP can configure one pixel PXL. In Figure 3 In an embodiment, the pixel PXL includes three sub-pixels SP1 to SP3, but the present disclosure is not limited thereto. For example, the pixel PXL can include two sub-pixels. Hereinafter, for convenience of description, an embodiment in which the pixel PXL includes first to third sub-pixels SP1 to SP3 is described.

[0081] Each of the first to third sub-pixels SP1 to SP3 can generate light of one of various colors such as red, green, blue, cyan, magenta, and yellow. Hereinafter, for a clear and brief description, an embodiment in which the first sub-pixel SP1 is configured to generate light of red, the second sub-pixel SP2 is configured to generate light of green, and the third sub-pixel SP3 is configured to generate light of blue is described.

[0082] Each of the first to third sub-pixels SP1 to SP3 can include at least one light emitting element configured to generate light. In an embodiment, the light emitting elements of the first to third sub-pixels SP1 to SP3 can generate light of the same color. For example, the light emitting elements of the first to third sub-pixels SP1 to SP3 can generate light of blue. In another embodiment, the light emitting elements of the first to third sub-pixels SP1 to SP3 can generate light of different colors. For example, the light emitting elements of the first to third sub-pixels SP1 to SP3 can generate light of red, green, and blue, respectively.

[0083] As the display panel DP, a display panel capable of self-emission such as a light emitting diode display panel (LED display panel) using a micro- or nano-scale light emitting diode as a light emitting element or an organic light emitting display panel (OLED panel) using an organic light emitting diode as a light emitting element, etc. can be used.

[0084] A component for controlling the sub-pixels SP can be disposed in the non-display area NDA. A line connected to the sub-pixels SP, for example, Figure 1The first to mth gate lines GL1 to GLm, the first to nth data lines DL1 to DLn, the power line PL, and the pixel control line PXCL of the display panel 100 can be disposed in the non-display area NDA.

[0085] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, and the controller 150 of the display panel 100 can be disposed in the non-display area NDA of the display panel DP. In an embodiment, the gate driver 120 can be disposed in the non-display area NDA, and the data driver 130, the voltage generator 140, and the controller 150 can be implemented as Figure 1 a driver integrated circuit DIC separate from the display panel DP, and the driver integrated circuit DIC can be connected to the lines disposed in the non-display area NDA. In another embodiment, the gate driver 120 can be implemented as one integrated circuit separate from the display panel DP together with the data driver 130, the voltage generator 140, and the controller 150.

[0086] The display area DA can have various shapes in a plan view. In an embodiment, the display area DA can have a closed loop shape including straight lines and / or curved lines as sides. For example, the display area DA can have a polygonal shape, a circular shape, a semicircular shape, an elliptical shape, or the like.

[0087] In an embodiment, the display panel DP can have a flat display surface. In another embodiment, the display panel DP can have a display surface that is at least partially circular. In an embodiment, the display panel DP can be bendable, foldable, or rollable, and the display panel DP and / or the substrate of the display panel DP can include a material having flexibility.

[0088] Figure 4 is a schematic cross-sectional view illustrating an embodiment of the display panel. Figure 3

[0089] Referring to Figure 4 , the display panel DP can include a substrate SUB, and a pixel circuit layer PCL, a display element layer DPL, and a light function layer LFL stacked sequentially on the substrate SUB in a third direction DR3 crossing the first direction DR1 and the second direction DR2.

[0090] The substrate SUB can be formed of an insulating material such as glass or resin. For example, the substrate SUB can include a glass substrate. In another embodiment, the substrate SUB can include a polyimide (PI) substrate. In another embodiment, the substrate SUB can include a silicon wafer substrate formed using a semiconductor process.

[0091] ​In an embodiment, the substrate SUB can be formed of a flexible material that can be bent or folded, and can have a single-layer structure or a multi-layer structure. For example, the flexible material can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the present disclosure is not limited thereto.

[0092] The pixel circuit layer PCL can be provided on the substrate SUB. The pixel circuit layer PCL can include insulating layers and semiconductor patterns and conductive patterns provided between the insulating layers. The conductive patterns of the pixel circuit layer PCL can be used as circuit elements and lines, etc.

[0093] The circuit elements of the pixel circuit layer PCL can include Figure 3 a sub-pixel circuit SPC (refer to Figure 2 ) of each of the sub-pixels SP. In other words, the circuit elements of the pixel circuit layer PCL can be provided as transistors and one or more capacitors of the sub-pixel circuit SPC.

[0094] The lines of the pixel circuit layer PCL can include lines connected to the sub-pixels SP. The lines of the pixel circuit layer PCL can include various signal lines and / or voltage lines for driving the display element layer DPL.

[0095] The display element layer DPL can be provided on the pixel circuit layer PCL. The display element layer DPL can include light emitting elements of the sub-pixels SP.

[0096] The light function layer LFL can be provided on the display element layer DPL. The light function layer LFL can include a light conversion pattern having color conversion particles and / or scattering particles. For example, the color conversion particles can include quantum dots. The quantum dots can change the wavelength (or color) of light emitted from the display element layer DPL. The light function layer LFL can further include a light scattering pattern having scattering particles. In an embodiment, the light conversion pattern and the light scattering pattern can be omitted.

[0097] The light function layer LFL can include a color filter layer including a color filter. The color filter can selectively transmit light of a specific wavelength (or a specific color). In an embodiment, the color filter layer can be omitted.

[0098] Although not illustrated, a window for protecting an exposed surface (or upper surface) of the display panel DP can be provided on the light functional layer LFL. The window can protect the display panel DP from external impact. The window can be coupled to the light functional layer LFL by an optically transparent adhesive (or attachment) member. The window can have a multi-layer structure including a glass substrate, a plastic film, and / or a plastic substrate. The multi-layer structure can be formed by a continuous process or an adhesive process using an adhesive layer. All or a portion of the window can be flexible.

[0099] Figure 5 is a schematic cross-sectional view illustrating another embodiment of a display panel of Figure 3 .

[0100] Referring to Figure 5 , the display panel DP’ can include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an input sensing layer SSL, and a light functional layer LFL. The substrate SUB, the pixel circuit layer PCL, the display element layer DPL, and the light functional layer LFL can be configured similarly to the substrate SUB, the pixel circuit layer PCL, the display element layer DPL, and the light functional layer LFL described with reference to Figure 4 , respectively. Hereinafter, a repeated description is omitted.

[0101] The input sensing layer SSL can sense a user input on an upper surface (or display surface) of the display panel DP’. The input sensing layer SSL can include a component suitable for sensing an external object such as a user’s hand or a pen. For example, the input sensing layer SSL can include a touch electrode.

[0102] Figure 6 is a schematic cross-sectional view illustrating an embodiment of a pixel of Figure 3 . Figure 6 Only the substrate SUB, the pixel circuit layer PCL, and the display element layer DPL of Figure 4 or Figure 5 are schematically illustrated.

[0103] Referring to Figure 6 , the display panel can include a first sub-pixel region SPA1 to a third sub-pixel region SPA3 in which first to third sub-pixels SP1 to SP3 of Figure 3 are respectively disposed.

[0104] The pixel circuit layer PCL can be disposed on the substrate SUB. The pixel circuit layer PCL can include a circuit element PXC, a contact electrode CTE, and an insulating layer ISL. The pixel circuit layer PCL can further include insulating layers and a semiconductor pattern and a conductive pattern disposed between the insulating layers.

[0105] The circuit elements PXC can be provided on the substrate SUB. Each of the circuit elements PXC can be provided as a transistor and a capacitor for each of the subpixels. The contact electrodes CTE can be provided on the circuit elements PXC. The contact electrodes CTE can be connected to the circuit elements PXC, respectively, and can electrically connect the light emitting elements LD and the circuit elements PXC to each other (refer to Figure 7 )..

[0106] The insulating layer ISL can cover the contact electrodes CTE. The insulating layer ISL can overlap the first to third subpixel areas SPA1 to SPA3 in a plan view, and can extend over the first to third subpixel areas SPA1 to SPA3. The insulating layer ISL can include an organic material.

[0107] The display element layer DPL can be provided on the insulating layer ISL. The display element layer DPL can include the insulating separation walls ISW, the insulating film ISF, the first to third anode electrodes AE1 to AE3, the first to third emission layers EML1 to EML3, the first to third cathode electrodes CE1 to CE3, the connection electrode CNE, the sub-electrode SBE, the pixel definition film PDL, and the encapsulation layer TFE. The connection electrode CNE can include the connection line CNL, the separation wall pattern PWP, and the auxiliary electrode AXE.

[0108] The insulating separation walls ISW can be provided on the insulating layer ISL. The insulating separation walls ISW can overlap the first to third subpixel areas SPA1 to SPA3, respectively, in a plan view, and the insulating separation walls ISW can be spaced apart from each other. Each of the insulating separation walls ISW can protrude from the insulating layer ISL. For example, each of the insulating separation walls ISW can be spaced apart from each other and protrude from the insulating layer ISL, rather than having a shape extending over the insulating layer ISL. Each of the insulating separation walls ISW can include an organic material.

[0109] The insulating film ISF can be provided on the insulating separation walls ISW, respectively. The insulating film ISF can overlap the insulating separation walls ISW, respectively, in a plan view, and the insulating film ISF can be spaced apart from each other. An area of each of the insulating film ISF can be greater than an area of each of the insulating separation walls ISW in a plan view, and each of the insulating film ISF can include an inorganic material.

[0110] The first to third anode electrodes AE1 to AE3 can be respectively disposed on the insulating film ISF. The first to third anode electrodes AE1 to AE3 can be respectively disposed in the first to third sub-pixel areas SPA1 to SPA3 and can respectively overlap the insulating separation wall ISW in a plan view, and the first to third anode electrodes AE1 to AE3 can be spaced apart from each other. Each of the first to third anode electrodes AE1 to AE3 can be provided as an anode electrode AE of a sub-pixel circuit SPC (refer to FIG. 1) connected to each of the first to third sub-pixels SP1 to SP3. Figure 3 Figure 2

[0111] Each of the first to third anode electrodes AE1 to AE3 can be spaced apart from the insulating layer ISL by the insulating separation wall ISW. An area of each of the first to third anode electrodes AE1 to AE3 can be greater than an area of each of the insulating separation walls ISW in a plan view.

[0112] Sub-electrodes SBE can be respectively disposed between the first to third anode electrodes AE1 to AE3 and the insulating film ISF. The sub-electrodes SBE can respectively completely overlap and contact (e.g., directly contact) the first to third anode electrodes AE1 to AE3. Each of the sub-electrodes SBE can include titanium.

[0113] Pixel definition layers PDL can be respectively disposed on the first to third anode electrodes AE1 to AE3. The pixel definition layers PDL can respectively surround edges of the first to third anode electrodes AE1 to AE3, and the pixel definition layers PDL can be spaced apart from each other. Accordingly, the pixel definition layers PDL can insulate the edges of the first to third anode electrodes AE1 to AE3 from the first to third cathode electrodes CE1 to CE3. The pixel definition layers PDL can respectively contact the insulating film ISF under the first to third anode electrodes AE1 to AE3, and thus, the edges of the first to third anode electrodes AE1 to AE3 can be covered by the pixel definition layers PDL and the insulating film ISF.

[0114] First to third emission layers EML1 to EML3 can be respectively disposed on the first to third anode electrodes AE1 to AE3 and the pixel definition layers PDL. The first to third emission layers EML1 to EML3 can respectively overlap the first to third anode electrodes AE1 to AE3 in a plan view, and the first to third emission layers EML1 to EML3 can be spaced apart from each other. For example, the first to third emission layers EML1 to EML3 can not overlap regions between the first to third sub-pixel areas SPA1 to SPA3, and can be separated from each other.​​

[0115] For example, the first to third emission layers EML1 to EML3 can generate red light, green light, and blue light, respectively. However, the disclosure is not limited thereto, and in another embodiment, all of the first to third light emitting elements LD1 to LD3 can generate blue light.

[0116] The first to third cathode electrodes CE1 to CE3 can be disposed on the first to third emission layers EML1 to EML3, respectively. The first to third cathode electrodes CE1 to CE3 can overlap the first to third emission layers EML1 to EML3, respectively, in a plan view, and the first to third cathode electrodes CE1 to CE3 can be spaced apart from each other. For example, the first to third cathode electrodes CE1 to CE3 can not overlap the areas between the first to third sub-pixel areas SPA1 to SPA3, and can be separated from each other.

[0117] Each of the first to third cathode electrodes CE1 to CE3 can be provided as a cathode electrode CE (see Figure 3 ) of a sub-pixel circuit SPC (see Figure 2 ) connected to each of the first to third sub-pixels SP1 to SP3 of Figure 2 ).

[0118] The first anode electrode AE1, the first emission layer EML1, and the first cathode electrode CE1 can configure the first light emitting element LD1, the second anode electrode AE2, the second emission layer EML2, and the second cathode electrode CE2 can configure the second light emitting element LD2, and the third anode electrode AE3, the third emission layer EML3, and the third cathode electrode CE3 can configure the third light emitting element LD3. Each of the first to third light emitting elements LD1 to LD3 can be provided as a light emitting element LD (see Figure 3 ) of a sub-pixel circuit SPC (see Figure 2 ) connected to each of the first to third sub-pixels SP1 to SP3 of Figure 2 ).

[0119] Each of the first to third light emitting elements LD1 to LD3 can have an area greater than a planar area of an insulating separation wall ISW overlapping the same in a plan view. For example, each of the first to third light emitting elements LD1 to LD3 can be spaced apart from an insulating layer ISL by the insulating separation wall ISW, and can configure a protruding tip structure because the area of each of the first to third light emitting elements LD1 to LD3 is greater than the area of the insulating separation wall ISW in a plan view.

[0120] In an embodiment, the connection electrode CNE can be disposed on the insulating layer ISL and entirely surround the insulating partition wall ISW, the insulating film ISF, the pixel definition layer PDL, and the first to third light emitting elements LD1 to LD3 in a cross-sectional view. The connection electrode CNE can be connected to the first to third cathode electrodes CE1 to CE3 and can entirely extend on the substrate SUB. Accordingly, the connection electrode CNE can connect the first to third cathode electrodes CE1 to CE3 to each other. The connection electrode CNE can be connected to the cathode electrode CE (refer to Figure 2 ), included in each of the first to third sub-pixels SP1 to SP3 in the display panel DP and can generally extend on the insulating layer ISL. Figure 2

[0121] The connection electrode CNE can include an auxiliary electrode AXE, a partition wall pattern PWP, and a connection line CNL.

[0122] The auxiliary electrode AXE can be disposed on the first to third cathode electrodes CE1 to CE3, respectively. The auxiliary electrode AXE can contact (e.g., directly contact) and can be connected to the first to third cathode electrodes CE1 to CE3, respectively. Each of the auxiliary electrodes AXE can surround the light emitting element LD and extend to a lower portion of the insulating film ISF. Each of the auxiliary electrodes AXE can include a transparent conductive oxide (TCO). For example, each of the auxiliary electrodes AXE can include indium zinc oxide (IZO).

[0123] The partition wall pattern PWP can surround the insulating partition wall ISW, respectively, and can be connected to the auxiliary electrode AXE, respectively. For example, the partition wall pattern PWP can surround a side surface of the insulating partition wall ISW, respectively, and can contact (e.g., directly contact) the auxiliary electrode AXE, respectively. Each of the partition wall patterns PWP can extend from the side surface of the insulating partition wall ISW to the lower portion of the insulating film ISF and can contact (e.g., directly contact) the auxiliary electrode AXE at the lower portion of the insulating film ISF. For example, each of the partition wall patterns PWP can contact the auxiliary electrode AXE at a lower portion of a tip structure formed by each of the first to third light emitting elements LD1 to LD3.

[0124] The insulating film ISF can be disposed between the partition wall pattern PWP and the first to third anode electrodes AE1 to AE3 overlapping the partition wall pattern PWP. Accordingly, the first to third anode electrodes AE1 to AE3 can be electrically insulated from the first to third cathode electrodes CE1 to CE3, respectively, by the insulating film ISF.

[0125] ​Each of the partition wall patterns PWP can also surround a portion of a lower surface of the insulating partition wall ISW. For example, each of the partition wall patterns PWP can extend from a side surface of the insulating partition wall ISW to a lower surface of the insulating partition wall ISW, and can be disposed between the insulating layer ISL and the insulating partition wall ISO. Accordingly, each of the partition wall patterns PWP can contact (e.g., directly contact) and can be connected to the connection line CNL extending on the insulating layer ISL.

[0126] Each of the partition wall patterns PWP can include a metal. For example, each of the partition wall patterns PWP can have a single layer or a multi-layer structure, and each layer can include at least one of titanium, molybdenum, and aluminum. However, the present disclosure is not limited thereto.

[0127] The connection line CNL can be disposed between the insulating layer ISL and the insulating partition wall ISW, and can extend on the insulating layer ISL. For example, the connection line CNL can extend entirely on the insulating layer ISL, rather than on an area where the insulating partition wall ISW and the insulating layer ISL contact each other. The connection line CNL can be disposed between the insulating layer ISL and the partition wall pattern PWP. For example, the connection line CNL can be connected to the partition wall pattern PWP extending to the lower surface of the insulating partition wall ISW. Accordingly, the connection line CNL can connect the partition wall patterns PWP spaced apart from each other.

[0128] In an embodiment, the auxiliary electrode AXE included in the connection electrode CNE, the partition wall pattern PWP, and the connection line CNL can contact (e.g., directly contact) and can be connected to each other, and thus, in the pixel PXL including the first to third sub-pixels SP1 to SP3, the cathode electrodes CE spaced apart from each other can be stably connected to each other.

[0129] The encapsulation layer TFE can be disposed on the connection electrode CNE. The encapsulation layer TFE can entirely cover the connection electrode CNE. The encapsulation layer TFE can be configured to prevent oxygen and / or moisture, etc. from permeating into the first to third light emitting elements LD1 to LD3. The encapsulation layer TFE can have a structure in which at least one organic film and at least one inorganic film are stacked.

[0130] In an embodiment, since the light emitting element LD is separated from the insulating layer ISL and protrudes by the insulating separation wall ISW, and the auxiliary electrode AXE included in the connection electrode CNE, the separation wall pattern PWP, and the connection line CNL are in contact (e.g., direct contact) with and connected to each other, the cathode electrode CE can be completely connected in the pixel PXL including the first to third sub-pixels SP1 to SP3. Accordingly, the shadow effect can be prevented, and a more uniform thickness of the emission layer EML can be ensured. By connecting the cathode electrode CE to each other using the auxiliary electrode AXE, the separation wall pattern PWP, and the connection line CNL in contact (e.g., direct contact) with each other, instead of connecting the cathode electrode CE with a single extended structure, disconnection and resistance increase due to step coverage can be prevented. Accordingly, the connection electrode CNE can stably connect the cathode electrode CE to each other, and the reliability of the display device can be improved.

[0131] Figure 7 is a schematic cross-sectional view of an embodiment of a contact portion between an anode electrode and a circuit element in an embodiment of Figure 6 . Accordingly, a brief description or repetition of what can be repeated with the above is not repeated.

[0132] Referring to Figure 7 , the circuit element PXC can be connected to the display element layer DPL through the contact electrode CTE. Each of the contact electrode CTE can be connected to at least one of the anode electrode AE and the sub-electrode SBE. To this end, a contact hole CNT for connection between the anode electrode AE and the sub-electrode SBE and the contact electrode CTE can be defined in the insulating layer ISL, the insulating separation wall ISW, and the insulating film ISF, respectively. For example, the contact hole CNT can be completely defined in the insulating layer ISL, the insulating separation wall ISW, and the insulating film ISF, which overlap each other. At least one of the anode electrode AE and the sub-electrode SBE can contact (e.g., direct contact) the contact electrode CTE through each of the contact hole CNT, and can be connected to the pixel circuit layer PCL.

[0133] The sub-electrode SBE can completely overlap the anode electrode AE in a plan view, can be disposed between the anode electrode AE and the contact electrode CTE, and can be used to stably connect the anode electrode AE and the contact electrode CTE.

[0134] The insulating patterns ISP can be respectively disposed between the first to third anode electrodes AE1 to AE3 and the first to third emission layers EML1 to EML3. The insulating patterns ISP can respectively overlap the contact holes CNT in a plan view. A planar area of each of the insulating patterns ISP can be smaller than a planar area of each of the first to third anode electrodes AE1 to AE3 in a plan view. Accordingly, each of the insulating patterns ISP can be disposed only in a portion overlapping the contact holes CNT, between the anode electrodes AE and the emission layers EML. For example, each of the insulating patterns ISP can insulate the anode electrodes AE and the cathode electrodes CE from each other in the portion overlapping the contact holes CNT.

[0135] Each of the insulating patterns ISP and the pixel definition layer PDL can include the same material and can be disposed in the same layer. For example, each of the insulating patterns ISP and the pixel definition layer PDL can be formed in the same process.

[0136] Figures 8 to 35 is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the disclosure. Figures 8 to 35 A method of manufacturing a display device DD according to the above-described embodiments with reference to Figures 1 to 7 is schematically illustrated. Accordingly, a brief description or repetition of what can be repeated with the above-described content is omitted.

[0137] With reference to Figure 8 , a pixel circuit layer PCL can be formed on the substrate SUB. For example, a circuit element PXC can be formed on the substrate SUB, a contact electrode CTE overlapping the first to third sub-pixel areas SPA1 to SPA3 in a plan view, respectively, can be formed on the circuit element PXC. An insulating layer ISL can be formed on the circuit element PXC and cover the contact electrode CTE. The insulating layer ISL can be formed of an organic material.

[0138] With reference to Figure 9 , a connection line CNL can be entirely formed on the insulating layer ISL. A first opening OP1 overlapping the first to third sub-pixel areas SPA1 to SPA3, respectively, can be formed in the connection line CNL. The first opening OP1 can overlap the contact electrode CTE in a plan view, respectively.

[0139] With reference to Figure 10The preliminary insulating layer PIS can be completely formed on the connection line CNL. Second openings OP2, which respectively overlap the first openings OP1 in a plan view, can be formed in the preliminary insulating layer PIS. A planar area of each of the second openings OP2 can be greater than a planar area of each of the first openings OP1 in the plan view. Accordingly, the connection line CNL can be partially exposed to the outside through the second openings OP2 of the preliminary insulating layer PIS.

[0140] Referring to Figure 11 The preliminary partition wall pattern PPW can be completely formed on the insulating layer ISL, the connection line CNL, and the preliminary insulating layer PIS. The preliminary partition wall pattern PPW can be formed in a single layer or a multi-layer structure, and each layer can be formed of at least one of titanium, molybdenum, and aluminum. However, the disclosure is not limited thereto.

[0141] Referring to Figure 12 The preliminary partition wall pattern PPW can be patterned to form the partition wall pattern PWP and third openings OP3. The partition wall pattern PWP can overlap the first to third sub-pixel areas SPA1 to SPA3, respectively, in a plan view, and the partition wall pattern PWP can be spaced apart from each other. The third openings OP3 can overlap the second openings OP2, respectively, in the plan view.

[0142] Each of the partition wall patterns PWP can be formed in a structure extending from a side surface of each of the second openings OP2 of the preliminary insulating layer PIS to an upper surface of the preliminary insulating layer PIS, and can be formed in a structure extending to an upper surface of the connection line CNL exposed by each of the second openings OP2. Accordingly, each of the partition wall patterns PWP can contact (e.g., directly contact) the connection line CNL, and can be connected to the connection line CNL.

[0143] Referring to Figure 13 The insulating partition walls ISW can be formed on the insulating layer ISL and the partition wall pattern PWP, respectively. Each of the insulating partition walls ISW can be formed at an inner side of the partition wall pattern PWP. For example, each of the insulating partition walls ISW can fill the inner side of the partition wall pattern PWP. The insulating partition walls ISW can be formed of an organic material.

[0144] Referring to Figure 14 The insulating films ISF can be formed on the partition wall pattern PWP and the insulating partition wall ISW, respectively. The insulating films ISF can overlap the first to third sub-pixel areas SPA1 to SPA3, respectively, in a plan view, and the insulating films ISF can be spaced apart from each other. Each of the insulating films ISF can completely overlap the insulating partition wall ISW, and can have an area greater than an area of the overlapping insulating partition wall ISW in the plan view.

[0145] Each of the insulating film ISFs can cover the upper surface of the partition wall pattern PWP extending to the upper surface of the preliminary insulating layer PIS. Each of the insulating film ISFs can be formed of an inorganic material.

[0146] After forming the insulating film ISF, contact holes CNTs (see reference) can be formed in the insulating film ISF, the insulating separator wall ISW, and the insulating layer ISL, passing through the insulating film ISF, the insulating separator wall ISW, and the insulating layer ISL. Figure 7 Each of the contact holes CNTs can be formed as a single hole through all the insulating film ISF, insulating partition wall ISW, and insulating layer ISL via the third opening OP3 of the partition wall pattern PWP and the first opening OP1 of the connecting line CNL.

[0147] refer to Figure 15 Sub-electrodes SBE can be formed on the insulating film ISF. In the planar view, the sub-electrodes SBE can overlap with the first sub-pixel region SPA1 to the third sub-pixel region SPA3 respectively, and the sub-electrodes SBE can be spaced apart from each other.

[0148] Each of the sub-electrodes SBEs can be formed spaced apart from the partition wall pattern PWP, with an insulating film ISF placed between the sub-electrode SBE and the partition wall pattern PWP, and the sub-electrode SBEs can be insulated from the partition wall pattern PWP by the insulating film ISF. Accordingly, the planar area of ​​each of the sub-electrodes SBEs can be smaller than the planar area of ​​each of the insulating film ISFs in a planar view. Each of the sub-electrodes SBEs can be formed of titanium.

[0149] refer to Figure 16 The first anode electrode AE1 to the third anode electrode AE3 can be formed on the sub-electrode SBE, respectively. In the planar view, the first anode electrode AE1 to the third anode electrode AE3 can overlap with the first sub-pixel region SPA1 to the third sub-pixel region SPA3, and the first anode electrode AE1 to the third anode electrode AE3 can be spaced apart from each other. In the planar view, the first anode electrode AE1 to the third anode electrode AE3 can completely overlap with the sub-electrode SBE and can contact the sub-electrode SBE.

[0150] The first to third anode electrodes AE1 to AE3 can be formed to be spaced apart from the partition wall pattern PWP with the insulating film ISF interposed therebetween, and the first to third anode electrodes AE1 to AE3 can be insulated from the partition wall pattern PWP by the insulating film ISF. For example, a planar area of each of the first to third anode electrodes AE1 to AE3 can be formed to be smaller than a planar area of each of the insulating films ISF in a plan view. Each of the first to third anode electrodes AE1 to AE3 can have an area larger than an area of the overlaid insulating partition wall ISW in a plan view, and each of the first to third anode electrodes AE1 to AE3 can be formed in a structure in which indium tin oxide and silver are alternately stacked with each other.

[0151] Referring to Figure 17 The pixel definition film PDL can be formed on the first to third anode electrodes AE1 to AE3, respectively. The pixel definition film PDL can be formed to surround edges of the first to third anode electrodes AE1 to AE3 and edges of the sub-electrodes SBE, respectively. For example, the first to third anode electrodes AE1 to AE3 and the sub-electrodes SBE can be insulated from the partition wall pattern PWP and the cathode electrode CE described below by the insulating film ISF and the pixel definition film PDL.

[0152] When the pixel definition film PDL is formed, an insulating pattern ISP overlapping the contact hole CNT can be formed on the first to third anode electrodes AE1 to AE3, respectively (refer to FIG. 6B). Figure 7 For example, the pixel definition film PDL and the insulating pattern ISP can be formed of the same material, and can be formed in the same process. The insulating pattern ISP can be formed to be spaced apart from the pixel definition film PDL.

[0153] Referring to Figure 18 The first photoresist pattern PR1 can be formed on the pixel definition layer PDL and the first to third anode electrodes AE1 to AE3, respectively. Each of the first photoresist patterns PR1 can cover configurations disposed in the first to third sub-pixel areas SPA1 to SPA3, except for the preliminary insulating layer PIS.

[0154] Referring to Figure 19 The preliminary insulating layer PIS can be completely removed using the first photoresist pattern PR1. For example, components other than the preliminary insulating layer PIS can be protected using the first photoresist pattern PR1, and the preliminary insulating layer PIS can be completely etched.

[0155] Referring to Figure 20The first photoresist pattern PR1 can be removed. Since the preliminary insulating layer PIS is completely etched, only the partition wall pattern PWP can be provided on the connection line CNL.

[0156] Since each of the insulating film ISF, the first to third anode electrodes AE1 to AE3, and the sub-electrode SBE has a larger planar area than each of the insulating partition walls ISW in a plan view, each of the insulating film ISF, the first to third anode electrodes AE1 to AE3, and the sub-electrode SBE can have a sharp end structure in which a side surface thereof protrudes much more than the insulating partition wall ISW. Each of the insulating partition walls ISW can be formed in a shape in which a planar area decreases in a direction toward the insulating layer ISL.

[0157] Referring to Figure 21 The first emission layer EML1 can be formed on the first to third anode electrodes AE1 to AE3, the pixel definition layer PDL, and the connection line CNL. The first emission layer EML1 can be completely formed in the first to third sub-pixel areas SPA1 to SPA3 without a separate mask. The first emission layer EML1 can not have a completely extended shape and can have a structure that is broken between the first to third sub-pixel areas SPA1 to SPA3 by a sharp end structure.

[0158] Referring to Figure 22 The first cathode electrode CE1 can be formed on the first emission layer EML1. The first cathode electrode CE1 can also be completely formed in the first to third sub-pixel areas SPA1 to SPA3 without a separate mask. The first cathode electrode CE1 can also not have a completely extended shape and can have a structure that is broken between the first to third sub-pixel areas SPA1 to SPA3 by a sharp end structure.

[0159] Referring to Figure 23 The first auxiliary electrode AXE1 can be formed on the first cathode electrode CE1. The first auxiliary electrode AXE1 can completely contact the first cathode electrode CE1. The first auxiliary electrode AXE1 can be completely formed in the first to third sub-pixel areas SPA1 to SPA3 without a separate mask. The first auxiliary electrode AXE1 can not have a completely extended shape and can have a structure that is broken between the first to third sub-pixel areas SPA1 to SPA3 by a sharp end structure.

[0160] However, the first auxiliary electrode AXE1 can surround the first emission layer EML1, the first cathode electrode CE1, and a portion of the separation wall pattern PWP on the insulating separation wall ISW. For example, the first auxiliary electrode AXE1 can be extended from the upper surface of the first cathode electrode CE1 to the portion where the separation wall pattern PWP is disposed and can be deposited, and thus, the separation wall pattern PWP and the first auxiliary electrode AXE1 can be in contact (direct contact) with each other.

[0161] Referring to Figure 24 The first encapsulation layer TFE1 can be formed on the first auxiliary electrode AXE1. The first encapsulation layer TFE1 can be formed entirely in the first to third sub-pixel areas SPA1 to SPA3. The first encapsulation layer TFE1 can have a shape extending entirely and can entirely cover the lower components.

[0162] Referring to Figure 25 A second photoresist pattern PR2 can be formed in the first sub-pixel area SPA1. The second photoresist pattern PR2 can overlap the first sub-pixel area SPA1 in a plan view, and can entirely cover the configurations (e.g., the first emission layer EML1, the first cathode electrode CE1, the first auxiliary electrode AXE1, and the first encapsulation layer TFE1) disposed in the first sub-pixel area SPA1.

[0163] Referring to Figure 26 The first emission layer EML1, the first cathode electrode CE1, the first auxiliary electrode AXE1, and the first encapsulation layer TFE1 in the second and third sub-pixel areas SPA2 and SPA3 can be removed using the second photoresist pattern PR2. For example, by using the second photoresist pattern PR2, the first emission layer EML1, the first cathode electrode CE1, the first auxiliary electrode AXE1, and the first encapsulation layer TFE1 in the first sub-pixel area SPA1 can be protected, and the remaining first emission layer EML1, the first cathode electrode CE1, the first auxiliary electrode AXE1, and the first encapsulation layer TFE1 can be etched.

[0164] Referring to Figure 27 The second photoresist pattern PR2 can be removed. Accordingly, only the first emission layer EML1, the first cathode electrode CE1, the first auxiliary electrode AXE1, and the first encapsulation layer TFE1 in the first sub-pixel area SPA1 can be left.

[0165] In the first sub-pixel area SPA1, the first anode electrode AE1, the first emission layer EML1, and the first cathode electrode CE1 can form a first light emitting element LD1. The first light emitting element LD1 can protrude laterally with respect to the insulating separation wall ISW to form a tip structure.

[0166] Referring to Figure 28The second emitter layer EML2 can be formed on the first encapsulation layer TFE1, the second anode electrode AE2 and the third anode electrode AE3, the pixel defining film PDL, and the connecting line CNL. The second emitter layer EML2 can be disposed on the first encapsulation layer TFE1 in the first sub-pixel region SPA1, and can be disposed on the second anode electrode AE2 and the third anode electrode AE3 in the second sub-pixel region SPA2 and the third sub-pixel region SPA3, respectively.

[0167] The second emitter layer EML2 can be formed entirely within the first sub-pixel region SPA1 to the third sub-pixel region SPA3 without requiring a separate mask. Similar to the first emitter layer EML1, the second emitter layer EML2 may not have a fully extended shape and can have a discontinuous structure between the first sub-pixel region SPA1 and the third sub-pixel region SPA3 through a pointed structure.

[0168] Similar to the first cathode electrode CE1, the first auxiliary electrode AXE1, and the first encapsulation layer TFE1, the second cathode electrode CE2 can be formed on the second emitter layer EML2, the second auxiliary electrode AXE2 can be formed on the second cathode electrode CE2, and the second encapsulation layer TFE2 can be formed on the second auxiliary electrode AXE2.

[0169] The second auxiliary electrode AXE2 may surround a portion of the second emitter layer EML2, the second cathode electrode CE2, and the partition wall pattern PWP on the insulating separator ISW in the second sub-pixel region SPA2 and the third sub-pixel region SPA3. For example, the second auxiliary electrode AXE2 may extend from the upper surface of the second cathode electrode CE2 in the second sub-pixel region SPA2 to the portion where the partition wall pattern PWP is disposed and may be deposited, and thus the partition wall pattern PWP and the second auxiliary electrode AXE2 may be in contact with each other (e.g., in direct contact).

[0170] refer to Figure 29 A third photoresist pattern PR3 can be formed in the second sub-pixel region SPA2. The third photoresist pattern PR3 can overlap with the second sub-pixel region SPA2 and can completely cover the structures disposed in the second sub-pixel region SPA2 (e.g., the second emitter layer EML2, the second cathode electrode CE2, the second auxiliary electrode AXE2, and the second encapsulation layer TFE2).

[0171] refer to Figure 30The second emission layer EML2, the second cathode electrode CE2, the second auxiliary electrode AXE2, and the second encapsulation layer TFE2 in the first sub-pixel area SPA1 and the third sub-pixel area SPA3 can be removed using the third photoresist pattern PR3. For example, by using the third photoresist pattern PR3, the second emission layer EML2, the second cathode electrode CE2, the second auxiliary electrode AXE2, and the second encapsulation layer TFE2 in the second sub-pixel area SPA2 can be protected, and the remaining second emission layer EML2, the second cathode electrode CE2, the second auxiliary electrode AXE2, and the second encapsulation layer TFE2 can be etched. The second encapsulation layer TFE2 can be etched so as to be connected to the first encapsulation layer TFE1 (for example, so as not to be spaced apart from the first encapsulation layer TFE1).

[0172] Referring to Figure 31 The third photoresist pattern PR3 can be removed. Accordingly, only the second emission layer EML2, the second cathode electrode CE2, the second auxiliary electrode AXE2, and the second encapsulation layer TFE2 in the second sub-pixel area SPA2 can be left.

[0173] In the second sub-pixel area SPA2, the second anode electrode AE2, the second emission layer EML2, and the second cathode electrode CE2 can form a second light emitting element LD2. The second light emitting element LD2 can protrude laterally with respect to the insulating partition wall ISW to form a tip structure.

[0174] Referring to Figure 32 The third emission layer EML3 can be formed on the first encapsulation layer TFE1 and the second encapsulation layer TFE2, the third anode electrode AE3, the pixel definition layer PDL, and the connection line CNL. The third emission layer EML3 can be disposed on the first encapsulation layer TFE1 and the second encapsulation layer TFE2 in the first sub-pixel area SPA1 and the second sub-pixel area SPA2, respectively, and can be disposed on the third anode electrode AE3 in the third sub-pixel area SPA3.

[0175] The third emission layer EML3 can be formed completely in the first sub-pixel area SPA1 to the third sub-pixel area SPA3 without a separate mask. Like the second emission layer EML2, the third emission layer EML3 can not have a completely extended shape, and can have a structure that is broken between the first sub-pixel area SPA1 to the third sub-pixel area SPA3 by a tip structure.

[0176] Like the second cathode electrode CE2, the second auxiliary electrode AXE2, and the second encapsulation layer TFE2, the third cathode electrode CE3 can be formed on the third emission layer EML3, the third auxiliary electrode AXE3 can be formed on the third cathode electrode CE3, and the third encapsulation layer TFE3 can be formed on the third auxiliary electrode AXE3.

[0177] The third auxiliary electrode AXE3 can surround the third emission layer EML3, the third cathode electrode CE3, and a portion of the separation wall pattern PWP on the insulating separation wall ISW in the third sub-pixel area SPA3. For example, the third auxiliary electrode AXE3 can be extended from an upper surface of the third cathode electrode CE3 to the portion where the separation wall pattern PWP is disposed and can be deposited, and thus, the separation wall pattern PWP and the third auxiliary electrode AXE3 can contact (e.g., directly contact).

[0178] Referring to Figure 33 A fourth photoresist pattern PR4 can be formed in the third sub-pixel area SPA3. The fourth photoresist pattern PR4 can overlap the third sub-pixel area SPA3 and can completely cover the configurations (e.g., the third emission layer EML3, the third cathode electrode CE3, the third auxiliary electrode AXE3, and the third encapsulation layer TFE3) disposed in the third sub-pixel area SPA3.

[0179] Referring to Figure 34 The third emission layer EML3, the third cathode electrode CE3, the third auxiliary electrode AXE3, and the third encapsulation layer TFE3 in the first sub-pixel area SPA1 and the second sub-pixel area SPA2 can be removed using the fourth photoresist pattern PR4. For example, by using the fourth photoresist pattern PR4, the third emission layer EML3, the third cathode electrode CE3, the third auxiliary electrode AXE3, and the third encapsulation layer TFE3 in the third sub-pixel area SPA3 can be protected, and the remaining third emission layer EML3, the third cathode electrode CE3, the third auxiliary electrode AXE3, and the third encapsulation layer TFE3 can be etched. The third encapsulation layer TFE3 can be etched so as to be connected to the second encapsulation layer TFE2 (e.g., so as not to be spaced apart from the second encapsulation layer TFE2).

[0180] Referring to Figure 35 The fourth photoresist pattern PR4 can be removed. Accordingly, only the third emission layer EML3, the third cathode electrode CE3, the third auxiliary electrode AXE3, and the third encapsulation layer TFE3 in the third sub-pixel area SPA3 can be left.

[0181] In the third sub-pixel area SPA3, the third anode electrode AE3, the third emission layer EML3, and the third cathode electrode CE3 can form a third light emitting element LD3. The third light emitting element LD3 can laterally protrude with respect to the insulating separation wall ISW to form a tip structure.

[0182] Accordingly, a display element layer DPL including the insulating separation wall ISW, the insulating film ISF, the first to third anode electrodes AE1 to AE3, the first to third emission layers EML1 to EML3, the first to third cathode electrodes CE1 to CE3, the connection electrode CNE, the sub-electrode SBE, the pixel definition film PDL, and the encapsulation layer TFE can be formed.

[0183] In an embodiment, due to the first to third auxiliary electrodes AXE1 to AXE3, the separation wall pattern PWP, and the connection line CNL can be completely extended while contacting each other, a connection electrode CNE including the first to third auxiliary electrodes AXE1 to AXE3, the separation wall pattern PWP, and the connection line CNL can be formed. The connection electrode CNE can be connected to the cathode electrode CE, can completely surround the cathode electrode CE and the insulating separation wall ISW, and can electrically connect the cathode electrodes CE spaced apart from each other.

[0184] In an embodiment, due to the anode electrode AE being spaced apart from the insulating layer ISL by the insulating separation wall ISW and protruding, in a case where the emission layer EML is completely deposited on the anode electrode AE, a shadow effect in which deposition is not well performed in a shadow part can be prevented. Accordingly, the emission layer EML of a more uniform thickness can be formed in the sub-pixel area. By connecting the cathode electrodes CE to each other, by using the auxiliary electrode AXE, the separation wall pattern PWP, and the connection line CNL connected while contacting each other, instead of connecting the cathode electrodes CE as a single extended structure, a step coverage problem in which deposition is not well performed in part can be prevented. For example, due to the prevention of disconnection and resistance increase due to the step coverage, the connection electrode CNE can stably connect the cathode electrodes CE to each other. Accordingly, the reliability of the display device can be improved.

[0185] Figure 36 is a schematic block diagram illustrating an embodiment of a display system.

[0186] Reference Figure 36 The display system 1000 can include a processor 1100 and a display device 1200.

[0187] The processor 1100 can perform various tasks and calculations. In an embodiment, the processor 1100 can include an application processor, a graphic processor, a microprocessor, and a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 through a bus system to control the other components.

[0188] The processor 1100 can transmit the image data IMG and the control signal CTRL to the display device 1200. The display device 1200 can display an image based on the image data IMG and the control signal CTRL. The display device 1200 can be similar to the display device 1200 described with reference to FIG. 1. Figure 1 The display device DD described is configured, and the image data IMG and the control signal CTRL can be provided as input image data IMG and a control signal CTRL of Figure 1 .

[0189] The display system 1000 can include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer (PC), a watch phone, a car display, smart glasses, a portable multimedia player (PMP), a navigation device, and an ultra-mobile personal computer (UMPC). The display system 1000 can include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0190] Figures 37 to 40 is a perspective view illustrating an application example of the display system of Figure 36 .

[0191] Referring to Figure 37 , Figure 36 , the display system 1000 can be applied to a smart watch 2000 including a display unit 2100 and a band unit 2200.

[0192] The smart watch 2000 can be a wearable electronic device. For example, the smart watch 2000 can have a structure in which the band unit 2200 can be mounted on a user's wrist. Here, the display system 1000 and / or the display device 1200 can be applied to the display unit 2100, and can provide image data including time information to the user.

[0193] Referring to Figure 38 , Figure 36 , the display system 1000 can be applied to a car display system 3000. Here, the car display system 3000 can include a computing system provided inside and / or outside a vehicle to provide image data.

[0194] For example, the display system 1000 and / or the display device 1200 can be applied to at least one of an infotainment panel 3100, an instrument panel 3200, a co-driver display 3300, a head-up display 3400, a side mirror display 3500, and a rear seat display 3600 provided in a vehicle.

[0195] Referring to Figure 39 , Figure 36The display system 1000 of FIG. 1 can be applied to smart glasses 4000. The smart glasses 4000 can be a wearable electronic device that can be worn on a user's head. For example, the smart glasses 4000 can be a wearable device for augmented reality.

[0196] The smart glasses 4000 can include a frame 4100 and a lens unit 4200. The frame 4100 can include a housing 4110 supporting the lens unit 4200 and an eye leg unit 4120 for a user to wear. The eye leg unit 4120 can be connected to the housing 4110 through a hinge and can be folded or unfolded with respect to the housing 4110.

[0197] A battery, a touchpad, a microphone, a camera, and the like can be built in the frame 4100. A projector outputting light and a processor controlling a light signal, and the like can be built in the frame 4100.

[0198] The lens unit 4200 can include an optical member that transmits or reflects light. For example, the lens unit 4200 can include glass or transparent synthetic resin, or the like.

[0199] To make the user's eyes recognize visual information, the lens unit 4200 can reflect an image through a light signal transmitted from the projector of the frame 4100 through a rear surface (for example, a surface facing a direction of the user's eyes) of the lens unit 4200. For example, the user can recognize visual information such as time and date displayed on the lens unit 4200. The projector and / or the lens unit 4200 can be a type of display device. The display device 1200 can be applied to the projector and / or the lens unit 4200.

[0200] Reference Figure 40 , Figure 36 The display system 1000 of FIG. 1 can be applied to a head-mounted display device 5000.

[0201] The head-mounted display device 5000 can be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device 5000 can be a wearable device for virtual reality or mixed reality.

[0202] The head-mounted display device 5000 can include a head-mounted band 5100 and a display device receiving housing 5200. The head-mounted band 5100 can be connected to the display device receiving housing 5200. The head-mounted band 5100 can include a horizontal band and / or a vertical band for fixing the head-mounted display device 5000 to a user's head. The horizontal band can be configured to surround a side of the user's head, and the vertical band can be configured to surround an upper portion of the user's head. However, the present disclosure is not limited thereto. For example, the head-mounted band 5100 can be implemented in the form of a spectacle frame or a helmet, or the like.

[0203] The display device receiving case 5200 can accommodate the display system 1000 and / or the display device 1200.

[0204] The above description is an example of technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and changes. Therefore, the above-described disclosed embodiments can be implemented alone or in combination with each other.

[0205] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but are intended to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The scope of protection of the present disclosure should be interpreted by the claims, and all technical spirits within the same scope should be interpreted to be included in the scope of the present disclosure.

Claims

1. A display device comprising: an anode electrode provided over a substrate; a light-emitting layer provided over the anode electrode; a cathode electrode provided over the light-emitting layer; an insulating partition wall provided between the substrate and the anode electrode, overlapping with the anode electrode in a plan view; and a connection electrode connected to the cathode electrode, surrounding the light-emitting layer, the cathode electrode, and the insulating partition wall, and extending over the substrate.

2. The display device according to claim 1, further comprising: an insulating layer provided between the substrate and the insulating partition wall.

3. The display device according to claim 2, wherein the insulating partition wall protrudes from the insulating layer, and the anode electrode is spaced apart from the insulating layer by the insulating partition wall. the connection electrode comprises:

4. The display device according to claim 2 or 3, wherein an auxiliary electrode provided over the cathode electrode and directly in contact with the cathode electrode; a partition wall pattern surrounding the insulating partition wall and connected to the auxiliary electrode; and a connection line provided between the insulating layer and the partition wall pattern, extending over the insulating layer, and connected to the partition wall pattern. the auxiliary electrode comprises a transparent conductive oxide.

5. The display device of claim 4, wherein, 6. The display device according to claim 4, further comprising: an insulating film provided between the insulating partition wall and the anode electrode, and provided between the partition wall pattern and the anode electrode.

7. The display device according to claim 6, further comprising: a sub-electrode provided between the anode electrode and the insulating film.

8. The display device according to claim 7, further comprising: a circuit element provided between the substrate and the insulating layer, and connected to at least one of the anode electrode and the sub-electrode. a contact hole for connection between the at least one of the anode electrode and the sub-electrode and the circuit element is defined in the insulating film, the insulating partition wall, and the insulating layer.

9. The display device of claim 8, wherein, 10. The display device according to claim 9, further comprising: a pixel defining film surrounding a periphery of the anode electrode and in contact with the insulating film.

11. The display device according to claim 10, further comprising: an insulating pattern provided between the anode electrode and the light-emitting layer, and overlapping with the contact hole in the plan view. the insulating pattern and the pixel defining film comprise the same material.

12. The display device of claim 11, wherein, 13. A display device comprising: anode electrodes provided over a substrate, overlapping with sub-pixel regions respectively in a plan view, and spaced apart from each other; light-emitting layers provided over the anode electrodes respectively; cathode electrodes provided over the light-emitting layers respectively and spaced apart from each other; insulating partition walls provided between the substrate and the anode electrodes, overlapping with the anode electrodes respectively in the plan view, and spaced apart from each other; and connection electrodes connecting the cathode electrodes to each other. the connection electrodes comprise: auxiliary electrodes provided over the cathode electrodes respectively and directly in contact with the cathode electrodes respectively; 14. The display device of claim 13, wherein, ​ ​ a partition wall pattern surrounding the insulating partition wall, each of the partition wall patterns overlapping a corresponding one of the auxiliary electrodes in the plan view and connected to the corresponding one of the auxiliary electrodes; and a connection line provided between the substrate and the partition wall pattern and connecting the partition wall pattern to each other.

15. The display device of claim 14, wherein, The connection line is provided between the substrate and the insulating partition wall and extends entirely over the substrate except for a portion overlapping the insulating partition wall in the plan view.

16. A method of manufacturing a display device, the method comprising: forming an insulating partition wall on a substrate; forming an anode electrode overlapping the insulating partition wall on the insulating partition wall; forming an emission layer on the anode electrode; forming a cathode electrode on the emission layer; and forming a connection electrode connected to the cathode electrode, surrounding the cathode electrode and the insulating partition wall, and extending over the substrate.

17. The method of claim 16, wherein, The forming of the connection electrode includes: forming a connection line including a first opening on the substrate before the forming of the insulating partition wall.

18. The method of claim 17, wherein, The forming of the connection electrode further includes: forming a preliminary insulating layer including a second opening overlapping the first opening in the plan view on the connection line; forming a preliminary partition wall pattern over an entire region of the connection line and the preliminary insulating layer; and forming a partition wall pattern including a third opening overlapping the second opening in the plan view by patterning the preliminary partition wall pattern.

19. The method of claim 18, wherein, The insulating partition wall is formed inside the partition wall pattern.

20. The method according to claim 18, wherein The forming of the connection electrode further includes forming an auxiliary electrode surrounding the emission layer and the cathode electrode on the cathode electrode after the forming of the cathode electrode, and The auxiliary electrode directly contacts the partition wall pattern.

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