Magnetoresistive random access memory and manufacturing method thereof

Abstract

The invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof, and the manufacturing method of the magnetoresistive random access memory (MRAM) mainly comprises the following steps: forming a spin-orbit torque (SOT) layer on a substrate, then forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first covering layer beside the MTJ, forming a second covering layer beside the MTJ, and forming a second covering layer beside the MTJ. Forming a second covering layer beside the first covering layer, wherein the top surface of the second covering layer is lower than the top surface of the first covering layer;

Description

TECHNICAL FIELD

[0001] The present application relates to a magnetoresistive random access memory (MRAM) element and a method for fabricating the same. BACKGROUND

[0002] It is known that the magnetoresistance (MR) effect is an effect in which the resistance of a material changes with an applied magnetic field. The physical quantity is defined as the difference in resistance with and without a magnetic field divided by the original resistance, and is used to represent the resistance change rate. At present, the magnetoresistance effect has been successfully applied in the production of hard disks, and has important commercial application value. In addition, using the characteristic that the giant magnetoresistance material has different resistance values in different magnetization states, a magnetic random access memory (MRAM) can also be made, which has the advantage of being able to continue to retain stored data without power.

[0003] The above-mentioned magnetoresistance effect is also applied in the field of magnetic field sensors, for example, an electronic compass component in a mobile phone matched with a global positioning system (GPS), which is used to provide information such as the moving direction of the user. At present, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned prior art usually include: occupying a large chip area, expensive manufacturing process, high power consumption, insufficient sensitivity, and being easily affected by temperature changes, etc., and it is necessary to further improve. SUMMARY

[0004] One embodiment of the present application discloses a method for fabricating a magnetoresistive random access memory (MRAM) element, which mainly forms a spin orbit torque (SOT) layer on a substrate, then forms a magnetic tunneling junction (MTJ) on the SOT layer, forms a first cover layer beside the MTJ, and then forms a second cover layer beside the first cover layer, wherein the top surface of the second cover layer is lower than the top surface of the first cover layer.

[0005] Another embodiment of the present disclosure discloses a magnetoresistive random access memory (MRAM) element, which mainly comprises a spin orbit torque (SOT) layer disposed on a substrate, a magnetic tunneling junction (MTJ) disposed on the SOT layer, a first capping layer disposed beside the MTJ, and a second capping layer disposed beside the first capping layer, wherein the top surface of the second capping layer is lower than the top surface of the first capping layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figures 1 to 10 A method for fabricating an MRAM cell according to an embodiment of the present disclosure is shown.

[0007] LEGEND

[0008] 12: substrate

[0009] 14: MRAM region

[0010] 16: interlayer dielectric layer

[0011] 18: metal interconnect structure

[0012] 20: metal interconnect structure

[0013] 22: intermetal dielectric layer

[0014] 24: metal interconnect

[0015] 26: stop layer

[0016] 28: intermetal dielectric layer

[0017] 30: metal interconnect

[0018] 32: metal interconnect

[0019] 34: barrier layer

[0020] 36: metal layer

[0021] 40: logic region

[0022] 42: lower electrode

[0023] 44: SOT layer

[0024] 46: free layer

[0025] 48: barrier layer

[0026] 50: fixed layer

[0027] 60: capping layer

[0028] 62: Upper electrode

[0029] 64: Dielectric layer

[0030] 66: MTJ stacked structure

[0031] 70:MTJ

[0032] 72: First covering layer

[0033] 74: First Oxide Layer

[0034] 76: Bottom anti-reflective layer

[0035] 78: Patterned Mask

[0036] 80: Second covering layer

[0037] 84: Second oxide layer

[0038] 86: Metal interconnects

[0039] 88: Stop Layer

[0040] 90: Intermetallic dielectric layer

[0041] 92: Metal interconnects

[0042] 94: Stop Layer

[0043] 108: Doped region

[0044] 110: Horizontal section

[0045] 112: Vertical section

[0046] 114: Part One

[0047] 116: Part Two Detailed Implementation

[0048] Please refer to Figures 1 to 10 , Figures 1 to 10 This is a schematic diagram illustrating a method for fabricating a semiconductor device, or more specifically, an MRAM cell, according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of semiconductor material, wherein the semiconductor material may be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 40 are preferably defined on the substrate 12.

[0049] Active (e.g., metal-oxide semiconductor (MOS) transistors) and passive elements, conductive layers, and dielectric layers (e.g., interlayer dielectric (ILD) 16) can be formed on substrate 12. More specifically, MOS transistor elements (e.g., planar or non-planar (e.g., fin structure transistors)) can be formed on substrate 12, where the MOS transistors can include gate structures (e.g., metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, etc., and ILD 16 can be formed on substrate 12 and over the MOS transistors, and ILD 16 can have contact plugs electrically connected to the gate and / or source / drain regions of the MOS transistors. The fabrication of planar or non-planar transistors and ILDs are well known in the art and will not be described in detail.

[0050] Metal interconnect structures 18, 20 are then formed on ILD 16 in MRAM region 14 and are electrically connected to the contact plugs described above. Metal interconnect structure 18 includes an intermetal dielectric layer 22 and a metal interconnect 24 embedded in intermetal dielectric layer 22, and metal interconnect structure 20 includes a stop layer 26, an intermetal dielectric layer 28, and a plurality of metal interconnects 30, 32 embedded in stop layer 26 and intermetal dielectric layer 28. It is noted that, at this stage, metal interconnects 24 are formed in intermetal dielectric layer 22 in logic region 40, but no metal interconnects are formed in intermetal dielectric layer 28 in logic region 40, in contrast to the formation of metal interconnects 24, 30, 32 in MRAM region 14.

[0051] In this embodiment, each metal interconnect 24 in the metal interconnect structure 18 preferably comprises a trench conductor, and each metal interconnect 30, 32 in the metal interconnect structure 20 comprises a via conductor. In addition, each metal interconnect 24, 30, 32 in each metal interconnect structure 18, 20 can be embedded in the intermetal dielectric layer 22, 28 and / or the stop layer 26 and electrically connected to each other according to a single damascene process or a dual damascene process. For example, each metal interconnect 24, 30, 32 can further comprise a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), and the like, but not limited thereto. Since the single damascene or dual damascene process is well known in the art, no further elaboration is provided herein. In addition, in this example, the metal layer 36 in the metal interconnect 24 preferably comprises copper, the metal layer 36 in the metal interconnect 30, 32 preferably comprises tungsten, the intermetal dielectric layer 22, 28 preferably comprises silicon oxide or a low-k dielectric layer, and the stop layer 26 comprises a nitrogen doped carbide (NDC) layer, silicon nitride, or silicon carbon nitride (SiCN), but not limited thereto.

[0052] Next, a selective bottom electrode 42, a spin orbit torque (SOT) layer 44, an MTJ stack 66, a capping layer 60, and a patterned top electrode 62 are formed on the metal interconnect structure 20. In this embodiment, the MTJ stack 66 is formed by sequentially forming a free layer 46, a barrier layer 48, a reference layer (not shown), a spacer (not shown), and a pinned layer 50 on the SOT layer 44. The free layer 46 can be formed of a ferromagnetic material, such as iron, cobalt, nickel, or an alloy thereof, such as cobalt-iron-boron (CoFeB), but not limited thereto, and the magnetization direction of the free layer 46 is "free" to change under an external magnetic field. The barrier layer 48 can be formed of an insulating material containing an oxide, such as aluminum oxide (AlO x ) or magnesium oxide (MgO), but not limited thereto.

[0053] The reference layer is preferably disposed between the barrier layer 48 and the spacer layer, which can comprise a ferromagnetic material such as iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), but is not limited thereto. The spacer layer comprises a non-magnetic layer of a non-magnetic material such as selected from the group consisting of ruthenium, iridium, and rhodium.

[0054] The fixed layer 50 can comprise a ferromagnetic material such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), cobalt (Co), etc. Alternatively, the fixed layer 50 can comprise an antiferromagnetic (AFM) material such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc. to fix or pin the direction of the magnetic moment of the adjacent layer. In detail, the fixed layer 50 can comprise a lower synthetic antiferromagnetic (SAF) layer, a coupling layer, and an upper synthetic antiferromagnetic layer, wherein the lower and upper synthetic antiferromagnetic layers can comprise the same or different materials and both can comprise a ferromagnetic material such as cobalt (Co), nickel (Ni), platinum (Pt), palladium (Pd), or combinations thereof, and the coupling layer preferably comprises a material such as ruthenium (Ru), tantalum (Ta), gadolinium (Gd), platinum (Pt), hafnium (Hf), or combinations thereof to provide mechanical and / or lattice support to the lower and upper synthetic antiferromagnetic layers.

[0055] In addition, in the present embodiment, the selective lower electrode 42 preferably comprises a conductive material such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), the SOT layer 44 preferably serves as a channel for a spin orbit torque (SOT) MRAM and thus can comprise tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), bismuth selenide (BiSe), or combinations thereof, the capping layer 60 preferably comprises a metal such as ruthenium, and the upper electrode 62 can comprise a conductive or dielectric material such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or combinations thereof. x Se 1-x ) or combinations thereof, the capping layer 60 preferably comprises a metal such as ruthenium, and the upper electrode 62 can comprise a conductive or dielectric material such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or combinations thereof.

[0056] In addition, in this embodiment, the patterned upper electrode 62 can be formed by forming a dielectric layer 64 made of silicon oxide on the unpatterned upper electrode 62, and then using a patterned mask (not shown), such as a patterned photoresist, to remove part of the dielectric layer 64 and the upper electrode 62 by means of, for example, reactive ion etching (RIE) to form a patterned dielectric layer 64 and a patterned upper electrode 62, and then selectively removing the dielectric layer 64 made of silicon oxide.

[0057] like Figure 2 As shown, a patterned dielectric layer 64 or a patterned top electrode 62 can then be used as a mask to remove part of the masking layer 60, part of the MTJ stack structure 66, and even part of the SOT layer 44 of the MRAM region 14 to form the MTJ 70. Then, a first masking layer 72 and a first oxide layer 74 are sequentially formed on the MTJ 70. Preferably, the MTJ stack structure 66 of the logic region 40 is completely removed at this stage, and in this embodiment, the etching process parameters are preferably adjusted in the aforementioned patterning process so that the top surface of the top electrode 62 directly above the MTJ 70 is curved. Because the top surface of the top electrode 62 is curved, the top surfaces of the first masking layer 72 and the first oxide layer 74 disposed thereon are also preferably curved. It should be noted that, in this stage, after the MTJ stack structure 66 is patterned using pattern transfer to form the MTJ 70, the resulting MTJ 70 sidewalls preferably have a curved surface with an inclined surface connecting to the top of the upper electrode 62. The subsequent first masking layer 72 also preferably conformally covers the surface of the MTJ 70 along the contours of the upper electrode 62 and the MTJ 70. Furthermore, in this embodiment, during the process of patterning the MTJ stack structure 66 to form the MTJ 70 using the above-described etching process, some metal atoms may adhere to the sidewalls of the MTJ 70 to form doped regions 108. These doped regions 108 may contain materials such as titanium nitride from the original upper electrode 62 and / or masking layer 60, as well as metal materials from the MTJ 70 such as iron, cobalt, nickel, or their alloys.

[0058] In this embodiment, the first masking layer 72 preferably comprises silicon nitride, while the first oxide layer 74 comprises silicon oxide such as tetraethoxysilane (TEOS). It should also be noted that when forming the MTJ 70 by patterning the MTJ stack structure 66 using the patterned upper electrode 62 in this stage, a portion of the SOT layer 44 can be selectively removed, so that the top surfaces of the remaining SOT layers 44 on both sides of the MTJ 70 are slightly lower than the top surface of the SOT layer 44 directly below the MTJ 70. According to another embodiment of the present invention, if no SOT layer 44 is removed during the formation of the MTJ 70, the top surfaces of the remaining SOT layers 44 on both sides of the MTJ 70 are preferably flush with the top surface of the SOT layer 44 directly below the MTJ 70. Furthermore, the first masking layer 72 and the first oxide layer 74 formed in this stage are preferably simultaneously disposed on the MRAM region 14 and the logic region 40.

[0059] like Figures 3 to 4 As shown, a bottom anti-reflective coating (BARC) 76 is first formed on the first oxide layer 74. Then, an etching process is performed using a patterned mask 78, such as a patterned photoresist, as a mask. Another RIE process is then used to remove a portion of the bottom anti-reflective coating 76, a portion of the first oxide layer 74, a portion of the first masking layer 72, and all the bottom anti-reflective coating 76 and first oxide layer 74 in the MRAM region 14, exposing the underlying first masking layer 72. This leaves the remaining first oxide layer 74 only in the MRAM region 14, but the underlying first masking layer 72 remains simultaneously in both the MRAM region 14 and the logic region 40. The bottom anti-reflective coating 76 can then be removed to expose the first oxide layer 74 in the MRAM region 14. It should be noted that after removing a portion of the first oxide layer 74 using the above etching process, it is preferable to remove a portion of the first masking layer 72, so that the sidewalls of the remaining first oxide layer 74 are flush with the sidewalls of the first masking layer 72.

[0060] Subsequently, as Figure 5As shown, an etching fabrication process can be performed without forming an additional patterning mask, such as removing all of the first oxide layer 74, part of the first capping layer 72, part of the SOT layer 44 and part of the lower electrode 42 of the MRAM region 14, and all of the first capping layer 72, all of the SOT layer 44, all of the lower electrode 42 and part of the intermetal dielectric layer 28 of the logic region 40 by using an ion beam etching (IBE) fabrication process different from the aforementioned and according to an angle c, so that the first capping layer 72, the SOT layer 44 and the lower electrode 42 of the MRAM region 14 form a cut-off inclined sidewall, and the remaining top surface of the intermetal dielectric layer 28 of the logic region 40 can be optionally slightly lower than the top surface of the intermetal dielectric layer 28 of the MRAM region 14. In this embodiment, the angle c is preferably less than 50 degrees or most preferably between 10-30 degrees.

[0061] It is worth noting that the IBE fabrication process used in this stage preferably simultaneously shapes the first capping layer 72 after removing the first oxide layer 74, such as locally reducing the first capping layer 72 originally having a uniform thickness so that the thickness of the first capping layer 72 above the MTJ 70 and on both sides of the SOT layer 44 of the MTJ 70 is slightly greater than the thickness of the first capping layer 72 of the sidewall of the MTJ 70. More specifically, the shaped first capping layer 72 is preferably formed with two included angles above the MTJ 70 and on both sides of the SOT layer 44 of the MTJ 70, wherein the top surface of the first capping layer 72 above the MTJ 70 preferably includes an angle a, the angle a includes an obtuse angle and the angle a is most preferably greater than 90 degrees or between 100-160 degrees, and the top surface between the SOT layer 44 and the first capping layer 72, the top surface between the lower electrode 72 and the first capping layer 72, or the top surface between the intermetal dielectric layer 28 and the first capping layer 72 on both sides of the MTJ 70 each includes an angle b, the angle b includes an acute angle and the angle b is most preferably less than 70 degrees or between 30-60 degrees.

[0062] Then as shown in FIG. 2B, a second oxide layer 76 is formed on the top surface of the first capping layer 72, the SOT layer 44 and the lower electrode 42 of the MRAM region 14, and the top surface of the first capping layer 72, the SOT layer 44 and the lower electrode 42 of the logic region 40. Figure 6As shown, a second masking layer 80 is formed on the surface of the first masking layer 72 in the MRAM region 14 and on the surface of the inter-metal dielectric layer 28 in the logic region 40. In this embodiment, the first masking layer 72 and the second masking layer 80 preferably contain the same material, for example, both preferably contain silicon nitride, wherein the first masking layer 72 is preferably a silicon-rich layer, that is, the silicon concentration of the first masking layer 72 is preferably greater than the silicon concentration of the second masking layer 80. Since the second cover layer 80 conformally covers the surface of the first cover layer 72, the second cover layer 80, which is disposed directly above the MTJ 70 and on both sides of the MTJ 70 as described above the first cover layer 72, preferably has two included angles. The top surface of the second cover layer 80 directly above the MTJ 70 preferably includes an angle α, which is an obtuse angle and is preferably between 100 and 160 degrees. The top surface of the SOT layer 44, the bottom electrode 72, or the intermetallic dielectric layer 28 on both sides of the MTJ 70 and the top surface of the second cover layer 80 each include an angle b, which is an acute angle and is preferably between 30 and 60 degrees.

[0063] Then as Figure 7 As shown, a single etch process can be performed using either a patterned mask or without a patterned mask to remove a portion of the second masking layer 80 of the MRAM region 14 and all of the second masking layers 80 of the logic region 40, exposing the top surface of the intermetallic dielectric layer 28. In this stage, after removing a portion of the second masking layer 80 above the first masking layer 72, the first masking layer 80 is preferably reshaped so that the remaining first masking layer 72 includes a horizontal portion 110 disposed on the SOT layer 44 and a vertical portion 112 disposed on the horizontal portion 110. The horizontal portion 110 is directly connected to the vertical portion 112, and the two together form an L-shape. Simultaneously, the remaining second masking layer 80 is preferably divided into a first portion 114 and a second portion 116 disposed on both sides of the vertical portion 112 and the horizontal portion 110, respectively. It should be noted that in this embodiment, each vertical part 112 is preferably disposed at an inclined angle next to the MTJ 70, wherein the angle between each vertical part 112 and the surface of the base 12 is preferably less than 90 degrees or more preferably between 60 and 80 degrees.

[0064] In this embodiment, the first part 114 is disposed next to the vertical part 112, and the second part 116 is disposed next to the horizontal part 110. The top surface of the first part 114 is lower than the top surface of the vertical part 112, and the top surface of the second part 116 is lower than the top surface of the horizontal part 110. In detail, the bottom surface of the first portion 114 to the top surface of the vertical portion 112 of the first masking layer 72 includes a height H1, the bottom surface of the second portion 116 to the top surface of the horizontal portion 110 includes a height H2, the top surface of the first portion 114 to the top surface of the vertical portion 112 includes a height H3 through which a portion of the second masking layer 80 is removed by the aforementioned etching, and the top surface of the second portion 116 to the top surface of the horizontal portion 110 includes a height H4 through which a portion of the second masking layer 80 is removed by the aforementioned back etching, wherein H3 = (0.2 to 0.5)H1 and H4 = (0.1 to 0.3)H2, that is, H3 is approximately equal to 0.2 to 0.5 times H1, and H4 is approximately equal to 0.1 to 0.3 times H2.

[0065] Please continue to refer to Figures 8 to 9 , Figures 8 to 9 These are continuations of an embodiment of the present invention at different angles. Figure 7 A schematic diagram illustrating the method for fabricating MRAM cells. (See diagram below.) Figures 8 to 9 As shown, a second oxide layer 84 is first formed in the MRAM region 14 and the logic region 40, and then a portion of the second oxide layer 84 is removed using a planarization process such as chemical mechanical polishing (CMP). Next, a pattern transfer process can be performed, for example, using a patterned mask to remove a portion of the second oxide layer 84, a portion of the first oxide layer 74, and a portion of the first masking layer 72 in the MRAM region 14, and a portion of the second oxide layer 84, a portion of the intermetallic dielectric layer 28, and a portion of the stop layer 26 in the logic region 40 to form contact holes (not shown) and expose the underlying upper electrode 62 and the metal interconnect 24. Then, the contact holes are filled with the desired conductive material, such as a barrier layer containing titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization process is performed, such as chemical mechanical polishing, to remove some of the conductive material to form a metal interconnect 86 that electrically connects the upper electrode 62 and the metal interconnect 24 within the contact hole. Because... Figure 8 A cross-sectional view of the area next to the metal interconnect 86. Figure 9 This is a cross-sectional view directly above the metal interconnect 86; therefore, the state of the metal interconnect 86 connected to the upper electrode 62 is only shown in [the diagram]. Figure 9 .

[0066] In this embodiment, the first oxide layer 74 and the second oxide layer 84 preferably comprise different dielectric constants, and the dielectric constant of the second oxide layer 84 is preferably less than the dielectric constant of the first oxide layer 74. The dielectric constant of the first oxide layer 74 is preferably between 3.2 and 4.2, and the dielectric constant of the second oxide layer 84 is preferably between 2.4 and 2.8 or most preferably about 2.6. The ratio of the dielectric constant of the first oxide layer 74 to the dielectric constant of the second oxide layer 84 is preferably between 1.2 and 1.6. For example, the first oxide layer 74 in this embodiment preferably comprises TEOS or silicon oxide, and the second oxide layer 84 preferably comprises an ultra low dielectric constant dielectric layer, such as a porous dielectric material, for example, but not limited to, silicon oxycarbide (SiOC) or silicon oxycarbide hydrogen (SiOCH).

[0067] Thereafter, as shown in Figure 10 , a stop layer 88 is formed on the metal interconnects 86, an intermetal dielectric layer 90 is formed on the stop layer 88 in the MRAM region 14 and the logic region 40, and a pattern transfer fabrication process is performed to remove portions of the intermetal dielectric layer 90 and portions of the stop layer 88 to form contact holes (not shown) and expose the underlying metal interconnects 86. Then, a desired conductive material, such as a barrier layer material comprising titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and the like, and a low resistance metal layer selected from tungsten (W), copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), and the like, or a combination thereof, is filled in the contact holes. A planarization fabrication process, such as a chemical mechanical polishing fabrication process, is then performed to remove portions of the metal material to form contact plugs or metal interconnects 92 in the contact holes to electrically connect the metal interconnects 86, and a stop layer 94 is then selectively formed on the metal interconnects 92. In this embodiment, the intermetal dielectric layer 90 preferably comprises an ultra low dielectric constant dielectric layer, such as a porous dielectric material, for example, but not limited to, silicon oxycarbide (SiOC) or silicon oxycarbide hydrogen (SiOCH).

[0068] Referring again to Figure 7 , Figure 7 A schematic diagram of the structure of an MRAM element of an embodiment of the present application is shown in Figure 7As shown, the MRAM element of the present application mainly comprises a SOT layer 44 disposed on a substrate 12, an MTJ 70 disposed on the SOT layer 44, a first capping layer 72 disposed on the MTJ 70 and beside the SOT layer 44, and a second capping layer 80 disposed on the first capping layer 72. The first capping layer 72 comprises a horizontal portion 110 disposed on the SOT layer 44 and a vertical portion 112 disposed on the horizontal portion 110, and the horizontal portion 110 is directly connected to the vertical portion 112. The second capping layer 80 comprises a first portion 114 disposed beside the vertical portion 112 and a second portion 116 disposed beside the horizontal portion 110, and the top surface of the first portion 114 is lower than the top surface of the vertical portion 112, and the top surface of the second portion 116 is lower than the top surface of the horizontal portion 110. As mentioned above, the height from the bottom surface of the first portion 114 to the top surface of the vertical portion 112 of the first capping layer 72 is H1, the height from the bottom surface of the second portion 116 to the top surface of the horizontal portion 110 is H2, the height from the top surface of the first portion 114 to the top surface of the vertical portion 112 is H3, and the height from the top surface of the second portion 116 to the top surface of the horizontal portion 110 is H4, wherein H3 = (0.2-0.5)H1 and H4 = (0.1-0.3)H2.

[0069] In summary, the present application mainly discloses a method for manufacturing a SOT MRAM element and related structure. The method mainly comprises the following steps: forming a SOT layer 44 and an MTJ 70 on a substrate, forming a first capping layer 72 on the MTJ and the SOT layer, forming a second capping layer 80 on the first capping layer 72, and removing part of the second capping layer and part of the first capping layer by etching, so that the remaining first capping layer comprises a horizontal portion 110 and a vertical portion 112, and the remaining second capping layer is divided into a first portion 114 disposed beside the vertical portion and a second portion 116 disposed beside the horizontal portion, wherein the top surface of the first portion 114 is lower than the top surface of the vertical portion 112, and the top surface of the second portion 116 is lower than the top surface of the horizontal portion 110. According to the preferred embodiment of the present application, the configuration can fill more intermetallic dielectric layers beside the MTJ in the subsequent process, thereby improving the insulation capability between elements.

[0070] The above description is only the preferred embodiment of the present application, and any equivalent changes and modifications made according to the claims of the present application should be included in the scope of the present application.

Claims

1. A method of fabricating a Magnetoresistive Random Access Memory (MRAM) element, characterized by, comprising: forming a spin orbit torque (SOT) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the spin orbit torque layer; forming a first capping layer next to the magnetic tunneling junction; and forming a second capping layer next to the first capping layer, wherein a top surface of the second capping layer is lower than a top surface of the first capping layer.

2. The method of claim 1, wherein the substrate comprises an MRAM region and a logic region, the method further comprising: forming an intermetal dielectric layer on the substrate; forming a first metal interconnect and a second metal interconnect in the intermetal dielectric layer; forming the spin orbit torque layer on the first metal interconnect and the second metal interconnect; forming an upper electrode on the magnetic tunneling junction; forming the first capping layer on the magnetic tunneling junction and the spin orbit torque layer; forming a first oxide layer on the first capping layer of the MRAM region and the logic region; performing a first etch process to remove the first oxide layer of the logic region; performing a second etch process to remove the first oxide layer of the MRAM region and shape the first capping layer; forming the second capping layer on the first capping layer; performing a third etch process to remove the second capping layer of the logic region; and forming a second oxide layer on the second capping layer.

3. The method of claim 2, wherein a top surface of the upper electrode comprises a curved surface.

4. The method of claim 1, wherein the first capping layer comprises: a horizontal portion disposed on the spin orbit torque layer; and a vertical portion disposed on the horizontal portion.

5. The method of claim 4, further comprising performing the third etch process to separate the second capping layer into a first portion and a second portion.

6. The method of claim 5, wherein the first portion is disposed next to the vertical portion.

7. The method of claim 6, wherein a top surface of the first portion is lower than a top surface of the vertical portion.

8. The method of claim 5, wherein the second portion is disposed next to the horizontal portion.

9. The method of claim 8, wherein a top surface of the second portion is lower than a top surface of the horizontal portion. comprising:

10. A Magnetoresistive Random Access Memory (MRAM) element comprising: a spin orbit torque (SOT) layer disposed on a substrate; a magnetic tunneling junction (MTJ) disposed on the spin orbit torque layer; a first capping layer disposed next to the magnetic tunneling junction; and a second capping layer disposed next to the first capping layer, wherein a top surface of the second capping layer is lower than a top surface of the first capping layer.

11. The MRAM element of claim 10, further comprising: an intermetal dielectric layer disposed on the substrate; a first metal interconnect and a second metal interconnect disposed in the intermetal dielectric layer; the spin orbit torque layer disposed on the first metal interconnect and the second metal interconnect; an upper electrode disposed on the magnetic tunneling junction; the first capping layer disposed next to the magnetic tunneling junction; and ​ ​ The second capping layer is disposed beside the first capping layer; and An oxidation layer is disposed on the second capping layer.

12. The MRAM element of claim 11, wherein the upper electrode top surface comprises a curved surface.

13. The MRAM element of claim 10, wherein the first capping layer comprises: a horizontal portion disposed on the spin-orbit torque layer; and a vertical portion disposed on the horizontal portion.

14. The MRAM element of claim 13, wherein the second capping layer comprises: a first portion disposed beside the vertical portion; and a second portion disposed beside the horizontal portion.

15. The MRAM element of claim 14, wherein the first portion top surface is lower than the vertical portion top surface.

16. The MRAM element of claim 14, wherein the second portion top surface is lower than the horizontal portion top surface.

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