Composite substrate and method for manufacturing a composite substrate

Abstract

The embodiment of the application provides a composite substrate and a preparation method of the composite substrate, relates to the technical field of semiconductor devices, and is used for solving the technical problem of a large bonding interface resistance of a composite substrate formed by bonding a 3C-SiC substrate and a 4H-SiC substrate in the related art; the composite substrate comprises a 3C-SiC layer and a 4H-SiC layer, the 4H-SiC layer comprises a first surface, and the 3C-SiC layer comprises a second surface; the first surface and / or the second surface comprises a high-concentration doped layer with N-type conductivity, and a bonding interface of the 3C-SiC layer and the 4H-SiC layer is a contact surface of the high-concentration doped layer and the second surface, the high-concentration doped layer and the first surface or the two high-concentration doped layers. The band bending effect of the high-concentration doped layer is used to adjust the interface band, the width and height of the potential barrier of the bonding interface are reduced, electrons pass through the potential barrier through a tunneling mechanism, the migration efficiency of the electrons at the heterojunction interface is improved, and the interface resistance is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a composite substrate and a preparation method of the composite substrate. BACKGROUND

[0002] The silicon carbide substrate is a monocrystalline wafer formed by processing a silicon carbide crystal through cutting, grinding, polishing, cleaning and the like. The 3C-SiC polycrystalline substrate in the silicon carbide substrate has the advantage of low resistivity, and is very suitable for being used as a support substrate to reduce the conduction loss. The 4H-SiC monocrystalline substrate in the silicon carbide substrate has the advantage of high electron mobility, and the electrons move fast therein, so that the device is fast in switching and high in frequency.

[0003] In the related art, the 3C-SiC polycrystalline substrate and the 4H-SiC monocrystalline substrate are combined by using a bonding process to form a composite substrate structure, so as to realize the unification of low loss and high frequency performance of the device.

[0004] However, there is a significant difference in electron affinity energy and band gap between the two crystal forms of 3C-SiC and 4H-SiC, so that a wide and high potential barrier is formed at the bonding interface of the two, the carriers (electrons) cannot directly cross the potential barrier, and can only rely on their own thermal energy to cross the potential barrier or the probability of crossing the potential barrier is reduced, resulting in that the current is seriously blocked at the bonding interface, the interface resistance is significantly increased, the conduction loss of the device is large, and the high frequency response capability and power density of the device are limited. SUMMARY

[0005] Embodiments of the present application provide a composite substrate and a preparation method of the composite substrate, to solve the technical problem of large bonding interface resistance of the composite substrate formed by bonding the 3C-SiC substrate and the 4H-SiC substrate in the related art.

[0006] In a first aspect, embodiments of the present application provide a composite substrate, comprising: a 3C-SiC layer; and a 4H-SiC layer, the 4H-SiC layer comprising a first surface, the 3C-SiC layer comprising a second surface, the first surface comprising a first high-concentration doped layer having N-type conductivity, and / or the second surface comprising a second high-concentration doped layer having N-type conductivity; a contact surface of the first high-concentration doped layer and the second surface, a contact surface of the second high-concentration doped layer and the first surface, or a contact surface of the first high-concentration doped layer and the second high-concentration doped layer is a bonding interface of the 3C-SiC layer and the 4H-SiC layer.

[0007] In a possible implementation, the 3C-SiC layer is a polycrystalline 3C-SiC layer; and the 4H-SiC layer is a monocrystalline 4H-SiC layer.

[0008] In a possible implementation, the doping concentration of the first high-concentration doped layer and the second high-concentration doped layer is 4 × 10¹ 9 cm⁻³~5 × 10²¹ cm⁻³.

[0009] In a possible implementation, the doping ions of the first high-concentration doped layer and the second high-concentration doped layer include one or more of phosphorus, nitrogen, and argon.

[0010] In a possible implementation, the thickness of the first high-concentration doped layer and the second high-concentration doped layer is 0 μm~0.3 μm.

[0011] In a possible implementation, the roughness of the first high-concentration doped layer and the second high-concentration doped layer is less than 5 nm.

[0012] In a second aspect, an embodiment of the present application provides a preparation method of a composite substrate, which is used for preparing the composite substrate described above, and includes the following steps: respectively performing polishing treatment on surfaces of a 3C-SiC layer and a 4H-SiC layer; forming a first high-concentration doped layer with N-type conductivity on a first surface of the 4H-SiC layer and / or forming a second high-concentration doped layer with N-type conductivity on a second surface of the 3C-SiC layer by an ion implantation process or an epitaxy process; and bonding the 3C-SiC layer and the 4H-SiC layer to each other to obtain a composite substrate; wherein a bonding interface of the 3C-SiC layer and the 4H-SiC layer is a contact surface of the first high-concentration doped layer and the second surface, a contact surface of the second high-concentration doped layer and the first surface, or a contact surface of the first high-concentration doped layer and the second high-concentration doped layer.

[0013] In a possible implementation, after the first high-concentration doped layer with N-type conductivity is formed on the first surface of the 4H-SiC layer by the ion implantation process or the epitaxy process, the method further includes: forming a doped layer with N-type conductivity on a third surface of the 4H-SiC layer by the ion implantation process or the epitaxy process; wherein the third surface is opposite to the first surface along a thickness direction of the 4H-SiC layer.

[0014] In a possible implementation, after the first high-concentration doped layer with N-type conductivity is formed on the first surface of the 4H-SiC layer by the ion implantation process or the epitaxy process, the method further includes: treating the 4H-SiC layer by a high-temperature annealing process; the annealing temperature of the high-temperature annealing process is 900 ℃~1900 ℃, and the annealing time is 5 min~90 min.

[0015] In a possible implementation, before the first high-concentration doped layer with N-type conductivity is formed on the first surface of the 4H-SiC layer by the ion implantation process, the method further includes: depositing a barrier layer on the first surface by chemical vapor deposition, the barrier layer being used to reduce damage to the first surface during ion implantation.

[0016] The composite substrate provided by the embodiments of the present application has the following effects:

[0017] By utilizing the band bending effect of the high-concentration doped layer to adjust the interface band structure, the width of the potential barrier of the bonding interface between 3C-SiC and 4H-SiC is shortened and the height of the potential barrier is reduced, so that the electrons pass through the potential barrier by a tunneling mechanism, the migration efficiency of the electrons at the heterojunction interface is improved, and thus the interface resistance is significantly reduced, thereby providing a key material basis for the development of high-performance semiconductor devices.

[0018] Meanwhile, when a large dose of ions is implanted, 4H-SiC and 3C-SiC are also amorphized, which exposes thicker dangling bonds on the bonding surface of 4H-SiC and 3C-SiC, and after the polycrystalline 3C-SiC is amorphized, the influence of the polycrystalline grain boundary on chemical mechanical polishing is avoided, the chemical reaction with the polishing liquid is more uniform, and it is easier to obtain 4H-SiC and 3C-SiC with low roughness, so that 4H-SiC is more easily bonded to 3C-SiC. BRIEF DESCRIPTION OF DRAWINGS

[0019] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the present application.

[0020] Figure 1 Structure diagram of the composite substrate provided by the embodiments of the present application Figure 1 ;

[0021] Figure 2 Structure diagram of the 4H-SiC layer in the preparation of the composite substrate provided by the embodiments of the present application

[0022] Figure 3 Comparison diagram of the simulation structure of the composite substrate provided by Embodiment 1 of the present application and the substrate of Comparative Example 1

[0023] Figure 4 Comparison of the band simulation results of the composite substrate provided by Embodiment 1 of the present application and the substrate of Comparative Example 1 Figure 1 ;

[0024] Figure 5 Comparison of the band simulation results of the composite substrate provided by Embodiment 1 of the present application and the substrate of Comparative Example 1 Figure 2 ;

[0025] Figure 6The current-voltage curve simulation result comparison chart of the composite substrate provided for Embodiment 1 of the present application and Comparative Example 1;

[0026] Figure 7 Structure diagram of the composite substrate provided for the present application Figure 2 .

[0027] Reference signs:

[0028] 100-3C-SiC layer;

[0029] 101-Second surface;

[0030] 200-4H-SiC layer;

[0031] 201-First surface; 202-Third surface;

[0032] 300-First high-concentration doped layer;

[0033] 400-Bonding interface;

[0034] 500-Doped layer;

[0035] 600-Second high-concentration doped layer.

[0036] The specific embodiments of the present application have been shown by the above-described drawings, and will be described in more detail hereinafter. These drawings and written descriptions are not intended to limit the scope of the concept of the present application by any means, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0037] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The following description is made with reference to the accompanying drawings in which like reference numerals represent like elements, unless the context dictates otherwise. The following exemplary embodiments described are not representative of all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0038] First, the terms involved in the present application are explained:

[0039] Polycrystalline 3C-SiC: Silicon carbide (SiC) is composed of silicon (Si) and carbon (C) in a 1:1 ratio, and 3C-SiC belongs to the cubic system, which is a crystal form of SiC. 3C represents that the stacking period of the crystal is 3 layers, and it is composed of a large number of small grains arranged in disorder inside, and there is a grain boundary between the grains, so it is "polycrystalline". This structure grows at a low cost, and the resistivity is 1 / 10 of that of 4H-SiC single crystal, the band gap is 2.3 eV, and the electron affinity is 0.7 eV~1.1 eV larger than that of 4H-SiC single crystal.

[0040] Monocrystalline 4H-SiC: A crystal form of SiC, but belongs to hexagonal system, 4H represents that the atomic layer stacking period is 4 layers, is a continuous ordered single crystal, no grain boundary, long-range order of atomic arrangement, band gap is 3.24eV, has high electron mobility and excellent thermal stability, suitable for high temperature and high pressure scenes and microwave radio frequency devices.

[0041] The composite substrate provided by the embodiment of the present application adjusts the interface energy band structure by using the energy band bending effect of the high-concentration doped layer, shortens the barrier width of the 3C-SiC and 4H-SiC bonding interface and reduces the barrier height, so that the electrons pass through the barrier through the tunneling mechanism, and the migration efficiency of the electrons at the heterojunction interface is improved, thereby significantly reducing the interface resistance.

[0042] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0043] Figure 1 Structure diagram of the composite substrate provided by the embodiment of the present application Figure 1 , Figure 7 Structure diagram of the composite substrate provided by the embodiment of the present application Figure 2 As shown in Figure 1 and Figure 7 , the composite substrate comprises a 3C-SiC layer 100 and a 4H-SiC layer 200.

[0044] The 3C-SiC layer 100 is a polycrystalline 3C-SiC layer, and the 4H-SiC layer 200 is a monocrystalline 4H-SiC layer.

[0045] The 4H-SiC layer 200 has a first surface 201 along its thickness, and the 3C-SiC layer 100 comprises a second surface 101 along its thickness.

[0046] A first high-concentration doped layer 300 with N-type conductivity is formed on the first surface 201 by using an ion implantation process or an epitaxy process.

[0047] Alternatively, a second high-concentration doped layer 600 with N-type conductivity is formed on the second surface 101 by using an ion implantation process or an epitaxy process.

[0048] Alternatively, the first high-concentration doped layer 300 and the second high-concentration doped layer 600 with N-type conductivity are formed on the first surface 201 and the second surface 101 respectively by ion implantation or epitaxy. The 3C-SiC layer 100 and the 4H-SiC layer 200 are bonded by a bonding process to form a composite substrate, wherein the bonding interface 400 between the 3C-SiC layer 100 and the 4H-SiC layer 200 is the contact surface between the first high-concentration doped layer 300 and the second surface 101, the contact surface between the second high-concentration doped layer 600 and the first surface 201, or the contact surface between the first high-concentration doped layer 300 and the second high-concentration doped layer 600.

[0049] When the high-concentration doped 4H-SiC layer 200 contacts the 3C-SiC layer 100, electrons will flow from the 4H-SiC with a higher Fermi level to the 3C-SiC with a lower Fermi level. For n-type doping, a positively charged ion region will be left on the side of the 4H-SiC layer 200 near the bonding interface 400, and a negatively charged electron accumulation region will be formed on the side of the 3C-SiC layer 100. This region of positive and negative charge separation is called a space charge region or a depletion region, and the electric field in the region will force the energy band to bend downward. The first high-concentration doped layer 300 raises the Fermi level of the 4H-SiC, so that the large energy band "step" originally existing between the 3C-SiC layer 100 and the 4H-SiC layer 200 is flattened to some extent. At the same time, the first high-concentration doped layer 300 doping means that the space charge region is very thin, so that the potential barrier becomes very thin.

[0050] When a potential barrier becomes both low and thin, electrons no longer need to have enough energy to "climb" over the potential barrier, but can directly "pass through" the potential barrier. The difficulty of electrons crossing the interface is greatly reduced, and under the same voltage, more current can pass through the interface, and the interface resistance is significantly reduced.

[0051] That is, the composite substrate provided by the embodiments of the present application adjusts the interface energy band structure by using the energy band bending effect of the high-concentration doped layer, shortens the potential barrier width and reduces the potential barrier height of the 3C-SiC and 4H-SiC bonding interface, makes electrons pass through the potential barrier by a tunneling mechanism, improves the migration efficiency of electrons at the heterojunction interface, and thus significantly reduces the interface resistance, thereby providing a key material basis for the development of high-performance semiconductor devices.

[0052] At the same time, when a large dose of ions is implanted, the 4H-SiC and the 3C-SiC will also be amorphized, exposing thicker dangling bonds on the bonding surface of the 4H-SiC and the 3C-SiC. After the polycrystalline 3C-SiC is amorphized, the influence of the polycrystalline grain boundary on chemical mechanical polishing is avoided, a chemical reaction with the polishing liquid is more uniform, and a 4H-SiC and a 3C-SiC with low roughness are more easily obtained, so that the 4H-SiC is more easily bonded to the 3C-SiC.

[0053] Similarly, the second high-concentration doped layer 600 is introduced into the 3C-SiC layer 100 for amorphization of the 3C-SiC layer, avoiding the influence of the polycrystalline grain boundary on the chemical mechanical polishing, and the chemical reaction with the polishing liquid is more uniform, and a 3C-SiC with low roughness is more easily obtained, so that the 4H-SiC is more easily bonded with the 3C-SiC.

[0054] In the embodiment of the present application, the doping concentration of the first high-concentration doped layer 300 and the second high-concentration doped layer 600 is 4 × 10¹ 9 ~ 5 × 10²¹ cm⁻³.

[0055] Within the above doping concentration range, the extremely high carrier concentration causes a severe bending of the energy band, compresses the interface barrier width to the nanometer level, and makes the barrier extremely thin, so that the electrons can directly cross under the high-efficiency tunneling mechanism. At the same time, the high-concentration doping introduces a large number of defects in the SiC lattice, further providing a shortcut for the electrons to cross the barrier. The electrons can easily flow through the interface, and the interface resistance becomes very low, and the heterojunction rectification characteristic is changed to the ideal ohmic characteristic.

[0056] It should be noted that the above high-concentration doping range can minimize the contact resistance while avoiding excessive damage to the material.

[0057] When the doping concentration of the high-concentration doped layer is lower than 4 × 10¹ 9 cm⁻³, the barrier is still too thick, the tunneling probability is insufficient, and the heterojunction still exhibits obvious rectification characteristics. When the doping concentration of the high-concentration doped layer is higher than 5 × 10²¹ cm⁻³, although a large number of defects are introduced in the SiC lattice, the more serious the lattice damage, the more likely to become a leakage path or a reliability hidden danger in device operation.

[0058] In the embodiment of the present application, the doping ions of the first high-concentration doped layer 300 and the second high-concentration doped layer 600 include one or more of phosphorus (P), nitrogen (N), and argon (Ar).

[0059] By selectively introducing electrically active dopants such as phosphorus (P) and nitrogen (N) to provide high-concentration carriers to induce band tunneling, and combining with the intentional manufacture of defects by implanting non-electrically active ions such as argon (Ar) to activate defect-assisted tunneling, the two work together to finally force the interface rectification characteristic to be changed to the ohmic characteristic, and the contact resistance is minimized.

[0060] In the embodiment of the present application, the thickness of the first high-concentration doped layer 300 and the second high-concentration doped layer 600 is 0 μm ~ 0.3 μm.

[0061] The high-concentration doped layer in the above thickness range is sufficient to form a stable and continuous functional layer, which can effectively reduce the interface resistance while minimizing the negative impact on the electrical properties of the bulk material and the process cost.

[0062] When the thickness of the high-concentration doped layer is greater than 0.3 μm, the doped layer is too thick, which increases the bulk resistance of the current in the longitudinal path; it also means that a higher implantation dose or energy is needed, which can cause more serious lattice damage; at the same time, it can cause difficulty in bond peeling.

[0063] In the embodiments of the present application, the roughness of the first high-concentration doped layer 300 and the second high-concentration doped layer 600 is less than 5 nm.

[0064] The ultra-low surface roughness of less than 5 nm creates an atomic-level flat contact interface for subsequent high-quality bonding, which can effectively avoid local high electric field, poor contact or interface void caused by surface undulation.

[0065] The embodiments of the present application also provide a preparation method of a composite substrate for preparing the composite substrate described above, which comprises the following steps:

[0066] Step 1: polishing the surfaces of the 3C-SiC layer 100 and the 4H-SiC layer 200, respectively.

[0067] The polishing treatment is a process of finely treating the surfaces of the 3C-SiC layer 100 and the 4H-SiC layer 200 by mechanical, chemical or a combination of both, so as to remove the surface damage layer and reduce the surface roughness, thereby obtaining an ultra-smooth surface which is atomic-level flat, has uniform chemical properties, consistent activity, bright as a mirror and free of defects, and prepares for subsequent bonding.

[0068] The surface roughness of the 3C-SiC layer 100 and the 4H-SiC layer 200 after the polishing treatment is less than 1 nm.

[0069] Step 2: forming a first high-concentration doped layer 300 with N-type conductivity on the first surface 201 of the 4H-SiC layer 200 by ion implantation process or epitaxy process, and / or forming a second high-concentration doped layer 600 with N-type conductivity on the second surface 101 of the 3C-SiC layer 100 by ion implantation process or epitaxy process.

[0070] The doping ions of the first high-concentration doped layer 300 and the second high-concentration doped layer 600 include one or more of phosphorus (P), nitrogen (N) and argon (Ar), and the doping concentration of the first high-concentration doped layer 300 and the second high-concentration doped layer 600 is 4 × 10¹ 95 x 10 21 cm -3, and the thickness of the first high-concentration doped layer 300 and the second high-concentration doped layer 600 is 0 μm ~ 0.3 μm.

[0071] Step 3: bonding the 3C-SiC layer 100 and the 4H-SiC layer 200 to each other by a bonding process to obtain a composite substrate; wherein the bonding interface 400 of the 3C-SiC layer 100 and the 4H-SiC layer 200 is the contact surface of the first high-concentration doped layer 300 and the second surface 101, the contact surface of the second high-concentration doped layer 600 and the first surface 201, or the contact surface of the first high-concentration doped layer 300 and the second high-concentration doped layer 600.

[0072] By utilizing the band bending effect of the first high-concentration doped layer 300 and the second high-concentration doped layer 600 to adjust the interface band structure, the width of the potential barrier of the bonding interface is shortened and the height of the potential barrier is reduced, so that the electrons pass through the potential barrier by the tunneling mechanism, and the migration efficiency of the electrons at the heterojunction interface is improved, thereby significantly reducing the interface resistance.

[0073] Reference Figure 2 In an embodiment of the present application, after step 2, the method further comprises: forming a doped layer 500 with N-type conductivity on the third surface 202 of the 4H-SiC layer 200 by an ion implantation process or an epitaxy process; wherein the third surface 202 and the first surface 201 are opposite along the thickness direction of the 4H-SiC layer 200.

[0074] Since high-concentration implantation can seriously damage the wafer surface and subsurface, a damage layer with high-density dislocations, micro-cracks and other defects is formed, and there is stress between this layer of material and the perfect crystal inside. After step 2, the third surface 202 is further ion doped to form a symmetrical doped structure, so that the double sides of the 4H-SiC layer 200 have compression stress layers with similar size and same direction, and the stresses of the double sides offset each other, so that the wafer as a whole returns to flatness, thereby compensating for the wafer warping problem caused by single-side implantation.

[0075] It should be noted that both sides are high-concentration doped of the same type (N-type).

[0076] It should be further noted that in the preparation process of the composite substrate, the doped layer 500 of the third surface 202 will disappear with the peeling; wherein the peeling is to form a layer of micro bubbles or defect layer at a specific depth (such as: 0.6 μm) by implanting hydrogen ions on one side of the doped layer 500, and only the 4H-SiC layer at the specific depth (such as: 0.6 μm) is left, and the rest is peeled off.

[0077] Similarly, after forming the second high-concentration doped layer 600 with N-type conductivity on the second surface 101 of the 3C-SiC layer 100 by the ion implantation process or the epitaxy process, the method further comprises: forming a doped layer 500 with N-type conductivity on a fourth surface of the 3C-SiC layer 100 by the ion implantation process or the epitaxy process; wherein the fourth surface is opposite to the second surface 101 along the thickness direction of the 3C-SiC layer 100.

[0078] In another embodiment of the present application, after step 2, the method further comprises: treating the 4H-SiC layer 200 by a high-temperature annealing process.

[0079] The high-temperature annealing process is to heat the warped wafer with internal residual stress to a high enough temperature, at which the material is transformed from a "rigid" state to a state with certain "plasticity". Under the driving of thermal energy, the dislocations and other defects inside the crystal start to move, recombine and annihilate, so that the "frozen" elastic strain energy is released, and the uneven stress distribution becomes uniform. When the wafer is uniformly and slowly cooled down, it will be solidified in a new state with lower stress and more flatness, and the warping is reduced or eliminated.

[0080] In the high-temperature annealing process, the annealing temperature is 900-1900℃, and the annealing time is 5-90min.

[0081] Similarly, after forming the second high-concentration doped layer 600 with N-type conductivity on the second surface 101 of the 3C-SiC layer 100 by the ion implantation process or the epitaxy process, the method further comprises: treating the 3C-SiC layer 100 by a high-temperature annealing process.

[0082] It should be noted that the ion doping on the double sides of the 4H-SiC layer 200 and / or the 3C-SiC layer 100 and the high-temperature annealing of the 4H-SiC layer 200 and / or the 3C-SiC layer 100 can be used in combination to solve the wafer warping problem.

[0083] In the embodiment of the present application, before step 2 of forming the first high-concentration doped layer 300 with N-type conductivity on the first surface 201 of the 4H-SiC layer 200 by the ion implantation process, the method further comprises: depositing a barrier layer on the first surface 201 by chemical vapor deposition, the barrier layer being used to reduce the damage to the first surface 201 during ion implantation.

[0084] In the embodiment of the present application, before step 2 of forming the first high-concentration doped layer 300 with N-type conductivity on the first surface 201 of the 4H-SiC layer 200 by the ion implantation process, the method further comprises: depositing a barrier layer on the first surface 201 by chemical vapor deposition, the barrier layer being used to reduce the damage to the first surface 201 during ion implantation.

[0085] It should be noted that the barrier layer is removed by chemical etching after step 2 is completed.

[0086] The composite substrate of the present application is described in detail below by way of Example 1.

[0087] The specific preparation steps of Example 1 are as follows:

[0088] Step one: preparation of a double-side polished substrate

[0089] A piece of N-type 4H-SiC single crystal substrate and a piece of 3C-SiC polycrystal substrate were prepared, and both of the substrates were double-side precision polished to the following specifications:

[0090] The surface roughness was < 1 nm, the total thickness variation was < 3 μm, the local thickness variation was < 1 μm, the bending degree was -20 μm ~ +20 μm, the warping degree was < 40 μm, the thickness of the 4H-SiC substrate was 350 μm, the thickness of the 3C-SiC substrate was 300 μm, the resistivity of the 4H-SiC single crystal substrate was 0.020 Ω·cm, and the resistivity of the 3C-SiC polycrystal substrate was 0.002 Ω·cm.

[0091] Step two: formation of a high-concentration doped layer on the growth surface of the 4H-SiC substrate

[0092] A 200 nm-thick SiO2 film was deposited on the growth surface of the 4H-SiC substrate by chemical vapor deposition as an ion implantation mask.

[0093] The growth surface of the 4H-SiC substrate was doped by ion implantation.

[0094] Nitrogen ions were implanted as donor impurities, the nitrogen ion implantation energy was 60 keV, and the dose was 3×10¹ 5 cm⁻².

[0095] After the above process, a N-type high-concentration doped layer with a thickness of about 0.2 μm and a nitrogen concentration of about 7×10 20 cm⁻³ was formed on the growth surface of the 4H-SiC substrate, and the surface roughness of the high-concentration doped layer was less than 3 nm.

[0096] Step three: adjustment of the flatness of the 4H-SiC substrate

[0097] In order to compensate for the wafer warping that may be caused by single-side implantation, nitrogen ions were implanted on the back surface of the 4H-SiC substrate, the nitrogen ion implantation energy was 60 keV, and the dose was 3×10¹ 5 cm⁻².

[0098] Subsequently, the wafer was annealed at a medium temperature in an argon atmosphere at 1850℃ for 20 minutes.

[0099] This process can effectively release the lattice stress, and finally adjust the wafer warpage to < 30 μm, meeting the substrate flatness requirement.

[0100] Step four: bonding to form a composite substrate

[0101] In an ultra-high vacuum environment, the 4H-SiC single crystal substrate treated above is aligned with the 3C-SiC polycrystalline substrate and a certain mechanical pressure is applied to perform direct bonding.

[0102] The initial bonding temperature is 800℃, and then high-temperature reinforced bonding is performed in an inert atmosphere at 1850℃ for 1 hour to form a firm bonding interface.

[0103] After the bonding is completed, the 4H-SiC substrate is subjected to roughness reduction treatment by combining mechanical grinding and chemical mechanical polishing.

[0104] Finally, a composite substrate is obtained, the 4H-SiC single crystal thin layer on the top of the composite substrate has a thickness of 0.6 μm, and an ohmic contact interface with low resistance is formed between the 4H-SiC single crystal thin layer and the 3C-SiC polycrystalline substrate.

[0105] Step five: simulation verification

[0106] As shown in Figure 3 , Comparative Example 1 is a substrate obtained by directly bonding 3C-SiC and 4H-SiC (Existing Technology), and the difference from Example 1 is that no high-concentration doped layer is provided between the 3C-SiC and the 4H-SiC.

[0107] The composite substrate prepared in Example 1 (This Patent) and the substrate of Comparative Example 1 are respectively subjected to simulation verification.

[0108] As shown in Figure 4 and Figure 5 , in a coordinate system with energy (Energy) as the vertical axis and depth (Depth) as the horizontal axis, the dashed line represents the energy band curve of Example 1, and the solid line represents the energy band curve of Comparative Example 1 without introducing a high-concentration doped layer. The energy band curve is used to describe the energy that an electron is "allowed" to have at different positions inside the material; EV in the energy band curve represents the valence band top, marking the highest energy boundary of the valence band; EC in the energy band curve represents the conduction band bottom, marking the lowest energy boundary of the conduction band. It can be seen that, compared with Comparative Example 1, the vertical energy value of EV and EC of Example 1 is reduced, indicating that the height of the potential barrier is reduced and the width of the potential barrier is shortened.

[0109] Step five: actual wafer verification

[0110] As shown in Figure 6As shown in the coordinate system with the current as the vertical axis and the voltage as the horizontal axis, the dotted line represents the volt-ampere characteristic curve of Example 1, and the solid line represents the volt-ampere characteristic curve of Comparative Example 1 without introducing the high-concentration doped layer; the greater the slope, the steeper the curve, indicating that the greater the current generated at the same voltage, and the smaller the resistance value; the smaller the slope, the flatter the curve, indicating that the smaller the current generated at the same voltage, and the greater the resistance value. It can be seen that Example 1 can adjust the heterojunction rectification characteristic to an ohmic characteristic, and reduce the interface resistance.

[0111] Therefore, the test results show that, under the premise of not affecting other electrical parameters, the specific contact resistance of the bonding interface of Example 1 is low, which is significantly better than that of Comparative Example 1 without introducing the high-concentration doped layer, proving the excellent effect of the application scheme in reducing the interface resistance.

[0112] In summary, the application provides a composite substrate and a preparation method of the composite substrate. The composite substrate comprises a 3C-SiC layer 100 and a 4H-SiC layer 200; the 4H-SiC layer 200 comprises a first surface 201, and the 3C-SiC layer 100 comprises a second surface 101; the first surface 201 comprises a first high-concentration doped layer 300 with N-type conductivity, and / or the second surface 101 comprises a second high-concentration doped layer 600 with N-type conductivity; a contact surface of the first high-concentration doped layer 300 and the second surface 101, a contact surface of the second high-concentration doped layer 600 and the first surface 201, or a contact surface of the first high-concentration doped layer 300 and the second high-concentration doped layer 600 is a bonding interface 400 of the 3C-SiC layer 100 and the 4H-SiC layer 200.

[0113] By utilizing the band bending effect of the first high-concentration doped layer 300 and the second high-concentration doped layer 600 to adjust the interface band structure, the barrier width of the bonding interface 400 of the 3C-SiC layer 100 and the 4H-SiC layer 200 is shortened, and the barrier height is reduced, so that electrons pass through the barrier through a tunneling mechanism, the migration efficiency of electrons at the heterojunction interface is improved, and thus the interface resistance is significantly reduced, providing a key material basis for the development of high-performance semiconductor devices.

[0114] At the same time, when a large dose of ions is implanted, 4H-SiC and 3C-SiC will also be amorphized, exposing thicker dangling bonds on the bonding surface of 4H-SiC and 3C-SiC, and after amorphizing the polycrystalline 3C-SiC, the influence of the polycrystalline grain boundary on chemical mechanical polishing is avoided, the chemical reaction with the polishing liquid is more uniform, and 4H-SiC and 3C-SiC with low roughness are more easily obtained, so that 4H-SiC is more easily bonded to 3C-SiC.

[0115] It should be understood that many of the materials and devices exemplified in this disclosure are articles of manufacture (i.e., articles of manufacture) according to this disclosure. The articles of manufacture can be manufactured as such or can be manufactured by combining the materials and devices exemplified in this disclosure. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. It should be understood that, in some embodiments, equivalents to the specific electrode structures and / or methods described herein can be employed without departing from the scope of the application. Accordingly, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," "having," "containing," "involving," "characterized by," "characterized into," and variations thereof herein, is meant to encompass the items listed thereafter, and equivalents thereof as well as additional items. Although the foregoing application has been described in some detail by way of illustration and example, it is not to be limited thereby, but rather, only by the scope of the appended claims.

Claims

1. A composite substrate, characterized in that, include: 3C-SiC layer (100); as well as A 4H-SiC layer (200) includes a first surface (201), a 3C-SiC layer (100) includes a second surface (101), the first surface (201) includes a first high-concentration doped layer (300) having N-type conductivity, and / or the second surface (101) includes a second high-concentration doped layer (600) having N-type conductivity; The contact surface between the first high-concentration doped layer (300) and the second surface (101), the contact surface between the second high-concentration doped layer (600) and the first surface (201), or the contact surface between the first high-concentration doped layer (300) and the second high-concentration doped layer (600) is the bonding interface (400) of the 3C-SiC layer (100) and the 4H-SiC layer (200). Wherein, the doping concentrations of the first high-concentration doped layer (300) and the second high-concentration doped layer (600) are: .

2. The composite substrate according to claim 1, characterized in that, The 3C-SiC layer (100) is a polycrystalline 3C-SiC layer; The 4H-SiC layer (200) is a single-crystal 4H-SiC layer.

3. The composite substrate according to claim 1 or 2, characterized in that, The dopant ions of the first high-concentration doped layer (300) and the second high-concentration doped layer (600) include one or more of phosphorus, nitrogen and argon.

4. The composite substrate according to claim 1 or 2, characterized in that, The thickness of the first high-concentration doped layer (300) and the second high-concentration doped layer (600) is 0 μm to 0.3 μm.

5. The composite substrate according to claim 1 or 2, characterized in that, The roughness of the first high-concentration doped layer (300) and the second high-concentration doped layer (600) is less than 5 nm.

6. A method for preparing a composite substrate, used to prepare the composite substrate according to any one of claims 1-5, characterized in that, include: The surfaces of the 3C-SiC layer (100) and the 4H-SiC layer (200) were polished respectively; A first high-concentration doped layer (300) with N-type conductivity is formed on the first surface (201) of the 4H-SiC layer (200) by ion implantation or epitaxy, and / or a second high-concentration doped layer (600) with N-type conductivity is formed on the second surface (101) of the 3C-SiC layer (100). The 3C-SiC layer (100) and the 4H-SiC layer (200) are bonded together to obtain a composite substrate; The bonding interface (400) between the 3C-SiC layer (100) and the 4H-SiC layer (200) is the contact surface between the first high-concentration doped layer (300) and the second surface (101), the contact surface between the second high-concentration doped layer (600) and the first surface (201), or the contact surface between the first high-concentration doped layer (300) and the second high-concentration doped layer (600).

7. The method for preparing the composite substrate according to claim 6, characterized in that, After forming a first high-concentration doped layer (300) with N-type conductivity on the first surface (201) of the 4H-SiC layer (200) by ion implantation or epitaxy, the method further includes: An N-type conductive doped layer (500) is formed on the third surface (202) by an ion implantation process. The third surface (202) is opposite to the first surface (201) along the thickness direction of the 4H-SiC layer (200).

8. The method for preparing the composite substrate according to claim 6, characterized in that, After forming a first high-concentration doped layer (300) with N-type conductivity on the first surface (201) of the 4H-SiC layer (200) by ion implantation or epitaxy, the method further includes: The 4H-SiC layer (200) is treated by a high-temperature annealing process. The annealing temperature during the high-temperature annealing process is 900℃~1900℃, and the annealing time is 5min~90min.

9. The method for preparing the composite substrate according to claim 6, characterized in that, Before forming a first high-concentration doped layer (300) with N-type conductivity on the first surface (201) of the 4H-SiC layer (200) by ion implantation, the method further includes: A barrier layer is deposited on the first surface (201) by chemical vapor deposition, the barrier layer being used to mitigate damage to the first surface (201) during ion implantation.

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